W3DNShaderInfo - Get shader information Verbose mode Shader: 9.frag.spv Compiling 9.frag.spv failed (23) with error: shader compilation failed due to errors Log: Shader size: 33284 bytes Parsing SPIR-V code Module Version: 1.2.0 Generator Magic Number: 0x80003 Upper bound on ids: 1458 Parsed instructions: OpCapability: : Shader 1: OpExtInstImport: : GLSL.std.450 OpMemoryModel: : addressing: Logical, memory: GLSL450 4: OpEntryPoint: : main, execution model: Fragment 4: OpExecutionMode: : OriginLowerLeft OpSource: : ESSL ver 310 4: OpName: : main 11: OpName: : gumColour(f1; 10: OpName: : i 14: OpName: : gumRamp(f1; 13: OpName: : i 18: OpName: : hash(f1; 17: OpName: : n 23: OpName: : noise(vf3; 22: OpName: : x 29: OpName: : smN2(vf2; 28: OpName: : p 32: OpName: : smN3(vf3; 31: OpName: : p 35: OpName: : fbm3(vf3; 34: OpName: : p 40: OpName: : rotate(f1;vf2; 38: OpName: : a 39: OpName: : v 43: OpName: : sugarybit(vf2; 42: OpName: : p 48: OpName: : sugarlayer(vf2;f1; 46: OpName: : t 47: OpName: : ndotv 52: OpName: : saturatecol(vf3; 51: OpName: : c 56: OpName: : sprinkles2(vf2;f1; 54: OpName: : coord 55: OpName: : ndotv 60: OpName: : sprinkles(vf2;f1; 58: OpName: : coord 59: OpName: : ndotv 66: OpName: : gummy(vf3;vf3;vf3; 63: OpName: : no 64: OpName: : vo 65: OpName: : v 69: OpName: : de(vf3; 68: OpName: : p 73: OpName: : marble(vf2; 72: OpName: : p 76: OpName: : cameraPos(f1; 75: OpName: : t 79: OpName: : targetPos(f1; 78: OpName: : ti 82: OpName: : cameraZoom(f1; 81: OpName: : ti 89: OpName: : trace(vf3;vf3;f1;f1; 85: OpName: : ro 86: OpName: : rd 87: OpName: : t 88: OpName: : max_t 96: OpName: : mainImage(vf4;vf2; 94: OpName: : fragColor 95: OpName: : fragCoord 99: OpName: : tc 103: OpName: : time 104: OpName: : colour 105: OpName: : ss 107: OpName: : is_choc 108: OpName: : t_per_target 111: OpName: : l 115: OpName: : icing_factor 178: OpName: : p 181: OpName: : f 192: OpName: : n 211: OpName: : param211 215: OpName: : param215 222: OpName: : param222 227: OpName: : param227 237: OpName: : param237 242: OpName: : param242 250: OpName: : param250 255: OpName: : param255 272: OpName: : param272 276: OpName: : param276 281: OpName: : f 284: OpName: : i 294: OpName: : x 301: OpName: : param301 344: OpName: : o 345: OpName: : a 365: OpName: : b 385: OpName: : t2 388: OpName: : p 393: OpName: : c 396: OpName: : a 404: OpName: : o 418: OpName: : s 419: OpName: : param419 426: OpName: : param426 431: OpName: : fres 445: OpName: : param445 447: OpName: : param447 449: OpName: : param449 453: OpName: : param453 463: OpName: : param463 469: OpName: : sprinkle 470: OpName: : i 493: OpName: : param493 494: OpName: : param494 513: OpName: : param513 514: OpName: : param514 519: OpName: : param519 520: OpName: : param520 528: OpName: : ndotv 533: OpName: : s0 544: OpName: : param544 545: OpName: : param545 548: OpName: : s1 549: OpName: : param549 552: OpName: : param552 555: OpName: : sprinkle 562: OpName: : ss 568: OpName: : tex 570: OpName: : param570 591: OpName: : param591 614: OpName: : fp 631: OpName: : ff 635: OpName: : param635 643: OpName: : param643 685: OpName: : sp 690: OpName: : pl 694: OpName: : d 713: OpName: : border_size 715: OpName: : corner_size 716: OpName: : c0 719: OpName: : c1 724: OpName: : rc1 734: OpName: : ccol 740: OpName: : param740 747: OpName: : pat 767: OpName: : param767 779: OpName: : param779 790: OpName: : param790 796: OpName: : bcol 800: OpName: : br 814: OpName: : cr 854: OpName: : target 858: OpName: : param858 899: OpName: : i 908: OpName: : d 914: OpName: : param914 938: OpName: : rp 944: OpName: : col 947: OpName: : e 948: OpName: : c 949: OpName: : param949 952: OpName: : n 957: OpName: : param957 965: OpName: : param965 973: OpName: : param973 979: OpName: : v 981: OpName: : h 998: OpName: : r 1011: OpName: : chocolour 1028: OpName: : param1028 1079: OpName: : param1079 1081: OpName: : param1081 1083: OpName: : param1083 1110: OpName: : iTime 1114: OpName: : iResolution 1120: OpName: : ti 1125: OpName: : tf 1130: OpName: : camo 1131: OpName: : param1131 1134: OpName: : camt 1137: OpName: : param1137 1139: OpName: : param1139 1146: OpName: : camd 1151: OpName: : camu 1156: OpName: : camv 1167: OpName: : m 1184: OpName: : q 1188: OpName: : p 1190: OpName: : ro 1201: OpName: : zoom 1204: OpName: : param1204 1206: OpName: : param1206 1212: OpName: : rd 1221: OpName: : t 1229: OpName: : t2 1238: OpName: : col 1239: OpName: : param1239 1241: OpName: : param1241 1243: OpName: : param1243 1245: OpName: : param1245 1249: OpName: : rp 1267: OpName: : c 1275: OpName: : xc 1278: OpName: : x 1289: OpName: : cc 1312: OpName: : param1312 1319: OpName: : h 1324: OpName: : r 1327: OpName: : rt 1330: OpName: : param1330 1331: OpName: : param1331 1333: OpName: : param1333 1341: OpName: : param1341 1357: OpName: : icing 1359: OpName: : iMouse 1381: OpName: : param1381 1396: OpName: : param1396 1430: OpName: : color 1432: OpName: : gl_FragCoord 1433: OpName: : param1433 1434: OpName: : param1434 1440: OpName: : finalColor 1442: OpName: : iDate 1443: OpName: : iFrame 1447: OpName: : iChannelResolution 1451: OpName: : iChannel0 1452: OpName: : iChannel1 1453: OpName: : iChannel2 1454: OpName: : iChannel3 1456: OpName: : gum_colours 1457: OpName: : gum_ramps 284: OpDecorate: : RelaxedPrecision 291: OpDecorate: : RelaxedPrecision 295: OpDecorate: : RelaxedPrecision 309: OpDecorate: : RelaxedPrecision 310: OpDecorate: : RelaxedPrecision 470: OpDecorate: : RelaxedPrecision 477: OpDecorate: : RelaxedPrecision 481: OpDecorate: : RelaxedPrecision 487: OpDecorate: : RelaxedPrecision 497: OpDecorate: : RelaxedPrecision 505: OpDecorate: : RelaxedPrecision 506: OpDecorate: : RelaxedPrecision 899: OpDecorate: : RelaxedPrecision 905: OpDecorate: : RelaxedPrecision 936: OpDecorate: : RelaxedPrecision 937: OpDecorate: : RelaxedPrecision 1432: OpDecorate: : BuiltIn(FragCoord) 1451: OpDecorate: : RelaxedPrecision 1451: OpDecorate: : DescriptorSet(0) 1452: OpDecorate: : RelaxedPrecision 1452: OpDecorate: : DescriptorSet(0) 1453: OpDecorate: : RelaxedPrecision 1453: OpDecorate: : DescriptorSet(0) 1454: OpDecorate: : RelaxedPrecision 1454: OpDecorate: : DescriptorSet(0) 2: OpTypeVoid: Void 3: OpTypeFunction: 2 << func() 6: OpTypeFloat: Float: 32 bits 7: OpTypePointer: ???Ptr: storage class: Function 8: OpTypeVector: ???Vector3: num-elements: 3, element type id: 6 9: OpTypeFunction: 8 << func(7) 16: OpTypeFunction: 6 << func(7) 20: OpTypePointer: ???Ptr: storage class: Function 21: OpTypeFunction: 6 << func(20) 25: OpTypeVector: ???Vector2: num-elements: 2, element type id: 6 26: OpTypePointer: ???Ptr: storage class: Function 27: OpTypeFunction: 6 << func(26) 37: OpTypeFunction: 25 << func(7, 26) 45: OpTypeFunction: 6 << func(26, 7) 50: OpTypeFunction: 8 << func(20) 62: OpTypeFunction: 8 << func(20, 20, 20) 71: OpTypeFunction: 8 << func(26) 84: OpTypeFunction: 8 << func(20, 20, 7, 7) 91: OpTypeVector: ???Vector4: num-elements: 4, element type id: 6 92: OpTypePointer: ???Ptr: storage class: Function 93: OpTypeFunction: 2 << func(92, 26) 98: OpTypePointer: ???Ptr: storage class: Private 99: OpVariable: 98: var99: storage class: Private 100: OpConstant: 6 const100 = 0x0 101: OpConstantComposite: 25 const101 = {id:100, id:100} 102: OpTypePointer: ???Ptr: storage class: Private 103: OpVariable: 102: var103: storage class: Private 104: OpVariable: 102: var104: storage class: Private 105: OpVariable: 102: var105: storage class: Private 106: OpConstant: 6 const106 = 0x3f800000 107: OpVariable: 102: var107: storage class: Private 108: OpVariable: 102: var108: storage class: Private 109: OpConstant: 6 const109 = 0x40400000 110: OpTypePointer: ???Ptr: storage class: Private 111: OpVariable: 110: var111: storage class: Private 112: OpConstant: 6 const112 = 0x3ea1e89b 113: OpConstant: 6 const113 = 0x3f72dce9 114: OpConstantComposite: 8 const114 = {id:112, id:113, id:100} 115: OpVariable: 102: var115: storage class: Private 117: OpTypeBool: Bool 121: OpConstant: 6 const121 = 0x3de147ae 122: OpConstant: 6 const122 = 0x3b03126f 123: OpConstantComposite: 8 const123 = {id:121, id:100, id:122} 127: OpConstant: 6 const127 = 0x40000000 131: OpConstant: 6 const131 = 0x3d75c28f 132: OpConstantComposite: 8 const132 = {id:122, id:131, id:100} 139: OpConstant: 6 const139 = 0x3ca3d70a 140: OpConstantComposite: 8 const140 = {id:100, id:139, id:121} 143: OpConstant: 6 const143 = 0x3c449ba6 144: OpConstantComposite: 8 const144 = {id:121, id:143, id:100} 151: OpConstant: 6 const151 = 0x3f4ccccd 152: OpConstantComposite: 8 const152 = {id:151, id:106, id:106} 159: OpConstantComposite: 8 const159 = {id:151, id:151, id:106} 166: OpConstantComposite: 8 const166 = {id:106, id:151, id:106} 173: OpConstant: 6 const173 = 0x472aee8c 193: OpTypeInt: UInt: 32 bits, unsigned 194: OpConstant: 193 const194 = 0x0 197: OpConstant: 193 const197 = 0x1 200: OpConstant: 6 const200 = 0x431d0000 203: OpConstant: 6 const203 = 0x42e20000 204: OpConstant: 193 const204 = 0x2 225: OpConstant: 6 const225 = 0x431e0000 240: OpConstant: 6 const240 = 0x42e40000 248: OpConstant: 6 const248 = 0x43870000 253: OpConstant: 6 const253 = 0x43878000 282: OpTypeInt: Int: 32 bits, signed 283: OpTypePointer: ???Ptr: storage class: Function 285: OpConstant: 282 const285 = 0x1 292: OpConstant: 282 const292 = 0x9 303: OpConstant: 6 const303 = 0x3f000000 340: OpConstant: 6 const340 = 0xbf800000 341: OpConstantComposite: 25 const341 = {id:340, id:340} 342: OpConstantComposite: 25 const342 = {id:106, id:106} 349: OpConstant: 6 const349 = 0x41000000 361: OpConstant: 6 const361 = 0x3f733333 377: OpConstant: 6 const377 = 0x40800000 391: OpConstantComposite: 25 const391 = {id:303, id:303} 401: OpConstant: 6 const401 = 0x40a00000 407: OpConstant: 6 const407 = 0x42540000 412: OpConstant: 6 const412 = 0x42fa0000 416: OpConstant: 6 const416 = 0x40200000 423: OpConstant: 6 const423 = 0x42c80000 424: OpConstantComposite: 25 const424 = {id:423, id:423} 435: OpConstant: 6 const435 = 0x3f666666 437: OpConstant: 6 const437 = 0x41c80000 471: OpConstant: 282 const471 = 0x0 478: OpConstant: 282 const478 = 0x4 483: OpConstant: 6 const483 = 0x41273333 489: OpConstant: 6 const489 = 0x3e4ccccd 511: OpConstant: 6 const511 = 0x3f400000 523: OpConstant: 6 const523 = 0x3e99999a 569: OpConstantComposite: 8 const569 = {id:303, id:303, id:303} 573: OpConstant: 6 const573 = 0x3f7ae148 576: OpConstant: 6 const576 = 0x3dcccccd 585: OpConstantComposite: 8 const585 = {id:127, id:127, id:127} 593: OpConstant: 6 const593 = 0x3f866666 602: OpConstant: 6 const602 = 0x3c23d70a 609: OpConstant: 6 const609 = 0x3fa66666 621: OpConstant: 6 const621 = 0x41200000 625: OpConstant: 6 const625 = 0x42ce0000 633: OpConstant: 6 const633 = 0x41f00000 637: OpConstant: 6 const637 = 0x3a83126f 647: OpConstant: 6 const647 = 0x3d4ccccd 664: OpConstantComposite: 25 const664 = {id:109, id:109} 666: OpConstant: 6 const666 = 0x3fc00000 667: OpConstantComposite: 25 const667 = {id:666, id:666} 671: OpConstant: 6 const671 = 0x3f333333 674: OpConstant: 6 const674 = 0x40e00000 678: OpConstant: 6 const678 = 0x41100000 704: OpConstant: 6 const704 = 0x3f19999a 714: OpConstant: 6 const714 = 0x3c75c28f 730: OpConstantComposite: 25 const730 = {id:106, id:340} 735: OpConstantComposite: 8 const735 = {id:576, id:576, id:647} 748: OpConstant: 6 const748 = 0x3ecccccd 749: OpConstant: 6 const749 = 0x3e75c28f 750: OpConstantComposite: 8 const750 = {id:748, id:748, id:749} 751: OpConstant: 6 const751 = 0x3f0f5c29 752: OpConstantComposite: 8 const752 = {id:671, id:671, id:751} 844: OpConstant: 6 const844 = 0x40c00000 848: OpConstant: 6 const848 = 0x3cf5c28f 860: OpConstantComposite: 8 const860 = {id:106, id:100, id:100} 863: OpConstant: 6 const863 = 0x41a00000 867: OpConstant: 6 const867 = 0xc0e00000 869: OpConstant: 6 const869 = 0x41600000 888: OpConstant: 6 const888 = 0x40600000 895: OpConstant: 6 const895 = 0x3fb33333 906: OpConstant: 282 const906 = 0x64 921: OpConstantComposite: 8 const921 = {id:100, id:100, id:100} 925: OpConstant: 6 const925 = 0x38d1b717 945: OpConstant: 6 const945 = 0x3ba3d70a 946: OpConstantComposite: 8 const946 = {id:139, id:602, id:945} 1012: OpConstant: 6 const1012 = 0x40266666 1013: OpConstantComposite: 8 const1013 = {id:377, id:377, id:1012} 1014: OpConstant: 6 const1014 = 0x3f47ae14 1015: OpConstant: 6 const1015 = 0x3eb851ec 1016: OpConstant: 6 const1016 = 0x3df5c28f 1017: OpConstantComposite: 8 const1017 = {id:1014, id:1015, id:1016} 1035: OpConstantComposite: 8 const1035 = {id:609, id:704, id:489} 1059: OpConstantComposite: 8 const1059 = {id:131, id:131, id:848} 1093: OpConstant: 6 const1093 = 0x43800000 1109: OpTypePointer: ???Ptr: storage class: UniformConstant 1110: OpVariable: 1109: var1110: storage class: UniformConstant 1113: OpTypePointer: ???Ptr: storage class: UniformConstant 1114: OpVariable: 1113: var1114: storage class: UniformConstant 1153: OpConstantComposite: 8 const1153 = {id:100, id:106, id:100} 1165: OpTypeMatrix: Matrix?x?: num-columns: 3, column type id: 8 1166: OpTypePointer: ???Ptr: storage class: Function 1230: OpConstant: 6 const1230 = 0xbc23d70a 1290: OpConstantComposite: 8 const1290 = {id:106, id:106, id:106} 1291: OpConstant: 6 const1291 = 0x3e800000 1292: OpConstantComposite: 8 const1292 = {id:303, id:303, id:1291} 1297: OpConstantComposite: 8 const1297 = {id:435, id:435, id:303} 1347: OpConstant: 6 const1347 = 0x3ea8f5c3 1348: OpConstant: 6 const1348 = 0x3f07ae14 1358: OpTypePointer: ???Ptr: storage class: UniformConstant 1359: OpVariable: 1358: var1359: storage class: UniformConstant 1369: OpConstant: 6 const1369 = 0xbe800000 1372: OpConstant: 6 const1372 = 0x3eb33333 1376: OpConstant: 6 const1376 = 0x40866666 1391: OpConstant: 6 const1391 = 0x4121999a 1409: OpConstant: 6 const1409 = 0x41800000 1431: OpTypePointer: ???Ptr: storage class: Input 1432: OpVariable: 1431: var1432: storage class: Input 1439: OpTypePointer: ???Ptr: storage class: Output 1440: OpVariable: 1439: var1440: storage class: Output 1442: OpVariable: 1358: var1442: storage class: UniformConstant 1443: OpVariable: 1109: var1443: storage class: UniformConstant 1444: OpConstant: 193 const1444 = 0x4 1445: OpTypeArray: ???[]: length id: 1444, element type id: 8 1446: OpTypePointer: ???Ptr: storage class: UniformConstant 1447: OpVariable: 1446: var1447: storage class: UniformConstant 1448: OpTypeImage: Image(6): 2D, no-depth, sampled, ReadOnly 1449: OpTypeSampledImage: SampledImage(1448) 1450: OpTypePointer: ???Ptr: storage class: UniformConstant 1451: OpVariable: 1450: var1451: storage class: UniformConstant 1452: OpVariable: 1450: var1452: storage class: UniformConstant 1453: OpVariable: 1450: var1453: storage class: UniformConstant 1454: OpVariable: 1450: var1454: storage class: UniformConstant 1455: OpTypePointer: ???Ptr: storage class: Private 1456: OpVariable: 1455: var1456: storage class: Private 1457: OpVariable: 1455: var1457: storage class: Private 4: OpFunction: func4(type: 3) 5: OpLabel: 1430: OpVariable: 92: var1430: storage class: Function 1433: OpVariable: 92: var1433: storage class: Function 1434: OpVariable: 26: var1434: storage class: Function OpStore: : 101 >> 99 OpStore: : 100 >> 103 OpStore: : 100 >> 104 OpStore: : 106 >> 105 OpStore: : 100 >> 107 OpStore: : 109 >> 108 OpStore: : 114 >> 111 OpStore: : 100 >> 115 1435: OpLoad: 91: tmp1435 << 1432 1436: OpVectorShuffle: 25: tmp1436 << 1435, 1435, 0, 1 OpStore: : 1436 >> 1434 1437: OpFunctionCall: 2: tmp1437(1433, 1434) 1438: OpLoad: 91: tmp1438 << 1433 OpStore: : 1438 >> 1430 1441: OpLoad: 91: tmp1441 << 1430 OpStore: : 1441 >> 1440 OpReturn: OpFunctionEnd: 11: OpFunction: func11(type: 9) 10: OpFunctionParameter: 7: var10: storage class: Function 12: OpLabel: 116: OpLoad: 6: tmp116 << 10 118: OpFOrdLessThan: 117: tmp118 << 116, 106 OpSelectionMerge: (merge: 120) OpBranchConditional: if(118) then branch to 119, else branch to 125 119: OpLabel: OpReturnValue: : << 123 125: OpLabel: 126: OpLoad: 6: tmp126 << 10 128: OpFOrdLessThan: 117: tmp128 << 126, 127 OpSelectionMerge: (merge: 130) OpBranchConditional: if(128) then branch to 129, else branch to 134 129: OpLabel: OpReturnValue: : << 132 134: OpLabel: 135: OpLoad: 6: tmp135 << 10 136: OpFOrdLessThan: 117: tmp136 << 135, 109 OpSelectionMerge: (merge: 138) OpBranchConditional: if(136) then branch to 137, else branch to 142 137: OpLabel: OpReturnValue: : << 140 142: OpLabel: OpReturnValue: : << 144 138: OpLabel: OpBranch: to 130 130: OpLabel: OpBranch: to 120 120: OpLabel: 146: OpUndef: 8: tmp146 << OpReturnValue: : << 146 OpFunctionEnd: 14: OpFunction: func14(type: 9) 13: OpFunctionParameter: 7: var13: storage class: Function 15: OpLabel: 147: OpLoad: 6: tmp147 << 13 148: OpFOrdLessThan: 117: tmp148 << 147, 106 OpSelectionMerge: (merge: 150) OpBranchConditional: if(148) then branch to 149, else branch to 154 149: OpLabel: OpReturnValue: : << 152 154: OpLabel: 155: OpLoad: 6: tmp155 << 13 156: OpFOrdLessThan: 117: tmp156 << 155, 127 OpSelectionMerge: (merge: 158) OpBranchConditional: if(156) then branch to 157, else branch to 161 157: OpLabel: OpReturnValue: : << 159 161: OpLabel: 162: OpLoad: 6: tmp162 << 13 163: OpFOrdLessThan: 117: tmp163 << 162, 109 OpSelectionMerge: (merge: 165) OpBranchConditional: if(163) then branch to 164, else branch to 168 164: OpLabel: OpReturnValue: : << 166 168: OpLabel: OpReturnValue: : << 159 165: OpLabel: OpBranch: to 158 158: OpLabel: OpBranch: to 150 150: OpLabel: 170: OpUndef: 8: tmp170 << OpReturnValue: : << 170 OpFunctionEnd: 18: OpFunction: func18(type: 16) 17: OpFunctionParameter: 7: var17: storage class: Function 19: OpLabel: 171: OpLoad: 6: tmp171 << 17 172: OpExtInst(13): 6: tmp172 << 171 174: OpFMul: 6: tmp174 << 172, 173 175: OpExtInst(10): 6: tmp175 << 174 OpReturnValue: : << 175 OpFunctionEnd: 23: OpFunction: func23(type: 21) 22: OpFunctionParameter: 20: var22: storage class: Function 24: OpLabel: 178: OpVariable: 20: var178: storage class: Function 181: OpVariable: 20: var181: storage class: Function 192: OpVariable: 7: var192: storage class: Function 211: OpVariable: 7: var211: storage class: Function 215: OpVariable: 7: var215: storage class: Function 222: OpVariable: 7: var222: storage class: Function 227: OpVariable: 7: var227: storage class: Function 237: OpVariable: 7: var237: storage class: Function 242: OpVariable: 7: var242: storage class: Function 250: OpVariable: 7: var250: storage class: Function 255: OpVariable: 7: var255: storage class: Function 179: OpLoad: 8: tmp179 << 22 180: OpExtInst(8): 8: tmp180 << 179 OpStore: : 180 >> 178 182: OpLoad: 8: tmp182 << 22 183: OpExtInst(10): 8: tmp183 << 182 OpStore: : 183 >> 181 184: OpLoad: 8: tmp184 << 181 185: OpLoad: 8: tmp185 << 181 186: OpFMul: 8: tmp186 << 184, 185 187: OpLoad: 8: tmp187 << 181 188: OpVectorTimesScalar: 8: tmp188 << 187, 127 189: OpCompositeConstruct: 8: tmp189 << 109, 109, 109 190: OpFSub: 8: tmp190 << 189, 188 191: OpFMul: 8: tmp191 << 186, 190 OpStore: : 191 >> 181 195: OpAccessChain: 7: 178[194] 196: OpLoad: 6: tmp196 << 195 198: OpAccessChain: 7: 178[197] 199: OpLoad: 6: tmp199 << 198 201: OpFMul: 6: tmp201 << 199, 200 202: OpFAdd: 6: tmp202 << 196, 201 205: OpAccessChain: 7: 178[204] 206: OpLoad: 6: tmp206 << 205 207: OpFMul: 6: tmp207 << 203, 206 208: OpFAdd: 6: tmp208 << 202, 207 OpStore: : 208 >> 192 209: OpLoad: 6: tmp209 << 192 210: OpFAdd: 6: tmp210 << 209, 100 OpStore: : 210 >> 211 212: OpFunctionCall: 6: tmp212(211) 213: OpLoad: 6: tmp213 << 192 214: OpFAdd: 6: tmp214 << 213, 106 OpStore: : 214 >> 215 216: OpFunctionCall: 6: tmp216(215) 217: OpAccessChain: 7: 181[194] 218: OpLoad: 6: tmp218 << 217 219: OpExtInst(46): 6: tmp219 << 212, 216, 218 220: OpLoad: 6: tmp220 << 192 221: OpFAdd: 6: tmp221 << 220, 200 OpStore: : 221 >> 222 223: OpFunctionCall: 6: tmp223(222) 224: OpLoad: 6: tmp224 << 192 226: OpFAdd: 6: tmp226 << 224, 225 OpStore: : 226 >> 227 228: OpFunctionCall: 6: tmp228(227) 229: OpAccessChain: 7: 181[194] 230: OpLoad: 6: tmp230 << 229 231: OpExtInst(46): 6: tmp231 << 223, 228, 230 232: OpAccessChain: 7: 181[197] 233: OpLoad: 6: tmp233 << 232 234: OpExtInst(46): 6: tmp234 << 219, 231, 233 235: OpLoad: 6: tmp235 << 192 236: OpFAdd: 6: tmp236 << 235, 203 OpStore: : 236 >> 237 238: OpFunctionCall: 6: tmp238(237) 239: OpLoad: 6: tmp239 << 192 241: OpFAdd: 6: tmp241 << 239, 240 OpStore: : 241 >> 242 243: OpFunctionCall: 6: tmp243(242) 244: OpAccessChain: 7: 181[194] 245: OpLoad: 6: tmp245 << 244 246: OpExtInst(46): 6: tmp246 << 238, 243, 245 247: OpLoad: 6: tmp247 << 192 249: OpFAdd: 6: tmp249 << 247, 248 OpStore: : 249 >> 250 251: OpFunctionCall: 6: tmp251(250) 252: OpLoad: 6: tmp252 << 192 254: OpFAdd: 6: tmp254 << 252, 253 OpStore: : 254 >> 255 256: OpFunctionCall: 6: tmp256(255) 257: OpAccessChain: 7: 181[194] 258: OpLoad: 6: tmp258 << 257 259: OpExtInst(46): 6: tmp259 << 251, 256, 258 260: OpAccessChain: 7: 181[197] 261: OpLoad: 6: tmp261 << 260 262: OpExtInst(46): 6: tmp262 << 246, 259, 261 263: OpAccessChain: 7: 181[204] 264: OpLoad: 6: tmp264 << 263 265: OpExtInst(46): 6: tmp265 << 234, 262, 264 OpReturnValue: : << 265 OpFunctionEnd: 29: OpFunction: func29(type: 27) 28: OpFunctionParameter: 26: var28: storage class: Function 30: OpLabel: 272: OpVariable: 20: var272: storage class: Function 268: OpLoad: 25: tmp268 << 28 269: OpCompositeExtract: 6: tmp269 << 268, 0 270: OpCompositeExtract: 6: tmp270 << 268, 1 271: OpCompositeConstruct: 8: tmp271 << 269, 270, 100 OpStore: : 271 >> 272 273: OpFunctionCall: 6: tmp273(272) OpReturnValue: : << 273 OpFunctionEnd: 32: OpFunction: func32(type: 21) 31: OpFunctionParameter: 20: var31: storage class: Function 33: OpLabel: 276: OpVariable: 20: var276: storage class: Function 277: OpLoad: 8: tmp277 << 31 OpStore: : 277 >> 276 278: OpFunctionCall: 6: tmp278(276) OpReturnValue: : << 278 OpFunctionEnd: 35: OpFunction: func35(type: 21) 34: OpFunctionParameter: 20: var34: storage class: Function 36: OpLabel: 281: OpVariable: 7: var281: storage class: Function 284: OpVariable: 283: var284: storage class: Function 294: OpVariable: 7: var294: storage class: Function 301: OpVariable: 20: var301: storage class: Function OpStore: : 100 >> 281 OpStore: : 285 >> 284 OpBranch: to 286 286: OpLabel: OpLoopMerge: (merge: 288, continue: 289) OpBranch: to 290 290: OpLabel: 291: OpLoad: 282: tmp291 << 284 293: OpSLessThanEqual: 117: tmp293 << 291, 292 OpBranchConditional: if(293) then branch to 287, else branch to 288 287: OpLabel: 295: OpLoad: 282: tmp295 << 284 296: OpConvertSToF: 6: tmp296 << 295 297: OpExtInst(29): 6: tmp297 << 296 OpStore: : 297 >> 294 298: OpLoad: 8: tmp298 << 34 299: OpLoad: 6: tmp299 << 294 300: OpVectorTimesScalar: 8: tmp300 << 298, 299 OpStore: : 300 >> 301 302: OpFunctionCall: 6: tmp302(301) 304: OpFSub: 6: tmp304 << 302, 303 305: OpLoad: 6: tmp305 << 294 306: OpFDiv: 6: tmp306 << 304, 305 307: OpLoad: 6: tmp307 << 281 308: OpFAdd: 6: tmp308 << 307, 306 OpStore: : 308 >> 281 OpBranch: to 289 289: OpLabel: 309: OpLoad: 282: tmp309 << 284 310: OpIAdd: 282: tmp310 << 309, 285 OpStore: : 310 >> 284 OpBranch: to 286 288: OpLabel: 311: OpLoad: 6: tmp311 << 281 OpReturnValue: : << 311 OpFunctionEnd: 40: OpFunction: func40(type: 37) 38: OpFunctionParameter: 7: var38: storage class: Function 39: OpFunctionParameter: 26: var39: storage class: Function 41: OpLabel: 314: OpLoad: 6: tmp314 << 38 315: OpExtInst(14): 6: tmp315 << 314 316: OpAccessChain: 7: 39[194] 317: OpLoad: 6: tmp317 << 316 318: OpFMul: 6: tmp318 << 315, 317 319: OpLoad: 6: tmp319 << 38 320: OpExtInst(13): 6: tmp320 << 319 321: OpAccessChain: 7: 39[197] 322: OpLoad: 6: tmp322 << 321 323: OpFMul: 6: tmp323 << 320, 322 324: OpFAdd: 6: tmp324 << 318, 323 325: OpLoad: 6: tmp325 << 38 326: OpExtInst(14): 6: tmp326 << 325 327: OpAccessChain: 7: 39[197] 328: OpLoad: 6: tmp328 << 327 329: OpFMul: 6: tmp329 << 326, 328 330: OpLoad: 6: tmp330 << 38 331: OpExtInst(13): 6: tmp331 << 330 332: OpAccessChain: 7: 39[194] 333: OpLoad: 6: tmp333 << 332 334: OpFMul: 6: tmp334 << 331, 333 335: OpFSub: 6: tmp335 << 329, 334 336: OpCompositeConstruct: 25: tmp336 << 324, 335 OpReturnValue: : << 336 OpFunctionEnd: 43: OpFunction: func43(type: 27) 42: OpFunctionParameter: 26: var42: storage class: Function 44: OpLabel: 344: OpVariable: 26: var344: storage class: Function 345: OpVariable: 7: var345: storage class: Function 365: OpVariable: 7: var365: storage class: Function 339: OpLoad: 25: tmp339 << 42 343: OpExtInst(43): 25: tmp343 << 339, 341, 342 OpStore: : 343 >> 42 OpStore: : 101 >> 344 346: OpAccessChain: 7: 42[194] 347: OpLoad: 6: tmp347 << 346 348: OpExtInst(4): 6: tmp348 << 347 350: OpExtInst(26): 6: tmp350 << 348, 349 351: OpFSub: 6: tmp351 << 106, 350 352: OpAccessChain: 7: 42[197] 353: OpLoad: 6: tmp353 << 352 354: OpAccessChain: 7: 344[197] 355: OpLoad: 6: tmp355 << 354 356: OpFAdd: 6: tmp356 << 353, 355 357: OpExtInst(4): 6: tmp357 << 356 358: OpExtInst(26): 6: tmp358 << 357, 349 359: OpFSub: 6: tmp359 << 106, 358 360: OpFMul: 6: tmp360 << 351, 359 362: OpFMul: 6: tmp362 << 360, 361 363: OpExtInst(26): 6: tmp363 << 362, 303 364: OpFSub: 6: tmp364 << 106, 363 OpStore: : 364 >> 345 366: OpAccessChain: 7: 42[194] 367: OpLoad: 6: tmp367 << 366 368: OpExtInst(4): 6: tmp368 << 367 369: OpExtInst(26): 6: tmp369 << 368, 349 370: OpFSub: 6: tmp370 << 106, 369 371: OpAccessChain: 7: 42[197] 372: OpLoad: 6: tmp372 << 371 373: OpExtInst(4): 6: tmp373 << 372 374: OpExtInst(26): 6: tmp374 << 373, 349 375: OpFSub: 6: tmp375 << 106, 374 376: OpFMul: 6: tmp376 << 370, 375 378: OpExtInst(26): 6: tmp378 << 376, 377 OpStore: : 378 >> 365 379: OpLoad: 6: tmp379 << 345 380: OpLoad: 6: tmp380 << 365 381: OpFMul: 6: tmp381 << 379, 380 382: OpFMul: 6: tmp382 << 381, 109 OpReturnValue: : << 382 OpFunctionEnd: 48: OpFunction: func48(type: 45) 46: OpFunctionParameter: 26: var46: storage class: Function 47: OpFunctionParameter: 7: var47: storage class: Function 49: OpLabel: 385: OpVariable: 26: var385: storage class: Function 388: OpVariable: 26: var388: storage class: Function 393: OpVariable: 26: var393: storage class: Function 396: OpVariable: 7: var396: storage class: Function 404: OpVariable: 26: var404: storage class: Function 418: OpVariable: 26: var418: storage class: Function 419: OpVariable: 26: var419: storage class: Function 426: OpVariable: 26: var426: storage class: Function 431: OpVariable: 7: var431: storage class: Function 445: OpVariable: 7: var445: storage class: Function 447: OpVariable: 26: var447: storage class: Function 449: OpVariable: 26: var449: storage class: Function 453: OpVariable: 26: var453: storage class: Function 386: OpLoad: 25: tmp386 << 46 387: OpVectorTimesScalar: 25: tmp387 << 386, 349 OpStore: : 387 >> 385 389: OpLoad: 25: tmp389 << 385 390: OpExtInst(10): 25: tmp390 << 389 392: OpFSub: 25: tmp392 << 390, 391 OpStore: : 392 >> 388 394: OpLoad: 25: tmp394 << 385 395: OpExtInst(8): 25: tmp395 << 394 OpStore: : 395 >> 393 397: OpAccessChain: 7: 393[194] 398: OpLoad: 6: tmp398 << 397 399: OpAccessChain: 7: 393[197] 400: OpLoad: 6: tmp400 << 399 402: OpFMul: 6: tmp402 << 400, 401 403: OpFAdd: 6: tmp403 << 398, 402 OpStore: : 403 >> 396 405: OpAccessChain: 7: 393[197] 406: OpLoad: 6: tmp406 << 405 408: OpFMul: 6: tmp408 << 406, 407 409: OpExtInst(14): 6: tmp409 << 408 410: OpAccessChain: 7: 393[194] 411: OpLoad: 6: tmp411 << 410 413: OpFMul: 6: tmp413 << 411, 412 414: OpExtInst(13): 6: tmp414 << 413 415: OpCompositeConstruct: 25: tmp415 << 409, 414 417: OpVectorTimesScalar: 25: tmp417 << 415, 416 OpStore: : 417 >> 404 420: OpLoad: 25: tmp420 << 393 OpStore: : 420 >> 419 421: OpFunctionCall: 6: tmp421(419) 422: OpLoad: 25: tmp422 << 393 425: OpFAdd: 25: tmp425 << 422, 424 OpStore: : 425 >> 426 427: OpFunctionCall: 6: tmp427(426) 428: OpCompositeConstruct: 25: tmp428 << 421, 427 429: OpCompositeConstruct: 25: tmp429 << 106, 106 430: OpFAdd: 25: tmp430 << 429, 428 OpStore: : 430 >> 418 432: OpLoad: 6: tmp432 << 47 433: OpFSub: 6: tmp433 << 106, 432 434: OpExtInst(26): 6: tmp434 << 433, 377 436: OpExtInst(46): 6: tmp436 << 106, 434, 435 438: OpFMul: 6: tmp438 << 436, 437 OpStore: : 438 >> 431 439: OpLoad: 25: tmp439 << 388 440: OpLoad: 25: tmp440 << 418 441: OpFMul: 25: tmp441 << 439, 440 442: OpVectorTimesScalar: 25: tmp442 << 441, 377 443: OpLoad: 25: tmp443 << 404 444: OpFAdd: 25: tmp444 << 442, 443 446: OpLoad: 6: tmp446 << 396 OpStore: : 446 >> 445 OpStore: : 444 >> 447 448: OpFunctionCall: 25: tmp448(445, 447) OpStore: : 448 >> 449 450: OpFunctionCall: 6: tmp450(449) 451: OpLoad: 25: tmp451 << 385 452: OpVectorTimesScalar: 25: tmp452 << 451, 401 OpStore: : 452 >> 453 454: OpFunctionCall: 6: tmp454(453) 455: OpFSub: 6: tmp455 << 454, 303 456: OpExtInst(40): 6: tmp456 << 100, 455 457: OpFMul: 6: tmp457 << 450, 456 458: OpLoad: 6: tmp458 << 431 459: OpFMul: 6: tmp459 << 457, 458 OpReturnValue: : << 459 OpFunctionEnd: 52: OpFunction: func52(type: 50) 51: OpFunctionParameter: 20: var51: storage class: Function 53: OpLabel: 463: OpVariable: 7: var463: storage class: Function 462: OpLoad: 8: tmp462 << 51 464: OpLoad: 6: tmp464 << 104 OpStore: : 464 >> 463 465: OpFunctionCall: 8: tmp465(463) 466: OpExtInst(26): 8: tmp466 << 462, 465 OpReturnValue: : << 466 OpFunctionEnd: 56: OpFunction: func56(type: 45) 54: OpFunctionParameter: 26: var54: storage class: Function 55: OpFunctionParameter: 7: var55: storage class: Function 57: OpLabel: 469: OpVariable: 7: var469: storage class: Function 470: OpVariable: 283: var470: storage class: Function 493: OpVariable: 26: var493: storage class: Function 494: OpVariable: 7: var494: storage class: Function OpStore: : 100 >> 469 OpStore: : 471 >> 470 OpBranch: to 472 472: OpLabel: OpLoopMerge: (merge: 474, continue: 475) OpBranch: to 476 476: OpLabel: 477: OpLoad: 282: tmp477 << 470 479: OpSLessThan: 117: tmp479 << 477, 478 OpBranchConditional: if(479) then branch to 473, else branch to 474 473: OpLabel: 480: OpLoad: 25: tmp480 << 54 481: OpLoad: 282: tmp481 << 470 482: OpConvertSToF: 6: tmp482 << 481 484: OpFMul: 6: tmp484 << 482, 483 485: OpCompositeConstruct: 25: tmp485 << 484, 484 486: OpFAdd: 25: tmp486 << 480, 485 487: OpLoad: 282: tmp487 << 470 488: OpConvertSToF: 6: tmp488 << 487 490: OpFMul: 6: tmp490 << 488, 489 491: OpFAdd: 6: tmp491 << 106, 490 492: OpVectorTimesScalar: 25: tmp492 << 486, 491 OpStore: : 492 >> 493 495: OpLoad: 6: tmp495 << 55 OpStore: : 495 >> 494 496: OpFunctionCall: 6: tmp496(493, 494) 497: OpLoad: 282: tmp497 << 470 498: OpConvertSToF: 6: tmp498 << 497 499: OpFDiv: 6: tmp499 << 498, 377 500: OpFSub: 6: tmp500 << 106, 499 501: OpExtInst(26): 6: tmp501 << 500, 377 502: OpFMul: 6: tmp502 << 496, 501 503: OpLoad: 6: tmp503 << 469 504: OpFAdd: 6: tmp504 << 503, 502 OpStore: : 504 >> 469 OpBranch: to 475 475: OpLabel: 505: OpLoad: 282: tmp505 << 470 506: OpIAdd: 282: tmp506 << 505, 285 OpStore: : 506 >> 470 OpBranch: to 472 474: OpLabel: 507: OpLoad: 6: tmp507 << 469 OpReturnValue: : << 507 OpFunctionEnd: 60: OpFunction: func60(type: 45) 58: OpFunctionParameter: 26: var58: storage class: Function 59: OpFunctionParameter: 7: var59: storage class: Function 61: OpLabel: 513: OpVariable: 26: var513: storage class: Function 514: OpVariable: 7: var514: storage class: Function 519: OpVariable: 26: var519: storage class: Function 520: OpVariable: 7: var520: storage class: Function 510: OpLoad: 25: tmp510 << 58 512: OpVectorTimesScalar: 25: tmp512 << 510, 511 OpStore: : 512 >> 513 515: OpLoad: 6: tmp515 << 59 OpStore: : 515 >> 514 516: OpFunctionCall: 6: tmp516(513, 514) 517: OpLoad: 25: tmp517 << 58 518: OpVectorTimesScalar: 25: tmp518 << 517, 127 OpStore: : 518 >> 519 521: OpLoad: 6: tmp521 << 59 OpStore: : 521 >> 520 522: OpFunctionCall: 6: tmp522(519, 520) 524: OpFMul: 6: tmp524 << 522, 523 525: OpFAdd: 6: tmp525 << 516, 524 OpReturnValue: : << 525 OpFunctionEnd: 66: OpFunction: func66(type: 62) 63: OpFunctionParameter: 20: var63: storage class: Function 64: OpFunctionParameter: 20: var64: storage class: Function 65: OpFunctionParameter: 20: var65: storage class: Function 67: OpLabel: 528: OpVariable: 7: var528: storage class: Function 533: OpVariable: 7: var533: storage class: Function 544: OpVariable: 26: var544: storage class: Function 545: OpVariable: 7: var545: storage class: Function 548: OpVariable: 7: var548: storage class: Function 549: OpVariable: 26: var549: storage class: Function 552: OpVariable: 7: var552: storage class: Function 555: OpVariable: 7: var555: storage class: Function 562: OpVariable: 7: var562: storage class: Function 568: OpVariable: 20: var568: storage class: Function 570: OpVariable: 7: var570: storage class: Function 591: OpVariable: 20: var591: storage class: Function 529: OpLoad: 8: tmp529 << 63 530: OpLoad: 8: tmp530 << 65 531: OpFNegate: 8: tmp531 << 530 532: OpDot: 6: tmp532 << 529, 531 OpStore: : 532 >> 528 534: OpAccessChain: 7: 63[204] 535: OpLoad: 6: tmp535 << 534 536: OpAccessChain: 7: 63[194] 537: OpLoad: 6: tmp537 << 536 538: OpExtInst(25): 6: tmp538 << 535, 537 539: OpAccessChain: 7: 63[197] 540: OpLoad: 6: tmp540 << 539 541: OpExtInst(16): 6: tmp541 << 540 542: OpCompositeConstruct: 25: tmp542 << 538, 541 543: OpVectorTimesScalar: 25: tmp543 << 542, 511 OpStore: : 543 >> 544 546: OpLoad: 6: tmp546 << 528 OpStore: : 546 >> 545 547: OpFunctionCall: 6: tmp547(544, 545) OpStore: : 547 >> 533 550: OpLoad: 8: tmp550 << 64 551: OpVectorShuffle: 25: tmp551 << 550, 550, 0, 2 OpStore: : 551 >> 549 553: OpLoad: 6: tmp553 << 528 OpStore: : 553 >> 552 554: OpFunctionCall: 6: tmp554(549, 552) OpStore: : 554 >> 548 556: OpLoad: 6: tmp556 << 533 557: OpLoad: 6: tmp557 << 548 558: OpAccessChain: 7: 63[197] 559: OpLoad: 6: tmp559 << 558 560: OpExtInst(49): 6: tmp560 << 523, 303, 559 561: OpExtInst(46): 6: tmp561 << 556, 557, 560 OpStore: : 561 >> 555 563: OpAccessChain: 7: 63[197] 564: OpLoad: 6: tmp564 << 563 565: OpFSub: 6: tmp565 << 564, 523 566: OpFMul: 6: tmp566 << 565, 401 567: OpExtInst(43): 6: tmp567 << 566, 100, 106 OpStore: : 567 >> 562 571: OpLoad: 6: tmp571 << 104 OpStore: : 571 >> 570 572: OpFunctionCall: 8: tmp572(570) 574: OpCompositeConstruct: 8: tmp574 << 573, 573, 573 575: OpExtInst(46): 8: tmp575 << 569, 572, 574 577: OpAccessChain: 102: 99[194] 578: OpLoad: 6: tmp578 << 577 579: OpExtInst(4): 6: tmp579 << 578 580: OpFSub: 6: tmp580 << 106, 579 581: OpFMul: 6: tmp581 << 580, 303 582: OpExtInst(26): 6: tmp582 << 581, 489 583: OpFAdd: 6: tmp583 << 576, 582 584: OpVectorTimesScalar: 8: tmp584 << 575, 583 586: OpLoad: 6: tmp586 << 555 587: OpLoad: 6: tmp587 << 562 588: OpFMul: 6: tmp588 << 586, 587 589: OpCompositeConstruct: 8: tmp589 << 588, 588, 588 590: OpExtInst(46): 8: tmp590 << 584, 585, 589 OpStore: : 590 >> 591 592: OpFunctionCall: 8: tmp592(591) OpStore: : 592 >> 568 594: OpLoad: 6: tmp594 << 528 595: OpFSub: 6: tmp595 << 593, 594 596: OpLoad: 8: tmp596 << 568 597: OpVectorTimesScalar: 8: tmp597 << 596, 595 OpStore: : 597 >> 568 598: OpLoad: 6: tmp598 << 528 599: OpFSub: 6: tmp599 << 106, 598 600: OpExtInst(26): 6: tmp600 << 599, 349 601: OpCompositeConstruct: 8: tmp601 << 600, 600, 600 603: OpVectorTimesScalar: 8: tmp603 << 601, 602 604: OpLoad: 8: tmp604 << 568 605: OpFAdd: 8: tmp605 << 604, 603 OpStore: : 605 >> 568 606: OpLoad: 8: tmp606 << 568 OpReturnValue: : << 606 OpFunctionEnd: 69: OpFunction: func69(type: 21) 68: OpFunctionParameter: 20: var68: storage class: Function 70: OpLabel: 614: OpVariable: 20: var614: storage class: Function 631: OpVariable: 7: var631: storage class: Function 635: OpVariable: 20: var635: storage class: Function 643: OpVariable: 20: var643: storage class: Function 685: OpVariable: 7: var685: storage class: Function 690: OpVariable: 7: var690: storage class: Function 694: OpVariable: 7: var694: storage class: Function 610: OpAccessChain: 7: 68[197] 611: OpLoad: 6: tmp611 << 610 612: OpFMul: 6: tmp612 << 611, 609 613: OpAccessChain: 7: 68[197] OpStore: : 612 >> 613 615: OpLoad: 8: tmp615 << 68 616: OpCompositeConstruct: 8: tmp616 << 109, 109, 109 617: OpFDiv: 8: tmp617 << 615, 616 618: OpExtInst(8): 8: tmp618 << 617 OpStore: : 618 >> 614 619: OpAccessChain: 7: 614[194] 620: OpLoad: 6: tmp620 << 619 622: OpFMul: 6: tmp622 << 620, 621 623: OpAccessChain: 7: 614[204] 624: OpLoad: 6: tmp624 << 623 626: OpFMul: 6: tmp626 << 624, 625 627: OpFSub: 6: tmp627 << 622, 626 628: OpExtInst(14): 6: tmp628 << 627 629: OpFAdd: 6: tmp629 << 628, 576 630: OpExtInst(48): 6: tmp630 << 100, 629 OpStore: : 630 >> 107 632: OpLoad: 8: tmp632 << 68 634: OpVectorTimesScalar: 8: tmp634 << 632, 633 OpStore: : 634 >> 635 636: OpFunctionCall: 6: tmp636(635) 638: OpFMul: 6: tmp638 << 636, 637 639: OpLoad: 6: tmp639 << 107 640: OpFMul: 6: tmp640 << 638, 639 641: OpLoad: 8: tmp641 << 68 642: OpVectorTimesScalar: 8: tmp642 << 641, 401 OpStore: : 642 >> 643 644: OpFunctionCall: 6: tmp644(643) 645: OpExtInst(40): 6: tmp645 << 100, 644 646: OpExtInst(26): 6: tmp646 << 645, 401 648: OpLoad: 6: tmp648 << 107 649: OpFSub: 6: tmp649 << 106, 648 650: OpFMul: 6: tmp650 << 647, 649 651: OpFAdd: 6: tmp651 << 602, 650 652: OpFMul: 6: tmp652 << 646, 651 653: OpFSub: 6: tmp653 << 640, 652 OpStore: : 653 >> 631 654: OpAccessChain: 7: 614[194] 655: OpLoad: 6: tmp655 << 654 656: OpAccessChain: 7: 614[204] 657: OpLoad: 6: tmp657 << 656 658: OpExtInst(13): 6: tmp658 << 657 659: OpFMul: 6: tmp659 << 658, 109 660: OpFAdd: 6: tmp660 << 655, 659 661: OpFMod: 6: tmp661 << 660, 377 OpStore: : 661 >> 104 662: OpLoad: 8: tmp662 << 68 663: OpVectorShuffle: 25: tmp663 << 662, 662, 0, 2 665: OpFMod: 25: tmp665 << 663, 664 668: OpFSub: 25: tmp668 << 665, 667 669: OpLoad: 8: tmp669 << 68 670: OpVectorShuffle: 8: tmp670 << 669, 668, 3, 1, 4 OpStore: : 670 >> 68 672: OpAccessChain: 7: 614[204] 673: OpLoad: 6: tmp673 << 672 675: OpFMul: 6: tmp675 << 673, 674 676: OpAccessChain: 7: 614[194] 677: OpLoad: 6: tmp677 << 676 679: OpFMul: 6: tmp679 << 677, 678 680: OpFAdd: 6: tmp680 << 675, 679 681: OpExtInst(14): 6: tmp681 << 680 682: OpFMul: 6: tmp682 << 303, 681 683: OpFAdd: 6: tmp683 << 303, 682 684: OpExtInst(46): 6: tmp684 << 671, 106, 683 OpStore: : 684 >> 105 686: OpLoad: 8: tmp686 << 68 687: OpExtInst(66): 6: tmp687 << 686 688: OpLoad: 6: tmp688 << 105 689: OpFSub: 6: tmp689 << 687, 688 OpStore: : 689 >> 685 691: OpAccessChain: 7: 68[197] 692: OpLoad: 6: tmp692 << 691 693: OpFNegate: 6: tmp693 << 692 OpStore: : 693 >> 690 695: OpLoad: 6: tmp695 << 685 696: OpExtInst(40): 6: tmp696 << 100, 695 697: OpLoad: 6: tmp697 << 690 698: OpExtInst(40): 6: tmp698 << 100, 697 699: OpCompositeConstruct: 25: tmp699 << 696, 698 700: OpExtInst(66): 6: tmp700 << 699 701: OpFSub: 6: tmp701 << 700, 576 702: OpLoad: 6: tmp702 << 631 703: OpFAdd: 6: tmp703 << 701, 702 705: OpFMul: 6: tmp705 << 703, 704 OpStore: : 705 >> 694 706: OpLoad: 6: tmp706 << 694 OpReturnValue: : << 706 OpFunctionEnd: 73: OpFunction: func73(type: 71) 72: OpFunctionParameter: 26: var72: storage class: Function 74: OpLabel: 713: OpVariable: 7: var713: storage class: Function 715: OpVariable: 7: var715: storage class: Function 716: OpVariable: 26: var716: storage class: Function 719: OpVariable: 26: var719: storage class: Function 724: OpVariable: 26: var724: storage class: Function 734: OpVariable: 20: var734: storage class: Function 740: OpVariable: 20: var740: storage class: Function 747: OpVariable: 20: var747: storage class: Function 767: OpVariable: 20: var767: storage class: Function 779: OpVariable: 20: var779: storage class: Function 790: OpVariable: 20: var790: storage class: Function 796: OpVariable: 20: var796: storage class: Function 800: OpVariable: 7: var800: storage class: Function 814: OpVariable: 7: var814: storage class: Function 709: OpAccessChain: 7: 72[194] 710: OpLoad: 6: tmp710 << 709 711: OpFAdd: 6: tmp711 << 710, 127 712: OpAccessChain: 7: 72[194] OpStore: : 711 >> 712 OpStore: : 714 >> 713 OpStore: : 714 >> 715 717: OpLoad: 25: tmp717 << 72 718: OpExtInst(8): 25: tmp718 << 717 OpStore: : 718 >> 716 720: OpLoad: 25: tmp720 << 72 721: OpLoad: 25: tmp721 << 716 722: OpFSub: 25: tmp722 << 720, 721 723: OpFSub: 25: tmp723 << 722, 391 OpStore: : 723 >> 719 725: OpAccessChain: 7: 719[194] 726: OpLoad: 6: tmp726 << 725 727: OpVectorTimesScalar: 25: tmp727 << 342, 726 728: OpAccessChain: 7: 719[197] 729: OpLoad: 6: tmp729 << 728 731: OpVectorTimesScalar: 25: tmp731 << 730, 729 732: OpFAdd: 25: tmp732 << 727, 731 733: OpVectorTimesScalar: 25: tmp733 << 732, 704 OpStore: : 733 >> 724 736: OpLoad: 25: tmp736 << 72 737: OpCompositeExtract: 6: tmp737 << 736, 0 738: OpCompositeExtract: 6: tmp738 << 736, 1 739: OpCompositeConstruct: 8: tmp739 << 737, 738, 100 OpStore: : 739 >> 740 741: OpFunctionCall: 6: tmp741(740) 742: OpFMul: 6: tmp742 << 741, 303 743: OpExtInst(40): 6: tmp743 << 100, 742 744: OpCompositeConstruct: 8: tmp744 << 743, 743, 743 745: OpCompositeConstruct: 8: tmp745 << 511, 511, 511 746: OpExtInst(46): 8: tmp746 << 735, 744, 745 OpStore: : 746 >> 734 753: OpLoad: 25: tmp753 << 716 754: OpVectorTimesScalar: 25: tmp754 << 753, 127 755: OpLoad: 25: tmp755 << 72 756: OpVectorTimesScalar: 25: tmp756 << 755, 106 757: OpFAdd: 25: tmp757 << 754, 756 758: OpLoad: 25: tmp758 << 72 759: OpVectorShuffle: 25: tmp759 << 758, 758, 1, 0 760: OpVectorTimesScalar: 25: tmp760 << 759, 127 761: OpExtInst(14): 25: tmp761 << 760 762: OpVectorTimesScalar: 25: tmp762 << 761, 748 763: OpFAdd: 25: tmp763 << 757, 762 764: OpCompositeExtract: 6: tmp764 << 763, 0 765: OpCompositeExtract: 6: tmp765 << 763, 1 766: OpCompositeConstruct: 8: tmp766 << 764, 765, 100 OpStore: : 766 >> 767 768: OpFunctionCall: 6: tmp768(767) 769: OpFAdd: 6: tmp769 << 303, 768 770: OpExtInst(49): 6: tmp770 << 748, 151, 769 771: OpFSub: 6: tmp771 << 106, 770 772: OpCompositeConstruct: 8: tmp772 << 771, 771, 771 773: OpExtInst(46): 8: tmp773 << 750, 752, 772 774: OpLoad: 25: tmp774 << 72 775: OpVectorTimesScalar: 25: tmp775 << 774, 671 776: OpCompositeExtract: 6: tmp776 << 775, 0 777: OpCompositeExtract: 6: tmp777 << 775, 1 778: OpCompositeConstruct: 8: tmp778 << 776, 777, 100 OpStore: : 778 >> 779 780: OpFunctionCall: 6: tmp780(779) 781: OpFMul: 6: tmp781 << 780, 106 782: OpExtInst(40): 6: tmp782 << 100, 781 783: OpCompositeConstruct: 8: tmp783 << 782, 782, 782 784: OpFAdd: 8: tmp784 << 773, 783 785: OpLoad: 25: tmp785 << 72 786: OpFNegate: 25: tmp786 << 785 787: OpCompositeExtract: 6: tmp787 << 786, 0 788: OpCompositeExtract: 6: tmp788 << 786, 1 789: OpCompositeConstruct: 8: tmp789 << 787, 788, 100 OpStore: : 789 >> 790 791: OpFunctionCall: 6: tmp791(790) 792: OpExtInst(49): 6: tmp792 << 489, 523, 791 793: OpCompositeConstruct: 8: tmp793 << 792, 792, 792 794: OpVectorTimesScalar: 8: tmp794 << 793, 489 795: OpFAdd: 8: tmp795 << 784, 794 OpStore: : 795 >> 747 797: OpLoad: 8: tmp797 << 747 798: OpCompositeConstruct: 8: tmp798 << 303, 303, 303 799: OpExtInst(46): 8: tmp799 << 797, 735, 798 OpStore: : 799 >> 796 801: OpLoad: 6: tmp801 << 713 802: OpFSub: 6: tmp802 << 303, 801 803: OpAccessChain: 7: 719[197] 804: OpLoad: 6: tmp804 << 803 805: OpExtInst(4): 6: tmp805 << 804 806: OpExtInst(49): 6: tmp806 << 802, 303, 805 807: OpLoad: 6: tmp807 << 713 808: OpFSub: 6: tmp808 << 303, 807 809: OpAccessChain: 7: 719[194] 810: OpLoad: 6: tmp810 << 809 811: OpExtInst(4): 6: tmp811 << 810 812: OpExtInst(49): 6: tmp812 << 808, 303, 811 813: OpExtInst(40): 6: tmp813 << 806, 812 OpStore: : 813 >> 800 815: OpLoad: 6: tmp815 << 715 816: OpFSub: 6: tmp816 << 303, 815 817: OpAccessChain: 7: 724[197] 818: OpLoad: 6: tmp818 << 817 819: OpExtInst(4): 6: tmp819 << 818 820: OpExtInst(49): 6: tmp820 << 816, 303, 819 821: OpLoad: 6: tmp821 << 715 822: OpFSub: 6: tmp822 << 303, 821 823: OpAccessChain: 7: 724[194] 824: OpLoad: 6: tmp824 << 823 825: OpExtInst(4): 6: tmp825 << 824 826: OpExtInst(49): 6: tmp826 << 822, 303, 825 827: OpExtInst(40): 6: tmp827 << 820, 826 OpStore: : 827 >> 814 828: OpLoad: 8: tmp828 << 747 829: OpLoad: 8: tmp829 << 796 830: OpLoad: 8: tmp830 << 734 831: OpLoad: 6: tmp831 << 814 832: OpCompositeConstruct: 8: tmp832 << 831, 831, 831 833: OpExtInst(46): 8: tmp833 << 829, 830, 832 834: OpLoad: 6: tmp834 << 814 835: OpLoad: 6: tmp835 << 800 836: OpExtInst(40): 6: tmp836 << 834, 835 837: OpCompositeConstruct: 8: tmp837 << 836, 836, 836 838: OpExtInst(46): 8: tmp838 << 828, 833, 837 839: OpVectorTimesScalar: 8: tmp839 << 838, 151 OpReturnValue: : << 839 OpFunctionEnd: 76: OpFunction: func76(type: 9) 75: OpFunctionParameter: 7: var75: storage class: Function 77: OpLabel: 842: OpLoad: 6: tmp842 << 75 843: OpFMul: 6: tmp843 << 842, 704 845: OpLoad: 6: tmp845 << 75 846: OpFMul: 6: tmp846 << 845, 377 847: OpExtInst(14): 6: tmp847 << 846 849: OpFMul: 6: tmp849 << 847, 848 850: OpFAdd: 6: tmp850 << 844, 849 851: OpCompositeConstruct: 8: tmp851 << 843, 850, 100 OpReturnValue: : << 851 OpFunctionEnd: 79: OpFunction: func79(type: 9) 78: OpFunctionParameter: 7: var78: storage class: Function 80: OpLabel: 854: OpVariable: 20: var854: storage class: Function 858: OpVariable: 7: var858: storage class: Function 855: OpLoad: 6: tmp855 << 78 856: OpLoad: 6: tmp856 << 108 857: OpFMul: 6: tmp857 << 855, 856 OpStore: : 857 >> 858 859: OpFunctionCall: 8: tmp859(858) 861: OpFMul: 8: tmp861 << 859, 860 862: OpLoad: 6: tmp862 << 78 864: OpFMul: 6: tmp864 << 862, 863 865: OpExtInst(14): 6: tmp865 << 864 866: OpFMul: 6: tmp866 << 865, 377 868: OpLoad: 6: tmp868 << 78 870: OpFMul: 6: tmp870 << 868, 869 871: OpExtInst(14): 6: tmp871 << 870 872: OpFMul: 6: tmp872 << 871, 109 873: OpFAdd: 6: tmp873 << 867, 872 874: OpCompositeConstruct: 8: tmp874 << 866, 100, 873 875: OpFAdd: 8: tmp875 << 861, 874 OpStore: : 875 >> 854 876: OpLoad: 8: tmp876 << 854 877: OpVectorShuffle: 25: tmp877 << 876, 876, 0, 2 878: OpCompositeConstruct: 25: tmp878 << 109, 109 879: OpFDiv: 25: tmp879 << 877, 878 880: OpExtInst(8): 25: tmp880 << 879 881: OpVectorTimesScalar: 25: tmp881 << 880, 109 882: OpFAdd: 25: tmp882 << 881, 667 883: OpLoad: 8: tmp883 << 854 884: OpVectorShuffle: 8: tmp884 << 883, 882, 3, 1, 4 OpStore: : 884 >> 854 885: OpLoad: 8: tmp885 << 854 OpReturnValue: : << 885 OpFunctionEnd: 82: OpFunction: func82(type: 16) 81: OpFunctionParameter: 7: var81: storage class: Function 83: OpLabel: 889: OpLoad: 6: tmp889 << 81 890: OpFMul: 6: tmp890 << 889, 633 891: OpExtInst(14): 6: tmp891 << 890 892: OpFMul: 6: tmp892 << 303, 891 893: OpFAdd: 6: tmp893 << 303, 892 894: OpExtInst(46): 6: tmp894 << 109, 888, 893 896: OpFMul: 6: tmp896 << 894, 895 OpReturnValue: : << 896 OpFunctionEnd: 89: OpFunction: func89(type: 84) 85: OpFunctionParameter: 20: var85: storage class: Function 86: OpFunctionParameter: 20: var86: storage class: Function 87: OpFunctionParameter: 7: var87: storage class: Function 88: OpFunctionParameter: 7: var88: storage class: Function 90: OpLabel: 899: OpVariable: 283: var899: storage class: Function 908: OpVariable: 7: var908: storage class: Function 914: OpVariable: 20: var914: storage class: Function 938: OpVariable: 20: var938: storage class: Function 944: OpVariable: 20: var944: storage class: Function 947: OpVariable: 7: var947: storage class: Function 948: OpVariable: 7: var948: storage class: Function 949: OpVariable: 20: var949: storage class: Function 952: OpVariable: 20: var952: storage class: Function 957: OpVariable: 20: var957: storage class: Function 965: OpVariable: 20: var965: storage class: Function 973: OpVariable: 20: var973: storage class: Function 979: OpVariable: 20: var979: storage class: Function 981: OpVariable: 20: var981: storage class: Function 998: OpVariable: 7: var998: storage class: Function 1011: OpVariable: 20: var1011: storage class: Function 1028: OpVariable: 20: var1028: storage class: Function 1079: OpVariable: 20: var1079: storage class: Function 1081: OpVariable: 20: var1081: storage class: Function 1083: OpVariable: 20: var1083: storage class: Function OpStore: : 471 >> 899 OpBranch: to 900 900: OpLabel: OpLoopMerge: (merge: 902, continue: 903) OpBranch: to 904 904: OpLabel: 905: OpLoad: 282: tmp905 << 899 907: OpSLessThan: 117: tmp907 << 905, 906 OpBranchConditional: if(907) then branch to 901, else branch to 902 901: OpLabel: 909: OpLoad: 8: tmp909 << 85 910: OpLoad: 8: tmp910 << 86 911: OpLoad: 6: tmp911 << 87 912: OpVectorTimesScalar: 8: tmp912 << 910, 911 913: OpFAdd: 8: tmp913 << 909, 912 OpStore: : 913 >> 914 915: OpFunctionCall: 6: tmp915(914) OpStore: : 915 >> 908 916: OpLoad: 6: tmp916 << 87 917: OpLoad: 6: tmp917 << 88 918: OpFOrdGreaterThan: 117: tmp918 << 916, 917 OpSelectionMerge: (merge: 920) OpBranchConditional: if(918) then branch to 919, else branch to 920 919: OpLabel: OpReturnValue: : << 921 920: OpLabel: 923: OpLoad: 6: tmp923 << 908 924: OpExtInst(4): 6: tmp924 << 923 926: OpFOrdLessThan: 117: tmp926 << 924, 925 OpSelectionMerge: (merge: 928) OpBranchConditional: if(926) then branch to 927, else branch to 928 927: OpLabel: OpBranch: to 902 928: OpLabel: 930: OpLoad: 6: tmp930 << 88 931: OpFAdd: 6: tmp931 << 930, 637 932: OpLoad: 6: tmp932 << 87 933: OpLoad: 6: tmp933 << 908 934: OpFAdd: 6: tmp934 << 932, 933 935: OpExtInst(37): 6: tmp935 << 931, 934 OpStore: : 935 >> 87 OpBranch: to 903 903: OpLabel: 936: OpLoad: 282: tmp936 << 899 937: OpIAdd: 282: tmp937 << 936, 285 OpStore: : 937 >> 899 OpBranch: to 900 902: OpLabel: 939: OpLoad: 8: tmp939 << 85 940: OpLoad: 8: tmp940 << 86 941: OpLoad: 6: tmp941 << 87 942: OpVectorTimesScalar: 8: tmp942 << 940, 941 943: OpFAdd: 8: tmp943 << 939, 942 OpStore: : 943 >> 938 OpStore: : 946 >> 944 OpStore: : 637 >> 947 950: OpLoad: 8: tmp950 << 938 OpStore: : 950 >> 949 951: OpFunctionCall: 6: tmp951(949) OpStore: : 951 >> 948 953: OpLoad: 8: tmp953 << 938 954: OpLoad: 6: tmp954 << 947 955: OpCompositeConstruct: 8: tmp955 << 954, 100, 100 956: OpFAdd: 8: tmp956 << 953, 955 OpStore: : 956 >> 957 958: OpFunctionCall: 6: tmp958(957) 959: OpLoad: 6: tmp959 << 948 960: OpFSub: 6: tmp960 << 958, 959 961: OpLoad: 8: tmp961 << 938 962: OpLoad: 6: tmp962 << 947 963: OpCompositeConstruct: 8: tmp963 << 100, 962, 100 964: OpFAdd: 8: tmp964 << 961, 963 OpStore: : 964 >> 965 966: OpFunctionCall: 6: tmp966(965) 967: OpLoad: 6: tmp967 << 948 968: OpFSub: 6: tmp968 << 966, 967 969: OpLoad: 8: tmp969 << 938 970: OpLoad: 6: tmp970 << 947 971: OpCompositeConstruct: 8: tmp971 << 100, 100, 970 972: OpFAdd: 8: tmp972 << 969, 971 OpStore: : 972 >> 973 974: OpFunctionCall: 6: tmp974(973) 975: OpLoad: 6: tmp975 << 948 976: OpFSub: 6: tmp976 << 974, 975 977: OpCompositeConstruct: 8: tmp977 << 960, 968, 976 978: OpExtInst(69): 8: tmp978 << 977 OpStore: : 978 >> 952 980: OpLoad: 8: tmp980 << 86 OpStore: : 980 >> 979 982: OpLoad: 8: tmp982 << 111 983: OpLoad: 8: tmp983 << 86 984: OpFSub: 8: tmp984 << 982, 983 985: OpExtInst(69): 8: tmp985 << 984 OpStore: : 985 >> 981 986: OpLoad: 6: tmp986 << 107 987: OpFOrdLessThan: 117: tmp987 << 986, 303 OpSelectionMerge: (merge: 989) OpBranchConditional: if(987) then branch to 988, else branch to 1078 988: OpLabel: 990: OpAccessChain: 7: 938[194] 991: OpLoad: 6: tmp991 << 990 992: OpFDiv: 6: tmp992 << 991, 109 993: OpExtInst(8): 6: tmp993 << 992 994: OpFMod: 6: tmp994 << 993, 127 995: OpFOrdGreaterThan: 117: tmp995 << 994, 303 OpSelectionMerge: (merge: 997) OpBranchConditional: if(995) then branch to 996, else branch to 1034 996: OpLabel: 999: OpLoad: 8: tmp999 << 938 1000: OpVectorShuffle: 25: tmp1000 << 999, 999, 0, 2 1001: OpLoad: 8: tmp1001 << 938 1002: OpVectorShuffle: 25: tmp1002 << 1001, 1001, 0, 2 1003: OpCompositeConstruct: 25: tmp1003 << 109, 109 1004: OpFDiv: 25: tmp1004 << 1002, 1003 1005: OpExtInst(8): 25: tmp1005 << 1004 1006: OpVectorTimesScalar: 25: tmp1006 << 1005, 109 1007: OpFAdd: 25: tmp1007 << 1006, 667 1008: OpExtInst(67): 6: tmp1008 << 1000, 1007 1009: OpFMul: 6: tmp1009 << 1008, 704 1010: OpExtInst(26): 6: tmp1010 << 1009, 127 OpStore: : 1010 >> 998 1018: OpLoad: 6: tmp1018 << 998 1019: OpFAdd: 6: tmp1019 << 303, 1018 1020: OpLoad: 6: tmp1020 << 998 1021: OpFAdd: 6: tmp1021 << 704, 1020 1022: OpLoad: 8: tmp1022 << 938 1023: OpVectorShuffle: 25: tmp1023 << 1022, 1022, 0, 2 1024: OpVectorTimesScalar: 25: tmp1024 << 1023, 621 1025: OpCompositeExtract: 6: tmp1025 << 1024, 0 1026: OpCompositeExtract: 6: tmp1026 << 1024, 1 1027: OpCompositeConstruct: 8: tmp1027 << 1025, 1026, 100 OpStore: : 1027 >> 1028 1029: OpFunctionCall: 6: tmp1029(1028) 1030: OpFAdd: 6: tmp1030 << 748, 1029 1031: OpExtInst(49): 6: tmp1031 << 1019, 1021, 1030 1032: OpCompositeConstruct: 8: tmp1032 << 1031, 1031, 1031 1033: OpExtInst(46): 8: tmp1033 << 1013, 1017, 1032 OpStore: : 1033 >> 1011 OpBranch: to 997 1034: OpLabel: 1036: OpAccessChain: 7: 938[194] 1037: OpLoad: 6: tmp1037 << 1036 1038: OpFMul: 6: tmp1038 << 1037, 621 1039: OpAccessChain: 7: 938[204] 1040: OpLoad: 6: tmp1040 << 1039 1041: OpFMul: 6: tmp1041 << 1040, 401 1042: OpExtInst(13): 6: tmp1042 << 1041 1043: OpFAdd: 6: tmp1043 << 1038, 1042 1044: OpExtInst(14): 6: tmp1044 << 1043 1045: OpFMul: 6: tmp1045 << 303, 1044 1046: OpFAdd: 6: tmp1046 << 303, 1045 1047: OpExtInst(49): 6: tmp1047 << 671, 435, 1046 1048: OpCompositeConstruct: 8: tmp1048 << 1047, 1047, 1047 1049: OpExtInst(46): 8: tmp1049 << 1035, 1013, 1048 OpStore: : 1049 >> 1011 OpBranch: to 997 997: OpLabel: 1050: OpLoad: 8: tmp1050 << 1011 1051: OpVectorTimesScalar: 8: tmp1051 << 1050, 576 1052: OpLoad: 8: tmp1052 << 952 1053: OpLoad: 8: tmp1053 << 111 1054: OpDot: 6: tmp1054 << 1052, 1053 1055: OpFMul: 6: tmp1055 << 303, 1054 1056: OpFAdd: 6: tmp1056 << 303, 1055 1057: OpCompositeConstruct: 8: tmp1057 << 1056, 1056, 1056 1058: OpFMul: 8: tmp1058 << 1051, 1057 1060: OpLoad: 8: tmp1060 << 981 1061: OpLoad: 8: tmp1061 << 952 1062: OpDot: 6: tmp1062 << 1060, 1061 1063: OpFMul: 6: tmp1063 << 303, 1062 1064: OpFAdd: 6: tmp1064 << 303, 1063 1065: OpExtInst(43): 6: tmp1065 << 1064, 100, 106 1066: OpExtInst(26): 6: tmp1066 << 1065, 863 1067: OpCompositeConstruct: 8: tmp1067 << 1066, 1066, 1066 1068: OpFMul: 8: tmp1068 << 1059, 1067 1069: OpFAdd: 8: tmp1069 << 1058, 1068 1070: OpLoad: 8: tmp1070 << 952 1071: OpLoad: 8: tmp1071 << 86 1072: OpFNegate: 8: tmp1072 << 1071 1073: OpDot: 6: tmp1073 << 1070, 1072 1074: OpExtInst(26): 6: tmp1074 << 1073, 127 1075: OpFMul: 6: tmp1075 << 704, 1074 1076: OpFAdd: 6: tmp1076 << 106, 1075 1077: OpVectorTimesScalar: 8: tmp1077 << 1069, 1076 OpStore: : 1077 >> 944 OpBranch: to 989 1078: OpLabel: 1080: OpLoad: 8: tmp1080 << 952 OpStore: : 1080 >> 1079 1082: OpLoad: 8: tmp1082 << 938 OpStore: : 1082 >> 1081 1084: OpLoad: 8: tmp1084 << 979 OpStore: : 1084 >> 1083 1085: OpFunctionCall: 8: tmp1085(1079, 1081, 1083) 1086: OpVectorTimesScalar: 8: tmp1086 << 1085, 401 1087: OpLoad: 8: tmp1087 << 981 1088: OpLoad: 8: tmp1088 << 952 1089: OpDot: 6: tmp1089 << 1087, 1088 1090: OpFMul: 6: tmp1090 << 303, 1089 1091: OpFAdd: 6: tmp1091 << 303, 1090 1092: OpExtInst(43): 6: tmp1092 << 1091, 100, 106 1094: OpExtInst(26): 6: tmp1094 << 1092, 1093 1095: OpExtInst(49): 6: tmp1095 << 303, 704, 1094 1096: OpCompositeConstruct: 8: tmp1096 << 1095, 1095, 1095 1097: OpVectorTimesScalar: 8: tmp1097 << 1096, 576 1098: OpFAdd: 8: tmp1098 << 1086, 1097 OpStore: : 1098 >> 944 OpBranch: to 989 989: OpLabel: 1099: OpAccessChain: 7: 938[197] 1100: OpLoad: 6: tmp1100 << 1099 1101: OpExtInst(40): 6: tmp1101 << 100, 1100 1102: OpExtInst(26): 6: tmp1102 << 1101, 303 1103: OpExtInst(46): 6: tmp1103 << 106, 1102, 704 1104: OpLoad: 8: tmp1104 << 944 1105: OpVectorTimesScalar: 8: tmp1105 << 1104, 1103 OpStore: : 1105 >> 944 1106: OpLoad: 8: tmp1106 << 944 OpReturnValue: : << 1106 OpFunctionEnd: 96: OpFunction: func96(type: 93) 94: OpFunctionParameter: 92: var94: storage class: Function 95: OpFunctionParameter: 26: var95: storage class: Function 97: OpLabel: 1120: OpVariable: 7: var1120: storage class: Function 1125: OpVariable: 7: var1125: storage class: Function 1130: OpVariable: 20: var1130: storage class: Function 1131: OpVariable: 7: var1131: storage class: Function 1134: OpVariable: 20: var1134: storage class: Function 1137: OpVariable: 7: var1137: storage class: Function 1139: OpVariable: 7: var1139: storage class: Function 1146: OpVariable: 20: var1146: storage class: Function 1151: OpVariable: 20: var1151: storage class: Function 1156: OpVariable: 20: var1156: storage class: Function 1167: OpVariable: 1166: var1167: storage class: Function 1184: OpVariable: 26: var1184: storage class: Function 1188: OpVariable: 26: var1188: storage class: Function 1190: OpVariable: 20: var1190: storage class: Function 1201: OpVariable: 7: var1201: storage class: Function 1204: OpVariable: 7: var1204: storage class: Function 1206: OpVariable: 7: var1206: storage class: Function 1212: OpVariable: 20: var1212: storage class: Function 1221: OpVariable: 7: var1221: storage class: Function 1229: OpVariable: 7: var1229: storage class: Function 1238: OpVariable: 20: var1238: storage class: Function 1239: OpVariable: 20: var1239: storage class: Function 1241: OpVariable: 20: var1241: storage class: Function 1243: OpVariable: 7: var1243: storage class: Function 1245: OpVariable: 7: var1245: storage class: Function 1249: OpVariable: 20: var1249: storage class: Function 1267: OpVariable: 26: var1267: storage class: Function 1275: OpVariable: 26: var1275: storage class: Function 1278: OpVariable: 7: var1278: storage class: Function 1289: OpVariable: 20: var1289: storage class: Function 1312: OpVariable: 26: var1312: storage class: Function 1319: OpVariable: 20: var1319: storage class: Function 1324: OpVariable: 20: var1324: storage class: Function 1327: OpVariable: 7: var1327: storage class: Function 1330: OpVariable: 7: var1330: storage class: Function 1331: OpVariable: 26: var1331: storage class: Function 1333: OpVariable: 26: var1333: storage class: Function 1341: OpVariable: 7: var1341: storage class: Function 1357: OpVariable: 7: var1357: storage class: Function 1381: OpVariable: 20: var1381: storage class: Function 1396: OpVariable: 20: var1396: storage class: Function 1111: OpLoad: 6: tmp1111 << 1110 OpStore: : 1111 >> 103 1112: OpLoad: 25: tmp1112 << 95 1115: OpLoad: 8: tmp1115 << 1114 1116: OpVectorShuffle: 25: tmp1116 << 1115, 1115, 0, 1 1117: OpFDiv: 25: tmp1117 << 1112, 1116 1118: OpVectorTimesScalar: 25: tmp1118 << 1117, 127 1119: OpFSub: 25: tmp1119 << 1118, 342 OpStore: : 1119 >> 99 1121: OpLoad: 6: tmp1121 << 103 1122: OpLoad: 6: tmp1122 << 108 1123: OpFDiv: 6: tmp1123 << 1121, 1122 1124: OpExtInst(8): 6: tmp1124 << 1123 OpStore: : 1124 >> 1120 1126: OpLoad: 6: tmp1126 << 103 1127: OpLoad: 6: tmp1127 << 108 1128: OpFDiv: 6: tmp1128 << 1126, 1127 1129: OpExtInst(10): 6: tmp1129 << 1128 OpStore: : 1129 >> 1125 1132: OpLoad: 6: tmp1132 << 103 OpStore: : 1132 >> 1131 1133: OpFunctionCall: 8: tmp1133(1131) OpStore: : 1133 >> 1130 1135: OpLoad: 6: tmp1135 << 1120 1136: OpFSub: 6: tmp1136 << 1135, 106 OpStore: : 1136 >> 1137 1138: OpFunctionCall: 8: tmp1138(1137) 1140: OpLoad: 6: tmp1140 << 1120 OpStore: : 1140 >> 1139 1141: OpFunctionCall: 8: tmp1141(1139) 1142: OpLoad: 6: tmp1142 << 1125 1143: OpExtInst(49): 6: tmp1143 << 523, 671, 1142 1144: OpCompositeConstruct: 8: tmp1144 << 1143, 1143, 1143 1145: OpExtInst(46): 8: tmp1145 << 1138, 1141, 1144 OpStore: : 1145 >> 1134 1147: OpLoad: 8: tmp1147 << 1134 1148: OpLoad: 8: tmp1148 << 1130 1149: OpFSub: 8: tmp1149 << 1147, 1148 1150: OpExtInst(69): 8: tmp1150 << 1149 OpStore: : 1150 >> 1146 1152: OpLoad: 8: tmp1152 << 1146 1154: OpExtInst(68): 8: tmp1154 << 1152, 1153 1155: OpExtInst(69): 8: tmp1155 << 1154 OpStore: : 1155 >> 1151 1157: OpLoad: 8: tmp1157 << 1151 1158: OpLoad: 8: tmp1158 << 1146 1159: OpExtInst(68): 8: tmp1159 << 1157, 1158 1160: OpExtInst(69): 8: tmp1160 << 1159 OpStore: : 1160 >> 1156 1161: OpLoad: 8: tmp1161 << 1146 1162: OpLoad: 8: tmp1162 << 1156 1163: OpExtInst(68): 8: tmp1163 << 1161, 1162 1164: OpExtInst(69): 8: tmp1164 << 1163 OpStore: : 1164 >> 1151 1168: OpLoad: 8: tmp1168 << 1151 1169: OpLoad: 8: tmp1169 << 1156 1170: OpLoad: 8: tmp1170 << 1146 1171: OpCompositeExtract: 6: tmp1171 << 1168, 0 1172: OpCompositeExtract: 6: tmp1172 << 1168, 1 1173: OpCompositeExtract: 6: tmp1173 << 1168, 2 1174: OpCompositeExtract: 6: tmp1174 << 1169, 0 1175: OpCompositeExtract: 6: tmp1175 << 1169, 1 1176: OpCompositeExtract: 6: tmp1176 << 1169, 2 1177: OpCompositeExtract: 6: tmp1177 << 1170, 0 1178: OpCompositeExtract: 6: tmp1178 << 1170, 1 1179: OpCompositeExtract: 6: tmp1179 << 1170, 2 1180: OpCompositeConstruct: 8: tmp1180 << 1171, 1172, 1173 1181: OpCompositeConstruct: 8: tmp1181 << 1174, 1175, 1176 1182: OpCompositeConstruct: 8: tmp1182 << 1177, 1178, 1179 1183: OpCompositeConstruct: 1165: tmp1183 << 1180, 1181, 1182 OpStore: : 1183 >> 1167 1185: OpLoad: 25: tmp1185 << 99 1186: OpVectorTimesScalar: 25: tmp1186 << 1185, 303 1187: OpFAdd: 25: tmp1187 << 1186, 391 OpStore: : 1187 >> 1184 1189: OpLoad: 25: tmp1189 << 99 OpStore: : 1189 >> 1188 1191: OpLoad: 8: tmp1191 << 1130 OpStore: : 1191 >> 1190 1192: OpAccessChain: 1109: 1114[194] 1193: OpLoad: 6: tmp1193 << 1192 1194: OpAccessChain: 1109: 1114[197] 1195: OpLoad: 6: tmp1195 << 1194 1196: OpFDiv: 6: tmp1196 << 1193, 1195 1197: OpAccessChain: 7: 1188[194] 1198: OpLoad: 6: tmp1198 << 1197 1199: OpFMul: 6: tmp1199 << 1198, 1196 1200: OpAccessChain: 7: 1188[194] OpStore: : 1199 >> 1200 1202: OpLoad: 6: tmp1202 << 1120 1203: OpFSub: 6: tmp1203 << 1202, 106 OpStore: : 1203 >> 1204 1205: OpFunctionCall: 6: tmp1205(1204) 1207: OpLoad: 6: tmp1207 << 1120 OpStore: : 1207 >> 1206 1208: OpFunctionCall: 6: tmp1208(1206) 1209: OpLoad: 6: tmp1209 << 1125 1210: OpExtInst(49): 6: tmp1210 << 671, 435, 1209 1211: OpExtInst(46): 6: tmp1211 << 1205, 1208, 1210 OpStore: : 1211 >> 1201 1213: OpLoad: 1165: tmp1213 << 1167 1214: OpLoad: 25: tmp1214 << 1188 1215: OpLoad: 6: tmp1215 << 1201 1216: OpCompositeExtract: 6: tmp1216 << 1214, 0 1217: OpCompositeExtract: 6: tmp1217 << 1214, 1 1218: OpCompositeConstruct: 8: tmp1218 << 1216, 1217, 1215 1219: OpExtInst(69): 8: tmp1219 << 1218 1220: OpMatrixTimesVector: 8: tmp1220 << 1213, 1219 OpStore: : 1220 >> 1212 1222: OpAccessChain: 7: 1190[197] 1223: OpLoad: 6: tmp1223 << 1222 1224: OpFSub: 6: tmp1224 << 106, 1223 1225: OpAccessChain: 7: 1212[197] 1226: OpLoad: 6: tmp1226 << 1225 1227: OpFDiv: 6: tmp1227 << 1224, 1226 1228: OpExtInst(40): 6: tmp1228 << 100, 1227 OpStore: : 1228 >> 1221 1231: OpAccessChain: 7: 1190[197] 1232: OpLoad: 6: tmp1232 << 1231 1233: OpFSub: 6: tmp1233 << 1230, 1232 1234: OpAccessChain: 7: 1212[197] 1235: OpLoad: 6: tmp1235 << 1234 1236: OpFDiv: 6: tmp1236 << 1233, 1235 1237: OpExtInst(40): 6: tmp1237 << 100, 1236 OpStore: : 1237 >> 1229 1240: OpLoad: 8: tmp1240 << 1190 OpStore: : 1240 >> 1239 1242: OpLoad: 8: tmp1242 << 1212 OpStore: : 1242 >> 1241 1244: OpLoad: 6: tmp1244 << 1221 OpStore: : 1244 >> 1243 1246: OpLoad: 6: tmp1246 << 1229 OpStore: : 1246 >> 1245 1247: OpFunctionCall: 8: tmp1247(1239, 1241, 1243, 1245) 1248: OpLoad: 6: tmp1248 << 1243 OpStore: : 1248 >> 1221 OpStore: : 1247 >> 1238 1250: OpLoad: 8: tmp1250 << 1190 1251: OpLoad: 8: tmp1251 << 1212 1252: OpLoad: 6: tmp1252 << 1221 1253: OpVectorTimesScalar: 8: tmp1253 << 1251, 1252 1254: OpFAdd: 8: tmp1254 << 1250, 1253 OpStore: : 1254 >> 1249 1255: OpAccessChain: 7: 1249[197] 1256: OpLoad: 6: tmp1256 << 1255 1257: OpFMul: 6: tmp1257 << 1256, 127 1258: OpExtInst(43): 6: tmp1258 << 1257, 100, 106 OpStore: : 1258 >> 115 1259: OpLoad: 6: tmp1259 << 1221 1260: OpFOrdGreaterThan: 117: tmp1260 << 1259, 100 1261: OpLoad: 6: tmp1261 << 1229 1262: OpLoad: 6: tmp1262 << 1221 1263: OpFOrdLessThan: 117: tmp1263 << 1261, 1262 1264: OpLogicalAnd: 117: tmp1264 << 1260, 1263 OpSelectionMerge: (merge: 1266) OpBranchConditional: if(1264) then branch to 1265, else branch to 1266 1265: OpLabel: 1268: OpLoad: 8: tmp1268 << 1190 1269: OpVectorShuffle: 25: tmp1269 << 1268, 1268, 0, 2 1270: OpLoad: 8: tmp1270 << 1212 1271: OpVectorShuffle: 25: tmp1271 << 1270, 1270, 0, 2 1272: OpLoad: 6: tmp1272 << 1229 1273: OpVectorTimesScalar: 25: tmp1273 << 1271, 1272 1274: OpFAdd: 25: tmp1274 << 1269, 1273 OpStore: : 1274 >> 1267 1276: OpLoad: 25: tmp1276 << 1267 1277: OpVectorTimesScalar: 25: tmp1277 << 1276, 151 OpStore: : 1277 >> 1275 1279: OpAccessChain: 7: 1275[194] 1280: OpLoad: 6: tmp1280 << 1279 1281: OpAccessChain: 7: 1275[197] 1282: OpLoad: 6: tmp1282 << 1281 1283: OpExtInst(10): 6: tmp1283 << 1282 1284: OpExtInst(48): 6: tmp1284 << 303, 1283 1285: OpFMul: 6: tmp1285 << 303, 1284 1286: OpFAdd: 6: tmp1286 << 1280, 1285 1287: OpExtInst(10): 6: tmp1287 << 1286 1288: OpExtInst(48): 6: tmp1288 << 303, 1287 OpStore: : 1288 >> 1278 1293: OpLoad: 6: tmp1293 << 1278 1294: OpCompositeConstruct: 8: tmp1294 << 1293, 1293, 1293 1295: OpExtInst(46): 8: tmp1295 << 1290, 1292, 1294 OpStore: : 1295 >> 1289 1296: OpLoad: 8: tmp1296 << 1289 1298: OpLoad: 25: tmp1298 << 1275 1299: OpVectorTimesScalar: 25: tmp1299 << 1298, 621 1300: OpAccessChain: 7: 1275[197] 1301: OpLoad: 6: tmp1301 << 1300 1302: OpFMul: 6: tmp1302 << 1301, 127 1303: OpExtInst(14): 6: tmp1303 << 1302 1304: OpFMul: 6: tmp1304 << 1303, 109 1305: OpAccessChain: 7: 1275[194] 1306: OpLoad: 6: tmp1306 << 1305 1307: OpFMul: 6: tmp1307 << 1306, 106 1308: OpExtInst(14): 6: tmp1308 << 1307 1309: OpFMul: 6: tmp1309 << 1308, 377 1310: OpCompositeConstruct: 25: tmp1310 << 1304, 1309 1311: OpFAdd: 25: tmp1311 << 1299, 1310 OpStore: : 1311 >> 1312 1313: OpFunctionCall: 6: tmp1313(1312) 1314: OpFMul: 6: tmp1314 << 303, 1313 1315: OpFAdd: 6: tmp1315 << 523, 1314 1316: OpExtInst(26): 6: tmp1316 << 1315, 377 1317: OpCompositeConstruct: 8: tmp1317 << 1316, 1316, 1316 1318: OpExtInst(46): 8: tmp1318 << 1296, 1297, 1317 OpStore: : 1318 >> 1289 1320: OpLoad: 8: tmp1320 << 111 1321: OpLoad: 8: tmp1321 << 1212 1322: OpFSub: 8: tmp1322 << 1320, 1321 1323: OpExtInst(69): 8: tmp1323 << 1322 OpStore: : 1323 >> 1319 1325: OpLoad: 8: tmp1325 << 1212 1326: OpExtInst(71): 8: tmp1326 << 1325, 1153 OpStore: : 1326 >> 1324 OpStore: : 100 >> 1327 1328: OpLoad: 25: tmp1328 << 1275 1329: OpVectorTimesScalar: 25: tmp1329 << 1328, 303 OpStore: : 127 >> 1330 OpStore: : 1329 >> 1331 1332: OpFunctionCall: 25: tmp1332(1330, 1331) OpStore: : 1332 >> 1333 1334: OpFunctionCall: 8: tmp1334(1333) OpStore: : 1334 >> 1289 1335: OpLoad: 25: tmp1335 << 1267 1336: OpCompositeConstruct: 25: tmp1336 << 109, 109 1337: OpFDiv: 25: tmp1337 << 1335, 1336 1338: OpExtInst(10): 25: tmp1338 << 1337 OpStore: : 1338 >> 1267 1339: OpLoad: 8: tmp1339 << 1289 1340: OpVectorTimesScalar: 8: tmp1340 << 1339, 151 1342: OpLoad: 6: tmp1342 << 104 OpStore: : 1342 >> 1341 1343: OpFunctionCall: 8: tmp1343(1341) 1344: OpVectorTimesScalar: 8: tmp1344 << 1343, 127 1345: OpLoad: 6: tmp1345 << 107 1346: OpVectorTimesScalar: 8: tmp1346 << 1344, 1345 1349: OpLoad: 25: tmp1349 << 1267 1350: OpExtInst(67): 6: tmp1350 << 391, 1349 1351: OpLoad: 6: tmp1351 << 105 1352: OpFDiv: 6: tmp1352 << 1350, 1351 1353: OpExtInst(49): 6: tmp1353 << 1347, 1348, 1352 1354: OpCompositeConstruct: 8: tmp1354 << 1353, 1353, 1353 1355: OpExtInst(46): 8: tmp1355 << 1346, 1290, 1354 1356: OpFMul: 8: tmp1356 << 1340, 1355 OpStore: : 1356 >> 1238 OpStore: : 106 >> 115 OpBranch: to 1266 1266: OpLabel: 1360: OpAccessChain: 1109: 1359[194] 1361: OpLoad: 6: tmp1361 << 1360 1362: OpAccessChain: 1109: 1114[194] 1363: OpLoad: 6: tmp1363 << 1362 1364: OpFDiv: 6: tmp1364 << 1361, 1363 1365: OpLoad: 6: tmp1365 << 115 1366: OpFMul: 6: tmp1366 << 1364, 1365 1367: OpFSub: 6: tmp1367 << 106, 1366 OpStore: : 1367 >> 1357 1368: OpLoad: 8: tmp1368 << 1238 1370: OpLoad: 6: tmp1370 << 1357 1371: OpFMul: 6: tmp1371 << 1369, 1370 1373: OpFAdd: 6: tmp1373 << 1371, 1372 1374: OpLoad: 8: tmp1374 << 1249 1375: OpVectorShuffle: 25: tmp1375 << 1374, 1374, 0, 2 1377: OpVectorTimesScalar: 25: tmp1377 << 1375, 1376 1378: OpCompositeExtract: 6: tmp1378 << 1377, 0 1379: OpCompositeExtract: 6: tmp1379 << 1377, 1 1380: OpCompositeConstruct: 8: tmp1380 << 1378, 1379, 100 OpStore: : 1380 >> 1381 1382: OpFunctionCall: 6: tmp1382(1381) 1383: OpFAdd: 6: tmp1383 << 1373, 1382 1384: OpExtInst(49): 6: tmp1384 << 303, 671, 1383 1385: OpFMul: 6: tmp1385 << 435, 1384 1386: OpLoad: 6: tmp1386 << 1357 1387: OpFMul: 6: tmp1387 << 1369, 1386 1388: OpFAdd: 6: tmp1388 << 1387, 523 1389: OpLoad: 8: tmp1389 << 1249 1390: OpVectorShuffle: 25: tmp1390 << 1389, 1389, 0, 2 1392: OpVectorTimesScalar: 25: tmp1392 << 1390, 1391 1393: OpCompositeExtract: 6: tmp1393 << 1392, 0 1394: OpCompositeExtract: 6: tmp1394 << 1392, 1 1395: OpCompositeConstruct: 8: tmp1395 << 1393, 1394, 100 OpStore: : 1395 >> 1396 1397: OpFunctionCall: 6: tmp1397(1396) 1398: OpFAdd: 6: tmp1398 << 1388, 1397 1399: OpExtInst(49): 6: tmp1399 << 303, 671, 1398 1400: OpFMul: 6: tmp1400 << 435, 1399 1401: OpFAdd: 6: tmp1401 << 1385, 1400 1402: OpCompositeConstruct: 8: tmp1402 << 1401, 1401, 1401 1403: OpExtInst(46): 8: tmp1403 << 1368, 1290, 1402 OpStore: : 1403 >> 1238 1404: OpLoad: 8: tmp1404 << 1238 1405: OpVectorTimesScalar: 8: tmp1405 << 1404, 895 1406: OpExtInst(31): 8: tmp1406 << 1405 1407: OpLoad: 91: tmp1407 << 94 1408: OpVectorShuffle: 91: tmp1408 << 1407, 1406, 4, 5, 6, 3 OpStore: : 1408 >> 94 1410: OpAccessChain: 7: 1184[194] 1411: OpLoad: 6: tmp1411 << 1410 1412: OpFMul: 6: tmp1412 << 1409, 1411 1413: OpAccessChain: 7: 1184[197] 1414: OpLoad: 6: tmp1414 << 1413 1415: OpFMul: 6: tmp1415 << 1412, 1414 1416: OpAccessChain: 7: 1184[194] 1417: OpLoad: 6: tmp1417 << 1416 1418: OpFSub: 6: tmp1418 << 106, 1417 1419: OpFMul: 6: tmp1419 << 1415, 1418 1420: OpAccessChain: 7: 1184[197] 1421: OpLoad: 6: tmp1421 << 1420 1422: OpFSub: 6: tmp1422 << 106, 1421 1423: OpFMul: 6: tmp1423 << 1419, 1422 1424: OpExtInst(26): 6: tmp1424 << 1423, 576 1425: OpLoad: 91: tmp1425 << 94 1426: OpVectorShuffle: 8: tmp1426 << 1425, 1425, 0, 1, 2 1427: OpVectorTimesScalar: 8: tmp1427 << 1426, 1424 1428: OpLoad: 91: tmp1428 << 94 1429: OpVectorShuffle: 91: tmp1429 << 1428, 1427, 4, 5, 6, 3 OpStore: : 1429 >> 94 OpReturn: OpFunctionEnd: Linking the instructions Initial Disassembly: Module Info: OpSource: : ESSL ver 310 1: OpExtInstImport: : GLSL.std.450 OpMemoryModel: : addressing: Logical, memory: GLSL450 Capabilities: OpCapability: : Shader Inputs: 1432: OpVariable: FloatVector4*: gl_FragCoord: storage class: Input Decorators: BuiltIn(FragCoord) Outputs: 1440: OpVariable: FloatVector4*: finalColor: storage class: Output Uniform Constants: 1110: OpVariable: Float*: iTime: storage class: UniformConstant 1114: OpVariable: FloatVector3*: iResolution: storage class: UniformConstant 1359: OpVariable: FloatVector4*: iMouse: storage class: UniformConstant 1442: OpVariable: FloatVector4*: iDate: storage class: UniformConstant 1443: OpVariable: Float*: iFrame: storage class: UniformConstant 1447: OpVariable: FloatVector3[4]*: iChannelResolution: storage class: UniformConstant Textures: 1451: OpVariable: SampledImage(Image(Float))*: iChannel0: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 1452: OpVariable: SampledImage(Image(Float))*: iChannel1: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 1453: OpVariable: SampledImage(Image(Float))*: iChannel2: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 1454: OpVariable: SampledImage(Image(Float))*: iChannel3: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) Entry Points: 4: OpEntryPoint: : main, execution model: Fragment, Function: Void main(), OriginLowerLeft Constants: 100: OpConstant: Float const100 = 0 101: OpConstantComposite: FloatVector2 const101 = {0, 0} 106: OpConstant: Float const106 = 1 109: OpConstant: Float const109 = 3 112: OpConstant: Float const112 = 0.316228 113: OpConstant: Float const113 = 0.948683 114: OpConstantComposite: FloatVector3 const114 = {0.316228, 0.948683, 0} 121: OpConstant: Float const121 = 0.11 122: OpConstant: Float const122 = 0.002 123: OpConstantComposite: FloatVector3 const123 = {0.11, 0, 0.002} 127: OpConstant: Float const127 = 2 131: OpConstant: Float const131 = 0.06 132: OpConstantComposite: FloatVector3 const132 = {0.002, 0.06, 0} 139: OpConstant: Float const139 = 0.02 140: OpConstantComposite: FloatVector3 const140 = {0, 0.02, 0.11} 143: OpConstant: Float const143 = 0.012 144: OpConstantComposite: FloatVector3 const144 = {0.11, 0.012, 0} 151: OpConstant: Float const151 = 0.8 152: OpConstantComposite: FloatVector3 const152 = {0.8, 1, 1} 159: OpConstantComposite: FloatVector3 const159 = {0.8, 0.8, 1} 166: OpConstantComposite: FloatVector3 const166 = {1, 0.8, 1} 173: OpConstant: Float const173 = 43758.5 194: OpConstant: UInt const194 = 0 197: OpConstant: UInt const197 = 1 200: OpConstant: Float const200 = 157 203: OpConstant: Float const203 = 113 204: OpConstant: UInt const204 = 2 225: OpConstant: Float const225 = 158 240: OpConstant: Float const240 = 114 248: OpConstant: Float const248 = 270 253: OpConstant: Float const253 = 271 285: OpConstant: Int const285 = 1 292: OpConstant: Int const292 = 9 303: OpConstant: Float const303 = 0.5 340: OpConstant: Float const340 = -1 341: OpConstantComposite: FloatVector2 const341 = {-1, -1} 342: OpConstantComposite: FloatVector2 const342 = {1, 1} 349: OpConstant: Float const349 = 8 361: OpConstant: Float const361 = 0.95 377: OpConstant: Float const377 = 4 391: OpConstantComposite: FloatVector2 const391 = {0.5, 0.5} 401: OpConstant: Float const401 = 5 407: OpConstant: Float const407 = 53 412: OpConstant: Float const412 = 125 416: OpConstant: Float const416 = 2.5 423: OpConstant: Float const423 = 100 424: OpConstantComposite: FloatVector2 const424 = {100, 100} 435: OpConstant: Float const435 = 0.9 437: OpConstant: Float const437 = 25 471: OpConstant: Int const471 = 0 478: OpConstant: Int const478 = 4 483: OpConstant: Float const483 = 10.45 489: OpConstant: Float const489 = 0.2 511: OpConstant: Float const511 = 0.75 523: OpConstant: Float const523 = 0.3 569: OpConstantComposite: FloatVector3 const569 = {0.5, 0.5, 0.5} 573: OpConstant: Float const573 = 0.98 576: OpConstant: Float const576 = 0.1 585: OpConstantComposite: FloatVector3 const585 = {2, 2, 2} 593: OpConstant: Float const593 = 1.05 602: OpConstant: Float const602 = 0.01 609: OpConstant: Float const609 = 1.3 621: OpConstant: Float const621 = 10 625: OpConstant: Float const625 = 103 633: OpConstant: Float const633 = 30 637: OpConstant: Float const637 = 0.001 647: OpConstant: Float const647 = 0.05 664: OpConstantComposite: FloatVector2 const664 = {3, 3} 666: OpConstant: Float const666 = 1.5 667: OpConstantComposite: FloatVector2 const667 = {1.5, 1.5} 671: OpConstant: Float const671 = 0.7 674: OpConstant: Float const674 = 7 678: OpConstant: Float const678 = 9 704: OpConstant: Float const704 = 0.6 714: OpConstant: Float const714 = 0.015 730: OpConstantComposite: FloatVector2 const730 = {1, -1} 735: OpConstantComposite: FloatVector3 const735 = {0.1, 0.1, 0.05} 748: OpConstant: Float const748 = 0.4 749: OpConstant: Float const749 = 0.24 750: OpConstantComposite: FloatVector3 const750 = {0.4, 0.4, 0.24} 751: OpConstant: Float const751 = 0.56 752: OpConstantComposite: FloatVector3 const752 = {0.7, 0.7, 0.56} 844: OpConstant: Float const844 = 6 848: OpConstant: Float const848 = 0.03 860: OpConstantComposite: FloatVector3 const860 = {1, 0, 0} 863: OpConstant: Float const863 = 20 867: OpConstant: Float const867 = -7 869: OpConstant: Float const869 = 14 888: OpConstant: Float const888 = 3.5 895: OpConstant: Float const895 = 1.4 906: OpConstant: Int const906 = 100 921: OpConstantComposite: FloatVector3 const921 = {0, 0, 0} 925: OpConstant: Float const925 = 0.0001 945: OpConstant: Float const945 = 0.005 946: OpConstantComposite: FloatVector3 const946 = {0.02, 0.01, 0.005} 1012: OpConstant: Float const1012 = 2.6 1013: OpConstantComposite: FloatVector3 const1013 = {4, 4, 2.6} 1014: OpConstant: Float const1014 = 0.78 1015: OpConstant: Float const1015 = 0.36 1016: OpConstant: Float const1016 = 0.12 1017: OpConstantComposite: FloatVector3 const1017 = {0.78, 0.36, 0.12} 1035: OpConstantComposite: FloatVector3 const1035 = {1.3, 0.6, 0.2} 1059: OpConstantComposite: FloatVector3 const1059 = {0.06, 0.06, 0.03} 1093: OpConstant: Float const1093 = 256 1153: OpConstantComposite: FloatVector3 const1153 = {0, 1, 0} 1230: OpConstant: Float const1230 = -0.01 1290: OpConstantComposite: FloatVector3 const1290 = {1, 1, 1} 1291: OpConstant: Float const1291 = 0.25 1292: OpConstantComposite: FloatVector3 const1292 = {0.5, 0.5, 0.25} 1297: OpConstantComposite: FloatVector3 const1297 = {0.9, 0.9, 0.5} 1347: OpConstant: Float const1347 = 0.33 1348: OpConstant: Float const1348 = 0.53 1369: OpConstant: Float const1369 = -0.25 1372: OpConstant: Float const1372 = 0.35 1376: OpConstant: Float const1376 = 4.2 1391: OpConstant: Float const1391 = 10.1 1409: OpConstant: Float const1409 = 16 1444: OpConstant: UInt const1444 = 4 Private Global Variables: 99: OpVariable: FloatVector2*: tc: storage class: Private 103: OpVariable: Float*: time: storage class: Private 104: OpVariable: Float*: colour: storage class: Private 105: OpVariable: Float*: ss: storage class: Private 107: OpVariable: Float*: is_choc: storage class: Private 108: OpVariable: Float*: t_per_target: storage class: Private 111: OpVariable: FloatVector3*: l: storage class: Private 115: OpVariable: Float*: icing_factor: storage class: Private 1456: OpVariable: FloatVector3[4]*: gum_colours: storage class: Private 1457: OpVariable: FloatVector3[4]*: gum_ramps: storage class: Private Disassembled Code: 4: OpFunction: Void main() 1430: OpVariable: FloatVector4*: color: storage class: Function 1433: OpVariable: FloatVector4*: param1433: storage class: Function 1434: OpVariable: FloatVector2*: param1434: storage class: Function 5: lb5: OpStore: : const101 >> tc OpStore: : const100 >> time OpStore: : const100 >> colour OpStore: : const106 >> ss OpStore: : const100 >> is_choc OpStore: : const109 >> t_per_target OpStore: : const114 >> l OpStore: : const100 >> icing_factor 1435: OpLoad: FloatVector4: tmp1435 << gl_FragCoord 1436: OpVectorShuffle: FloatVector2: tmp1436 << tmp1435, tmp1435, 0, 1 OpStore: : tmp1436 >> param1434 1437: OpFunctionCall: Void: mainImage(vf4;vf2;(param1433, param1434) 1438: OpLoad: FloatVector4: tmp1438 << param1433 OpStore: : tmp1438 >> color 1441: OpLoad: FloatVector4: tmp1441 << color OpStore: : tmp1441 >> finalColor OpReturn: 11: OpFunction: FloatVector3 gumColour(f1;(Float* i) 12: lb12: 116: OpLoad: Float: tmp116 << i 118: OpFOrdLessThan: Bool: tmp118 << tmp116, const106 OpSelectionMerge: (merge: lb120) OpBranchConditional: if(tmp118) then branch to lb119, else branch to lb125 119: lb119: OpReturnValue: : << const123 125: lb125: 126: OpLoad: Float: tmp126 << i 128: OpFOrdLessThan: Bool: tmp128 << tmp126, const127 OpSelectionMerge: (merge: lb130) OpBranchConditional: if(tmp128) then branch to lb129, else branch to lb134 129: lb129: OpReturnValue: : << const132 134: lb134: 135: OpLoad: Float: tmp135 << i 136: OpFOrdLessThan: Bool: tmp136 << tmp135, const109 OpSelectionMerge: (merge: lb138) OpBranchConditional: if(tmp136) then branch to lb137, else branch to lb142 137: lb137: OpReturnValue: : << const140 142: lb142: OpReturnValue: : << const144 138: lb138: OpBranch: to lb130 130: lb130: OpBranch: to lb120 120: lb120: 146: OpUndef: FloatVector3: tmp146 << OpReturnValue: : << tmp146 14: OpFunction: FloatVector3 gumRamp(f1;(Float* i) 15: lb15: 147: OpLoad: Float: tmp147 << i 148: OpFOrdLessThan: Bool: tmp148 << tmp147, const106 OpSelectionMerge: (merge: lb150) OpBranchConditional: if(tmp148) then branch to lb149, else branch to lb154 149: lb149: OpReturnValue: : << const152 154: lb154: 155: OpLoad: Float: tmp155 << i 156: OpFOrdLessThan: Bool: tmp156 << tmp155, const127 OpSelectionMerge: (merge: lb158) OpBranchConditional: if(tmp156) then branch to lb157, else branch to lb161 157: lb157: OpReturnValue: : << const159 161: lb161: 162: OpLoad: Float: tmp162 << i 163: OpFOrdLessThan: Bool: tmp163 << tmp162, const109 OpSelectionMerge: (merge: lb165) OpBranchConditional: if(tmp163) then branch to lb164, else branch to lb168 164: lb164: OpReturnValue: : << const166 168: lb168: OpReturnValue: : << const159 165: lb165: OpBranch: to lb158 158: lb158: OpBranch: to lb150 150: lb150: 170: OpUndef: FloatVector3: tmp170 << OpReturnValue: : << tmp170 18: OpFunction: Float hash(f1;(Float* n) 19: lb19: 171: OpLoad: Float: tmp171 << n 172: OpExtInst(Sin): Float: tmp172 << tmp171 174: OpFMul: Float: tmp174 << tmp172, const173 175: OpExtInst(Fract): Float: tmp175 << tmp174 OpReturnValue: : << tmp175 23: OpFunction: Float noise(vf3;(FloatVector3* x) 178: OpVariable: FloatVector3*: p: storage class: Function 181: OpVariable: FloatVector3*: f: storage class: Function 192: OpVariable: Float*: n: storage class: Function 211: OpVariable: Float*: param211: storage class: Function 215: OpVariable: Float*: param215: storage class: Function 222: OpVariable: Float*: param222: storage class: Function 227: OpVariable: Float*: param227: storage class: Function 237: OpVariable: Float*: param237: storage class: Function 242: OpVariable: Float*: param242: storage class: Function 250: OpVariable: Float*: param250: storage class: Function 255: OpVariable: Float*: param255: storage class: Function 24: lb24: 179: OpLoad: FloatVector3: tmp179 << x 180: OpExtInst(Floor): FloatVector3: tmp180 << tmp179 OpStore: : tmp180 >> p 182: OpLoad: FloatVector3: tmp182 << x 183: OpExtInst(Fract): FloatVector3: tmp183 << tmp182 OpStore: : tmp183 >> f 184: OpLoad: FloatVector3: tmp184 << f 185: OpLoad: FloatVector3: tmp185 << f 186: OpFMul: FloatVector3: tmp186 << tmp184, tmp185 187: OpLoad: FloatVector3: tmp187 << f 188: OpVectorTimesScalar: FloatVector3: tmp188 << tmp187, const127 189: OpCompositeConstruct: FloatVector3: tmp189 << const109, const109, const109 190: OpFSub: FloatVector3: tmp190 << tmp189, tmp188 191: OpFMul: FloatVector3: tmp191 << tmp186, tmp190 OpStore: : tmp191 >> f 195: OpAccessChain: Float*: p[0] 196: OpLoad: Float: tmp196 << p[0] 198: OpAccessChain: Float*: p[1] 199: OpLoad: Float: tmp199 << p[1] 201: OpFMul: Float: tmp201 << tmp199, const200 202: OpFAdd: Float: tmp202 << tmp196, tmp201 205: OpAccessChain: Float*: p[2] 206: OpLoad: Float: tmp206 << p[2] 207: OpFMul: Float: tmp207 << const203, tmp206 208: OpFAdd: Float: tmp208 << tmp202, tmp207 OpStore: : tmp208 >> n 209: OpLoad: Float: tmp209 << n 210: OpFAdd: Float: tmp210 << tmp209, const100 OpStore: : tmp210 >> param211 212: OpFunctionCall: Float: hash(f1;(param211) 213: OpLoad: Float: tmp213 << n 214: OpFAdd: Float: tmp214 << tmp213, const106 OpStore: : tmp214 >> param215 216: OpFunctionCall: Float: hash(f1;(param215) 217: OpAccessChain: Float*: f[0] 218: OpLoad: Float: tmp218 << f[0] 219: OpExtInst(FMix): Float: tmp219 << hash(f1;, hash(f1;, tmp218 220: OpLoad: Float: tmp220 << n 221: OpFAdd: Float: tmp221 << tmp220, const200 OpStore: : tmp221 >> param222 223: OpFunctionCall: Float: hash(f1;(param222) 224: OpLoad: Float: tmp224 << n 226: OpFAdd: Float: tmp226 << tmp224, const225 OpStore: : tmp226 >> param227 228: OpFunctionCall: Float: hash(f1;(param227) 229: OpAccessChain: Float*: f[0] 230: OpLoad: Float: tmp230 << f[0] 231: OpExtInst(FMix): Float: tmp231 << hash(f1;, hash(f1;, tmp230 232: OpAccessChain: Float*: f[1] 233: OpLoad: Float: tmp233 << f[1] 234: OpExtInst(FMix): Float: tmp234 << tmp219, tmp231, tmp233 235: OpLoad: Float: tmp235 << n 236: OpFAdd: Float: tmp236 << tmp235, const203 OpStore: : tmp236 >> param237 238: OpFunctionCall: Float: hash(f1;(param237) 239: OpLoad: Float: tmp239 << n 241: OpFAdd: Float: tmp241 << tmp239, const240 OpStore: : tmp241 >> param242 243: OpFunctionCall: Float: hash(f1;(param242) 244: OpAccessChain: Float*: f[0] 245: OpLoad: Float: tmp245 << f[0] 246: OpExtInst(FMix): Float: tmp246 << hash(f1;, hash(f1;, tmp245 247: OpLoad: Float: tmp247 << n 249: OpFAdd: Float: tmp249 << tmp247, const248 OpStore: : tmp249 >> param250 251: OpFunctionCall: Float: hash(f1;(param250) 252: OpLoad: Float: tmp252 << n 254: OpFAdd: Float: tmp254 << tmp252, const253 OpStore: : tmp254 >> param255 256: OpFunctionCall: Float: hash(f1;(param255) 257: OpAccessChain: Float*: f[0] 258: OpLoad: Float: tmp258 << f[0] 259: OpExtInst(FMix): Float: tmp259 << hash(f1;, hash(f1;, tmp258 260: OpAccessChain: Float*: f[1] 261: OpLoad: Float: tmp261 << f[1] 262: OpExtInst(FMix): Float: tmp262 << tmp246, tmp259, tmp261 263: OpAccessChain: Float*: f[2] 264: OpLoad: Float: tmp264 << f[2] 265: OpExtInst(FMix): Float: tmp265 << tmp234, tmp262, tmp264 OpReturnValue: : << tmp265 29: OpFunction: Float smN2(vf2;(FloatVector2* p) 272: OpVariable: FloatVector3*: param272: storage class: Function 30: lb30: 268: OpLoad: FloatVector2: tmp268 << p 269: OpCompositeExtract: Float: tmp269 << tmp268, 0 270: OpCompositeExtract: Float: tmp270 << tmp268, 1 271: OpCompositeConstruct: FloatVector3: tmp271 << tmp269, tmp270, const100 OpStore: : tmp271 >> param272 273: OpFunctionCall: Float: noise(vf3;(param272) OpReturnValue: : << noise(vf3; 32: OpFunction: Float smN3(vf3;(FloatVector3* p) 276: OpVariable: FloatVector3*: param276: storage class: Function 33: lb33: 277: OpLoad: FloatVector3: tmp277 << p OpStore: : tmp277 >> param276 278: OpFunctionCall: Float: noise(vf3;(param276) OpReturnValue: : << noise(vf3; 35: OpFunction: Float fbm3(vf3;(FloatVector3* p) 281: OpVariable: Float*: f: storage class: Function 284: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 294: OpVariable: Float*: x: storage class: Function 301: OpVariable: FloatVector3*: param301: storage class: Function 36: lb36: OpStore: : const100 >> f OpStore: : const285 >> i OpBranch: to lb286 286: lb286: OpLoopMerge: (merge: lb288, continue: lb289) OpBranch: to lb290 290: lb290: 291: OpLoad: Int: tmp291 << i Decorators: RelaxedPrecision 293: OpSLessThanEqual: Bool: tmp293 << tmp291, const292 OpBranchConditional: if(tmp293) then branch to lb287, else branch to lb288 287: lb287: 295: OpLoad: Int: tmp295 << i Decorators: RelaxedPrecision 296: OpConvertSToF: Float: tmp296 << tmp295 297: OpExtInst(Exp2): Float: tmp297 << tmp296 OpStore: : tmp297 >> x 298: OpLoad: FloatVector3: tmp298 << p 299: OpLoad: Float: tmp299 << x 300: OpVectorTimesScalar: FloatVector3: tmp300 << tmp298, tmp299 OpStore: : tmp300 >> param301 302: OpFunctionCall: Float: noise(vf3;(param301) 304: OpFSub: Float: tmp304 << noise(vf3;, const303 305: OpLoad: Float: tmp305 << x 306: OpFDiv: Float: tmp306 << tmp304, tmp305 307: OpLoad: Float: tmp307 << f 308: OpFAdd: Float: tmp308 << tmp307, tmp306 OpStore: : tmp308 >> f OpBranch: to lb289 289: lb289: 309: OpLoad: Int: tmp309 << i Decorators: RelaxedPrecision 310: OpIAdd: Int: tmp310 << tmp309, const285 Decorators: RelaxedPrecision OpStore: : tmp310 >> i OpBranch: to lb286 288: lb288: 311: OpLoad: Float: tmp311 << f OpReturnValue: : << tmp311 40: OpFunction: FloatVector2 rotate(f1;vf2;(Float* a, FloatVector2* v) 41: lb41: 314: OpLoad: Float: tmp314 << a 315: OpExtInst(Cos): Float: tmp315 << tmp314 316: OpAccessChain: Float*: v[0] 317: OpLoad: Float: tmp317 << v[0] 318: OpFMul: Float: tmp318 << tmp315, tmp317 319: OpLoad: Float: tmp319 << a 320: OpExtInst(Sin): Float: tmp320 << tmp319 321: OpAccessChain: Float*: v[1] 322: OpLoad: Float: tmp322 << v[1] 323: OpFMul: Float: tmp323 << tmp320, tmp322 324: OpFAdd: Float: tmp324 << tmp318, tmp323 325: OpLoad: Float: tmp325 << a 326: OpExtInst(Cos): Float: tmp326 << tmp325 327: OpAccessChain: Float*: v[1] 328: OpLoad: Float: tmp328 << v[1] 329: OpFMul: Float: tmp329 << tmp326, tmp328 330: OpLoad: Float: tmp330 << a 331: OpExtInst(Sin): Float: tmp331 << tmp330 332: OpAccessChain: Float*: v[0] 333: OpLoad: Float: tmp333 << v[0] 334: OpFMul: Float: tmp334 << tmp331, tmp333 335: OpFSub: Float: tmp335 << tmp329, tmp334 336: OpCompositeConstruct: FloatVector2: tmp336 << tmp324, tmp335 OpReturnValue: : << tmp336 43: OpFunction: Float sugarybit(vf2;(FloatVector2* p) 344: OpVariable: FloatVector2*: o: storage class: Function 345: OpVariable: Float*: a: storage class: Function 365: OpVariable: Float*: b: storage class: Function 44: lb44: 339: OpLoad: FloatVector2: tmp339 << p 343: OpExtInst(FClamp): FloatVector2: tmp343 << tmp339, const341, const342 OpStore: : tmp343 >> p OpStore: : const101 >> o 346: OpAccessChain: Float*: p[0] 347: OpLoad: Float: tmp347 << p[0] 348: OpExtInst(FAbs): Float: tmp348 << tmp347 350: OpExtInst(Pow): Float: tmp350 << tmp348, const349 351: OpFSub: Float: tmp351 << const106, tmp350 352: OpAccessChain: Float*: p[1] 353: OpLoad: Float: tmp353 << p[1] 354: OpAccessChain: Float*: o[1] 355: OpLoad: Float: tmp355 << o[1] 356: OpFAdd: Float: tmp356 << tmp353, tmp355 357: OpExtInst(FAbs): Float: tmp357 << tmp356 358: OpExtInst(Pow): Float: tmp358 << tmp357, const349 359: OpFSub: Float: tmp359 << const106, tmp358 360: OpFMul: Float: tmp360 << tmp351, tmp359 362: OpFMul: Float: tmp362 << tmp360, const361 363: OpExtInst(Pow): Float: tmp363 << tmp362, const303 364: OpFSub: Float: tmp364 << const106, tmp363 OpStore: : tmp364 >> a 366: OpAccessChain: Float*: p[0] 367: OpLoad: Float: tmp367 << p[0] 368: OpExtInst(FAbs): Float: tmp368 << tmp367 369: OpExtInst(Pow): Float: tmp369 << tmp368, const349 370: OpFSub: Float: tmp370 << const106, tmp369 371: OpAccessChain: Float*: p[1] 372: OpLoad: Float: tmp372 << p[1] 373: OpExtInst(FAbs): Float: tmp373 << tmp372 374: OpExtInst(Pow): Float: tmp374 << tmp373, const349 375: OpFSub: Float: tmp375 << const106, tmp374 376: OpFMul: Float: tmp376 << tmp370, tmp375 378: OpExtInst(Pow): Float: tmp378 << tmp376, const377 OpStore: : tmp378 >> b 379: OpLoad: Float: tmp379 << a 380: OpLoad: Float: tmp380 << b 381: OpFMul: Float: tmp381 << tmp379, tmp380 382: OpFMul: Float: tmp382 << tmp381, const109 OpReturnValue: : << tmp382 48: OpFunction: Float sugarlayer(vf2;f1;(FloatVector2* t, Float* ndotv) 385: OpVariable: FloatVector2*: t2: storage class: Function 388: OpVariable: FloatVector2*: p: storage class: Function 393: OpVariable: FloatVector2*: c: storage class: Function 396: OpVariable: Float*: a: storage class: Function 404: OpVariable: FloatVector2*: o: storage class: Function 418: OpVariable: FloatVector2*: s: storage class: Function 419: OpVariable: FloatVector2*: param419: storage class: Function 426: OpVariable: FloatVector2*: param426: storage class: Function 431: OpVariable: Float*: fres: storage class: Function 445: OpVariable: Float*: param445: storage class: Function 447: OpVariable: FloatVector2*: param447: storage class: Function 449: OpVariable: FloatVector2*: param449: storage class: Function 453: OpVariable: FloatVector2*: param453: storage class: Function 49: lb49: 386: OpLoad: FloatVector2: tmp386 << t 387: OpVectorTimesScalar: FloatVector2: tmp387 << tmp386, const349 OpStore: : tmp387 >> t2 389: OpLoad: FloatVector2: tmp389 << t2 390: OpExtInst(Fract): FloatVector2: tmp390 << tmp389 392: OpFSub: FloatVector2: tmp392 << tmp390, const391 OpStore: : tmp392 >> p 394: OpLoad: FloatVector2: tmp394 << t2 395: OpExtInst(Floor): FloatVector2: tmp395 << tmp394 OpStore: : tmp395 >> c 397: OpAccessChain: Float*: c[0] 398: OpLoad: Float: tmp398 << c[0] 399: OpAccessChain: Float*: c[1] 400: OpLoad: Float: tmp400 << c[1] 402: OpFMul: Float: tmp402 << tmp400, const401 403: OpFAdd: Float: tmp403 << tmp398, tmp402 OpStore: : tmp403 >> a 405: OpAccessChain: Float*: c[1] 406: OpLoad: Float: tmp406 << c[1] 408: OpFMul: Float: tmp408 << tmp406, const407 409: OpExtInst(Cos): Float: tmp409 << tmp408 410: OpAccessChain: Float*: c[0] 411: OpLoad: Float: tmp411 << c[0] 413: OpFMul: Float: tmp413 << tmp411, const412 414: OpExtInst(Sin): Float: tmp414 << tmp413 415: OpCompositeConstruct: FloatVector2: tmp415 << tmp409, tmp414 417: OpVectorTimesScalar: FloatVector2: tmp417 << tmp415, const416 OpStore: : tmp417 >> o 420: OpLoad: FloatVector2: tmp420 << c OpStore: : tmp420 >> param419 421: OpFunctionCall: Float: smN2(vf2;(param419) 422: OpLoad: FloatVector2: tmp422 << c 425: OpFAdd: FloatVector2: tmp425 << tmp422, const424 OpStore: : tmp425 >> param426 427: OpFunctionCall: Float: smN2(vf2;(param426) 428: OpCompositeConstruct: FloatVector2: tmp428 << smN2(vf2;, smN2(vf2; 429: OpCompositeConstruct: FloatVector2: tmp429 << const106, const106 430: OpFAdd: FloatVector2: tmp430 << tmp429, tmp428 OpStore: : tmp430 >> s 432: OpLoad: Float: tmp432 << ndotv 433: OpFSub: Float: tmp433 << const106, tmp432 434: OpExtInst(Pow): Float: tmp434 << tmp433, const377 436: OpExtInst(FMix): Float: tmp436 << const106, tmp434, const435 438: OpFMul: Float: tmp438 << tmp436, const437 OpStore: : tmp438 >> fres 439: OpLoad: FloatVector2: tmp439 << p 440: OpLoad: FloatVector2: tmp440 << s 441: OpFMul: FloatVector2: tmp441 << tmp439, tmp440 442: OpVectorTimesScalar: FloatVector2: tmp442 << tmp441, const377 443: OpLoad: FloatVector2: tmp443 << o 444: OpFAdd: FloatVector2: tmp444 << tmp442, tmp443 446: OpLoad: Float: tmp446 << a OpStore: : tmp446 >> param445 OpStore: : tmp444 >> param447 448: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param445, param447) OpStore: : rotate(f1;vf2; >> param449 450: OpFunctionCall: Float: sugarybit(vf2;(param449) 451: OpLoad: FloatVector2: tmp451 << t2 452: OpVectorTimesScalar: FloatVector2: tmp452 << tmp451, const401 OpStore: : tmp452 >> param453 454: OpFunctionCall: Float: smN2(vf2;(param453) 455: OpFSub: Float: tmp455 << smN2(vf2;, const303 456: OpExtInst(FMax): Float: tmp456 << const100, tmp455 457: OpFMul: Float: tmp457 << sugarybit(vf2;, tmp456 458: OpLoad: Float: tmp458 << fres 459: OpFMul: Float: tmp459 << tmp457, tmp458 OpReturnValue: : << tmp459 52: OpFunction: FloatVector3 saturatecol(vf3;(FloatVector3* c) 463: OpVariable: Float*: param463: storage class: Function 53: lb53: 462: OpLoad: FloatVector3: tmp462 << c 464: OpLoad: Float: tmp464 << colour OpStore: : tmp464 >> param463 465: OpFunctionCall: FloatVector3: gumRamp(f1;(param463) 466: OpExtInst(Pow): FloatVector3: tmp466 << tmp462, gumRamp(f1; OpReturnValue: : << tmp466 56: OpFunction: Float sprinkles2(vf2;f1;(FloatVector2* coord, Float* ndotv) 469: OpVariable: Float*: sprinkle: storage class: Function 470: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 493: OpVariable: FloatVector2*: param493: storage class: Function 494: OpVariable: Float*: param494: storage class: Function 57: lb57: OpStore: : const100 >> sprinkle OpStore: : const471 >> i OpBranch: to lb472 472: lb472: OpLoopMerge: (merge: lb474, continue: lb475) OpBranch: to lb476 476: lb476: 477: OpLoad: Int: tmp477 << i Decorators: RelaxedPrecision 479: OpSLessThan: Bool: tmp479 << tmp477, const478 OpBranchConditional: if(tmp479) then branch to lb473, else branch to lb474 473: lb473: 480: OpLoad: FloatVector2: tmp480 << coord 481: OpLoad: Int: tmp481 << i Decorators: RelaxedPrecision 482: OpConvertSToF: Float: tmp482 << tmp481 484: OpFMul: Float: tmp484 << tmp482, const483 485: OpCompositeConstruct: FloatVector2: tmp485 << tmp484, tmp484 486: OpFAdd: FloatVector2: tmp486 << tmp480, tmp485 487: OpLoad: Int: tmp487 << i Decorators: RelaxedPrecision 488: OpConvertSToF: Float: tmp488 << tmp487 490: OpFMul: Float: tmp490 << tmp488, const489 491: OpFAdd: Float: tmp491 << const106, tmp490 492: OpVectorTimesScalar: FloatVector2: tmp492 << tmp486, tmp491 OpStore: : tmp492 >> param493 495: OpLoad: Float: tmp495 << ndotv OpStore: : tmp495 >> param494 496: OpFunctionCall: Float: sugarlayer(vf2;f1;(param493, param494) 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision 498: OpConvertSToF: Float: tmp498 << tmp497 499: OpFDiv: Float: tmp499 << tmp498, const377 500: OpFSub: Float: tmp500 << const106, tmp499 501: OpExtInst(Pow): Float: tmp501 << tmp500, const377 502: OpFMul: Float: tmp502 << sugarlayer(vf2;f1;, tmp501 503: OpLoad: Float: tmp503 << sprinkle 504: OpFAdd: Float: tmp504 << tmp503, tmp502 OpStore: : tmp504 >> sprinkle OpBranch: to lb475 475: lb475: 505: OpLoad: Int: tmp505 << i Decorators: RelaxedPrecision 506: OpIAdd: Int: tmp506 << tmp505, const285 Decorators: RelaxedPrecision OpStore: : tmp506 >> i OpBranch: to lb472 474: lb474: 507: OpLoad: Float: tmp507 << sprinkle OpReturnValue: : << tmp507 60: OpFunction: Float sprinkles(vf2;f1;(FloatVector2* coord, Float* ndotv) 513: OpVariable: FloatVector2*: param513: storage class: Function 514: OpVariable: Float*: param514: storage class: Function 519: OpVariable: FloatVector2*: param519: storage class: Function 520: OpVariable: Float*: param520: storage class: Function 61: lb61: 510: OpLoad: FloatVector2: tmp510 << coord 512: OpVectorTimesScalar: FloatVector2: tmp512 << tmp510, const511 OpStore: : tmp512 >> param513 515: OpLoad: Float: tmp515 << ndotv OpStore: : tmp515 >> param514 516: OpFunctionCall: Float: sprinkles2(vf2;f1;(param513, param514) 517: OpLoad: FloatVector2: tmp517 << coord 518: OpVectorTimesScalar: FloatVector2: tmp518 << tmp517, const127 OpStore: : tmp518 >> param519 521: OpLoad: Float: tmp521 << ndotv OpStore: : tmp521 >> param520 522: OpFunctionCall: Float: sprinkles2(vf2;f1;(param519, param520) 524: OpFMul: Float: tmp524 << sprinkles2(vf2;f1;, const523 525: OpFAdd: Float: tmp525 << sprinkles2(vf2;f1;, tmp524 OpReturnValue: : << tmp525 66: OpFunction: FloatVector3 gummy(vf3;vf3;vf3;(FloatVector3* no, FloatVector3* vo, FloatVector3* v) 528: OpVariable: Float*: ndotv: storage class: Function 533: OpVariable: Float*: s0: storage class: Function 544: OpVariable: FloatVector2*: param544: storage class: Function 545: OpVariable: Float*: param545: storage class: Function 548: OpVariable: Float*: s1: storage class: Function 549: OpVariable: FloatVector2*: param549: storage class: Function 552: OpVariable: Float*: param552: storage class: Function 555: OpVariable: Float*: sprinkle: storage class: Function 562: OpVariable: Float*: ss: storage class: Function 568: OpVariable: FloatVector3*: tex: storage class: Function 570: OpVariable: Float*: param570: storage class: Function 591: OpVariable: FloatVector3*: param591: storage class: Function 67: lb67: 529: OpLoad: FloatVector3: tmp529 << no 530: OpLoad: FloatVector3: tmp530 << v 531: OpFNegate: FloatVector3: tmp531 << tmp530 532: OpDot: Float: tmp532 << tmp529, tmp531 OpStore: : tmp532 >> ndotv 534: OpAccessChain: Float*: no[2] 535: OpLoad: Float: tmp535 << no[2] 536: OpAccessChain: Float*: no[0] 537: OpLoad: Float: tmp537 << no[0] 538: OpExtInst(Atan2): Float: tmp538 << tmp535, tmp537 539: OpAccessChain: Float*: no[1] 540: OpLoad: Float: tmp540 << no[1] 541: OpExtInst(Asin): Float: tmp541 << tmp540 542: OpCompositeConstruct: FloatVector2: tmp542 << tmp538, tmp541 543: OpVectorTimesScalar: FloatVector2: tmp543 << tmp542, const511 OpStore: : tmp543 >> param544 546: OpLoad: Float: tmp546 << ndotv OpStore: : tmp546 >> param545 547: OpFunctionCall: Float: sprinkles(vf2;f1;(param544, param545) OpStore: : sprinkles(vf2;f1; >> s0 550: OpLoad: FloatVector3: tmp550 << vo 551: OpVectorShuffle: FloatVector2: tmp551 << tmp550, tmp550, 0, 2 OpStore: : tmp551 >> param549 553: OpLoad: Float: tmp553 << ndotv OpStore: : tmp553 >> param552 554: OpFunctionCall: Float: sprinkles(vf2;f1;(param549, param552) OpStore: : sprinkles(vf2;f1; >> s1 556: OpLoad: Float: tmp556 << s0 557: OpLoad: Float: tmp557 << s1 558: OpAccessChain: Float*: no[1] 559: OpLoad: Float: tmp559 << no[1] 560: OpExtInst(SmoothStep): Float: tmp560 << const523, const303, tmp559 561: OpExtInst(FMix): Float: tmp561 << tmp556, tmp557, tmp560 OpStore: : tmp561 >> sprinkle 563: OpAccessChain: Float*: no[1] 564: OpLoad: Float: tmp564 << no[1] 565: OpFSub: Float: tmp565 << tmp564, const523 566: OpFMul: Float: tmp566 << tmp565, const401 567: OpExtInst(FClamp): Float: tmp567 << tmp566, const100, const106 OpStore: : tmp567 >> ss 571: OpLoad: Float: tmp571 << colour OpStore: : tmp571 >> param570 572: OpFunctionCall: FloatVector3: gumColour(f1;(param570) 574: OpCompositeConstruct: FloatVector3: tmp574 << const573, const573, const573 575: OpExtInst(FMix): FloatVector3: tmp575 << const569, gumColour(f1;, tmp574 577: OpAccessChain: Float*: tc[0] 578: OpLoad: Float: tmp578 << tc[0] 579: OpExtInst(FAbs): Float: tmp579 << tmp578 580: OpFSub: Float: tmp580 << const106, tmp579 581: OpFMul: Float: tmp581 << tmp580, const303 582: OpExtInst(Pow): Float: tmp582 << tmp581, const489 583: OpFAdd: Float: tmp583 << const576, tmp582 584: OpVectorTimesScalar: FloatVector3: tmp584 << tmp575, tmp583 586: OpLoad: Float: tmp586 << sprinkle 587: OpLoad: Float: tmp587 << ss 588: OpFMul: Float: tmp588 << tmp586, tmp587 589: OpCompositeConstruct: FloatVector3: tmp589 << tmp588, tmp588, tmp588 590: OpExtInst(FMix): FloatVector3: tmp590 << tmp584, const585, tmp589 OpStore: : tmp590 >> param591 592: OpFunctionCall: FloatVector3: saturatecol(vf3;(param591) OpStore: : saturatecol(vf3; >> tex 594: OpLoad: Float: tmp594 << ndotv 595: OpFSub: Float: tmp595 << const593, tmp594 596: OpLoad: FloatVector3: tmp596 << tex 597: OpVectorTimesScalar: FloatVector3: tmp597 << tmp596, tmp595 OpStore: : tmp597 >> tex 598: OpLoad: Float: tmp598 << ndotv 599: OpFSub: Float: tmp599 << const106, tmp598 600: OpExtInst(Pow): Float: tmp600 << tmp599, const349 601: OpCompositeConstruct: FloatVector3: tmp601 << tmp600, tmp600, tmp600 603: OpVectorTimesScalar: FloatVector3: tmp603 << tmp601, const602 604: OpLoad: FloatVector3: tmp604 << tex 605: OpFAdd: FloatVector3: tmp605 << tmp604, tmp603 OpStore: : tmp605 >> tex 606: OpLoad: FloatVector3: tmp606 << tex OpReturnValue: : << tmp606 69: OpFunction: Float de(vf3;(FloatVector3* p) 614: OpVariable: FloatVector3*: fp: storage class: Function 631: OpVariable: Float*: ff: storage class: Function 635: OpVariable: FloatVector3*: param635: storage class: Function 643: OpVariable: FloatVector3*: param643: storage class: Function 685: OpVariable: Float*: sp: storage class: Function 690: OpVariable: Float*: pl: storage class: Function 694: OpVariable: Float*: d: storage class: Function 70: lb70: 610: OpAccessChain: Float*: p[1] 611: OpLoad: Float: tmp611 << p[1] 612: OpFMul: Float: tmp612 << tmp611, const609 613: OpAccessChain: Float*: p[1] OpStore: : tmp612 >> p[1] 615: OpLoad: FloatVector3: tmp615 << p 616: OpCompositeConstruct: FloatVector3: tmp616 << const109, const109, const109 617: OpFDiv: FloatVector3: tmp617 << tmp615, tmp616 618: OpExtInst(Floor): FloatVector3: tmp618 << tmp617 OpStore: : tmp618 >> fp 619: OpAccessChain: Float*: fp[0] 620: OpLoad: Float: tmp620 << fp[0] 622: OpFMul: Float: tmp622 << tmp620, const621 623: OpAccessChain: Float*: fp[2] 624: OpLoad: Float: tmp624 << fp[2] 626: OpFMul: Float: tmp626 << tmp624, const625 627: OpFSub: Float: tmp627 << tmp622, tmp626 628: OpExtInst(Cos): Float: tmp628 << tmp627 629: OpFAdd: Float: tmp629 << tmp628, const576 630: OpExtInst(Step): Float: tmp630 << const100, tmp629 OpStore: : tmp630 >> is_choc 632: OpLoad: FloatVector3: tmp632 << p 634: OpVectorTimesScalar: FloatVector3: tmp634 << tmp632, const633 OpStore: : tmp634 >> param635 636: OpFunctionCall: Float: smN3(vf3;(param635) 638: OpFMul: Float: tmp638 << smN3(vf3;, const637 639: OpLoad: Float: tmp639 << is_choc 640: OpFMul: Float: tmp640 << tmp638, tmp639 641: OpLoad: FloatVector3: tmp641 << p 642: OpVectorTimesScalar: FloatVector3: tmp642 << tmp641, const401 OpStore: : tmp642 >> param643 644: OpFunctionCall: Float: smN3(vf3;(param643) 645: OpExtInst(FMax): Float: tmp645 << const100, smN3(vf3; 646: OpExtInst(Pow): Float: tmp646 << tmp645, const401 648: OpLoad: Float: tmp648 << is_choc 649: OpFSub: Float: tmp649 << const106, tmp648 650: OpFMul: Float: tmp650 << const647, tmp649 651: OpFAdd: Float: tmp651 << const602, tmp650 652: OpFMul: Float: tmp652 << tmp646, tmp651 653: OpFSub: Float: tmp653 << tmp640, tmp652 OpStore: : tmp653 >> ff 654: OpAccessChain: Float*: fp[0] 655: OpLoad: Float: tmp655 << fp[0] 656: OpAccessChain: Float*: fp[2] 657: OpLoad: Float: tmp657 << fp[2] 658: OpExtInst(Sin): Float: tmp658 << tmp657 659: OpFMul: Float: tmp659 << tmp658, const109 660: OpFAdd: Float: tmp660 << tmp655, tmp659 661: OpFMod: Float: tmp661 << tmp660, const377 OpStore: : tmp661 >> colour 662: OpLoad: FloatVector3: tmp662 << p 663: OpVectorShuffle: FloatVector2: tmp663 << tmp662, tmp662, 0, 2 665: OpFMod: FloatVector2: tmp665 << tmp663, const664 668: OpFSub: FloatVector2: tmp668 << tmp665, const667 669: OpLoad: FloatVector3: tmp669 << p 670: OpVectorShuffle: FloatVector3: tmp670 << tmp669, tmp668, 3, 1, 4 OpStore: : tmp670 >> p 672: OpAccessChain: Float*: fp[2] 673: OpLoad: Float: tmp673 << fp[2] 675: OpFMul: Float: tmp675 << tmp673, const674 676: OpAccessChain: Float*: fp[0] 677: OpLoad: Float: tmp677 << fp[0] 679: OpFMul: Float: tmp679 << tmp677, const678 680: OpFAdd: Float: tmp680 << tmp675, tmp679 681: OpExtInst(Cos): Float: tmp681 << tmp680 682: OpFMul: Float: tmp682 << const303, tmp681 683: OpFAdd: Float: tmp683 << const303, tmp682 684: OpExtInst(FMix): Float: tmp684 << const671, const106, tmp683 OpStore: : tmp684 >> ss 686: OpLoad: FloatVector3: tmp686 << p 687: OpExtInst(Length): Float: tmp687 << tmp686 688: OpLoad: Float: tmp688 << ss 689: OpFSub: Float: tmp689 << tmp687, tmp688 OpStore: : tmp689 >> sp 691: OpAccessChain: Float*: p[1] 692: OpLoad: Float: tmp692 << p[1] 693: OpFNegate: Float: tmp693 << tmp692 OpStore: : tmp693 >> pl 695: OpLoad: Float: tmp695 << sp 696: OpExtInst(FMax): Float: tmp696 << const100, tmp695 697: OpLoad: Float: tmp697 << pl 698: OpExtInst(FMax): Float: tmp698 << const100, tmp697 699: OpCompositeConstruct: FloatVector2: tmp699 << tmp696, tmp698 700: OpExtInst(Length): Float: tmp700 << tmp699 701: OpFSub: Float: tmp701 << tmp700, const576 702: OpLoad: Float: tmp702 << ff 703: OpFAdd: Float: tmp703 << tmp701, tmp702 705: OpFMul: Float: tmp705 << tmp703, const704 OpStore: : tmp705 >> d 706: OpLoad: Float: tmp706 << d OpReturnValue: : << tmp706 73: OpFunction: FloatVector3 marble(vf2;(FloatVector2* p) 713: OpVariable: Float*: border_size: storage class: Function 715: OpVariable: Float*: corner_size: storage class: Function 716: OpVariable: FloatVector2*: c0: storage class: Function 719: OpVariable: FloatVector2*: c1: storage class: Function 724: OpVariable: FloatVector2*: rc1: storage class: Function 734: OpVariable: FloatVector3*: ccol: storage class: Function 740: OpVariable: FloatVector3*: param740: storage class: Function 747: OpVariable: FloatVector3*: pat: storage class: Function 767: OpVariable: FloatVector3*: param767: storage class: Function 779: OpVariable: FloatVector3*: param779: storage class: Function 790: OpVariable: FloatVector3*: param790: storage class: Function 796: OpVariable: FloatVector3*: bcol: storage class: Function 800: OpVariable: Float*: br: storage class: Function 814: OpVariable: Float*: cr: storage class: Function 74: lb74: 709: OpAccessChain: Float*: p[0] 710: OpLoad: Float: tmp710 << p[0] 711: OpFAdd: Float: tmp711 << tmp710, const127 712: OpAccessChain: Float*: p[0] OpStore: : tmp711 >> p[0] OpStore: : const714 >> border_size OpStore: : const714 >> corner_size 717: OpLoad: FloatVector2: tmp717 << p 718: OpExtInst(Floor): FloatVector2: tmp718 << tmp717 OpStore: : tmp718 >> c0 720: OpLoad: FloatVector2: tmp720 << p 721: OpLoad: FloatVector2: tmp721 << c0 722: OpFSub: FloatVector2: tmp722 << tmp720, tmp721 723: OpFSub: FloatVector2: tmp723 << tmp722, const391 OpStore: : tmp723 >> c1 725: OpAccessChain: Float*: c1[0] 726: OpLoad: Float: tmp726 << c1[0] 727: OpVectorTimesScalar: FloatVector2: tmp727 << const342, tmp726 728: OpAccessChain: Float*: c1[1] 729: OpLoad: Float: tmp729 << c1[1] 731: OpVectorTimesScalar: FloatVector2: tmp731 << const730, tmp729 732: OpFAdd: FloatVector2: tmp732 << tmp727, tmp731 733: OpVectorTimesScalar: FloatVector2: tmp733 << tmp732, const704 OpStore: : tmp733 >> rc1 736: OpLoad: FloatVector2: tmp736 << p 737: OpCompositeExtract: Float: tmp737 << tmp736, 0 738: OpCompositeExtract: Float: tmp738 << tmp736, 1 739: OpCompositeConstruct: FloatVector3: tmp739 << tmp737, tmp738, const100 OpStore: : tmp739 >> param740 741: OpFunctionCall: Float: fbm3(vf3;(param740) 742: OpFMul: Float: tmp742 << fbm3(vf3;, const303 743: OpExtInst(FMax): Float: tmp743 << const100, tmp742 744: OpCompositeConstruct: FloatVector3: tmp744 << tmp743, tmp743, tmp743 745: OpCompositeConstruct: FloatVector3: tmp745 << const511, const511, const511 746: OpExtInst(FMix): FloatVector3: tmp746 << const735, tmp744, tmp745 OpStore: : tmp746 >> ccol 753: OpLoad: FloatVector2: tmp753 << c0 754: OpVectorTimesScalar: FloatVector2: tmp754 << tmp753, const127 755: OpLoad: FloatVector2: tmp755 << p 756: OpVectorTimesScalar: FloatVector2: tmp756 << tmp755, const106 757: OpFAdd: FloatVector2: tmp757 << tmp754, tmp756 758: OpLoad: FloatVector2: tmp758 << p 759: OpVectorShuffle: FloatVector2: tmp759 << tmp758, tmp758, 1, 0 760: OpVectorTimesScalar: FloatVector2: tmp760 << tmp759, const127 761: OpExtInst(Cos): FloatVector2: tmp761 << tmp760 762: OpVectorTimesScalar: FloatVector2: tmp762 << tmp761, const748 763: OpFAdd: FloatVector2: tmp763 << tmp757, tmp762 764: OpCompositeExtract: Float: tmp764 << tmp763, 0 765: OpCompositeExtract: Float: tmp765 << tmp763, 1 766: OpCompositeConstruct: FloatVector3: tmp766 << tmp764, tmp765, const100 OpStore: : tmp766 >> param767 768: OpFunctionCall: Float: fbm3(vf3;(param767) 769: OpFAdd: Float: tmp769 << const303, fbm3(vf3; 770: OpExtInst(SmoothStep): Float: tmp770 << const748, const151, tmp769 771: OpFSub: Float: tmp771 << const106, tmp770 772: OpCompositeConstruct: FloatVector3: tmp772 << tmp771, tmp771, tmp771 773: OpExtInst(FMix): FloatVector3: tmp773 << const750, const752, tmp772 774: OpLoad: FloatVector2: tmp774 << p 775: OpVectorTimesScalar: FloatVector2: tmp775 << tmp774, const671 776: OpCompositeExtract: Float: tmp776 << tmp775, 0 777: OpCompositeExtract: Float: tmp777 << tmp775, 1 778: OpCompositeConstruct: FloatVector3: tmp778 << tmp776, tmp777, const100 OpStore: : tmp778 >> param779 780: OpFunctionCall: Float: fbm3(vf3;(param779) 781: OpFMul: Float: tmp781 << fbm3(vf3;, const106 782: OpExtInst(FMax): Float: tmp782 << const100, tmp781 783: OpCompositeConstruct: FloatVector3: tmp783 << tmp782, tmp782, tmp782 784: OpFAdd: FloatVector3: tmp784 << tmp773, tmp783 785: OpLoad: FloatVector2: tmp785 << p 786: OpFNegate: FloatVector2: tmp786 << tmp785 787: OpCompositeExtract: Float: tmp787 << tmp786, 0 788: OpCompositeExtract: Float: tmp788 << tmp786, 1 789: OpCompositeConstruct: FloatVector3: tmp789 << tmp787, tmp788, const100 OpStore: : tmp789 >> param790 791: OpFunctionCall: Float: fbm3(vf3;(param790) 792: OpExtInst(SmoothStep): Float: tmp792 << const489, const523, fbm3(vf3; 793: OpCompositeConstruct: FloatVector3: tmp793 << tmp792, tmp792, tmp792 794: OpVectorTimesScalar: FloatVector3: tmp794 << tmp793, const489 795: OpFAdd: FloatVector3: tmp795 << tmp784, tmp794 OpStore: : tmp795 >> pat 797: OpLoad: FloatVector3: tmp797 << pat 798: OpCompositeConstruct: FloatVector3: tmp798 << const303, const303, const303 799: OpExtInst(FMix): FloatVector3: tmp799 << tmp797, const735, tmp798 OpStore: : tmp799 >> bcol 801: OpLoad: Float: tmp801 << border_size 802: OpFSub: Float: tmp802 << const303, tmp801 803: OpAccessChain: Float*: c1[1] 804: OpLoad: Float: tmp804 << c1[1] 805: OpExtInst(FAbs): Float: tmp805 << tmp804 806: OpExtInst(SmoothStep): Float: tmp806 << tmp802, const303, tmp805 807: OpLoad: Float: tmp807 << border_size 808: OpFSub: Float: tmp808 << const303, tmp807 809: OpAccessChain: Float*: c1[0] 810: OpLoad: Float: tmp810 << c1[0] 811: OpExtInst(FAbs): Float: tmp811 << tmp810 812: OpExtInst(SmoothStep): Float: tmp812 << tmp808, const303, tmp811 813: OpExtInst(FMax): Float: tmp813 << tmp806, tmp812 OpStore: : tmp813 >> br 815: OpLoad: Float: tmp815 << corner_size 816: OpFSub: Float: tmp816 << const303, tmp815 817: OpAccessChain: Float*: rc1[1] 818: OpLoad: Float: tmp818 << rc1[1] 819: OpExtInst(FAbs): Float: tmp819 << tmp818 820: OpExtInst(SmoothStep): Float: tmp820 << tmp816, const303, tmp819 821: OpLoad: Float: tmp821 << corner_size 822: OpFSub: Float: tmp822 << const303, tmp821 823: OpAccessChain: Float*: rc1[0] 824: OpLoad: Float: tmp824 << rc1[0] 825: OpExtInst(FAbs): Float: tmp825 << tmp824 826: OpExtInst(SmoothStep): Float: tmp826 << tmp822, const303, tmp825 827: OpExtInst(FMax): Float: tmp827 << tmp820, tmp826 OpStore: : tmp827 >> cr 828: OpLoad: FloatVector3: tmp828 << pat 829: OpLoad: FloatVector3: tmp829 << bcol 830: OpLoad: FloatVector3: tmp830 << ccol 831: OpLoad: Float: tmp831 << cr 832: OpCompositeConstruct: FloatVector3: tmp832 << tmp831, tmp831, tmp831 833: OpExtInst(FMix): FloatVector3: tmp833 << tmp829, tmp830, tmp832 834: OpLoad: Float: tmp834 << cr 835: OpLoad: Float: tmp835 << br 836: OpExtInst(FMax): Float: tmp836 << tmp834, tmp835 837: OpCompositeConstruct: FloatVector3: tmp837 << tmp836, tmp836, tmp836 838: OpExtInst(FMix): FloatVector3: tmp838 << tmp828, tmp833, tmp837 839: OpVectorTimesScalar: FloatVector3: tmp839 << tmp838, const151 OpReturnValue: : << tmp839 76: OpFunction: FloatVector3 cameraPos(f1;(Float* t) 77: lb77: 842: OpLoad: Float: tmp842 << t 843: OpFMul: Float: tmp843 << tmp842, const704 845: OpLoad: Float: tmp845 << t 846: OpFMul: Float: tmp846 << tmp845, const377 847: OpExtInst(Cos): Float: tmp847 << tmp846 849: OpFMul: Float: tmp849 << tmp847, const848 850: OpFAdd: Float: tmp850 << const844, tmp849 851: OpCompositeConstruct: FloatVector3: tmp851 << tmp843, tmp850, const100 OpReturnValue: : << tmp851 79: OpFunction: FloatVector3 targetPos(f1;(Float* ti) 854: OpVariable: FloatVector3*: target: storage class: Function 858: OpVariable: Float*: param858: storage class: Function 80: lb80: 855: OpLoad: Float: tmp855 << ti 856: OpLoad: Float: tmp856 << t_per_target 857: OpFMul: Float: tmp857 << tmp855, tmp856 OpStore: : tmp857 >> param858 859: OpFunctionCall: FloatVector3: cameraPos(f1;(param858) 861: OpFMul: FloatVector3: tmp861 << cameraPos(f1;, const860 862: OpLoad: Float: tmp862 << ti 864: OpFMul: Float: tmp864 << tmp862, const863 865: OpExtInst(Cos): Float: tmp865 << tmp864 866: OpFMul: Float: tmp866 << tmp865, const377 868: OpLoad: Float: tmp868 << ti 870: OpFMul: Float: tmp870 << tmp868, const869 871: OpExtInst(Cos): Float: tmp871 << tmp870 872: OpFMul: Float: tmp872 << tmp871, const109 873: OpFAdd: Float: tmp873 << const867, tmp872 874: OpCompositeConstruct: FloatVector3: tmp874 << tmp866, const100, tmp873 875: OpFAdd: FloatVector3: tmp875 << tmp861, tmp874 OpStore: : tmp875 >> target 876: OpLoad: FloatVector3: tmp876 << target 877: OpVectorShuffle: FloatVector2: tmp877 << tmp876, tmp876, 0, 2 878: OpCompositeConstruct: FloatVector2: tmp878 << const109, const109 879: OpFDiv: FloatVector2: tmp879 << tmp877, tmp878 880: OpExtInst(Floor): FloatVector2: tmp880 << tmp879 881: OpVectorTimesScalar: FloatVector2: tmp881 << tmp880, const109 882: OpFAdd: FloatVector2: tmp882 << tmp881, const667 883: OpLoad: FloatVector3: tmp883 << target 884: OpVectorShuffle: FloatVector3: tmp884 << tmp883, tmp882, 3, 1, 4 OpStore: : tmp884 >> target 885: OpLoad: FloatVector3: tmp885 << target OpReturnValue: : << tmp885 82: OpFunction: Float cameraZoom(f1;(Float* ti) 83: lb83: 889: OpLoad: Float: tmp889 << ti 890: OpFMul: Float: tmp890 << tmp889, const633 891: OpExtInst(Cos): Float: tmp891 << tmp890 892: OpFMul: Float: tmp892 << const303, tmp891 893: OpFAdd: Float: tmp893 << const303, tmp892 894: OpExtInst(FMix): Float: tmp894 << const109, const888, tmp893 896: OpFMul: Float: tmp896 << tmp894, const895 OpReturnValue: : << tmp896 89: OpFunction: FloatVector3 trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* t, Float* max_t) 899: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 908: OpVariable: Float*: d: storage class: Function 914: OpVariable: FloatVector3*: param914: storage class: Function 938: OpVariable: FloatVector3*: rp: storage class: Function 944: OpVariable: FloatVector3*: col: storage class: Function 947: OpVariable: Float*: e: storage class: Function 948: OpVariable: Float*: c: storage class: Function 949: OpVariable: FloatVector3*: param949: storage class: Function 952: OpVariable: FloatVector3*: n: storage class: Function 957: OpVariable: FloatVector3*: param957: storage class: Function 965: OpVariable: FloatVector3*: param965: storage class: Function 973: OpVariable: FloatVector3*: param973: storage class: Function 979: OpVariable: FloatVector3*: v: storage class: Function 981: OpVariable: FloatVector3*: h: storage class: Function 998: OpVariable: Float*: r: storage class: Function 1011: OpVariable: FloatVector3*: chocolour: storage class: Function 1028: OpVariable: FloatVector3*: param1028: storage class: Function 1079: OpVariable: FloatVector3*: param1079: storage class: Function 1081: OpVariable: FloatVector3*: param1081: storage class: Function 1083: OpVariable: FloatVector3*: param1083: storage class: Function 90: lb90: OpStore: : const471 >> i OpBranch: to lb900 900: lb900: OpLoopMerge: (merge: lb902, continue: lb903) OpBranch: to lb904 904: lb904: 905: OpLoad: Int: tmp905 << i Decorators: RelaxedPrecision 907: OpSLessThan: Bool: tmp907 << tmp905, const906 OpBranchConditional: if(tmp907) then branch to lb901, else branch to lb902 901: lb901: 909: OpLoad: FloatVector3: tmp909 << ro 910: OpLoad: FloatVector3: tmp910 << rd 911: OpLoad: Float: tmp911 << t 912: OpVectorTimesScalar: FloatVector3: tmp912 << tmp910, tmp911 913: OpFAdd: FloatVector3: tmp913 << tmp909, tmp912 OpStore: : tmp913 >> param914 915: OpFunctionCall: Float: de(vf3;(param914) OpStore: : de(vf3; >> d 916: OpLoad: Float: tmp916 << t 917: OpLoad: Float: tmp917 << max_t 918: OpFOrdGreaterThan: Bool: tmp918 << tmp916, tmp917 OpSelectionMerge: (merge: lb920) OpBranchConditional: if(tmp918) then branch to lb919, else branch to lb920 919: lb919: OpReturnValue: : << const921 920: lb920: 923: OpLoad: Float: tmp923 << d 924: OpExtInst(FAbs): Float: tmp924 << tmp923 926: OpFOrdLessThan: Bool: tmp926 << tmp924, const925 OpSelectionMerge: (merge: lb928) OpBranchConditional: if(tmp926) then branch to lb927, else branch to lb928 927: lb927: OpBranch: to lb902 928: lb928: 930: OpLoad: Float: tmp930 << max_t 931: OpFAdd: Float: tmp931 << tmp930, const637 932: OpLoad: Float: tmp932 << t 933: OpLoad: Float: tmp933 << d 934: OpFAdd: Float: tmp934 << tmp932, tmp933 935: OpExtInst(FMin): Float: tmp935 << tmp931, tmp934 OpStore: : tmp935 >> t OpBranch: to lb903 903: lb903: 936: OpLoad: Int: tmp936 << i Decorators: RelaxedPrecision 937: OpIAdd: Int: tmp937 << tmp936, const285 Decorators: RelaxedPrecision OpStore: : tmp937 >> i OpBranch: to lb900 902: lb902: 939: OpLoad: FloatVector3: tmp939 << ro 940: OpLoad: FloatVector3: tmp940 << rd 941: OpLoad: Float: tmp941 << t 942: OpVectorTimesScalar: FloatVector3: tmp942 << tmp940, tmp941 943: OpFAdd: FloatVector3: tmp943 << tmp939, tmp942 OpStore: : tmp943 >> rp OpStore: : const946 >> col OpStore: : const637 >> e 950: OpLoad: FloatVector3: tmp950 << rp OpStore: : tmp950 >> param949 951: OpFunctionCall: Float: de(vf3;(param949) OpStore: : de(vf3; >> c 953: OpLoad: FloatVector3: tmp953 << rp 954: OpLoad: Float: tmp954 << e 955: OpCompositeConstruct: FloatVector3: tmp955 << tmp954, const100, const100 956: OpFAdd: FloatVector3: tmp956 << tmp953, tmp955 OpStore: : tmp956 >> param957 958: OpFunctionCall: Float: de(vf3;(param957) 959: OpLoad: Float: tmp959 << c 960: OpFSub: Float: tmp960 << de(vf3;, tmp959 961: OpLoad: FloatVector3: tmp961 << rp 962: OpLoad: Float: tmp962 << e 963: OpCompositeConstruct: FloatVector3: tmp963 << const100, tmp962, const100 964: OpFAdd: FloatVector3: tmp964 << tmp961, tmp963 OpStore: : tmp964 >> param965 966: OpFunctionCall: Float: de(vf3;(param965) 967: OpLoad: Float: tmp967 << c 968: OpFSub: Float: tmp968 << de(vf3;, tmp967 969: OpLoad: FloatVector3: tmp969 << rp 970: OpLoad: Float: tmp970 << e 971: OpCompositeConstruct: FloatVector3: tmp971 << const100, const100, tmp970 972: OpFAdd: FloatVector3: tmp972 << tmp969, tmp971 OpStore: : tmp972 >> param973 974: OpFunctionCall: Float: de(vf3;(param973) 975: OpLoad: Float: tmp975 << c 976: OpFSub: Float: tmp976 << de(vf3;, tmp975 977: OpCompositeConstruct: FloatVector3: tmp977 << tmp960, tmp968, tmp976 978: OpExtInst(Normalize): FloatVector3: tmp978 << tmp977 OpStore: : tmp978 >> n 980: OpLoad: FloatVector3: tmp980 << rd OpStore: : tmp980 >> v 982: OpLoad: FloatVector3: tmp982 << l 983: OpLoad: FloatVector3: tmp983 << rd 984: OpFSub: FloatVector3: tmp984 << tmp982, tmp983 985: OpExtInst(Normalize): FloatVector3: tmp985 << tmp984 OpStore: : tmp985 >> h 986: OpLoad: Float: tmp986 << is_choc 987: OpFOrdLessThan: Bool: tmp987 << tmp986, const303 OpSelectionMerge: (merge: lb989) OpBranchConditional: if(tmp987) then branch to lb988, else branch to lb1078 988: lb988: 990: OpAccessChain: Float*: rp[0] 991: OpLoad: Float: tmp991 << rp[0] 992: OpFDiv: Float: tmp992 << tmp991, const109 993: OpExtInst(Floor): Float: tmp993 << tmp992 994: OpFMod: Float: tmp994 << tmp993, const127 995: OpFOrdGreaterThan: Bool: tmp995 << tmp994, const303 OpSelectionMerge: (merge: lb997) OpBranchConditional: if(tmp995) then branch to lb996, else branch to lb1034 996: lb996: 999: OpLoad: FloatVector3: tmp999 << rp 1000: OpVectorShuffle: FloatVector2: tmp1000 << tmp999, tmp999, 0, 2 1001: OpLoad: FloatVector3: tmp1001 << rp 1002: OpVectorShuffle: FloatVector2: tmp1002 << tmp1001, tmp1001, 0, 2 1003: OpCompositeConstruct: FloatVector2: tmp1003 << const109, const109 1004: OpFDiv: FloatVector2: tmp1004 << tmp1002, tmp1003 1005: OpExtInst(Floor): FloatVector2: tmp1005 << tmp1004 1006: OpVectorTimesScalar: FloatVector2: tmp1006 << tmp1005, const109 1007: OpFAdd: FloatVector2: tmp1007 << tmp1006, const667 1008: OpExtInst(Distance): Float: tmp1008 << tmp1000, tmp1007 1009: OpFMul: Float: tmp1009 << tmp1008, const704 1010: OpExtInst(Pow): Float: tmp1010 << tmp1009, const127 OpStore: : tmp1010 >> r 1018: OpLoad: Float: tmp1018 << r 1019: OpFAdd: Float: tmp1019 << const303, tmp1018 1020: OpLoad: Float: tmp1020 << r 1021: OpFAdd: Float: tmp1021 << const704, tmp1020 1022: OpLoad: FloatVector3: tmp1022 << rp 1023: OpVectorShuffle: FloatVector2: tmp1023 << tmp1022, tmp1022, 0, 2 1024: OpVectorTimesScalar: FloatVector2: tmp1024 << tmp1023, const621 1025: OpCompositeExtract: Float: tmp1025 << tmp1024, 0 1026: OpCompositeExtract: Float: tmp1026 << tmp1024, 1 1027: OpCompositeConstruct: FloatVector3: tmp1027 << tmp1025, tmp1026, const100 OpStore: : tmp1027 >> param1028 1029: OpFunctionCall: Float: fbm3(vf3;(param1028) 1030: OpFAdd: Float: tmp1030 << const748, fbm3(vf3; 1031: OpExtInst(SmoothStep): Float: tmp1031 << tmp1019, tmp1021, tmp1030 1032: OpCompositeConstruct: FloatVector3: tmp1032 << tmp1031, tmp1031, tmp1031 1033: OpExtInst(FMix): FloatVector3: tmp1033 << const1013, const1017, tmp1032 OpStore: : tmp1033 >> chocolour OpBranch: to lb997 1034: lb1034: 1036: OpAccessChain: Float*: rp[0] 1037: OpLoad: Float: tmp1037 << rp[0] 1038: OpFMul: Float: tmp1038 << tmp1037, const621 1039: OpAccessChain: Float*: rp[2] 1040: OpLoad: Float: tmp1040 << rp[2] 1041: OpFMul: Float: tmp1041 << tmp1040, const401 1042: OpExtInst(Sin): Float: tmp1042 << tmp1041 1043: OpFAdd: Float: tmp1043 << tmp1038, tmp1042 1044: OpExtInst(Cos): Float: tmp1044 << tmp1043 1045: OpFMul: Float: tmp1045 << const303, tmp1044 1046: OpFAdd: Float: tmp1046 << const303, tmp1045 1047: OpExtInst(SmoothStep): Float: tmp1047 << const671, const435, tmp1046 1048: OpCompositeConstruct: FloatVector3: tmp1048 << tmp1047, tmp1047, tmp1047 1049: OpExtInst(FMix): FloatVector3: tmp1049 << const1035, const1013, tmp1048 OpStore: : tmp1049 >> chocolour OpBranch: to lb997 997: lb997: 1050: OpLoad: FloatVector3: tmp1050 << chocolour 1051: OpVectorTimesScalar: FloatVector3: tmp1051 << tmp1050, const576 1052: OpLoad: FloatVector3: tmp1052 << n 1053: OpLoad: FloatVector3: tmp1053 << l 1054: OpDot: Float: tmp1054 << tmp1052, tmp1053 1055: OpFMul: Float: tmp1055 << const303, tmp1054 1056: OpFAdd: Float: tmp1056 << const303, tmp1055 1057: OpCompositeConstruct: FloatVector3: tmp1057 << tmp1056, tmp1056, tmp1056 1058: OpFMul: FloatVector3: tmp1058 << tmp1051, tmp1057 1060: OpLoad: FloatVector3: tmp1060 << h 1061: OpLoad: FloatVector3: tmp1061 << n 1062: OpDot: Float: tmp1062 << tmp1060, tmp1061 1063: OpFMul: Float: tmp1063 << const303, tmp1062 1064: OpFAdd: Float: tmp1064 << const303, tmp1063 1065: OpExtInst(FClamp): Float: tmp1065 << tmp1064, const100, const106 1066: OpExtInst(Pow): Float: tmp1066 << tmp1065, const863 1067: OpCompositeConstruct: FloatVector3: tmp1067 << tmp1066, tmp1066, tmp1066 1068: OpFMul: FloatVector3: tmp1068 << const1059, tmp1067 1069: OpFAdd: FloatVector3: tmp1069 << tmp1058, tmp1068 1070: OpLoad: FloatVector3: tmp1070 << n 1071: OpLoad: FloatVector3: tmp1071 << rd 1072: OpFNegate: FloatVector3: tmp1072 << tmp1071 1073: OpDot: Float: tmp1073 << tmp1070, tmp1072 1074: OpExtInst(Pow): Float: tmp1074 << tmp1073, const127 1075: OpFMul: Float: tmp1075 << const704, tmp1074 1076: OpFAdd: Float: tmp1076 << const106, tmp1075 1077: OpVectorTimesScalar: FloatVector3: tmp1077 << tmp1069, tmp1076 OpStore: : tmp1077 >> col OpBranch: to lb989 1078: lb1078: 1080: OpLoad: FloatVector3: tmp1080 << n OpStore: : tmp1080 >> param1079 1082: OpLoad: FloatVector3: tmp1082 << rp OpStore: : tmp1082 >> param1081 1084: OpLoad: FloatVector3: tmp1084 << v OpStore: : tmp1084 >> param1083 1085: OpFunctionCall: FloatVector3: gummy(vf3;vf3;vf3;(param1079, param1081, param1083) 1086: OpVectorTimesScalar: FloatVector3: tmp1086 << gummy(vf3;vf3;vf3;, const401 1087: OpLoad: FloatVector3: tmp1087 << h 1088: OpLoad: FloatVector3: tmp1088 << n 1089: OpDot: Float: tmp1089 << tmp1087, tmp1088 1090: OpFMul: Float: tmp1090 << const303, tmp1089 1091: OpFAdd: Float: tmp1091 << const303, tmp1090 1092: OpExtInst(FClamp): Float: tmp1092 << tmp1091, const100, const106 1094: OpExtInst(Pow): Float: tmp1094 << tmp1092, const1093 1095: OpExtInst(SmoothStep): Float: tmp1095 << const303, const704, tmp1094 1096: OpCompositeConstruct: FloatVector3: tmp1096 << tmp1095, tmp1095, tmp1095 1097: OpVectorTimesScalar: FloatVector3: tmp1097 << tmp1096, const576 1098: OpFAdd: FloatVector3: tmp1098 << tmp1086, tmp1097 OpStore: : tmp1098 >> col OpBranch: to lb989 989: lb989: 1099: OpAccessChain: Float*: rp[1] 1100: OpLoad: Float: tmp1100 << rp[1] 1101: OpExtInst(FMax): Float: tmp1101 << const100, tmp1100 1102: OpExtInst(Pow): Float: tmp1102 << tmp1101, const303 1103: OpExtInst(FMix): Float: tmp1103 << const106, tmp1102, const704 1104: OpLoad: FloatVector3: tmp1104 << col 1105: OpVectorTimesScalar: FloatVector3: tmp1105 << tmp1104, tmp1103 OpStore: : tmp1105 >> col 1106: OpLoad: FloatVector3: tmp1106 << col OpReturnValue: : << tmp1106 96: OpFunction: Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) 1120: OpVariable: Float*: ti: storage class: Function 1125: OpVariable: Float*: tf: storage class: Function 1130: OpVariable: FloatVector3*: camo: storage class: Function 1131: OpVariable: Float*: param1131: storage class: Function 1134: OpVariable: FloatVector3*: camt: storage class: Function 1137: OpVariable: Float*: param1137: storage class: Function 1139: OpVariable: Float*: param1139: storage class: Function 1146: OpVariable: FloatVector3*: camd: storage class: Function 1151: OpVariable: FloatVector3*: camu: storage class: Function 1156: OpVariable: FloatVector3*: camv: storage class: Function 1167: OpVariable: FloatMatrix3x3*: m: storage class: Function 1184: OpVariable: FloatVector2*: q: storage class: Function 1188: OpVariable: FloatVector2*: p: storage class: Function 1190: OpVariable: FloatVector3*: ro: storage class: Function 1201: OpVariable: Float*: zoom: storage class: Function 1204: OpVariable: Float*: param1204: storage class: Function 1206: OpVariable: Float*: param1206: storage class: Function 1212: OpVariable: FloatVector3*: rd: storage class: Function 1221: OpVariable: Float*: t: storage class: Function 1229: OpVariable: Float*: t2: storage class: Function 1238: OpVariable: FloatVector3*: col: storage class: Function 1239: OpVariable: FloatVector3*: param1239: storage class: Function 1241: OpVariable: FloatVector3*: param1241: storage class: Function 1243: OpVariable: Float*: param1243: storage class: Function 1245: OpVariable: Float*: param1245: storage class: Function 1249: OpVariable: FloatVector3*: rp: storage class: Function 1267: OpVariable: FloatVector2*: c: storage class: Function 1275: OpVariable: FloatVector2*: xc: storage class: Function 1278: OpVariable: Float*: x: storage class: Function 1289: OpVariable: FloatVector3*: cc: storage class: Function 1312: OpVariable: FloatVector2*: param1312: storage class: Function 1319: OpVariable: FloatVector3*: h: storage class: Function 1324: OpVariable: FloatVector3*: r: storage class: Function 1327: OpVariable: Float*: rt: storage class: Function 1330: OpVariable: Float*: param1330: storage class: Function 1331: OpVariable: FloatVector2*: param1331: storage class: Function 1333: OpVariable: FloatVector2*: param1333: storage class: Function 1341: OpVariable: Float*: param1341: storage class: Function 1357: OpVariable: Float*: icing: storage class: Function 1381: OpVariable: FloatVector3*: param1381: storage class: Function 1396: OpVariable: FloatVector3*: param1396: storage class: Function 97: lb97: 1111: OpLoad: Float: tmp1111 << iTime OpStore: : tmp1111 >> time 1112: OpLoad: FloatVector2: tmp1112 << fragCoord 1115: OpLoad: FloatVector3: tmp1115 << iResolution 1116: OpVectorShuffle: FloatVector2: tmp1116 << tmp1115, tmp1115, 0, 1 1117: OpFDiv: FloatVector2: tmp1117 << tmp1112, tmp1116 1118: OpVectorTimesScalar: FloatVector2: tmp1118 << tmp1117, const127 1119: OpFSub: FloatVector2: tmp1119 << tmp1118, const342 OpStore: : tmp1119 >> tc 1121: OpLoad: Float: tmp1121 << time 1122: OpLoad: Float: tmp1122 << t_per_target 1123: OpFDiv: Float: tmp1123 << tmp1121, tmp1122 1124: OpExtInst(Floor): Float: tmp1124 << tmp1123 OpStore: : tmp1124 >> ti 1126: OpLoad: Float: tmp1126 << time 1127: OpLoad: Float: tmp1127 << t_per_target 1128: OpFDiv: Float: tmp1128 << tmp1126, tmp1127 1129: OpExtInst(Fract): Float: tmp1129 << tmp1128 OpStore: : tmp1129 >> tf 1132: OpLoad: Float: tmp1132 << time OpStore: : tmp1132 >> param1131 1133: OpFunctionCall: FloatVector3: cameraPos(f1;(param1131) OpStore: : cameraPos(f1; >> camo 1135: OpLoad: Float: tmp1135 << ti 1136: OpFSub: Float: tmp1136 << tmp1135, const106 OpStore: : tmp1136 >> param1137 1138: OpFunctionCall: FloatVector3: targetPos(f1;(param1137) 1140: OpLoad: Float: tmp1140 << ti OpStore: : tmp1140 >> param1139 1141: OpFunctionCall: FloatVector3: targetPos(f1;(param1139) 1142: OpLoad: Float: tmp1142 << tf 1143: OpExtInst(SmoothStep): Float: tmp1143 << const523, const671, tmp1142 1144: OpCompositeConstruct: FloatVector3: tmp1144 << tmp1143, tmp1143, tmp1143 1145: OpExtInst(FMix): FloatVector3: tmp1145 << targetPos(f1;, targetPos(f1;, tmp1144 OpStore: : tmp1145 >> camt 1147: OpLoad: FloatVector3: tmp1147 << camt 1148: OpLoad: FloatVector3: tmp1148 << camo 1149: OpFSub: FloatVector3: tmp1149 << tmp1147, tmp1148 1150: OpExtInst(Normalize): FloatVector3: tmp1150 << tmp1149 OpStore: : tmp1150 >> camd 1152: OpLoad: FloatVector3: tmp1152 << camd 1154: OpExtInst(Cross): FloatVector3: tmp1154 << tmp1152, const1153 1155: OpExtInst(Normalize): FloatVector3: tmp1155 << tmp1154 OpStore: : tmp1155 >> camu 1157: OpLoad: FloatVector3: tmp1157 << camu 1158: OpLoad: FloatVector3: tmp1158 << camd 1159: OpExtInst(Cross): FloatVector3: tmp1159 << tmp1157, tmp1158 1160: OpExtInst(Normalize): FloatVector3: tmp1160 << tmp1159 OpStore: : tmp1160 >> camv 1161: OpLoad: FloatVector3: tmp1161 << camd 1162: OpLoad: FloatVector3: tmp1162 << camv 1163: OpExtInst(Cross): FloatVector3: tmp1163 << tmp1161, tmp1162 1164: OpExtInst(Normalize): FloatVector3: tmp1164 << tmp1163 OpStore: : tmp1164 >> camu 1168: OpLoad: FloatVector3: tmp1168 << camu 1169: OpLoad: FloatVector3: tmp1169 << camv 1170: OpLoad: FloatVector3: tmp1170 << camd 1171: OpCompositeExtract: Float: tmp1171 << tmp1168, 0 1172: OpCompositeExtract: Float: tmp1172 << tmp1168, 1 1173: OpCompositeExtract: Float: tmp1173 << tmp1168, 2 1174: OpCompositeExtract: Float: tmp1174 << tmp1169, 0 1175: OpCompositeExtract: Float: tmp1175 << tmp1169, 1 1176: OpCompositeExtract: Float: tmp1176 << tmp1169, 2 1177: OpCompositeExtract: Float: tmp1177 << tmp1170, 0 1178: OpCompositeExtract: Float: tmp1178 << tmp1170, 1 1179: OpCompositeExtract: Float: tmp1179 << tmp1170, 2 1180: OpCompositeConstruct: FloatVector3: tmp1180 << tmp1171, tmp1172, tmp1173 1181: OpCompositeConstruct: FloatVector3: tmp1181 << tmp1174, tmp1175, tmp1176 1182: OpCompositeConstruct: FloatVector3: tmp1182 << tmp1177, tmp1178, tmp1179 1183: OpCompositeConstruct: FloatMatrix3x3: tmp1183 << tmp1180, tmp1181, tmp1182 OpStore: : tmp1183 >> m 1185: OpLoad: FloatVector2: tmp1185 << tc 1186: OpVectorTimesScalar: FloatVector2: tmp1186 << tmp1185, const303 1187: OpFAdd: FloatVector2: tmp1187 << tmp1186, const391 OpStore: : tmp1187 >> q 1189: OpLoad: FloatVector2: tmp1189 << tc OpStore: : tmp1189 >> p 1191: OpLoad: FloatVector3: tmp1191 << camo OpStore: : tmp1191 >> ro 1192: OpAccessChain: Float*: iResolution[0] 1193: OpLoad: Float: tmp1193 << iResolution[0] 1194: OpAccessChain: Float*: iResolution[1] 1195: OpLoad: Float: tmp1195 << iResolution[1] 1196: OpFDiv: Float: tmp1196 << tmp1193, tmp1195 1197: OpAccessChain: Float*: p[0] 1198: OpLoad: Float: tmp1198 << p[0] 1199: OpFMul: Float: tmp1199 << tmp1198, tmp1196 1200: OpAccessChain: Float*: p[0] OpStore: : tmp1199 >> p[0] 1202: OpLoad: Float: tmp1202 << ti 1203: OpFSub: Float: tmp1203 << tmp1202, const106 OpStore: : tmp1203 >> param1204 1205: OpFunctionCall: Float: cameraZoom(f1;(param1204) 1207: OpLoad: Float: tmp1207 << ti OpStore: : tmp1207 >> param1206 1208: OpFunctionCall: Float: cameraZoom(f1;(param1206) 1209: OpLoad: Float: tmp1209 << tf 1210: OpExtInst(SmoothStep): Float: tmp1210 << const671, const435, tmp1209 1211: OpExtInst(FMix): Float: tmp1211 << cameraZoom(f1;, cameraZoom(f1;, tmp1210 OpStore: : tmp1211 >> zoom 1213: OpLoad: FloatMatrix3x3: tmp1213 << m 1214: OpLoad: FloatVector2: tmp1214 << p 1215: OpLoad: Float: tmp1215 << zoom 1216: OpCompositeExtract: Float: tmp1216 << tmp1214, 0 1217: OpCompositeExtract: Float: tmp1217 << tmp1214, 1 1218: OpCompositeConstruct: FloatVector3: tmp1218 << tmp1216, tmp1217, tmp1215 1219: OpExtInst(Normalize): FloatVector3: tmp1219 << tmp1218 1220: OpMatrixTimesVector: FloatVector3: tmp1220 << tmp1213, tmp1219 OpStore: : tmp1220 >> rd 1222: OpAccessChain: Float*: ro[1] 1223: OpLoad: Float: tmp1223 << ro[1] 1224: OpFSub: Float: tmp1224 << const106, tmp1223 1225: OpAccessChain: Float*: rd[1] 1226: OpLoad: Float: tmp1226 << rd[1] 1227: OpFDiv: Float: tmp1227 << tmp1224, tmp1226 1228: OpExtInst(FMax): Float: tmp1228 << const100, tmp1227 OpStore: : tmp1228 >> t 1231: OpAccessChain: Float*: ro[1] 1232: OpLoad: Float: tmp1232 << ro[1] 1233: OpFSub: Float: tmp1233 << const1230, tmp1232 1234: OpAccessChain: Float*: rd[1] 1235: OpLoad: Float: tmp1235 << rd[1] 1236: OpFDiv: Float: tmp1236 << tmp1233, tmp1235 1237: OpExtInst(FMax): Float: tmp1237 << const100, tmp1236 OpStore: : tmp1237 >> t2 1240: OpLoad: FloatVector3: tmp1240 << ro OpStore: : tmp1240 >> param1239 1242: OpLoad: FloatVector3: tmp1242 << rd OpStore: : tmp1242 >> param1241 1244: OpLoad: Float: tmp1244 << t OpStore: : tmp1244 >> param1243 1246: OpLoad: Float: tmp1246 << t2 OpStore: : tmp1246 >> param1245 1247: OpFunctionCall: FloatVector3: trace(vf3;vf3;f1;f1;(param1239, param1241, param1243, param1245) 1248: OpLoad: Float: tmp1248 << param1243 OpStore: : tmp1248 >> t OpStore: : trace(vf3;vf3;f1;f1; >> col 1250: OpLoad: FloatVector3: tmp1250 << ro 1251: OpLoad: FloatVector3: tmp1251 << rd 1252: OpLoad: Float: tmp1252 << t 1253: OpVectorTimesScalar: FloatVector3: tmp1253 << tmp1251, tmp1252 1254: OpFAdd: FloatVector3: tmp1254 << tmp1250, tmp1253 OpStore: : tmp1254 >> rp 1255: OpAccessChain: Float*: rp[1] 1256: OpLoad: Float: tmp1256 << rp[1] 1257: OpFMul: Float: tmp1257 << tmp1256, const127 1258: OpExtInst(FClamp): Float: tmp1258 << tmp1257, const100, const106 OpStore: : tmp1258 >> icing_factor 1259: OpLoad: Float: tmp1259 << t 1260: OpFOrdGreaterThan: Bool: tmp1260 << tmp1259, const100 1261: OpLoad: Float: tmp1261 << t2 1262: OpLoad: Float: tmp1262 << t 1263: OpFOrdLessThan: Bool: tmp1263 << tmp1261, tmp1262 1264: OpLogicalAnd: Bool: tmp1264 << tmp1260, tmp1263 OpSelectionMerge: (merge: lb1266) OpBranchConditional: if(tmp1264) then branch to lb1265, else branch to lb1266 1265: lb1265: 1268: OpLoad: FloatVector3: tmp1268 << ro 1269: OpVectorShuffle: FloatVector2: tmp1269 << tmp1268, tmp1268, 0, 2 1270: OpLoad: FloatVector3: tmp1270 << rd 1271: OpVectorShuffle: FloatVector2: tmp1271 << tmp1270, tmp1270, 0, 2 1272: OpLoad: Float: tmp1272 << t2 1273: OpVectorTimesScalar: FloatVector2: tmp1273 << tmp1271, tmp1272 1274: OpFAdd: FloatVector2: tmp1274 << tmp1269, tmp1273 OpStore: : tmp1274 >> c 1276: OpLoad: FloatVector2: tmp1276 << c 1277: OpVectorTimesScalar: FloatVector2: tmp1277 << tmp1276, const151 OpStore: : tmp1277 >> xc 1279: OpAccessChain: Float*: xc[0] 1280: OpLoad: Float: tmp1280 << xc[0] 1281: OpAccessChain: Float*: xc[1] 1282: OpLoad: Float: tmp1282 << xc[1] 1283: OpExtInst(Fract): Float: tmp1283 << tmp1282 1284: OpExtInst(Step): Float: tmp1284 << const303, tmp1283 1285: OpFMul: Float: tmp1285 << const303, tmp1284 1286: OpFAdd: Float: tmp1286 << tmp1280, tmp1285 1287: OpExtInst(Fract): Float: tmp1287 << tmp1286 1288: OpExtInst(Step): Float: tmp1288 << const303, tmp1287 OpStore: : tmp1288 >> x 1293: OpLoad: Float: tmp1293 << x 1294: OpCompositeConstruct: FloatVector3: tmp1294 << tmp1293, tmp1293, tmp1293 1295: OpExtInst(FMix): FloatVector3: tmp1295 << const1290, const1292, tmp1294 OpStore: : tmp1295 >> cc 1296: OpLoad: FloatVector3: tmp1296 << cc 1298: OpLoad: FloatVector2: tmp1298 << xc 1299: OpVectorTimesScalar: FloatVector2: tmp1299 << tmp1298, const621 1300: OpAccessChain: Float*: xc[1] 1301: OpLoad: Float: tmp1301 << xc[1] 1302: OpFMul: Float: tmp1302 << tmp1301, const127 1303: OpExtInst(Cos): Float: tmp1303 << tmp1302 1304: OpFMul: Float: tmp1304 << tmp1303, const109 1305: OpAccessChain: Float*: xc[0] 1306: OpLoad: Float: tmp1306 << xc[0] 1307: OpFMul: Float: tmp1307 << tmp1306, const106 1308: OpExtInst(Cos): Float: tmp1308 << tmp1307 1309: OpFMul: Float: tmp1309 << tmp1308, const377 1310: OpCompositeConstruct: FloatVector2: tmp1310 << tmp1304, tmp1309 1311: OpFAdd: FloatVector2: tmp1311 << tmp1299, tmp1310 OpStore: : tmp1311 >> param1312 1313: OpFunctionCall: Float: smN2(vf2;(param1312) 1314: OpFMul: Float: tmp1314 << const303, smN2(vf2; 1315: OpFAdd: Float: tmp1315 << const523, tmp1314 1316: OpExtInst(Pow): Float: tmp1316 << tmp1315, const377 1317: OpCompositeConstruct: FloatVector3: tmp1317 << tmp1316, tmp1316, tmp1316 1318: OpExtInst(FMix): FloatVector3: tmp1318 << tmp1296, const1297, tmp1317 OpStore: : tmp1318 >> cc 1320: OpLoad: FloatVector3: tmp1320 << l 1321: OpLoad: FloatVector3: tmp1321 << rd 1322: OpFSub: FloatVector3: tmp1322 << tmp1320, tmp1321 1323: OpExtInst(Normalize): FloatVector3: tmp1323 << tmp1322 OpStore: : tmp1323 >> h 1325: OpLoad: FloatVector3: tmp1325 << rd 1326: OpExtInst(Reflect): FloatVector3: tmp1326 << tmp1325, const1153 OpStore: : tmp1326 >> r OpStore: : const100 >> rt 1328: OpLoad: FloatVector2: tmp1328 << xc 1329: OpVectorTimesScalar: FloatVector2: tmp1329 << tmp1328, const303 OpStore: : const127 >> param1330 OpStore: : tmp1329 >> param1331 1332: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param1330, param1331) OpStore: : rotate(f1;vf2; >> param1333 1334: OpFunctionCall: FloatVector3: marble(vf2;(param1333) OpStore: : marble(vf2; >> cc 1335: OpLoad: FloatVector2: tmp1335 << c 1336: OpCompositeConstruct: FloatVector2: tmp1336 << const109, const109 1337: OpFDiv: FloatVector2: tmp1337 << tmp1335, tmp1336 1338: OpExtInst(Fract): FloatVector2: tmp1338 << tmp1337 OpStore: : tmp1338 >> c 1339: OpLoad: FloatVector3: tmp1339 << cc 1340: OpVectorTimesScalar: FloatVector3: tmp1340 << tmp1339, const151 1342: OpLoad: Float: tmp1342 << colour OpStore: : tmp1342 >> param1341 1343: OpFunctionCall: FloatVector3: gumColour(f1;(param1341) 1344: OpVectorTimesScalar: FloatVector3: tmp1344 << gumColour(f1;, const127 1345: OpLoad: Float: tmp1345 << is_choc 1346: OpVectorTimesScalar: FloatVector3: tmp1346 << tmp1344, tmp1345 1349: OpLoad: FloatVector2: tmp1349 << c 1350: OpExtInst(Distance): Float: tmp1350 << const391, tmp1349 1351: OpLoad: Float: tmp1351 << ss 1352: OpFDiv: Float: tmp1352 << tmp1350, tmp1351 1353: OpExtInst(SmoothStep): Float: tmp1353 << const1347, const1348, tmp1352 1354: OpCompositeConstruct: FloatVector3: tmp1354 << tmp1353, tmp1353, tmp1353 1355: OpExtInst(FMix): FloatVector3: tmp1355 << tmp1346, const1290, tmp1354 1356: OpFMul: FloatVector3: tmp1356 << tmp1340, tmp1355 OpStore: : tmp1356 >> col OpStore: : const106 >> icing_factor OpBranch: to lb1266 1266: lb1266: 1360: OpAccessChain: Float*: iMouse[0] 1361: OpLoad: Float: tmp1361 << iMouse[0] 1362: OpAccessChain: Float*: iResolution[0] 1363: OpLoad: Float: tmp1363 << iResolution[0] 1364: OpFDiv: Float: tmp1364 << tmp1361, tmp1363 1365: OpLoad: Float: tmp1365 << icing_factor 1366: OpFMul: Float: tmp1366 << tmp1364, tmp1365 1367: OpFSub: Float: tmp1367 << const106, tmp1366 OpStore: : tmp1367 >> icing 1368: OpLoad: FloatVector3: tmp1368 << col 1370: OpLoad: Float: tmp1370 << icing 1371: OpFMul: Float: tmp1371 << const1369, tmp1370 1373: OpFAdd: Float: tmp1373 << tmp1371, const1372 1374: OpLoad: FloatVector3: tmp1374 << rp 1375: OpVectorShuffle: FloatVector2: tmp1375 << tmp1374, tmp1374, 0, 2 1377: OpVectorTimesScalar: FloatVector2: tmp1377 << tmp1375, const1376 1378: OpCompositeExtract: Float: tmp1378 << tmp1377, 0 1379: OpCompositeExtract: Float: tmp1379 << tmp1377, 1 1380: OpCompositeConstruct: FloatVector3: tmp1380 << tmp1378, tmp1379, const100 OpStore: : tmp1380 >> param1381 1382: OpFunctionCall: Float: fbm3(vf3;(param1381) 1383: OpFAdd: Float: tmp1383 << tmp1373, fbm3(vf3; 1384: OpExtInst(SmoothStep): Float: tmp1384 << const303, const671, tmp1383 1385: OpFMul: Float: tmp1385 << const435, tmp1384 1386: OpLoad: Float: tmp1386 << icing 1387: OpFMul: Float: tmp1387 << const1369, tmp1386 1388: OpFAdd: Float: tmp1388 << tmp1387, const523 1389: OpLoad: FloatVector3: tmp1389 << rp 1390: OpVectorShuffle: FloatVector2: tmp1390 << tmp1389, tmp1389, 0, 2 1392: OpVectorTimesScalar: FloatVector2: tmp1392 << tmp1390, const1391 1393: OpCompositeExtract: Float: tmp1393 << tmp1392, 0 1394: OpCompositeExtract: Float: tmp1394 << tmp1392, 1 1395: OpCompositeConstruct: FloatVector3: tmp1395 << tmp1393, tmp1394, const100 OpStore: : tmp1395 >> param1396 1397: OpFunctionCall: Float: fbm3(vf3;(param1396) 1398: OpFAdd: Float: tmp1398 << tmp1388, fbm3(vf3; 1399: OpExtInst(SmoothStep): Float: tmp1399 << const303, const671, tmp1398 1400: OpFMul: Float: tmp1400 << const435, tmp1399 1401: OpFAdd: Float: tmp1401 << tmp1385, tmp1400 1402: OpCompositeConstruct: FloatVector3: tmp1402 << tmp1401, tmp1401, tmp1401 1403: OpExtInst(FMix): FloatVector3: tmp1403 << tmp1368, const1290, tmp1402 OpStore: : tmp1403 >> col 1404: OpLoad: FloatVector3: tmp1404 << col 1405: OpVectorTimesScalar: FloatVector3: tmp1405 << tmp1404, const895 1406: OpExtInst(Sqrt): FloatVector3: tmp1406 << tmp1405 1407: OpLoad: FloatVector4: tmp1407 << fragColor 1408: OpVectorShuffle: FloatVector4: tmp1408 << tmp1407, tmp1406, 4, 5, 6, 3 OpStore: : tmp1408 >> fragColor 1410: OpAccessChain: Float*: q[0] 1411: OpLoad: Float: tmp1411 << q[0] 1412: OpFMul: Float: tmp1412 << const1409, tmp1411 1413: OpAccessChain: Float*: q[1] 1414: OpLoad: Float: tmp1414 << q[1] 1415: OpFMul: Float: tmp1415 << tmp1412, tmp1414 1416: OpAccessChain: Float*: q[0] 1417: OpLoad: Float: tmp1417 << q[0] 1418: OpFSub: Float: tmp1418 << const106, tmp1417 1419: OpFMul: Float: tmp1419 << tmp1415, tmp1418 1420: OpAccessChain: Float*: q[1] 1421: OpLoad: Float: tmp1421 << q[1] 1422: OpFSub: Float: tmp1422 << const106, tmp1421 1423: OpFMul: Float: tmp1423 << tmp1419, tmp1422 1424: OpExtInst(Pow): Float: tmp1424 << tmp1423, const576 1425: OpLoad: FloatVector4: tmp1425 << fragColor 1426: OpVectorShuffle: FloatVector3: tmp1426 << tmp1425, tmp1425, 0, 1, 2 1427: OpVectorTimesScalar: FloatVector3: tmp1427 << tmp1426, tmp1424 1428: OpLoad: FloatVector4: tmp1428 << fragColor 1429: OpVectorShuffle: FloatVector4: tmp1429 << tmp1428, tmp1427, 4, 5, 6, 3 OpStore: : tmp1429 >> fragColor OpReturn: Performing hardware-independent optimization... Variable color Variable color is redundant. Removing both it and related Load/Store instructions. Variable param1433 Variable param1434 Removed 1 redundant local variables from function main Variable p Variable p is redundant. Removing both it and related Load/Store instructions. Variable f Variable n Variable n is redundant. Removing both it and related Load/Store instructions. Variable param211 Variable param215 Variable param222 Variable param227 Variable param237 Variable param242 Variable param250 Variable param255 Removed 2 redundant local variables from function noise(vf3; Variable param272 Variable param276 Variable f Variable i Variable x Variable x is redundant. Removing both it and related Load/Store instructions. Variable param301 Removed 1 redundant local variables from function fbm3(vf3; Variable o Variable o is redundant. Removing both it and related Load/Store instructions. Variable a Variable a is redundant. Removing both it and related Load/Store instructions. Variable b Variable b is redundant. Removing both it and related Load/Store instructions. Removed 3 redundant local variables from function sugarybit(vf2; Variable t2 Variable t2 is redundant. Removing both it and related Load/Store instructions. Variable p Variable p is redundant. Removing both it and related Load/Store instructions. Variable c Variable c is redundant. Removing both it and related Load/Store instructions. Variable a Variable a is redundant. Removing both it and related Load/Store instructions. Variable o Variable o is redundant. Removing both it and related Load/Store instructions. Variable s Variable s is redundant. Removing both it and related Load/Store instructions. Variable param419 Variable param426 Variable fres Variable fres is redundant. Removing both it and related Load/Store instructions. Variable param445 Variable param447 Variable param449 Variable param453 Removed 7 redundant local variables from function sugarlayer(vf2;f1; Variable param463 Variable sprinkle Variable i Variable param493 Variable param494 Variable param513 Variable param514 Variable param519 Variable param520 Variable ndotv Variable ndotv is redundant. Removing both it and related Load/Store instructions. Variable s0 Variable s0 is redundant. Removing both it and related Load/Store instructions. Variable param544 Variable param545 Variable s1 Variable s1 is redundant. Removing both it and related Load/Store instructions. Variable param549 Variable param552 Variable sprinkle Variable sprinkle is redundant. Removing both it and related Load/Store instructions. Variable ss Variable ss is redundant. Removing both it and related Load/Store instructions. Variable tex Variable param570 Variable param591 Removed 5 redundant local variables from function gummy(vf3;vf3;vf3; Variable fp Variable fp is redundant. Removing both it and related Load/Store instructions. Variable ff Variable ff is redundant. Removing both it and related Load/Store instructions. Variable param635 Variable param643 Variable sp Variable sp is redundant. Removing both it and related Load/Store instructions. Variable pl Variable pl is redundant. Removing both it and related Load/Store instructions. Variable d Variable d is redundant. Removing both it and related Load/Store instructions. Removed 5 redundant local variables from function de(vf3; Variable border_size Variable border_size is redundant. Removing both it and related Load/Store instructions. Variable corner_size Variable corner_size is redundant. Removing both it and related Load/Store instructions. Variable c0 Variable c0 is redundant. Removing both it and related Load/Store instructions. Variable c1 Variable c1 is redundant. Removing both it and related Load/Store instructions. Variable rc1 Variable rc1 is redundant. Removing both it and related Load/Store instructions. Variable ccol Variable ccol is redundant. Removing both it and related Load/Store instructions. Variable param740 Variable pat Variable pat is redundant. Removing both it and related Load/Store instructions. Variable param767 Variable param779 Variable param790 Variable bcol Variable bcol is redundant. Removing both it and related Load/Store instructions. Variable br Variable br is redundant. Removing both it and related Load/Store instructions. Variable cr Variable cr is redundant. Removing both it and related Load/Store instructions. Removed 10 redundant local variables from function marble(vf2; Variable target Variable param858 Variable i Variable d Variable d is redundant. Removing both it and related Load/Store instructions. Variable param914 Variable rp Variable rp is redundant. Removing both it and related Load/Store instructions. Variable col Variable e Variable e is redundant. Removing both it and related Load/Store instructions. Variable c Variable c is redundant. Removing both it and related Load/Store instructions. Variable param949 Variable n Variable n is redundant. Removing both it and related Load/Store instructions. Variable param957 Variable param965 Variable param973 Variable v Variable v is redundant. Removing both it and related Load/Store instructions. Variable h Variable h is redundant. Removing both it and related Load/Store instructions. Variable r Variable r is redundant. Removing both it and related Load/Store instructions. Variable chocolour Variable param1028 Variable param1079 Variable param1081 Variable param1083 Removed 8 redundant local variables from function trace(vf3;vf3;f1;f1; Variable ti Variable ti is redundant. Removing both it and related Load/Store instructions. Variable tf Variable tf is redundant. Removing both it and related Load/Store instructions. Variable camo Variable camo is redundant. Removing both it and related Load/Store instructions. Variable param1131 Variable camt Variable camt is redundant. Removing both it and related Load/Store instructions. Variable param1137 Variable param1139 Variable camd Variable camd is redundant. Removing both it and related Load/Store instructions. Variable camu Variable camv Variable camv is redundant. Removing both it and related Load/Store instructions. Variable m Variable m is redundant. Removing both it and related Load/Store instructions. Variable q Variable q is redundant. Removing both it and related Load/Store instructions. Variable p Variable ro Variable ro is redundant. Removing both it and related Load/Store instructions. Variable zoom Variable zoom is redundant. Removing both it and related Load/Store instructions. Variable param1204 Variable param1206 Variable rd Variable rd is redundant. Removing both it and related Load/Store instructions. Variable t Variable t2 Variable t2 is redundant. Removing both it and related Load/Store instructions. Variable col Variable param1239 Variable param1241 Variable param1243 Variable param1245 Variable rp Variable rp is redundant. Removing both it and related Load/Store instructions. Variable c Variable xc Variable xc is redundant. Removing both it and related Load/Store instructions. Variable x Variable x is redundant. Removing both it and related Load/Store instructions. Variable cc Variable param1312 Variable h Variable h is redundant. Removing both it and related Load/Store instructions. Variable r Variable r is redundant. Removing both it and related Load/Store instructions. Variable rt Variable rt is redundant. Removing both it and related Load/Store instructions. Variable param1330 Variable param1331 Variable param1333 Variable param1341 Variable icing Variable icing is redundant. Removing both it and related Load/Store instructions. Variable param1381 Variable param1396 Removed 19 redundant local variables from function mainImage(vf4;vf2; Optimization done. Optimized Disassembly: Module Info: OpSource: : ESSL ver 310 1: OpExtInstImport: : GLSL.std.450 OpMemoryModel: : addressing: Logical, memory: GLSL450 Capabilities: OpCapability: : Shader Inputs: 1432: OpVariable: FloatVector4*: gl_FragCoord: storage class: Input Decorators: BuiltIn(FragCoord) Outputs: 1440: OpVariable: FloatVector4*: finalColor: storage class: Output Uniform Constants: 1110: OpVariable: Float*: iTime: storage class: UniformConstant 1114: OpVariable: FloatVector3*: iResolution: storage class: UniformConstant 1359: OpVariable: FloatVector4*: iMouse: storage class: UniformConstant 1442: OpVariable: FloatVector4*: iDate: storage class: UniformConstant 1443: OpVariable: Float*: iFrame: storage class: UniformConstant 1447: OpVariable: FloatVector3[4]*: iChannelResolution: storage class: UniformConstant Textures: 1451: OpVariable: SampledImage(Image(Float))*: iChannel0: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 1452: OpVariable: SampledImage(Image(Float))*: iChannel1: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 1453: OpVariable: SampledImage(Image(Float))*: iChannel2: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 1454: OpVariable: SampledImage(Image(Float))*: iChannel3: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) Entry Points: 4: OpEntryPoint: : main, execution model: Fragment, Function: Void main(), OriginLowerLeft Constants: 100: OpConstant: Float const100 = 0 101: OpConstantComposite: FloatVector2 const101 = {0, 0} 106: OpConstant: Float const106 = 1 109: OpConstant: Float const109 = 3 112: OpConstant: Float const112 = 0.316228 113: OpConstant: Float const113 = 0.948683 114: OpConstantComposite: FloatVector3 const114 = {0.316228, 0.948683, 0} 121: OpConstant: Float const121 = 0.11 122: OpConstant: Float const122 = 0.002 123: OpConstantComposite: FloatVector3 const123 = {0.11, 0, 0.002} 127: OpConstant: Float const127 = 2 131: OpConstant: Float const131 = 0.06 132: OpConstantComposite: FloatVector3 const132 = {0.002, 0.06, 0} 139: OpConstant: Float const139 = 0.02 140: OpConstantComposite: FloatVector3 const140 = {0, 0.02, 0.11} 143: OpConstant: Float const143 = 0.012 144: OpConstantComposite: FloatVector3 const144 = {0.11, 0.012, 0} 151: OpConstant: Float const151 = 0.8 152: OpConstantComposite: FloatVector3 const152 = {0.8, 1, 1} 159: OpConstantComposite: FloatVector3 const159 = {0.8, 0.8, 1} 166: OpConstantComposite: FloatVector3 const166 = {1, 0.8, 1} 173: OpConstant: Float const173 = 43758.5 194: OpConstant: UInt const194 = 0 197: OpConstant: UInt const197 = 1 200: OpConstant: Float const200 = 157 203: OpConstant: Float const203 = 113 204: OpConstant: UInt const204 = 2 225: OpConstant: Float const225 = 158 240: OpConstant: Float const240 = 114 248: OpConstant: Float const248 = 270 253: OpConstant: Float const253 = 271 285: OpConstant: Int const285 = 1 292: OpConstant: Int const292 = 9 303: OpConstant: Float const303 = 0.5 340: OpConstant: Float const340 = -1 341: OpConstantComposite: FloatVector2 const341 = {-1, -1} 342: OpConstantComposite: FloatVector2 const342 = {1, 1} 349: OpConstant: Float const349 = 8 361: OpConstant: Float const361 = 0.95 377: OpConstant: Float const377 = 4 391: OpConstantComposite: FloatVector2 const391 = {0.5, 0.5} 401: OpConstant: Float const401 = 5 407: OpConstant: Float const407 = 53 412: OpConstant: Float const412 = 125 416: OpConstant: Float const416 = 2.5 423: OpConstant: Float const423 = 100 424: OpConstantComposite: FloatVector2 const424 = {100, 100} 435: OpConstant: Float const435 = 0.9 437: OpConstant: Float const437 = 25 471: OpConstant: Int const471 = 0 478: OpConstant: Int const478 = 4 483: OpConstant: Float const483 = 10.45 489: OpConstant: Float const489 = 0.2 511: OpConstant: Float const511 = 0.75 523: OpConstant: Float const523 = 0.3 569: OpConstantComposite: FloatVector3 const569 = {0.5, 0.5, 0.5} 573: OpConstant: Float const573 = 0.98 576: OpConstant: Float const576 = 0.1 585: OpConstantComposite: FloatVector3 const585 = {2, 2, 2} 593: OpConstant: Float const593 = 1.05 602: OpConstant: Float const602 = 0.01 609: OpConstant: Float const609 = 1.3 621: OpConstant: Float const621 = 10 625: OpConstant: Float const625 = 103 633: OpConstant: Float const633 = 30 637: OpConstant: Float const637 = 0.001 647: OpConstant: Float const647 = 0.05 664: OpConstantComposite: FloatVector2 const664 = {3, 3} 666: OpConstant: Float const666 = 1.5 667: OpConstantComposite: FloatVector2 const667 = {1.5, 1.5} 671: OpConstant: Float const671 = 0.7 674: OpConstant: Float const674 = 7 678: OpConstant: Float const678 = 9 704: OpConstant: Float const704 = 0.6 714: OpConstant: Float const714 = 0.015 730: OpConstantComposite: FloatVector2 const730 = {1, -1} 735: OpConstantComposite: FloatVector3 const735 = {0.1, 0.1, 0.05} 748: OpConstant: Float const748 = 0.4 749: OpConstant: Float const749 = 0.24 750: OpConstantComposite: FloatVector3 const750 = {0.4, 0.4, 0.24} 751: OpConstant: Float const751 = 0.56 752: OpConstantComposite: FloatVector3 const752 = {0.7, 0.7, 0.56} 844: OpConstant: Float const844 = 6 848: OpConstant: Float const848 = 0.03 860: OpConstantComposite: FloatVector3 const860 = {1, 0, 0} 863: OpConstant: Float const863 = 20 867: OpConstant: Float const867 = -7 869: OpConstant: Float const869 = 14 888: OpConstant: Float const888 = 3.5 895: OpConstant: Float const895 = 1.4 906: OpConstant: Int const906 = 100 921: OpConstantComposite: FloatVector3 const921 = {0, 0, 0} 925: OpConstant: Float const925 = 0.0001 945: OpConstant: Float const945 = 0.005 946: OpConstantComposite: FloatVector3 const946 = {0.02, 0.01, 0.005} 1012: OpConstant: Float const1012 = 2.6 1013: OpConstantComposite: FloatVector3 const1013 = {4, 4, 2.6} 1014: OpConstant: Float const1014 = 0.78 1015: OpConstant: Float const1015 = 0.36 1016: OpConstant: Float const1016 = 0.12 1017: OpConstantComposite: FloatVector3 const1017 = {0.78, 0.36, 0.12} 1035: OpConstantComposite: FloatVector3 const1035 = {1.3, 0.6, 0.2} 1059: OpConstantComposite: FloatVector3 const1059 = {0.06, 0.06, 0.03} 1093: OpConstant: Float const1093 = 256 1153: OpConstantComposite: FloatVector3 const1153 = {0, 1, 0} 1230: OpConstant: Float const1230 = -0.01 1290: OpConstantComposite: FloatVector3 const1290 = {1, 1, 1} 1291: OpConstant: Float const1291 = 0.25 1292: OpConstantComposite: FloatVector3 const1292 = {0.5, 0.5, 0.25} 1297: OpConstantComposite: FloatVector3 const1297 = {0.9, 0.9, 0.5} 1347: OpConstant: Float const1347 = 0.33 1348: OpConstant: Float const1348 = 0.53 1369: OpConstant: Float const1369 = -0.25 1372: OpConstant: Float const1372 = 0.35 1376: OpConstant: Float const1376 = 4.2 1391: OpConstant: Float const1391 = 10.1 1409: OpConstant: Float const1409 = 16 1444: OpConstant: UInt const1444 = 4 Private Global Variables: 99: OpVariable: FloatVector2*: tc: storage class: Private 103: OpVariable: Float*: time: storage class: Private 104: OpVariable: Float*: colour: storage class: Private 105: OpVariable: Float*: ss: storage class: Private 107: OpVariable: Float*: is_choc: storage class: Private 108: OpVariable: Float*: t_per_target: storage class: Private 111: OpVariable: FloatVector3*: l: storage class: Private 115: OpVariable: Float*: icing_factor: storage class: Private 1456: OpVariable: FloatVector3[4]*: gum_colours: storage class: Private 1457: OpVariable: FloatVector3[4]*: gum_ramps: storage class: Private Disassembled Code: 4: OpFunction: Void main() 1433: OpVariable: FloatVector4*: param1433: storage class: Function 1434: OpVariable: FloatVector2*: param1434: storage class: Function 5: lb5: OpStore: : const101 >> tc OpStore: : const100 >> time OpStore: : const100 >> colour OpStore: : const106 >> ss OpStore: : const100 >> is_choc OpStore: : const109 >> t_per_target OpStore: : const114 >> l OpStore: : const100 >> icing_factor 1435: OpLoad: FloatVector4: tmp1435 << gl_FragCoord 1436: OpVectorShuffle: FloatVector2: tmp1436 << tmp1435, tmp1435, 0, 1 OpStore: : tmp1436 >> param1434 1437: OpFunctionCall: Void: mainImage(vf4;vf2;(param1433, param1434) 1438: OpLoad: FloatVector4: tmp1438 << param1433 OpStore: : tmp1438 >> finalColor OpReturn: 11: OpFunction: FloatVector3 gumColour(f1;(Float* i) 12: lb12: 116: OpLoad: Float: tmp116 << i 118: OpFOrdLessThan: Bool: tmp118 << tmp116, const106 OpSelectionMerge: (merge: lb120) OpBranchConditional: if(tmp118) then branch to lb119, else branch to lb125 119: lb119: OpReturnValue: : << const123 125: lb125: 126: OpLoad: Float: tmp126 << i 128: OpFOrdLessThan: Bool: tmp128 << tmp126, const127 OpSelectionMerge: (merge: lb130) OpBranchConditional: if(tmp128) then branch to lb129, else branch to lb134 129: lb129: OpReturnValue: : << const132 134: lb134: 135: OpLoad: Float: tmp135 << i 136: OpFOrdLessThan: Bool: tmp136 << tmp135, const109 OpSelectionMerge: (merge: lb138) OpBranchConditional: if(tmp136) then branch to lb137, else branch to lb142 137: lb137: OpReturnValue: : << const140 142: lb142: OpReturnValue: : << const144 138: lb138: OpBranch: to lb130 130: lb130: OpBranch: to lb120 120: lb120: 146: OpUndef: FloatVector3: tmp146 << OpReturnValue: : << tmp146 14: OpFunction: FloatVector3 gumRamp(f1;(Float* i) 15: lb15: 147: OpLoad: Float: tmp147 << i 148: OpFOrdLessThan: Bool: tmp148 << tmp147, const106 OpSelectionMerge: (merge: lb150) OpBranchConditional: if(tmp148) then branch to lb149, else branch to lb154 149: lb149: OpReturnValue: : << const152 154: lb154: 155: OpLoad: Float: tmp155 << i 156: OpFOrdLessThan: Bool: tmp156 << tmp155, const127 OpSelectionMerge: (merge: lb158) OpBranchConditional: if(tmp156) then branch to lb157, else branch to lb161 157: lb157: OpReturnValue: : << const159 161: lb161: 162: OpLoad: Float: tmp162 << i 163: OpFOrdLessThan: Bool: tmp163 << tmp162, const109 OpSelectionMerge: (merge: lb165) OpBranchConditional: if(tmp163) then branch to lb164, else branch to lb168 164: lb164: OpReturnValue: : << const166 168: lb168: OpReturnValue: : << const159 165: lb165: OpBranch: to lb158 158: lb158: OpBranch: to lb150 150: lb150: 170: OpUndef: FloatVector3: tmp170 << OpReturnValue: : << tmp170 18: OpFunction: Float hash(f1;(Float* n) 19: lb19: 171: OpLoad: Float: tmp171 << n 172: OpExtInst(Sin): Float: tmp172 << tmp171 174: OpFMul: Float: tmp174 << tmp172, const173 175: OpExtInst(Fract): Float: tmp175 << tmp174 OpReturnValue: : << tmp175 23: OpFunction: Float noise(vf3;(FloatVector3* x) 181: OpVariable: FloatVector3*: f: storage class: Function 211: OpVariable: Float*: param211: storage class: Function 215: OpVariable: Float*: param215: storage class: Function 222: OpVariable: Float*: param222: storage class: Function 227: OpVariable: Float*: param227: storage class: Function 237: OpVariable: Float*: param237: storage class: Function 242: OpVariable: Float*: param242: storage class: Function 250: OpVariable: Float*: param250: storage class: Function 255: OpVariable: Float*: param255: storage class: Function 24: lb24: 179: OpLoad: FloatVector3: tmp179 << x 180: OpExtInst(Floor): FloatVector3: tmp180 << tmp179 182: OpLoad: FloatVector3: tmp182 << x 183: OpExtInst(Fract): FloatVector3: tmp183 << tmp182 OpStore: : tmp183 >> f 184: OpLoad: FloatVector3: tmp184 << f 185: OpLoad: FloatVector3: tmp185 << f 186: OpFMul: FloatVector3: tmp186 << tmp184, tmp185 187: OpLoad: FloatVector3: tmp187 << f 188: OpVectorTimesScalar: FloatVector3: tmp188 << tmp187, const127 189: OpCompositeConstruct: FloatVector3: tmp189 << const109, const109, const109 190: OpFSub: FloatVector3: tmp190 << tmp189, tmp188 191: OpFMul: FloatVector3: tmp191 << tmp186, tmp190 OpStore: : tmp191 >> f 195: OpAccessChain: Float*: p[0] 196: OpCompositeExtract: Float: tmp196 << tmp180, 0 198: OpAccessChain: Float*: p[1] 199: OpCompositeExtract: Float: tmp199 << tmp180, 1 201: OpFMul: Float: tmp201 << tmp199, const200 202: OpFAdd: Float: tmp202 << tmp196, tmp201 205: OpAccessChain: Float*: p[2] 206: OpCompositeExtract: Float: tmp206 << tmp180, 2 207: OpFMul: Float: tmp207 << const203, tmp206 208: OpFAdd: Float: tmp208 << tmp202, tmp207 210: OpFAdd: Float: tmp210 << tmp208, const100 OpStore: : tmp210 >> param211 212: OpFunctionCall: Float: hash(f1;(param211) 214: OpFAdd: Float: tmp214 << tmp208, const106 OpStore: : tmp214 >> param215 216: OpFunctionCall: Float: hash(f1;(param215) 217: OpAccessChain: Float*: f[0] 218: OpLoad: Float: tmp218 << f[0] 219: OpExtInst(FMix): Float: tmp219 << hash(f1;, hash(f1;, tmp218 221: OpFAdd: Float: tmp221 << tmp208, const200 OpStore: : tmp221 >> param222 223: OpFunctionCall: Float: hash(f1;(param222) 226: OpFAdd: Float: tmp226 << tmp208, const225 OpStore: : tmp226 >> param227 228: OpFunctionCall: Float: hash(f1;(param227) 229: OpAccessChain: Float*: f[0] 230: OpLoad: Float: tmp230 << f[0] 231: OpExtInst(FMix): Float: tmp231 << hash(f1;, hash(f1;, tmp230 232: OpAccessChain: Float*: f[1] 233: OpLoad: Float: tmp233 << f[1] 234: OpExtInst(FMix): Float: tmp234 << tmp219, tmp231, tmp233 236: OpFAdd: Float: tmp236 << tmp208, const203 OpStore: : tmp236 >> param237 238: OpFunctionCall: Float: hash(f1;(param237) 241: OpFAdd: Float: tmp241 << tmp208, const240 OpStore: : tmp241 >> param242 243: OpFunctionCall: Float: hash(f1;(param242) 244: OpAccessChain: Float*: f[0] 245: OpLoad: Float: tmp245 << f[0] 246: OpExtInst(FMix): Float: tmp246 << hash(f1;, hash(f1;, tmp245 249: OpFAdd: Float: tmp249 << tmp208, const248 OpStore: : tmp249 >> param250 251: OpFunctionCall: Float: hash(f1;(param250) 254: OpFAdd: Float: tmp254 << tmp208, const253 OpStore: : tmp254 >> param255 256: OpFunctionCall: Float: hash(f1;(param255) 257: OpAccessChain: Float*: f[0] 258: OpLoad: Float: tmp258 << f[0] 259: OpExtInst(FMix): Float: tmp259 << hash(f1;, hash(f1;, tmp258 260: OpAccessChain: Float*: f[1] 261: OpLoad: Float: tmp261 << f[1] 262: OpExtInst(FMix): Float: tmp262 << tmp246, tmp259, tmp261 263: OpAccessChain: Float*: f[2] 264: OpLoad: Float: tmp264 << f[2] 265: OpExtInst(FMix): Float: tmp265 << tmp234, tmp262, tmp264 OpReturnValue: : << tmp265 29: OpFunction: Float smN2(vf2;(FloatVector2* p) 272: OpVariable: FloatVector3*: param272: storage class: Function 30: lb30: 268: OpLoad: FloatVector2: tmp268 << p 269: OpCompositeExtract: Float: tmp269 << tmp268, 0 270: OpCompositeExtract: Float: tmp270 << tmp268, 1 271: OpCompositeConstruct: FloatVector3: tmp271 << tmp269, tmp270, const100 OpStore: : tmp271 >> param272 273: OpFunctionCall: Float: noise(vf3;(param272) OpReturnValue: : << noise(vf3; 32: OpFunction: Float smN3(vf3;(FloatVector3* p) 276: OpVariable: FloatVector3*: param276: storage class: Function 33: lb33: 277: OpLoad: FloatVector3: tmp277 << p OpStore: : tmp277 >> param276 278: OpFunctionCall: Float: noise(vf3;(param276) OpReturnValue: : << noise(vf3; 35: OpFunction: Float fbm3(vf3;(FloatVector3* p) 281: OpVariable: Float*: f: storage class: Function 284: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 301: OpVariable: FloatVector3*: param301: storage class: Function 36: lb36: OpStore: : const100 >> f OpStore: : const285 >> i OpBranch: to lb286 286: lb286: OpLoopMerge: (merge: lb288, continue: lb289) OpBranch: to lb290 290: lb290: 291: OpLoad: Int: tmp291 << i Decorators: RelaxedPrecision 293: OpSLessThanEqual: Bool: tmp293 << tmp291, const292 OpBranchConditional: if(tmp293) then branch to lb287, else branch to lb288 287: lb287: 295: OpLoad: Int: tmp295 << i Decorators: RelaxedPrecision 296: OpConvertSToF: Float: tmp296 << tmp295 297: OpExtInst(Exp2): Float: tmp297 << tmp296 298: OpLoad: FloatVector3: tmp298 << p 300: OpVectorTimesScalar: FloatVector3: tmp300 << tmp298, tmp297 OpStore: : tmp300 >> param301 302: OpFunctionCall: Float: noise(vf3;(param301) 304: OpFSub: Float: tmp304 << noise(vf3;, const303 306: OpFDiv: Float: tmp306 << tmp304, tmp297 307: OpLoad: Float: tmp307 << f 308: OpFAdd: Float: tmp308 << tmp307, tmp306 OpStore: : tmp308 >> f OpBranch: to lb289 289: lb289: 309: OpLoad: Int: tmp309 << i Decorators: RelaxedPrecision 310: OpIAdd: Int: tmp310 << tmp309, const285 Decorators: RelaxedPrecision OpStore: : tmp310 >> i OpBranch: to lb286 288: lb288: 311: OpLoad: Float: tmp311 << f OpReturnValue: : << tmp311 40: OpFunction: FloatVector2 rotate(f1;vf2;(Float* a, FloatVector2* v) 41: lb41: 314: OpLoad: Float: tmp314 << a 315: OpExtInst(Cos): Float: tmp315 << tmp314 316: OpAccessChain: Float*: v[0] 317: OpLoad: Float: tmp317 << v[0] 318: OpFMul: Float: tmp318 << tmp315, tmp317 319: OpLoad: Float: tmp319 << a 320: OpExtInst(Sin): Float: tmp320 << tmp319 321: OpAccessChain: Float*: v[1] 322: OpLoad: Float: tmp322 << v[1] 323: OpFMul: Float: tmp323 << tmp320, tmp322 324: OpFAdd: Float: tmp324 << tmp318, tmp323 325: OpLoad: Float: tmp325 << a 326: OpExtInst(Cos): Float: tmp326 << tmp325 327: OpAccessChain: Float*: v[1] 328: OpLoad: Float: tmp328 << v[1] 329: OpFMul: Float: tmp329 << tmp326, tmp328 330: OpLoad: Float: tmp330 << a 331: OpExtInst(Sin): Float: tmp331 << tmp330 332: OpAccessChain: Float*: v[0] 333: OpLoad: Float: tmp333 << v[0] 334: OpFMul: Float: tmp334 << tmp331, tmp333 335: OpFSub: Float: tmp335 << tmp329, tmp334 336: OpCompositeConstruct: FloatVector2: tmp336 << tmp324, tmp335 OpReturnValue: : << tmp336 43: OpFunction: Float sugarybit(vf2;(FloatVector2* p) 44: lb44: 339: OpLoad: FloatVector2: tmp339 << p 343: OpExtInst(FClamp): FloatVector2: tmp343 << tmp339, const341, const342 OpStore: : tmp343 >> p 346: OpAccessChain: Float*: p[0] 347: OpLoad: Float: tmp347 << p[0] 348: OpExtInst(FAbs): Float: tmp348 << tmp347 350: OpExtInst(Pow): Float: tmp350 << tmp348, const349 351: OpFSub: Float: tmp351 << const106, tmp350 352: OpAccessChain: Float*: p[1] 353: OpLoad: Float: tmp353 << p[1] 354: OpAccessChain: Float*: o[1] 355: OpCompositeExtract: Float: tmp355 << const101, 1 356: OpFAdd: Float: tmp356 << tmp353, tmp355 357: OpExtInst(FAbs): Float: tmp357 << tmp356 358: OpExtInst(Pow): Float: tmp358 << tmp357, const349 359: OpFSub: Float: tmp359 << const106, tmp358 360: OpFMul: Float: tmp360 << tmp351, tmp359 362: OpFMul: Float: tmp362 << tmp360, const361 363: OpExtInst(Pow): Float: tmp363 << tmp362, const303 364: OpFSub: Float: tmp364 << const106, tmp363 366: OpAccessChain: Float*: p[0] 367: OpLoad: Float: tmp367 << p[0] 368: OpExtInst(FAbs): Float: tmp368 << tmp367 369: OpExtInst(Pow): Float: tmp369 << tmp368, const349 370: OpFSub: Float: tmp370 << const106, tmp369 371: OpAccessChain: Float*: p[1] 372: OpLoad: Float: tmp372 << p[1] 373: OpExtInst(FAbs): Float: tmp373 << tmp372 374: OpExtInst(Pow): Float: tmp374 << tmp373, const349 375: OpFSub: Float: tmp375 << const106, tmp374 376: OpFMul: Float: tmp376 << tmp370, tmp375 378: OpExtInst(Pow): Float: tmp378 << tmp376, const377 381: OpFMul: Float: tmp381 << tmp364, tmp378 382: OpFMul: Float: tmp382 << tmp381, const109 OpReturnValue: : << tmp382 48: OpFunction: Float sugarlayer(vf2;f1;(FloatVector2* t, Float* ndotv) 419: OpVariable: FloatVector2*: param419: storage class: Function 426: OpVariable: FloatVector2*: param426: storage class: Function 445: OpVariable: Float*: param445: storage class: Function 447: OpVariable: FloatVector2*: param447: storage class: Function 449: OpVariable: FloatVector2*: param449: storage class: Function 453: OpVariable: FloatVector2*: param453: storage class: Function 49: lb49: 386: OpLoad: FloatVector2: tmp386 << t 387: OpVectorTimesScalar: FloatVector2: tmp387 << tmp386, const349 390: OpExtInst(Fract): FloatVector2: tmp390 << tmp387 392: OpFSub: FloatVector2: tmp392 << tmp390, const391 395: OpExtInst(Floor): FloatVector2: tmp395 << tmp387 397: OpAccessChain: Float*: c[0] 398: OpCompositeExtract: Float: tmp398 << tmp395, 0 399: OpAccessChain: Float*: c[1] 400: OpCompositeExtract: Float: tmp400 << tmp395, 1 402: OpFMul: Float: tmp402 << tmp400, const401 403: OpFAdd: Float: tmp403 << tmp398, tmp402 405: OpAccessChain: Float*: c[1] 406: OpCompositeExtract: Float: tmp406 << tmp395, 1 408: OpFMul: Float: tmp408 << tmp406, const407 409: OpExtInst(Cos): Float: tmp409 << tmp408 410: OpAccessChain: Float*: c[0] 411: OpCompositeExtract: Float: tmp411 << tmp395, 0 413: OpFMul: Float: tmp413 << tmp411, const412 414: OpExtInst(Sin): Float: tmp414 << tmp413 415: OpCompositeConstruct: FloatVector2: tmp415 << tmp409, tmp414 417: OpVectorTimesScalar: FloatVector2: tmp417 << tmp415, const416 OpStore: : tmp395 >> param419 421: OpFunctionCall: Float: smN2(vf2;(param419) 425: OpFAdd: FloatVector2: tmp425 << tmp395, const424 OpStore: : tmp425 >> param426 427: OpFunctionCall: Float: smN2(vf2;(param426) 428: OpCompositeConstruct: FloatVector2: tmp428 << smN2(vf2;, smN2(vf2; 429: OpCompositeConstruct: FloatVector2: tmp429 << const106, const106 430: OpFAdd: FloatVector2: tmp430 << tmp429, tmp428 432: OpLoad: Float: tmp432 << ndotv 433: OpFSub: Float: tmp433 << const106, tmp432 434: OpExtInst(Pow): Float: tmp434 << tmp433, const377 436: OpExtInst(FMix): Float: tmp436 << const106, tmp434, const435 438: OpFMul: Float: tmp438 << tmp436, const437 441: OpFMul: FloatVector2: tmp441 << tmp392, tmp430 442: OpVectorTimesScalar: FloatVector2: tmp442 << tmp441, const377 444: OpFAdd: FloatVector2: tmp444 << tmp442, tmp417 OpStore: : tmp403 >> param445 OpStore: : tmp444 >> param447 448: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param445, param447) OpStore: : rotate(f1;vf2; >> param449 450: OpFunctionCall: Float: sugarybit(vf2;(param449) 452: OpVectorTimesScalar: FloatVector2: tmp452 << tmp387, const401 OpStore: : tmp452 >> param453 454: OpFunctionCall: Float: smN2(vf2;(param453) 455: OpFSub: Float: tmp455 << smN2(vf2;, const303 456: OpExtInst(FMax): Float: tmp456 << const100, tmp455 457: OpFMul: Float: tmp457 << sugarybit(vf2;, tmp456 459: OpFMul: Float: tmp459 << tmp457, tmp438 OpReturnValue: : << tmp459 52: OpFunction: FloatVector3 saturatecol(vf3;(FloatVector3* c) 463: OpVariable: Float*: param463: storage class: Function 53: lb53: 462: OpLoad: FloatVector3: tmp462 << c 464: OpLoad: Float: tmp464 << colour OpStore: : tmp464 >> param463 465: OpFunctionCall: FloatVector3: gumRamp(f1;(param463) 466: OpExtInst(Pow): FloatVector3: tmp466 << tmp462, gumRamp(f1; OpReturnValue: : << tmp466 56: OpFunction: Float sprinkles2(vf2;f1;(FloatVector2* coord, Float* ndotv) 469: OpVariable: Float*: sprinkle: storage class: Function 470: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 493: OpVariable: FloatVector2*: param493: storage class: Function 494: OpVariable: Float*: param494: storage class: Function 57: lb57: OpStore: : const100 >> sprinkle OpStore: : const471 >> i OpBranch: to lb472 472: lb472: OpLoopMerge: (merge: lb474, continue: lb475) OpBranch: to lb476 476: lb476: 477: OpLoad: Int: tmp477 << i Decorators: RelaxedPrecision 479: OpSLessThan: Bool: tmp479 << tmp477, const478 OpBranchConditional: if(tmp479) then branch to lb473, else branch to lb474 473: lb473: 480: OpLoad: FloatVector2: tmp480 << coord 481: OpLoad: Int: tmp481 << i Decorators: RelaxedPrecision 482: OpConvertSToF: Float: tmp482 << tmp481 484: OpFMul: Float: tmp484 << tmp482, const483 485: OpCompositeConstruct: FloatVector2: tmp485 << tmp484, tmp484 486: OpFAdd: FloatVector2: tmp486 << tmp480, tmp485 487: OpLoad: Int: tmp487 << i Decorators: RelaxedPrecision 488: OpConvertSToF: Float: tmp488 << tmp487 490: OpFMul: Float: tmp490 << tmp488, const489 491: OpFAdd: Float: tmp491 << const106, tmp490 492: OpVectorTimesScalar: FloatVector2: tmp492 << tmp486, tmp491 OpStore: : tmp492 >> param493 495: OpLoad: Float: tmp495 << ndotv OpStore: : tmp495 >> param494 496: OpFunctionCall: Float: sugarlayer(vf2;f1;(param493, param494) 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision 498: OpConvertSToF: Float: tmp498 << tmp497 499: OpFDiv: Float: tmp499 << tmp498, const377 500: OpFSub: Float: tmp500 << const106, tmp499 501: OpExtInst(Pow): Float: tmp501 << tmp500, const377 502: OpFMul: Float: tmp502 << sugarlayer(vf2;f1;, tmp501 503: OpLoad: Float: tmp503 << sprinkle 504: OpFAdd: Float: tmp504 << tmp503, tmp502 OpStore: : tmp504 >> sprinkle OpBranch: to lb475 475: lb475: 505: OpLoad: Int: tmp505 << i Decorators: RelaxedPrecision 506: OpIAdd: Int: tmp506 << tmp505, const285 Decorators: RelaxedPrecision OpStore: : tmp506 >> i OpBranch: to lb472 474: lb474: 507: OpLoad: Float: tmp507 << sprinkle OpReturnValue: : << tmp507 60: OpFunction: Float sprinkles(vf2;f1;(FloatVector2* coord, Float* ndotv) 513: OpVariable: FloatVector2*: param513: storage class: Function 514: OpVariable: Float*: param514: storage class: Function 519: OpVariable: FloatVector2*: param519: storage class: Function 520: OpVariable: Float*: param520: storage class: Function 61: lb61: 510: OpLoad: FloatVector2: tmp510 << coord 512: OpVectorTimesScalar: FloatVector2: tmp512 << tmp510, const511 OpStore: : tmp512 >> param513 515: OpLoad: Float: tmp515 << ndotv OpStore: : tmp515 >> param514 516: OpFunctionCall: Float: sprinkles2(vf2;f1;(param513, param514) 517: OpLoad: FloatVector2: tmp517 << coord 518: OpVectorTimesScalar: FloatVector2: tmp518 << tmp517, const127 OpStore: : tmp518 >> param519 521: OpLoad: Float: tmp521 << ndotv OpStore: : tmp521 >> param520 522: OpFunctionCall: Float: sprinkles2(vf2;f1;(param519, param520) 524: OpFMul: Float: tmp524 << sprinkles2(vf2;f1;, const523 525: OpFAdd: Float: tmp525 << sprinkles2(vf2;f1;, tmp524 OpReturnValue: : << tmp525 66: OpFunction: FloatVector3 gummy(vf3;vf3;vf3;(FloatVector3* no, FloatVector3* vo, FloatVector3* v) 544: OpVariable: FloatVector2*: param544: storage class: Function 545: OpVariable: Float*: param545: storage class: Function 549: OpVariable: FloatVector2*: param549: storage class: Function 552: OpVariable: Float*: param552: storage class: Function 568: OpVariable: FloatVector3*: tex: storage class: Function 570: OpVariable: Float*: param570: storage class: Function 591: OpVariable: FloatVector3*: param591: storage class: Function 67: lb67: 529: OpLoad: FloatVector3: tmp529 << no 530: OpLoad: FloatVector3: tmp530 << v 531: OpFNegate: FloatVector3: tmp531 << tmp530 532: OpDot: Float: tmp532 << tmp529, tmp531 534: OpAccessChain: Float*: no[2] 535: OpLoad: Float: tmp535 << no[2] 536: OpAccessChain: Float*: no[0] 537: OpLoad: Float: tmp537 << no[0] 538: OpExtInst(Atan2): Float: tmp538 << tmp535, tmp537 539: OpAccessChain: Float*: no[1] 540: OpLoad: Float: tmp540 << no[1] 541: OpExtInst(Asin): Float: tmp541 << tmp540 542: OpCompositeConstruct: FloatVector2: tmp542 << tmp538, tmp541 543: OpVectorTimesScalar: FloatVector2: tmp543 << tmp542, const511 OpStore: : tmp543 >> param544 OpStore: : tmp532 >> param545 547: OpFunctionCall: Float: sprinkles(vf2;f1;(param544, param545) 550: OpLoad: FloatVector3: tmp550 << vo 551: OpVectorShuffle: FloatVector2: tmp551 << tmp550, tmp550, 0, 2 OpStore: : tmp551 >> param549 OpStore: : tmp532 >> param552 554: OpFunctionCall: Float: sprinkles(vf2;f1;(param549, param552) 558: OpAccessChain: Float*: no[1] 559: OpLoad: Float: tmp559 << no[1] 560: OpExtInst(SmoothStep): Float: tmp560 << const523, const303, tmp559 561: OpExtInst(FMix): Float: tmp561 << sprinkles(vf2;f1;, sprinkles(vf2;f1;, tmp560 563: OpAccessChain: Float*: no[1] 564: OpLoad: Float: tmp564 << no[1] 565: OpFSub: Float: tmp565 << tmp564, const523 566: OpFMul: Float: tmp566 << tmp565, const401 567: OpExtInst(FClamp): Float: tmp567 << tmp566, const100, const106 571: OpLoad: Float: tmp571 << colour OpStore: : tmp571 >> param570 572: OpFunctionCall: FloatVector3: gumColour(f1;(param570) 574: OpCompositeConstruct: FloatVector3: tmp574 << const573, const573, const573 575: OpExtInst(FMix): FloatVector3: tmp575 << const569, gumColour(f1;, tmp574 577: OpAccessChain: Float*: tc[0] 578: OpLoad: Float: tmp578 << tc[0] 579: OpExtInst(FAbs): Float: tmp579 << tmp578 580: OpFSub: Float: tmp580 << const106, tmp579 581: OpFMul: Float: tmp581 << tmp580, const303 582: OpExtInst(Pow): Float: tmp582 << tmp581, const489 583: OpFAdd: Float: tmp583 << const576, tmp582 584: OpVectorTimesScalar: FloatVector3: tmp584 << tmp575, tmp583 588: OpFMul: Float: tmp588 << tmp561, tmp567 589: OpCompositeConstruct: FloatVector3: tmp589 << tmp588, tmp588, tmp588 590: OpExtInst(FMix): FloatVector3: tmp590 << tmp584, const585, tmp589 OpStore: : tmp590 >> param591 592: OpFunctionCall: FloatVector3: saturatecol(vf3;(param591) OpStore: : saturatecol(vf3; >> tex 595: OpFSub: Float: tmp595 << const593, tmp532 596: OpLoad: FloatVector3: tmp596 << tex 597: OpVectorTimesScalar: FloatVector3: tmp597 << tmp596, tmp595 OpStore: : tmp597 >> tex 599: OpFSub: Float: tmp599 << const106, tmp532 600: OpExtInst(Pow): Float: tmp600 << tmp599, const349 601: OpCompositeConstruct: FloatVector3: tmp601 << tmp600, tmp600, tmp600 603: OpVectorTimesScalar: FloatVector3: tmp603 << tmp601, const602 604: OpLoad: FloatVector3: tmp604 << tex 605: OpFAdd: FloatVector3: tmp605 << tmp604, tmp603 OpStore: : tmp605 >> tex 606: OpLoad: FloatVector3: tmp606 << tex OpReturnValue: : << tmp606 69: OpFunction: Float de(vf3;(FloatVector3* p) 635: OpVariable: FloatVector3*: param635: storage class: Function 643: OpVariable: FloatVector3*: param643: storage class: Function 70: lb70: 610: OpAccessChain: Float*: p[1] 611: OpLoad: Float: tmp611 << p[1] 612: OpFMul: Float: tmp612 << tmp611, const609 613: OpAccessChain: Float*: p[1] OpStore: : tmp612 >> p[1] 615: OpLoad: FloatVector3: tmp615 << p 616: OpCompositeConstruct: FloatVector3: tmp616 << const109, const109, const109 617: OpFDiv: FloatVector3: tmp617 << tmp615, tmp616 618: OpExtInst(Floor): FloatVector3: tmp618 << tmp617 619: OpAccessChain: Float*: fp[0] 620: OpCompositeExtract: Float: tmp620 << tmp618, 0 622: OpFMul: Float: tmp622 << tmp620, const621 623: OpAccessChain: Float*: fp[2] 624: OpCompositeExtract: Float: tmp624 << tmp618, 2 626: OpFMul: Float: tmp626 << tmp624, const625 627: OpFSub: Float: tmp627 << tmp622, tmp626 628: OpExtInst(Cos): Float: tmp628 << tmp627 629: OpFAdd: Float: tmp629 << tmp628, const576 630: OpExtInst(Step): Float: tmp630 << const100, tmp629 OpStore: : tmp630 >> is_choc 632: OpLoad: FloatVector3: tmp632 << p 634: OpVectorTimesScalar: FloatVector3: tmp634 << tmp632, const633 OpStore: : tmp634 >> param635 636: OpFunctionCall: Float: smN3(vf3;(param635) 638: OpFMul: Float: tmp638 << smN3(vf3;, const637 639: OpLoad: Float: tmp639 << is_choc 640: OpFMul: Float: tmp640 << tmp638, tmp639 641: OpLoad: FloatVector3: tmp641 << p 642: OpVectorTimesScalar: FloatVector3: tmp642 << tmp641, const401 OpStore: : tmp642 >> param643 644: OpFunctionCall: Float: smN3(vf3;(param643) 645: OpExtInst(FMax): Float: tmp645 << const100, smN3(vf3; 646: OpExtInst(Pow): Float: tmp646 << tmp645, const401 648: OpLoad: Float: tmp648 << is_choc 649: OpFSub: Float: tmp649 << const106, tmp648 650: OpFMul: Float: tmp650 << const647, tmp649 651: OpFAdd: Float: tmp651 << const602, tmp650 652: OpFMul: Float: tmp652 << tmp646, tmp651 653: OpFSub: Float: tmp653 << tmp640, tmp652 654: OpAccessChain: Float*: fp[0] 655: OpCompositeExtract: Float: tmp655 << tmp618, 0 656: OpAccessChain: Float*: fp[2] 657: OpCompositeExtract: Float: tmp657 << tmp618, 2 658: OpExtInst(Sin): Float: tmp658 << tmp657 659: OpFMul: Float: tmp659 << tmp658, const109 660: OpFAdd: Float: tmp660 << tmp655, tmp659 661: OpFMod: Float: tmp661 << tmp660, const377 OpStore: : tmp661 >> colour 662: OpLoad: FloatVector3: tmp662 << p 663: OpVectorShuffle: FloatVector2: tmp663 << tmp662, tmp662, 0, 2 665: OpFMod: FloatVector2: tmp665 << tmp663, const664 668: OpFSub: FloatVector2: tmp668 << tmp665, const667 669: OpLoad: FloatVector3: tmp669 << p 670: OpVectorShuffle: FloatVector3: tmp670 << tmp669, tmp668, 3, 1, 4 OpStore: : tmp670 >> p 672: OpAccessChain: Float*: fp[2] 673: OpCompositeExtract: Float: tmp673 << tmp618, 2 675: OpFMul: Float: tmp675 << tmp673, const674 676: OpAccessChain: Float*: fp[0] 677: OpCompositeExtract: Float: tmp677 << tmp618, 0 679: OpFMul: Float: tmp679 << tmp677, const678 680: OpFAdd: Float: tmp680 << tmp675, tmp679 681: OpExtInst(Cos): Float: tmp681 << tmp680 682: OpFMul: Float: tmp682 << const303, tmp681 683: OpFAdd: Float: tmp683 << const303, tmp682 684: OpExtInst(FMix): Float: tmp684 << const671, const106, tmp683 OpStore: : tmp684 >> ss 686: OpLoad: FloatVector3: tmp686 << p 687: OpExtInst(Length): Float: tmp687 << tmp686 688: OpLoad: Float: tmp688 << ss 689: OpFSub: Float: tmp689 << tmp687, tmp688 691: OpAccessChain: Float*: p[1] 692: OpLoad: Float: tmp692 << p[1] 693: OpFNegate: Float: tmp693 << tmp692 696: OpExtInst(FMax): Float: tmp696 << const100, tmp689 698: OpExtInst(FMax): Float: tmp698 << const100, tmp693 699: OpCompositeConstruct: FloatVector2: tmp699 << tmp696, tmp698 700: OpExtInst(Length): Float: tmp700 << tmp699 701: OpFSub: Float: tmp701 << tmp700, const576 703: OpFAdd: Float: tmp703 << tmp701, tmp653 705: OpFMul: Float: tmp705 << tmp703, const704 OpReturnValue: : << tmp705 73: OpFunction: FloatVector3 marble(vf2;(FloatVector2* p) 740: OpVariable: FloatVector3*: param740: storage class: Function 767: OpVariable: FloatVector3*: param767: storage class: Function 779: OpVariable: FloatVector3*: param779: storage class: Function 790: OpVariable: FloatVector3*: param790: storage class: Function 74: lb74: 709: OpAccessChain: Float*: p[0] 710: OpLoad: Float: tmp710 << p[0] 711: OpFAdd: Float: tmp711 << tmp710, const127 712: OpAccessChain: Float*: p[0] OpStore: : tmp711 >> p[0] 717: OpLoad: FloatVector2: tmp717 << p 718: OpExtInst(Floor): FloatVector2: tmp718 << tmp717 720: OpLoad: FloatVector2: tmp720 << p 722: OpFSub: FloatVector2: tmp722 << tmp720, tmp718 723: OpFSub: FloatVector2: tmp723 << tmp722, const391 725: OpAccessChain: Float*: c1[0] 726: OpCompositeExtract: Float: tmp726 << tmp723, 0 727: OpVectorTimesScalar: FloatVector2: tmp727 << const342, tmp726 728: OpAccessChain: Float*: c1[1] 729: OpCompositeExtract: Float: tmp729 << tmp723, 1 731: OpVectorTimesScalar: FloatVector2: tmp731 << const730, tmp729 732: OpFAdd: FloatVector2: tmp732 << tmp727, tmp731 733: OpVectorTimesScalar: FloatVector2: tmp733 << tmp732, const704 736: OpLoad: FloatVector2: tmp736 << p 737: OpCompositeExtract: Float: tmp737 << tmp736, 0 738: OpCompositeExtract: Float: tmp738 << tmp736, 1 739: OpCompositeConstruct: FloatVector3: tmp739 << tmp737, tmp738, const100 OpStore: : tmp739 >> param740 741: OpFunctionCall: Float: fbm3(vf3;(param740) 742: OpFMul: Float: tmp742 << fbm3(vf3;, const303 743: OpExtInst(FMax): Float: tmp743 << const100, tmp742 744: OpCompositeConstruct: FloatVector3: tmp744 << tmp743, tmp743, tmp743 745: OpCompositeConstruct: FloatVector3: tmp745 << const511, const511, const511 746: OpExtInst(FMix): FloatVector3: tmp746 << const735, tmp744, tmp745 754: OpVectorTimesScalar: FloatVector2: tmp754 << tmp718, const127 755: OpLoad: FloatVector2: tmp755 << p 756: OpVectorTimesScalar: FloatVector2: tmp756 << tmp755, const106 757: OpFAdd: FloatVector2: tmp757 << tmp754, tmp756 758: OpLoad: FloatVector2: tmp758 << p 759: OpVectorShuffle: FloatVector2: tmp759 << tmp758, tmp758, 1, 0 760: OpVectorTimesScalar: FloatVector2: tmp760 << tmp759, const127 761: OpExtInst(Cos): FloatVector2: tmp761 << tmp760 762: OpVectorTimesScalar: FloatVector2: tmp762 << tmp761, const748 763: OpFAdd: FloatVector2: tmp763 << tmp757, tmp762 764: OpCompositeExtract: Float: tmp764 << tmp763, 0 765: OpCompositeExtract: Float: tmp765 << tmp763, 1 766: OpCompositeConstruct: FloatVector3: tmp766 << tmp764, tmp765, const100 OpStore: : tmp766 >> param767 768: OpFunctionCall: Float: fbm3(vf3;(param767) 769: OpFAdd: Float: tmp769 << const303, fbm3(vf3; 770: OpExtInst(SmoothStep): Float: tmp770 << const748, const151, tmp769 771: OpFSub: Float: tmp771 << const106, tmp770 772: OpCompositeConstruct: FloatVector3: tmp772 << tmp771, tmp771, tmp771 773: OpExtInst(FMix): FloatVector3: tmp773 << const750, const752, tmp772 774: OpLoad: FloatVector2: tmp774 << p 775: OpVectorTimesScalar: FloatVector2: tmp775 << tmp774, const671 776: OpCompositeExtract: Float: tmp776 << tmp775, 0 777: OpCompositeExtract: Float: tmp777 << tmp775, 1 778: OpCompositeConstruct: FloatVector3: tmp778 << tmp776, tmp777, const100 OpStore: : tmp778 >> param779 780: OpFunctionCall: Float: fbm3(vf3;(param779) 781: OpFMul: Float: tmp781 << fbm3(vf3;, const106 782: OpExtInst(FMax): Float: tmp782 << const100, tmp781 783: OpCompositeConstruct: FloatVector3: tmp783 << tmp782, tmp782, tmp782 784: OpFAdd: FloatVector3: tmp784 << tmp773, tmp783 785: OpLoad: FloatVector2: tmp785 << p 786: OpFNegate: FloatVector2: tmp786 << tmp785 787: OpCompositeExtract: Float: tmp787 << tmp786, 0 788: OpCompositeExtract: Float: tmp788 << tmp786, 1 789: OpCompositeConstruct: FloatVector3: tmp789 << tmp787, tmp788, const100 OpStore: : tmp789 >> param790 791: OpFunctionCall: Float: fbm3(vf3;(param790) 792: OpExtInst(SmoothStep): Float: tmp792 << const489, const523, fbm3(vf3; 793: OpCompositeConstruct: FloatVector3: tmp793 << tmp792, tmp792, tmp792 794: OpVectorTimesScalar: FloatVector3: tmp794 << tmp793, const489 795: OpFAdd: FloatVector3: tmp795 << tmp784, tmp794 798: OpCompositeConstruct: FloatVector3: tmp798 << const303, const303, const303 799: OpExtInst(FMix): FloatVector3: tmp799 << tmp795, const735, tmp798 802: OpFSub: Float: tmp802 << const303, const714 803: OpAccessChain: Float*: c1[1] 804: OpCompositeExtract: Float: tmp804 << tmp723, 1 805: OpExtInst(FAbs): Float: tmp805 << tmp804 806: OpExtInst(SmoothStep): Float: tmp806 << tmp802, const303, tmp805 808: OpFSub: Float: tmp808 << const303, const714 809: OpAccessChain: Float*: c1[0] 810: OpCompositeExtract: Float: tmp810 << tmp723, 0 811: OpExtInst(FAbs): Float: tmp811 << tmp810 812: OpExtInst(SmoothStep): Float: tmp812 << tmp808, const303, tmp811 813: OpExtInst(FMax): Float: tmp813 << tmp806, tmp812 816: OpFSub: Float: tmp816 << const303, const714 817: OpAccessChain: Float*: rc1[1] 818: OpCompositeExtract: Float: tmp818 << tmp733, 1 819: OpExtInst(FAbs): Float: tmp819 << tmp818 820: OpExtInst(SmoothStep): Float: tmp820 << tmp816, const303, tmp819 822: OpFSub: Float: tmp822 << const303, const714 823: OpAccessChain: Float*: rc1[0] 824: OpCompositeExtract: Float: tmp824 << tmp733, 0 825: OpExtInst(FAbs): Float: tmp825 << tmp824 826: OpExtInst(SmoothStep): Float: tmp826 << tmp822, const303, tmp825 827: OpExtInst(FMax): Float: tmp827 << tmp820, tmp826 832: OpCompositeConstruct: FloatVector3: tmp832 << tmp827, tmp827, tmp827 833: OpExtInst(FMix): FloatVector3: tmp833 << tmp799, tmp746, tmp832 836: OpExtInst(FMax): Float: tmp836 << tmp827, tmp813 837: OpCompositeConstruct: FloatVector3: tmp837 << tmp836, tmp836, tmp836 838: OpExtInst(FMix): FloatVector3: tmp838 << tmp795, tmp833, tmp837 839: OpVectorTimesScalar: FloatVector3: tmp839 << tmp838, const151 OpReturnValue: : << tmp839 76: OpFunction: FloatVector3 cameraPos(f1;(Float* t) 77: lb77: 842: OpLoad: Float: tmp842 << t 843: OpFMul: Float: tmp843 << tmp842, const704 845: OpLoad: Float: tmp845 << t 846: OpFMul: Float: tmp846 << tmp845, const377 847: OpExtInst(Cos): Float: tmp847 << tmp846 849: OpFMul: Float: tmp849 << tmp847, const848 850: OpFAdd: Float: tmp850 << const844, tmp849 851: OpCompositeConstruct: FloatVector3: tmp851 << tmp843, tmp850, const100 OpReturnValue: : << tmp851 79: OpFunction: FloatVector3 targetPos(f1;(Float* ti) 854: OpVariable: FloatVector3*: target: storage class: Function 858: OpVariable: Float*: param858: storage class: Function 80: lb80: 855: OpLoad: Float: tmp855 << ti 856: OpLoad: Float: tmp856 << t_per_target 857: OpFMul: Float: tmp857 << tmp855, tmp856 OpStore: : tmp857 >> param858 859: OpFunctionCall: FloatVector3: cameraPos(f1;(param858) 861: OpFMul: FloatVector3: tmp861 << cameraPos(f1;, const860 862: OpLoad: Float: tmp862 << ti 864: OpFMul: Float: tmp864 << tmp862, const863 865: OpExtInst(Cos): Float: tmp865 << tmp864 866: OpFMul: Float: tmp866 << tmp865, const377 868: OpLoad: Float: tmp868 << ti 870: OpFMul: Float: tmp870 << tmp868, const869 871: OpExtInst(Cos): Float: tmp871 << tmp870 872: OpFMul: Float: tmp872 << tmp871, const109 873: OpFAdd: Float: tmp873 << const867, tmp872 874: OpCompositeConstruct: FloatVector3: tmp874 << tmp866, const100, tmp873 875: OpFAdd: FloatVector3: tmp875 << tmp861, tmp874 OpStore: : tmp875 >> target 876: OpLoad: FloatVector3: tmp876 << target 877: OpVectorShuffle: FloatVector2: tmp877 << tmp876, tmp876, 0, 2 878: OpCompositeConstruct: FloatVector2: tmp878 << const109, const109 879: OpFDiv: FloatVector2: tmp879 << tmp877, tmp878 880: OpExtInst(Floor): FloatVector2: tmp880 << tmp879 881: OpVectorTimesScalar: FloatVector2: tmp881 << tmp880, const109 882: OpFAdd: FloatVector2: tmp882 << tmp881, const667 883: OpLoad: FloatVector3: tmp883 << target 884: OpVectorShuffle: FloatVector3: tmp884 << tmp883, tmp882, 3, 1, 4 OpStore: : tmp884 >> target 885: OpLoad: FloatVector3: tmp885 << target OpReturnValue: : << tmp885 82: OpFunction: Float cameraZoom(f1;(Float* ti) 83: lb83: 889: OpLoad: Float: tmp889 << ti 890: OpFMul: Float: tmp890 << tmp889, const633 891: OpExtInst(Cos): Float: tmp891 << tmp890 892: OpFMul: Float: tmp892 << const303, tmp891 893: OpFAdd: Float: tmp893 << const303, tmp892 894: OpExtInst(FMix): Float: tmp894 << const109, const888, tmp893 896: OpFMul: Float: tmp896 << tmp894, const895 OpReturnValue: : << tmp896 89: OpFunction: FloatVector3 trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* t, Float* max_t) 899: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 914: OpVariable: FloatVector3*: param914: storage class: Function 944: OpVariable: FloatVector3*: col: storage class: Function 949: OpVariable: FloatVector3*: param949: storage class: Function 957: OpVariable: FloatVector3*: param957: storage class: Function 965: OpVariable: FloatVector3*: param965: storage class: Function 973: OpVariable: FloatVector3*: param973: storage class: Function 1011: OpVariable: FloatVector3*: chocolour: storage class: Function 1028: OpVariable: FloatVector3*: param1028: storage class: Function 1079: OpVariable: FloatVector3*: param1079: storage class: Function 1081: OpVariable: FloatVector3*: param1081: storage class: Function 1083: OpVariable: FloatVector3*: param1083: storage class: Function 90: lb90: OpStore: : const471 >> i OpBranch: to lb900 900: lb900: OpLoopMerge: (merge: lb902, continue: lb903) OpBranch: to lb904 904: lb904: 905: OpLoad: Int: tmp905 << i Decorators: RelaxedPrecision 907: OpSLessThan: Bool: tmp907 << tmp905, const906 OpBranchConditional: if(tmp907) then branch to lb901, else branch to lb902 901: lb901: 909: OpLoad: FloatVector3: tmp909 << ro 910: OpLoad: FloatVector3: tmp910 << rd 911: OpLoad: Float: tmp911 << t 912: OpVectorTimesScalar: FloatVector3: tmp912 << tmp910, tmp911 913: OpFAdd: FloatVector3: tmp913 << tmp909, tmp912 OpStore: : tmp913 >> param914 915: OpFunctionCall: Float: de(vf3;(param914) 916: OpLoad: Float: tmp916 << t 917: OpLoad: Float: tmp917 << max_t 918: OpFOrdGreaterThan: Bool: tmp918 << tmp916, tmp917 OpSelectionMerge: (merge: lb920) OpBranchConditional: if(tmp918) then branch to lb919, else branch to lb920 919: lb919: OpReturnValue: : << const921 920: lb920: 924: OpExtInst(FAbs): Float: tmp924 << de(vf3; 926: OpFOrdLessThan: Bool: tmp926 << tmp924, const925 OpSelectionMerge: (merge: lb928) OpBranchConditional: if(tmp926) then branch to lb927, else branch to lb928 927: lb927: OpBranch: to lb902 928: lb928: 930: OpLoad: Float: tmp930 << max_t 931: OpFAdd: Float: tmp931 << tmp930, const637 932: OpLoad: Float: tmp932 << t 934: OpFAdd: Float: tmp934 << tmp932, de(vf3; 935: OpExtInst(FMin): Float: tmp935 << tmp931, tmp934 OpStore: : tmp935 >> t OpBranch: to lb903 903: lb903: 936: OpLoad: Int: tmp936 << i Decorators: RelaxedPrecision 937: OpIAdd: Int: tmp937 << tmp936, const285 Decorators: RelaxedPrecision OpStore: : tmp937 >> i OpBranch: to lb900 902: lb902: 939: OpLoad: FloatVector3: tmp939 << ro 940: OpLoad: FloatVector3: tmp940 << rd 941: OpLoad: Float: tmp941 << t 942: OpVectorTimesScalar: FloatVector3: tmp942 << tmp940, tmp941 943: OpFAdd: FloatVector3: tmp943 << tmp939, tmp942 OpStore: : const946 >> col OpStore: : tmp943 >> param949 951: OpFunctionCall: Float: de(vf3;(param949) 955: OpCompositeConstruct: FloatVector3: tmp955 << const637, const100, const100 956: OpFAdd: FloatVector3: tmp956 << tmp943, tmp955 OpStore: : tmp956 >> param957 958: OpFunctionCall: Float: de(vf3;(param957) 960: OpFSub: Float: tmp960 << de(vf3;, de(vf3; 963: OpCompositeConstruct: FloatVector3: tmp963 << const100, const637, const100 964: OpFAdd: FloatVector3: tmp964 << tmp943, tmp963 OpStore: : tmp964 >> param965 966: OpFunctionCall: Float: de(vf3;(param965) 968: OpFSub: Float: tmp968 << de(vf3;, de(vf3; 971: OpCompositeConstruct: FloatVector3: tmp971 << const100, const100, const637 972: OpFAdd: FloatVector3: tmp972 << tmp943, tmp971 OpStore: : tmp972 >> param973 974: OpFunctionCall: Float: de(vf3;(param973) 976: OpFSub: Float: tmp976 << de(vf3;, de(vf3; 977: OpCompositeConstruct: FloatVector3: tmp977 << tmp960, tmp968, tmp976 978: OpExtInst(Normalize): FloatVector3: tmp978 << tmp977 980: OpLoad: FloatVector3: tmp980 << rd 982: OpLoad: FloatVector3: tmp982 << l 983: OpLoad: FloatVector3: tmp983 << rd 984: OpFSub: FloatVector3: tmp984 << tmp982, tmp983 985: OpExtInst(Normalize): FloatVector3: tmp985 << tmp984 986: OpLoad: Float: tmp986 << is_choc 987: OpFOrdLessThan: Bool: tmp987 << tmp986, const303 OpSelectionMerge: (merge: lb989) OpBranchConditional: if(tmp987) then branch to lb988, else branch to lb1078 988: lb988: 990: OpAccessChain: Float*: rp[0] 991: OpCompositeExtract: Float: tmp991 << tmp943, 0 992: OpFDiv: Float: tmp992 << tmp991, const109 993: OpExtInst(Floor): Float: tmp993 << tmp992 994: OpFMod: Float: tmp994 << tmp993, const127 995: OpFOrdGreaterThan: Bool: tmp995 << tmp994, const303 OpSelectionMerge: (merge: lb997) OpBranchConditional: if(tmp995) then branch to lb996, else branch to lb1034 996: lb996: 1000: OpVectorShuffle: FloatVector2: tmp1000 << tmp943, tmp943, 0, 2 1002: OpVectorShuffle: FloatVector2: tmp1002 << tmp943, tmp943, 0, 2 1003: OpCompositeConstruct: FloatVector2: tmp1003 << const109, const109 1004: OpFDiv: FloatVector2: tmp1004 << tmp1002, tmp1003 1005: OpExtInst(Floor): FloatVector2: tmp1005 << tmp1004 1006: OpVectorTimesScalar: FloatVector2: tmp1006 << tmp1005, const109 1007: OpFAdd: FloatVector2: tmp1007 << tmp1006, const667 1008: OpExtInst(Distance): Float: tmp1008 << tmp1000, tmp1007 1009: OpFMul: Float: tmp1009 << tmp1008, const704 1010: OpExtInst(Pow): Float: tmp1010 << tmp1009, const127 1019: OpFAdd: Float: tmp1019 << const303, tmp1010 1021: OpFAdd: Float: tmp1021 << const704, tmp1010 1023: OpVectorShuffle: FloatVector2: tmp1023 << tmp943, tmp943, 0, 2 1024: OpVectorTimesScalar: FloatVector2: tmp1024 << tmp1023, const621 1025: OpCompositeExtract: Float: tmp1025 << tmp1024, 0 1026: OpCompositeExtract: Float: tmp1026 << tmp1024, 1 1027: OpCompositeConstruct: FloatVector3: tmp1027 << tmp1025, tmp1026, const100 OpStore: : tmp1027 >> param1028 1029: OpFunctionCall: Float: fbm3(vf3;(param1028) 1030: OpFAdd: Float: tmp1030 << const748, fbm3(vf3; 1031: OpExtInst(SmoothStep): Float: tmp1031 << tmp1019, tmp1021, tmp1030 1032: OpCompositeConstruct: FloatVector3: tmp1032 << tmp1031, tmp1031, tmp1031 1033: OpExtInst(FMix): FloatVector3: tmp1033 << const1013, const1017, tmp1032 OpStore: : tmp1033 >> chocolour OpBranch: to lb997 1034: lb1034: 1036: OpAccessChain: Float*: rp[0] 1037: OpCompositeExtract: Float: tmp1037 << tmp943, 0 1038: OpFMul: Float: tmp1038 << tmp1037, const621 1039: OpAccessChain: Float*: rp[2] 1040: OpCompositeExtract: Float: tmp1040 << tmp943, 2 1041: OpFMul: Float: tmp1041 << tmp1040, const401 1042: OpExtInst(Sin): Float: tmp1042 << tmp1041 1043: OpFAdd: Float: tmp1043 << tmp1038, tmp1042 1044: OpExtInst(Cos): Float: tmp1044 << tmp1043 1045: OpFMul: Float: tmp1045 << const303, tmp1044 1046: OpFAdd: Float: tmp1046 << const303, tmp1045 1047: OpExtInst(SmoothStep): Float: tmp1047 << const671, const435, tmp1046 1048: OpCompositeConstruct: FloatVector3: tmp1048 << tmp1047, tmp1047, tmp1047 1049: OpExtInst(FMix): FloatVector3: tmp1049 << const1035, const1013, tmp1048 OpStore: : tmp1049 >> chocolour OpBranch: to lb997 997: lb997: 1050: OpLoad: FloatVector3: tmp1050 << chocolour 1051: OpVectorTimesScalar: FloatVector3: tmp1051 << tmp1050, const576 1053: OpLoad: FloatVector3: tmp1053 << l 1054: OpDot: Float: tmp1054 << tmp978, tmp1053 1055: OpFMul: Float: tmp1055 << const303, tmp1054 1056: OpFAdd: Float: tmp1056 << const303, tmp1055 1057: OpCompositeConstruct: FloatVector3: tmp1057 << tmp1056, tmp1056, tmp1056 1058: OpFMul: FloatVector3: tmp1058 << tmp1051, tmp1057 1062: OpDot: Float: tmp1062 << tmp985, tmp978 1063: OpFMul: Float: tmp1063 << const303, tmp1062 1064: OpFAdd: Float: tmp1064 << const303, tmp1063 1065: OpExtInst(FClamp): Float: tmp1065 << tmp1064, const100, const106 1066: OpExtInst(Pow): Float: tmp1066 << tmp1065, const863 1067: OpCompositeConstruct: FloatVector3: tmp1067 << tmp1066, tmp1066, tmp1066 1068: OpFMul: FloatVector3: tmp1068 << const1059, tmp1067 1069: OpFAdd: FloatVector3: tmp1069 << tmp1058, tmp1068 1071: OpLoad: FloatVector3: tmp1071 << rd 1072: OpFNegate: FloatVector3: tmp1072 << tmp1071 1073: OpDot: Float: tmp1073 << tmp978, tmp1072 1074: OpExtInst(Pow): Float: tmp1074 << tmp1073, const127 1075: OpFMul: Float: tmp1075 << const704, tmp1074 1076: OpFAdd: Float: tmp1076 << const106, tmp1075 1077: OpVectorTimesScalar: FloatVector3: tmp1077 << tmp1069, tmp1076 OpStore: : tmp1077 >> col OpBranch: to lb989 1078: lb1078: OpStore: : tmp978 >> param1079 OpStore: : tmp943 >> param1081 OpStore: : tmp980 >> param1083 1085: OpFunctionCall: FloatVector3: gummy(vf3;vf3;vf3;(param1079, param1081, param1083) 1086: OpVectorTimesScalar: FloatVector3: tmp1086 << gummy(vf3;vf3;vf3;, const401 1089: OpDot: Float: tmp1089 << tmp985, tmp978 1090: OpFMul: Float: tmp1090 << const303, tmp1089 1091: OpFAdd: Float: tmp1091 << const303, tmp1090 1092: OpExtInst(FClamp): Float: tmp1092 << tmp1091, const100, const106 1094: OpExtInst(Pow): Float: tmp1094 << tmp1092, const1093 1095: OpExtInst(SmoothStep): Float: tmp1095 << const303, const704, tmp1094 1096: OpCompositeConstruct: FloatVector3: tmp1096 << tmp1095, tmp1095, tmp1095 1097: OpVectorTimesScalar: FloatVector3: tmp1097 << tmp1096, const576 1098: OpFAdd: FloatVector3: tmp1098 << tmp1086, tmp1097 OpStore: : tmp1098 >> col OpBranch: to lb989 989: lb989: 1099: OpAccessChain: Float*: rp[1] 1100: OpCompositeExtract: Float: tmp1100 << tmp943, 1 1101: OpExtInst(FMax): Float: tmp1101 << const100, tmp1100 1102: OpExtInst(Pow): Float: tmp1102 << tmp1101, const303 1103: OpExtInst(FMix): Float: tmp1103 << const106, tmp1102, const704 1104: OpLoad: FloatVector3: tmp1104 << col 1105: OpVectorTimesScalar: FloatVector3: tmp1105 << tmp1104, tmp1103 OpStore: : tmp1105 >> col 1106: OpLoad: FloatVector3: tmp1106 << col OpReturnValue: : << tmp1106 96: OpFunction: Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) 1131: OpVariable: Float*: param1131: storage class: Function 1137: OpVariable: Float*: param1137: storage class: Function 1139: OpVariable: Float*: param1139: storage class: Function 1151: OpVariable: FloatVector3*: camu: storage class: Function 1188: OpVariable: FloatVector2*: p: storage class: Function 1204: OpVariable: Float*: param1204: storage class: Function 1206: OpVariable: Float*: param1206: storage class: Function 1221: OpVariable: Float*: t: storage class: Function 1238: OpVariable: FloatVector3*: col: storage class: Function 1239: OpVariable: FloatVector3*: param1239: storage class: Function 1241: OpVariable: FloatVector3*: param1241: storage class: Function 1243: OpVariable: Float*: param1243: storage class: Function 1245: OpVariable: Float*: param1245: storage class: Function 1267: OpVariable: FloatVector2*: c: storage class: Function 1289: OpVariable: FloatVector3*: cc: storage class: Function 1312: OpVariable: FloatVector2*: param1312: storage class: Function 1330: OpVariable: Float*: param1330: storage class: Function 1331: OpVariable: FloatVector2*: param1331: storage class: Function 1333: OpVariable: FloatVector2*: param1333: storage class: Function 1341: OpVariable: Float*: param1341: storage class: Function 1381: OpVariable: FloatVector3*: param1381: storage class: Function 1396: OpVariable: FloatVector3*: param1396: storage class: Function 97: lb97: 1111: OpLoad: Float: tmp1111 << iTime OpStore: : tmp1111 >> time 1112: OpLoad: FloatVector2: tmp1112 << fragCoord 1115: OpLoad: FloatVector3: tmp1115 << iResolution 1116: OpVectorShuffle: FloatVector2: tmp1116 << tmp1115, tmp1115, 0, 1 1117: OpFDiv: FloatVector2: tmp1117 << tmp1112, tmp1116 1118: OpVectorTimesScalar: FloatVector2: tmp1118 << tmp1117, const127 1119: OpFSub: FloatVector2: tmp1119 << tmp1118, const342 OpStore: : tmp1119 >> tc 1121: OpLoad: Float: tmp1121 << time 1122: OpLoad: Float: tmp1122 << t_per_target 1123: OpFDiv: Float: tmp1123 << tmp1121, tmp1122 1124: OpExtInst(Floor): Float: tmp1124 << tmp1123 1126: OpLoad: Float: tmp1126 << time 1127: OpLoad: Float: tmp1127 << t_per_target 1128: OpFDiv: Float: tmp1128 << tmp1126, tmp1127 1129: OpExtInst(Fract): Float: tmp1129 << tmp1128 1132: OpLoad: Float: tmp1132 << time OpStore: : tmp1132 >> param1131 1133: OpFunctionCall: FloatVector3: cameraPos(f1;(param1131) 1136: OpFSub: Float: tmp1136 << tmp1124, const106 OpStore: : tmp1136 >> param1137 1138: OpFunctionCall: FloatVector3: targetPos(f1;(param1137) OpStore: : tmp1124 >> param1139 1141: OpFunctionCall: FloatVector3: targetPos(f1;(param1139) 1143: OpExtInst(SmoothStep): Float: tmp1143 << const523, const671, tmp1129 1144: OpCompositeConstruct: FloatVector3: tmp1144 << tmp1143, tmp1143, tmp1143 1145: OpExtInst(FMix): FloatVector3: tmp1145 << targetPos(f1;, targetPos(f1;, tmp1144 1149: OpFSub: FloatVector3: tmp1149 << tmp1145, cameraPos(f1; 1150: OpExtInst(Normalize): FloatVector3: tmp1150 << tmp1149 1154: OpExtInst(Cross): FloatVector3: tmp1154 << tmp1150, const1153 1155: OpExtInst(Normalize): FloatVector3: tmp1155 << tmp1154 OpStore: : tmp1155 >> camu 1157: OpLoad: FloatVector3: tmp1157 << camu 1159: OpExtInst(Cross): FloatVector3: tmp1159 << tmp1157, tmp1150 1160: OpExtInst(Normalize): FloatVector3: tmp1160 << tmp1159 1163: OpExtInst(Cross): FloatVector3: tmp1163 << tmp1150, tmp1160 1164: OpExtInst(Normalize): FloatVector3: tmp1164 << tmp1163 OpStore: : tmp1164 >> camu 1168: OpLoad: FloatVector3: tmp1168 << camu 1171: OpCompositeExtract: Float: tmp1171 << tmp1168, 0 1172: OpCompositeExtract: Float: tmp1172 << tmp1168, 1 1173: OpCompositeExtract: Float: tmp1173 << tmp1168, 2 1174: OpCompositeExtract: Float: tmp1174 << tmp1160, 0 1175: OpCompositeExtract: Float: tmp1175 << tmp1160, 1 1176: OpCompositeExtract: Float: tmp1176 << tmp1160, 2 1177: OpCompositeExtract: Float: tmp1177 << tmp1150, 0 1178: OpCompositeExtract: Float: tmp1178 << tmp1150, 1 1179: OpCompositeExtract: Float: tmp1179 << tmp1150, 2 1180: OpCompositeConstruct: FloatVector3: tmp1180 << tmp1171, tmp1172, tmp1173 1181: OpCompositeConstruct: FloatVector3: tmp1181 << tmp1174, tmp1175, tmp1176 1182: OpCompositeConstruct: FloatVector3: tmp1182 << tmp1177, tmp1178, tmp1179 1183: OpCompositeConstruct: FloatMatrix3x3: tmp1183 << tmp1180, tmp1181, tmp1182 1185: OpLoad: FloatVector2: tmp1185 << tc 1186: OpVectorTimesScalar: FloatVector2: tmp1186 << tmp1185, const303 1187: OpFAdd: FloatVector2: tmp1187 << tmp1186, const391 1189: OpLoad: FloatVector2: tmp1189 << tc OpStore: : tmp1189 >> p 1192: OpAccessChain: Float*: iResolution[0] 1193: OpLoad: Float: tmp1193 << iResolution[0] 1194: OpAccessChain: Float*: iResolution[1] 1195: OpLoad: Float: tmp1195 << iResolution[1] 1196: OpFDiv: Float: tmp1196 << tmp1193, tmp1195 1197: OpAccessChain: Float*: p[0] 1198: OpLoad: Float: tmp1198 << p[0] 1199: OpFMul: Float: tmp1199 << tmp1198, tmp1196 1200: OpAccessChain: Float*: p[0] OpStore: : tmp1199 >> p[0] 1203: OpFSub: Float: tmp1203 << tmp1124, const106 OpStore: : tmp1203 >> param1204 1205: OpFunctionCall: Float: cameraZoom(f1;(param1204) OpStore: : tmp1124 >> param1206 1208: OpFunctionCall: Float: cameraZoom(f1;(param1206) 1210: OpExtInst(SmoothStep): Float: tmp1210 << const671, const435, tmp1129 1211: OpExtInst(FMix): Float: tmp1211 << cameraZoom(f1;, cameraZoom(f1;, tmp1210 1214: OpLoad: FloatVector2: tmp1214 << p 1216: OpCompositeExtract: Float: tmp1216 << tmp1214, 0 1217: OpCompositeExtract: Float: tmp1217 << tmp1214, 1 1218: OpCompositeConstruct: FloatVector3: tmp1218 << tmp1216, tmp1217, tmp1211 1219: OpExtInst(Normalize): FloatVector3: tmp1219 << tmp1218 1220: OpMatrixTimesVector: FloatVector3: tmp1220 << tmp1183, tmp1219 1222: OpAccessChain: Float*: ro[1] 1223: OpCompositeExtract: Float: tmp1223 << cameraPos(f1;, 1 1224: OpFSub: Float: tmp1224 << const106, tmp1223 1225: OpAccessChain: Float*: rd[1] 1226: OpCompositeExtract: Float: tmp1226 << tmp1220, 1 1227: OpFDiv: Float: tmp1227 << tmp1224, tmp1226 1228: OpExtInst(FMax): Float: tmp1228 << const100, tmp1227 OpStore: : tmp1228 >> t 1231: OpAccessChain: Float*: ro[1] 1232: OpCompositeExtract: Float: tmp1232 << cameraPos(f1;, 1 1233: OpFSub: Float: tmp1233 << const1230, tmp1232 1234: OpAccessChain: Float*: rd[1] 1235: OpCompositeExtract: Float: tmp1235 << tmp1220, 1 1236: OpFDiv: Float: tmp1236 << tmp1233, tmp1235 1237: OpExtInst(FMax): Float: tmp1237 << const100, tmp1236 OpStore: : cameraPos(f1; >> param1239 OpStore: : tmp1220 >> param1241 1244: OpLoad: Float: tmp1244 << t OpStore: : tmp1244 >> param1243 OpStore: : tmp1237 >> param1245 1247: OpFunctionCall: FloatVector3: trace(vf3;vf3;f1;f1;(param1239, param1241, param1243, param1245) 1248: OpLoad: Float: tmp1248 << param1243 OpStore: : tmp1248 >> t OpStore: : trace(vf3;vf3;f1;f1; >> col 1252: OpLoad: Float: tmp1252 << t 1253: OpVectorTimesScalar: FloatVector3: tmp1253 << tmp1220, tmp1252 1254: OpFAdd: FloatVector3: tmp1254 << cameraPos(f1;, tmp1253 1255: OpAccessChain: Float*: rp[1] 1256: OpCompositeExtract: Float: tmp1256 << tmp1254, 1 1257: OpFMul: Float: tmp1257 << tmp1256, const127 1258: OpExtInst(FClamp): Float: tmp1258 << tmp1257, const100, const106 OpStore: : tmp1258 >> icing_factor 1259: OpLoad: Float: tmp1259 << t 1260: OpFOrdGreaterThan: Bool: tmp1260 << tmp1259, const100 1262: OpLoad: Float: tmp1262 << t 1263: OpFOrdLessThan: Bool: tmp1263 << tmp1237, tmp1262 1264: OpLogicalAnd: Bool: tmp1264 << tmp1260, tmp1263 OpSelectionMerge: (merge: lb1266) OpBranchConditional: if(tmp1264) then branch to lb1265, else branch to lb1266 1265: lb1265: 1269: OpVectorShuffle: FloatVector2: tmp1269 << cameraPos(f1;, cameraPos(f1;, 0, 2 1271: OpVectorShuffle: FloatVector2: tmp1271 << tmp1220, tmp1220, 0, 2 1273: OpVectorTimesScalar: FloatVector2: tmp1273 << tmp1271, tmp1237 1274: OpFAdd: FloatVector2: tmp1274 << tmp1269, tmp1273 OpStore: : tmp1274 >> c 1276: OpLoad: FloatVector2: tmp1276 << c 1277: OpVectorTimesScalar: FloatVector2: tmp1277 << tmp1276, const151 1279: OpAccessChain: Float*: xc[0] 1280: OpCompositeExtract: Float: tmp1280 << tmp1277, 0 1281: OpAccessChain: Float*: xc[1] 1282: OpCompositeExtract: Float: tmp1282 << tmp1277, 1 1283: OpExtInst(Fract): Float: tmp1283 << tmp1282 1284: OpExtInst(Step): Float: tmp1284 << const303, tmp1283 1285: OpFMul: Float: tmp1285 << const303, tmp1284 1286: OpFAdd: Float: tmp1286 << tmp1280, tmp1285 1287: OpExtInst(Fract): Float: tmp1287 << tmp1286 1288: OpExtInst(Step): Float: tmp1288 << const303, tmp1287 1294: OpCompositeConstruct: FloatVector3: tmp1294 << tmp1288, tmp1288, tmp1288 1295: OpExtInst(FMix): FloatVector3: tmp1295 << const1290, const1292, tmp1294 OpStore: : tmp1295 >> cc 1296: OpLoad: FloatVector3: tmp1296 << cc 1299: OpVectorTimesScalar: FloatVector2: tmp1299 << tmp1277, const621 1300: OpAccessChain: Float*: xc[1] 1301: OpCompositeExtract: Float: tmp1301 << tmp1277, 1 1302: OpFMul: Float: tmp1302 << tmp1301, const127 1303: OpExtInst(Cos): Float: tmp1303 << tmp1302 1304: OpFMul: Float: tmp1304 << tmp1303, const109 1305: OpAccessChain: Float*: xc[0] 1306: OpCompositeExtract: Float: tmp1306 << tmp1277, 0 1307: OpFMul: Float: tmp1307 << tmp1306, const106 1308: OpExtInst(Cos): Float: tmp1308 << tmp1307 1309: OpFMul: Float: tmp1309 << tmp1308, const377 1310: OpCompositeConstruct: FloatVector2: tmp1310 << tmp1304, tmp1309 1311: OpFAdd: FloatVector2: tmp1311 << tmp1299, tmp1310 OpStore: : tmp1311 >> param1312 1313: OpFunctionCall: Float: smN2(vf2;(param1312) 1314: OpFMul: Float: tmp1314 << const303, smN2(vf2; 1315: OpFAdd: Float: tmp1315 << const523, tmp1314 1316: OpExtInst(Pow): Float: tmp1316 << tmp1315, const377 1317: OpCompositeConstruct: FloatVector3: tmp1317 << tmp1316, tmp1316, tmp1316 1318: OpExtInst(FMix): FloatVector3: tmp1318 << tmp1296, const1297, tmp1317 OpStore: : tmp1318 >> cc 1320: OpLoad: FloatVector3: tmp1320 << l 1322: OpFSub: FloatVector3: tmp1322 << tmp1320, tmp1220 1323: OpExtInst(Normalize): FloatVector3: tmp1323 << tmp1322 1326: OpExtInst(Reflect): FloatVector3: tmp1326 << tmp1220, const1153 1329: OpVectorTimesScalar: FloatVector2: tmp1329 << tmp1277, const303 OpStore: : const127 >> param1330 OpStore: : tmp1329 >> param1331 1332: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param1330, param1331) OpStore: : rotate(f1;vf2; >> param1333 1334: OpFunctionCall: FloatVector3: marble(vf2;(param1333) OpStore: : marble(vf2; >> cc 1335: OpLoad: FloatVector2: tmp1335 << c 1336: OpCompositeConstruct: FloatVector2: tmp1336 << const109, const109 1337: OpFDiv: FloatVector2: tmp1337 << tmp1335, tmp1336 1338: OpExtInst(Fract): FloatVector2: tmp1338 << tmp1337 OpStore: : tmp1338 >> c 1339: OpLoad: FloatVector3: tmp1339 << cc 1340: OpVectorTimesScalar: FloatVector3: tmp1340 << tmp1339, const151 1342: OpLoad: Float: tmp1342 << colour OpStore: : tmp1342 >> param1341 1343: OpFunctionCall: FloatVector3: gumColour(f1;(param1341) 1344: OpVectorTimesScalar: FloatVector3: tmp1344 << gumColour(f1;, const127 1345: OpLoad: Float: tmp1345 << is_choc 1346: OpVectorTimesScalar: FloatVector3: tmp1346 << tmp1344, tmp1345 1349: OpLoad: FloatVector2: tmp1349 << c 1350: OpExtInst(Distance): Float: tmp1350 << const391, tmp1349 1351: OpLoad: Float: tmp1351 << ss 1352: OpFDiv: Float: tmp1352 << tmp1350, tmp1351 1353: OpExtInst(SmoothStep): Float: tmp1353 << const1347, const1348, tmp1352 1354: OpCompositeConstruct: FloatVector3: tmp1354 << tmp1353, tmp1353, tmp1353 1355: OpExtInst(FMix): FloatVector3: tmp1355 << tmp1346, const1290, tmp1354 1356: OpFMul: FloatVector3: tmp1356 << tmp1340, tmp1355 OpStore: : tmp1356 >> col OpStore: : const106 >> icing_factor OpBranch: to lb1266 1266: lb1266: 1360: OpAccessChain: Float*: iMouse[0] 1361: OpLoad: Float: tmp1361 << iMouse[0] 1362: OpAccessChain: Float*: iResolution[0] 1363: OpLoad: Float: tmp1363 << iResolution[0] 1364: OpFDiv: Float: tmp1364 << tmp1361, tmp1363 1365: OpLoad: Float: tmp1365 << icing_factor 1366: OpFMul: Float: tmp1366 << tmp1364, tmp1365 1367: OpFSub: Float: tmp1367 << const106, tmp1366 1368: OpLoad: FloatVector3: tmp1368 << col 1371: OpFMul: Float: tmp1371 << const1369, tmp1367 1373: OpFAdd: Float: tmp1373 << tmp1371, const1372 1375: OpVectorShuffle: FloatVector2: tmp1375 << tmp1254, tmp1254, 0, 2 1377: OpVectorTimesScalar: FloatVector2: tmp1377 << tmp1375, const1376 1378: OpCompositeExtract: Float: tmp1378 << tmp1377, 0 1379: OpCompositeExtract: Float: tmp1379 << tmp1377, 1 1380: OpCompositeConstruct: FloatVector3: tmp1380 << tmp1378, tmp1379, const100 OpStore: : tmp1380 >> param1381 1382: OpFunctionCall: Float: fbm3(vf3;(param1381) 1383: OpFAdd: Float: tmp1383 << tmp1373, fbm3(vf3; 1384: OpExtInst(SmoothStep): Float: tmp1384 << const303, const671, tmp1383 1385: OpFMul: Float: tmp1385 << const435, tmp1384 1387: OpFMul: Float: tmp1387 << const1369, tmp1367 1388: OpFAdd: Float: tmp1388 << tmp1387, const523 1390: OpVectorShuffle: FloatVector2: tmp1390 << tmp1254, tmp1254, 0, 2 1392: OpVectorTimesScalar: FloatVector2: tmp1392 << tmp1390, const1391 1393: OpCompositeExtract: Float: tmp1393 << tmp1392, 0 1394: OpCompositeExtract: Float: tmp1394 << tmp1392, 1 1395: OpCompositeConstruct: FloatVector3: tmp1395 << tmp1393, tmp1394, const100 OpStore: : tmp1395 >> param1396 1397: OpFunctionCall: Float: fbm3(vf3;(param1396) 1398: OpFAdd: Float: tmp1398 << tmp1388, fbm3(vf3; 1399: OpExtInst(SmoothStep): Float: tmp1399 << const303, const671, tmp1398 1400: OpFMul: Float: tmp1400 << const435, tmp1399 1401: OpFAdd: Float: tmp1401 << tmp1385, tmp1400 1402: OpCompositeConstruct: FloatVector3: tmp1402 << tmp1401, tmp1401, tmp1401 1403: OpExtInst(FMix): FloatVector3: tmp1403 << tmp1368, const1290, tmp1402 OpStore: : tmp1403 >> col 1404: OpLoad: FloatVector3: tmp1404 << col 1405: OpVectorTimesScalar: FloatVector3: tmp1405 << tmp1404, const895 1406: OpExtInst(Sqrt): FloatVector3: tmp1406 << tmp1405 1407: OpLoad: FloatVector4: tmp1407 << fragColor 1408: OpVectorShuffle: FloatVector4: tmp1408 << tmp1407, tmp1406, 4, 5, 6, 3 OpStore: : tmp1408 >> fragColor 1410: OpAccessChain: Float*: q[0] 1411: OpCompositeExtract: Float: tmp1411 << tmp1187, 0 1412: OpFMul: Float: tmp1412 << const1409, tmp1411 1413: OpAccessChain: Float*: q[1] 1414: OpCompositeExtract: Float: tmp1414 << tmp1187, 1 1415: OpFMul: Float: tmp1415 << tmp1412, tmp1414 1416: OpAccessChain: Float*: q[0] 1417: OpCompositeExtract: Float: tmp1417 << tmp1187, 0 1418: OpFSub: Float: tmp1418 << const106, tmp1417 1419: OpFMul: Float: tmp1419 << tmp1415, tmp1418 1420: OpAccessChain: Float*: q[1] 1421: OpCompositeExtract: Float: tmp1421 << tmp1187, 1 1422: OpFSub: Float: tmp1422 << const106, tmp1421 1423: OpFMul: Float: tmp1423 << tmp1419, tmp1422 1424: OpExtInst(Pow): Float: tmp1424 << tmp1423, const576 1425: OpLoad: FloatVector4: tmp1425 << fragColor 1426: OpVectorShuffle: FloatVector3: tmp1426 << tmp1425, tmp1425, 0, 1, 2 1427: OpVectorTimesScalar: FloatVector3: tmp1427 << tmp1426, tmp1424 1428: OpLoad: FloatVector4: tmp1428 << fragColor 1429: OpVectorShuffle: FloatVector4: tmp1429 << tmp1428, tmp1427, 4, 5, 6, 3 OpStore: : tmp1429 >> fragColor OpReturn: Generating the compiled code... Intermediate disassembly (pre optimization): Program Type: Fragment Special Input Variables: offset: unset, size: 16, FloatVector4 gl_FragCoord BuiltIn(FragCoord) Textures: offset: 0, size: 4, Float iChannel0 offset: 1, size: 4, Float iChannel1 offset: 2, size: 4, Float iChannel2 offset: 3, size: 4, Float iChannel3 Output Variables: offset: 0, size: 16, FloatVector4 finalColor Uniform Constants: offset: 0, size: 4, Float iTime offset: 4, size: 12, FloatVector3 iResolution offset: 16, size: 16, FloatVector4 iMouse offset: 32, size: 16, FloatVector4 iDate offset: 48, size: 4, Float iFrame offset: 52, size: 48, FloatVector3 iChannelResolution[4] Private Global Variables: offset: unset, size: 8, FloatVector2 tc offset: unset, size: 4, Float time offset: unset, size: 4, Float colour offset: unset, size: 4, Float ss offset: unset, size: 4, Float is_choc offset: unset, size: 4, Float t_per_target offset: unset, size: 12, FloatVector3 l offset: unset, size: 4, Float icing_factor offset: unset, size: 48, FloatVector3 gum_colours[4] offset: unset, size: 48, FloatVector3 gum_ramps[4] Constants: Float const100: 0 FloatVector2 const101: {0, 0} Float const106: 1 Float const109: 3 Float const112: 0.316228 Float const113: 0.948683 FloatVector3 const114: {0.316228, 0.948683, 0} Float const121: 0.11 Float const122: 0.002 FloatVector3 const123: {0.11, 0, 0.002} Float const127: 2 Float const131: 0.06 FloatVector3 const132: {0.002, 0.06, 0} Float const139: 0.02 FloatVector3 const140: {0, 0.02, 0.11} Float const143: 0.012 FloatVector3 const144: {0.11, 0.012, 0} Float const151: 0.8 FloatVector3 const152: {0.8, 1, 1} FloatVector3 const159: {0.8, 0.8, 1} FloatVector3 const166: {1, 0.8, 1} Float const173: 43758.5 UInt32 const194: 0 UInt32 const197: 1 Float const200: 157 Float const203: 113 UInt32 const204: 2 Float const225: 158 Float const240: 114 Float const248: 270 Float const253: 271 Int32 const285: 1 Int32 const292: 9 Float const303: 0.5 Float const340: -1 FloatVector2 const341: {-1, -1} FloatVector2 const342: {1, 1} Float const349: 8 Float const361: 0.95 Float const377: 4 FloatVector2 const391: {0.5, 0.5} Float const401: 5 Float const407: 53 Float const412: 125 Float const416: 2.5 Float const423: 100 FloatVector2 const424: {100, 100} Float const435: 0.9 Float const437: 25 Int32 const471: 0 Int32 const478: 4 Float const483: 10.45 Float const489: 0.2 Float const511: 0.75 Float const523: 0.3 FloatVector3 const569: {0.5, 0.5, 0.5} Float const573: 0.98 Float const576: 0.1 FloatVector3 const585: {2, 2, 2} Float const593: 1.05 Float const602: 0.01 Float const609: 1.3 Float const621: 10 Float const625: 103 Float const633: 30 Float const637: 0.001 Float const647: 0.05 FloatVector2 const664: {3, 3} Float const666: 1.5 FloatVector2 const667: {1.5, 1.5} Float const671: 0.7 Float const674: 7 Float const678: 9 Float const704: 0.6 Float const714: 0.015 FloatVector2 const730: {1, -1} FloatVector3 const735: {0.1, 0.1, 0.05} Float const748: 0.4 Float const749: 0.24 FloatVector3 const750: {0.4, 0.4, 0.24} Float const751: 0.56 FloatVector3 const752: {0.7, 0.7, 0.56} Float const844: 6 Float const848: 0.03 FloatVector3 const860: {1, 0, 0} Float const863: 20 Float const867: -7 Float const869: 14 Float const888: 3.5 Float const895: 1.4 Int32 const906: 100 FloatVector3 const921: {0, 0, 0} Float const925: 0.0001 Float const945: 0.005 FloatVector3 const946: {0.02, 0.01, 0.005} Float const1012: 2.6 FloatVector3 const1013: {4, 4, 2.6} Float const1014: 0.78 Float const1015: 0.36 Float const1016: 0.12 FloatVector3 const1017: {0.78, 0.36, 0.12} FloatVector3 const1035: {1.3, 0.6, 0.2} FloatVector3 const1059: {0.06, 0.06, 0.03} Float const1093: 256 FloatVector3 const1153: {0, 1, 0} Float const1230: -0.01 FloatVector3 const1290: {1, 1, 1} Float const1291: 0.25 FloatVector3 const1292: {0.5, 0.5, 0.25} FloatVector3 const1297: {0.9, 0.9, 0.5} Float const1347: 0.33 Float const1348: 0.53 Float const1369: -0.25 Float const1372: 0.35 Float const1376: 4.2 Float const1391: 10.1 Float const1409: 16 UInt32 const1444: 4 Function Local Variables: offset: unset, size: 16, FloatVector4 main.param1433 offset: unset, size: 8, FloatVector2 main.param1434 offset: unset, size: 16, FloatVector4 main.fragColor offset: unset, size: 8, FloatVector2 main.fragCoord offset: unset, size: 4, Float main.i offset: unset, size: 4, Float gumColour(f1;.i offset: unset, size: 4, Float gumRamp(f1;.n offset: unset, size: 12, FloatVector3 hash(f1;.x offset: unset, size: 12, FloatVector3 noise(vf3;.f offset: unset, size: 4, Float noise(vf3;.param211 offset: unset, size: 4, Float noise(vf3;.param215 offset: unset, size: 4, Float noise(vf3;.param222 offset: unset, size: 4, Float noise(vf3;.param227 offset: unset, size: 4, Float noise(vf3;.param237 offset: unset, size: 4, Float noise(vf3;.param242 offset: unset, size: 4, Float noise(vf3;.param250 offset: unset, size: 4, Float noise(vf3;.param255 offset: unset, size: 8, FloatVector2 noise(vf3;.p offset: unset, size: 12, FloatVector3 smN2(vf2;.param272 offset: unset, size: 12, FloatVector3 smN2(vf2;.p offset: unset, size: 12, FloatVector3 smN3(vf3;.param276 offset: unset, size: 12, FloatVector3 smN3(vf3;.p offset: unset, size: 4, Float fbm3(vf3;.f offset: unset, size: 4, Int32 fbm3(vf3;.i offset: unset, size: 12, FloatVector3 fbm3(vf3;.param301 offset: unset, size: 4, Float fbm3(vf3;.a offset: unset, size: 8, FloatVector2 fbm3(vf3;.v offset: unset, size: 8, FloatVector2 rotate(f1;vf2;.p offset: unset, size: 8, FloatVector2 sugarybit(vf2;.t offset: unset, size: 4, Float sugarybit(vf2;.ndotv offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param419 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param426 offset: unset, size: 4, Float sugarlayer(vf2;f1;.param445 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param447 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param449 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param453 offset: unset, size: 12, FloatVector3 sugarlayer(vf2;f1;.c offset: unset, size: 4, Float saturatecol(vf3;.param463 offset: unset, size: 8, FloatVector2 saturatecol(vf3;.coord offset: unset, size: 4, Float saturatecol(vf3;.ndotv offset: unset, size: 4, Float sprinkles2(vf2;f1;.sprinkle offset: unset, size: 4, Int32 sprinkles2(vf2;f1;.i offset: unset, size: 8, FloatVector2 sprinkles2(vf2;f1;.param493 offset: unset, size: 4, Float sprinkles2(vf2;f1;.param494 offset: unset, size: 8, FloatVector2 sprinkles2(vf2;f1;.coord offset: unset, size: 4, Float sprinkles2(vf2;f1;.ndotv offset: unset, size: 8, FloatVector2 sprinkles(vf2;f1;.param513 offset: unset, size: 4, Float sprinkles(vf2;f1;.param514 offset: unset, size: 8, FloatVector2 sprinkles(vf2;f1;.param519 offset: unset, size: 4, Float sprinkles(vf2;f1;.param520 offset: unset, size: 12, FloatVector3 sprinkles(vf2;f1;.no offset: unset, size: 12, FloatVector3 sprinkles(vf2;f1;.vo offset: unset, size: 12, FloatVector3 sprinkles(vf2;f1;.v offset: unset, size: 8, FloatVector2 gummy(vf3;vf3;vf3;.param544 offset: unset, size: 4, Float gummy(vf3;vf3;vf3;.param545 offset: unset, size: 8, FloatVector2 gummy(vf3;vf3;vf3;.param549 offset: unset, size: 4, Float gummy(vf3;vf3;vf3;.param552 offset: unset, size: 12, FloatVector3 gummy(vf3;vf3;vf3;.tex offset: unset, size: 4, Float gummy(vf3;vf3;vf3;.param570 offset: unset, size: 12, FloatVector3 gummy(vf3;vf3;vf3;.param591 offset: unset, size: 12, FloatVector3 gummy(vf3;vf3;vf3;.p offset: unset, size: 12, FloatVector3 de(vf3;.param635 offset: unset, size: 12, FloatVector3 de(vf3;.param643 offset: unset, size: 8, FloatVector2 de(vf3;.p offset: unset, size: 12, FloatVector3 marble(vf2;.param740 offset: unset, size: 12, FloatVector3 marble(vf2;.param767 offset: unset, size: 12, FloatVector3 marble(vf2;.param779 offset: unset, size: 12, FloatVector3 marble(vf2;.param790 offset: unset, size: 4, Float marble(vf2;.t offset: unset, size: 4, Float cameraPos(f1;.ti offset: unset, size: 12, FloatVector3 targetPos(f1;.target offset: unset, size: 4, Float targetPos(f1;.param858 offset: unset, size: 4, Float targetPos(f1;.ti offset: unset, size: 12, FloatVector3 cameraZoom(f1;.ro offset: unset, size: 12, FloatVector3 cameraZoom(f1;.rd offset: unset, size: 4, Float cameraZoom(f1;.t offset: unset, size: 4, Float cameraZoom(f1;.max_t offset: unset, size: 4, Int32 trace(vf3;vf3;f1;f1;.i offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param914 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.col offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param949 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param957 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param965 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param973 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.chocolour offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1028 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1079 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1081 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1083 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1131 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1137 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1139 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.camu offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.p offset: unset, size: 4, Float mainImage(vf4;vf2;.param1204 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1206 offset: unset, size: 4, Float mainImage(vf4;vf2;.t offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.col offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1239 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1241 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1243 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1245 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.c offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.cc offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param1312 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1330 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param1331 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param1333 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1341 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1381 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1396 Instructions: V_SUB_F32 vDst(VGPR14) src0(SGPR2) src1(VGPR14) // VOP2 # Void main() Function: Void main() # lb5 Label: lb5 # OpStore: : const101 >> tc V_MOV_B32 vDst(VGPR26) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR27) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR24) src0(VGPR26) V_MOV_B32 vDst(VGPR25) src0(VGPR27) # OpStore: : const100 >> time V_MOV_B32 vDst(VGPR29) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR28) src0(VGPR29) # OpStore: : const100 >> colour V_MOV_B32 vDst(VGPR31) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR30) src0(VGPR31) # OpStore: : const106 >> ss V_MOV_B32 vDst(VGPR32) src0(1_0_F) # OpStore: : const100 >> is_choc V_MOV_B32 vDst(VGPR34) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR33) src0(VGPR34) # OpStore: : const109 >> t_per_target V_MOV_B32 vDst(VGPR36) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR35) src0(VGPR36) # OpStore: : const114 >> l V_MOV_B32 vDst(VGPR40) src0(LITERAL_CONST) const: 0x3ea1e89b V_MOV_B32 vDst(VGPR41) src0(LITERAL_CONST) const: 0x3f72dce9 V_MOV_B32 vDst(VGPR42) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR37) src0(VGPR40) V_MOV_B32 vDst(VGPR38) src0(VGPR41) V_MOV_B32 vDst(VGPR39) src0(VGPR42) # OpStore: : const100 >> icing_factor V_MOV_B32 vDst(VGPR44) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR43) src0(VGPR44) # 1435: OpLoad: FloatVector4: tmp1435 << gl_FragCoord V_MOV_B32 vDst(VGPR45) src0(VGPR13) V_MOV_B32 vDst(VGPR46) src0(VGPR14) V_MOV_B32 vDst(VGPR47) src0(VGPR15) V_MOV_B32 vDst(VGPR48) src0(VGPR16) # 1436: OpVectorShuffle: FloatVector2: tmp1436 << tmp1435, tmp1435, 0, 1 V_MOV_B32 vDst(VGPR49) src0(VGPR45) V_MOV_B32 vDst(VGPR50) src0(VGPR46) # OpStore: : tmp1436 >> param1434 V_MOV_B32 vDst(VGPR22) src0(VGPR49) V_MOV_B32 vDst(VGPR23) src0(VGPR50) # 1437: OpFunctionCall: Void: mainImage(vf4;vf2;(param1433, param1434) S_ADD_U32 sDst(SGPR12) src0(LITERAL_CONST) src1(0) const: 0x12 # VGPR[18:21] S_ADD_U32 sDst(SGPR13) src0(LITERAL_CONST) src1(0) const: 0x16 # VGPR[22:23] S_MOV_B64 sDst(SGPR14) src0(EXEC) # Indirect branch to mainImage(vf4;vf2;: ??? S_GETPC_B64 sDst(SGPR10) src0(SGPR10) S_ADD_U32 sDst(SGPR10) src0(SGPR10) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR11) src0(SGPR11) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR10) src0(SGPR10) S_MOV_B64 sDst(EXEC) src0(SGPR14) # .lbl0 # 1438: OpLoad: FloatVector4: tmp1438 << param1433 # OpStore: : tmp1438 >> finalColor V_MOV_B32 vDst(VGPR51) src0(VGPR18) V_MOV_B32 vDst(VGPR52) src0(VGPR19) V_MOV_B32 vDst(VGPR53) src0(VGPR20) V_MOV_B32 vDst(VGPR54) src0(VGPR21) # OpReturn: S_ENDPGM 0 # FloatVector3 gumColour(f1;(Float* i) Function: FloatVector3 gumColour(f1;() S_MOV_B64 sDst(SGPR20) src0(EXEC) # lb12 Label: lb12 # 116: OpLoad: Float: tmp116 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR55) src0(VGPR0) # 118: OpFOrdLessThan: Bool: tmp118 << tmp116, const106 V_MOV_B32 vDst(VGPR56) src0(1_0_F) V_CMP_LT_F32 dst(SGPR22) src0(VGPR55) src1(VGPR56) // VOP3a # OpSelectionMerge: (merge: lb120) # CF Block: Merge: lb120 S_MOV_B64 sDst(SGPR24) src0(EXEC) # OpBranchConditional: if(tmp118) then branch to lb119, else branch to lb125 # CF Block: Cond Branch: true: lb119, false: lb125 S_AND_B64 sDst(EXEC) src0(SGPR22) src1(EXEC) S_CBRANCH_EXECZ ??? lb125 S_BRANCH ??? lb119 # lb119 Label: lb119 # OpReturnValue: : << const123 V_MOV_B32 vDst(VGPR57) src0(LITERAL_CONST) const: 0x3de147ae V_MOV_B32 vDst(VGPR58) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR59) src0(LITERAL_CONST) const: 0x3b03126f S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR57) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR58) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR59) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # lb125 Label: lb125 # 126: OpLoad: Float: tmp126 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR60) src0(VGPR0) # 128: OpFOrdLessThan: Bool: tmp128 << tmp126, const127 V_MOV_B32 vDst(VGPR61) src0(2_0_F) V_CMP_LT_F32 dst(SGPR26) src0(VGPR60) src1(VGPR61) // VOP3a # OpSelectionMerge: (merge: lb130) # CF Block: Merge: lb130 S_MOV_B64 sDst(SGPR28) src0(EXEC) # OpBranchConditional: if(tmp128) then branch to lb129, else branch to lb134 # CF Block: Cond Branch: true: lb129, false: lb134 S_AND_B64 sDst(EXEC) src0(SGPR26) src1(EXEC) S_CBRANCH_EXECZ ??? lb134 S_BRANCH ??? lb129 # lb129 Label: lb129 # OpReturnValue: : << const132 V_MOV_B32 vDst(VGPR62) src0(LITERAL_CONST) const: 0x3b03126f V_MOV_B32 vDst(VGPR63) src0(LITERAL_CONST) const: 0x3d75c28f V_MOV_B32 vDst(VGPR64) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR62) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR63) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR64) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # lb134 Label: lb134 # 135: OpLoad: Float: tmp135 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR65) src0(VGPR0) # 136: OpFOrdLessThan: Bool: tmp136 << tmp135, const109 V_MOV_B32 vDst(VGPR66) src0(LITERAL_CONST) const: 0x40400000 V_CMP_LT_F32 dst(SGPR30) src0(VGPR65) src1(VGPR66) // VOP3a # OpSelectionMerge: (merge: lb138) # CF Block: Merge: lb138 S_MOV_B64 sDst(SGPR32) src0(EXEC) # OpBranchConditional: if(tmp136) then branch to lb137, else branch to lb142 # CF Block: Cond Branch: true: lb137, false: lb142 S_AND_B64 sDst(EXEC) src0(SGPR30) src1(EXEC) S_CBRANCH_EXECZ ??? lb142 S_BRANCH ??? lb137 # lb137 Label: lb137 # OpReturnValue: : << const140 V_MOV_B32 vDst(VGPR67) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR68) src0(LITERAL_CONST) const: 0x3ca3d70a V_MOV_B32 vDst(VGPR69) src0(LITERAL_CONST) const: 0x3de147ae S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR67) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR68) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR69) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # lb142 Label: lb142 # OpReturnValue: : << const144 V_MOV_B32 vDst(VGPR70) src0(LITERAL_CONST) const: 0x3de147ae V_MOV_B32 vDst(VGPR71) src0(LITERAL_CONST) const: 0x3c449ba6 V_MOV_B32 vDst(VGPR72) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR70) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR71) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR72) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # lb138 Label: lb138 # OpBranch: to lb130 S_BRANCH ??? lb130 # lb130 Label: lb130 # OpBranch: to lb120 S_BRANCH ??? lb120 # lb120 Label: lb120 # 146: OpUndef: FloatVector3: tmp146 << # OpReturnValue: : << tmp146 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR34) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR35) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR36) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # FloatVector3 gumRamp(f1;(Float* i) Function: FloatVector3 gumRamp(f1;() S_MOV_B64 sDst(SGPR42) src0(EXEC) # lb15 Label: lb15 # 147: OpLoad: Float: tmp147 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR41) const: 0x0 V_MOVRELS_B32 vDst(VGPR73) src0(VGPR0) # 148: OpFOrdLessThan: Bool: tmp148 << tmp147, const106 V_MOV_B32 vDst(VGPR74) src0(1_0_F) V_CMP_LT_F32 dst(SGPR44) src0(VGPR73) src1(VGPR74) // VOP3a # OpSelectionMerge: (merge: lb150) # CF Block: Merge: lb150 S_MOV_B64 sDst(SGPR46) src0(EXEC) # OpBranchConditional: if(tmp148) then branch to lb149, else branch to lb154 # CF Block: Cond Branch: true: lb149, false: lb154 S_AND_B64 sDst(EXEC) src0(SGPR44) src1(EXEC) S_CBRANCH_EXECZ ??? lb154 S_BRANCH ??? lb149 # lb149 Label: lb149 # OpReturnValue: : << const152 V_MOV_B32 vDst(VGPR75) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR76) src0(1_0_F) V_MOV_B32 vDst(VGPR77) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR75) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR76) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR77) S_SETPC_B64 sDst(SGPR38) src0(SGPR38) # lb154 Label: lb154 # 155: OpLoad: Float: tmp155 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR41) const: 0x0 V_MOVRELS_B32 vDst(VGPR78) src0(VGPR0) # 156: OpFOrdLessThan: Bool: tmp156 << tmp155, const127 V_MOV_B32 vDst(VGPR79) src0(2_0_F) V_CMP_LT_F32 dst(SGPR48) src0(VGPR78) src1(VGPR79) // VOP3a # OpSelectionMerge: (merge: lb158) # CF Block: Merge: lb158 S_MOV_B64 sDst(SGPR50) src0(EXEC) # OpBranchConditional: if(tmp156) then branch to lb157, else branch to lb161 # CF Block: Cond Branch: true: lb157, false: lb161 S_AND_B64 sDst(EXEC) src0(SGPR48) src1(EXEC) S_CBRANCH_EXECZ ??? lb161 S_BRANCH ??? lb157 # lb157 Label: lb157 # OpReturnValue: : << const159 V_MOV_B32 vDst(VGPR80) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR81) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR82) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR80) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR81) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR82) S_SETPC_B64 sDst(SGPR38) src0(SGPR38) # lb161 Label: lb161 # 162: OpLoad: Float: tmp162 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR41) const: 0x0 V_MOVRELS_B32 vDst(VGPR83) src0(VGPR0) # 163: OpFOrdLessThan: Bool: tmp163 << tmp162, const109 V_MOV_B32 vDst(VGPR84) src0(LITERAL_CONST) const: 0x40400000 V_CMP_LT_F32 dst(SGPR52) src0(VGPR83) src1(VGPR84) // VOP3a # OpSelectionMerge: (merge: lb165) # CF Block: Merge: lb165 S_MOV_B64 sDst(SGPR54) src0(EXEC) # OpBranchConditional: if(tmp163) then branch to lb164, else branch to lb168 # CF Block: Cond Branch: true: lb164, false: lb168 S_AND_B64 sDst(EXEC) src0(SGPR52) src1(EXEC) S_CBRANCH_EXECZ ??? lb168 S_BRANCH ??? lb164 # lb164 Label: lb164 # OpReturnValue: : << const166 V_MOV_B32 vDst(VGPR85) src0(1_0_F) V_MOV_B32 vDst(VGPR86) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR87) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR85) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR86) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR87) S_SETPC_B64 sDst(SGPR38) src0(SGPR38) # lb168 Label: lb168 # OpReturnValue: : << const159 V_MOV_B32 vDst(VGPR88) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR89) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR90) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR88) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR89) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR90) S_SETPC_B64 sDst(SGPR38) src0(SGPR38) # lb165 Label: lb165 # OpBranch: to lb158 S_BRANCH ??? lb158 # lb158 Label: lb158 # OpBranch: to lb150 S_BRANCH ??? lb150 # lb150 Label: lb150 # 170: OpUndef: FloatVector3: tmp170 << # OpReturnValue: : << tmp170 S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR56) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR57) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR58) S_SETPC_B64 sDst(SGPR38) src0(SGPR38) # Float hash(f1;(Float* n) Function: Float hash(f1;() S_MOV_B64 sDst(SGPR64) src0(EXEC) # lb19 Label: lb19 # 171: OpLoad: Float: tmp171 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR63) const: 0x0 V_MOVRELS_B32 vDst(VGPR91) src0(VGPR0) # 172: OpExtInst(Sin): Float: tmp172 << tmp171 V_MUL_F32 vDst(VGPR92) src0(LITERAL_CONST) src1(VGPR91) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR92) src0(VGPR92) V_SIN_F32 vDst(VGPR92) src0(VGPR92) # 174: OpFMul: Float: tmp174 << tmp172, const173 V_MOV_B32 vDst(VGPR93) src0(LITERAL_CONST) const: 0x472aee8c V_MUL_F32 vDst(VGPR94) src0(VGPR92) src1(VGPR93) // VOP2 # 175: OpExtInst(Fract): Float: tmp175 << tmp174 V_FRACT_F32 vDst(VGPR95) src0(VGPR94) # OpReturnValue: : << tmp175 S_MOV_B32 sDst(M0) src0(SGPR62) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR95) S_SETPC_B64 sDst(SGPR60) src0(SGPR60) # Float noise(vf3;(FloatVector3* x) Function: Float noise(vf3;() S_MOV_B64 sDst(SGPR70) src0(EXEC) # lb24 Label: lb24 # 179: OpLoad: FloatVector3: tmp179 << x S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR69) const: 0x0 V_MOVRELS_B32 vDst(VGPR107) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR108) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR109) src0(VGPR2) # 180: OpExtInst(Floor): FloatVector3: tmp180 << tmp179 V_FLOOR_F32 vDst(VGPR110) src0(VGPR107) V_FLOOR_F32 vDst(VGPR111) src0(VGPR108) V_FLOOR_F32 vDst(VGPR112) src0(VGPR109) # 182: OpLoad: FloatVector3: tmp182 << x S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR69) const: 0x0 V_MOVRELS_B32 vDst(VGPR113) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR114) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR115) src0(VGPR2) # 183: OpExtInst(Fract): FloatVector3: tmp183 << tmp182 V_FRACT_F32 vDst(VGPR116) src0(VGPR113) V_FRACT_F32 vDst(VGPR117) src0(VGPR114) V_FRACT_F32 vDst(VGPR118) src0(VGPR115) # OpStore: : tmp183 >> f V_MOV_B32 vDst(VGPR96) src0(VGPR116) V_MOV_B32 vDst(VGPR97) src0(VGPR117) V_MOV_B32 vDst(VGPR98) src0(VGPR118) # 184: OpLoad: FloatVector3: tmp184 << f # 185: OpLoad: FloatVector3: tmp185 << f # 186: OpFMul: FloatVector3: tmp186 << tmp184, tmp185 V_MUL_F32 vDst(VGPR119) src0(VGPR96) src1(VGPR96) // VOP2 V_MUL_F32 vDst(VGPR120) src0(VGPR97) src1(VGPR97) // VOP2 V_MUL_F32 vDst(VGPR121) src0(VGPR98) src1(VGPR98) // VOP2 # 187: OpLoad: FloatVector3: tmp187 << f # 188: OpVectorTimesScalar: FloatVector3: tmp188 << tmp187, const127 V_MOV_B32 vDst(VGPR125) src0(2_0_F) V_MUL_F32 vDst(VGPR122) src0(VGPR125) src1(VGPR96) // VOP2 V_MUL_F32 vDst(VGPR123) src0(VGPR125) src1(VGPR97) // VOP2 V_MUL_F32 vDst(VGPR124) src0(VGPR125) src1(VGPR98) // VOP2 # 189: OpCompositeConstruct: FloatVector3: tmp189 << const109, const109, const109 V_MOV_B32 vDst(VGPR129) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR126) src0(VGPR129) V_MOV_B32 vDst(VGPR130) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR127) src0(VGPR130) V_MOV_B32 vDst(VGPR131) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR128) src0(VGPR131) # 190: OpFSub: FloatVector3: tmp190 << tmp189, tmp188 V_SUB_F32 vDst(VGPR132) src0(VGPR126) src1(VGPR122) // VOP2 V_SUB_F32 vDst(VGPR133) src0(VGPR127) src1(VGPR123) // VOP2 V_SUB_F32 vDst(VGPR134) src0(VGPR128) src1(VGPR124) // VOP2 # 191: OpFMul: FloatVector3: tmp191 << tmp186, tmp190 V_MUL_F32 vDst(VGPR135) src0(VGPR119) src1(VGPR132) // VOP2 V_MUL_F32 vDst(VGPR136) src0(VGPR120) src1(VGPR133) // VOP2 V_MUL_F32 vDst(VGPR137) src0(VGPR121) src1(VGPR134) // VOP2 # OpStore: : tmp191 >> f V_MOV_B32 vDst(VGPR96) src0(VGPR135) V_MOV_B32 vDst(VGPR97) src0(VGPR136) V_MOV_B32 vDst(VGPR98) src0(VGPR137) # 195: OpAccessChain: Float*: p[0] # 196: OpCompositeExtract: Float: tmp196 << tmp180, 0 V_MOV_B32 vDst(VGPR138) src0(VGPR110) # 198: OpAccessChain: Float*: p[1] # 199: OpCompositeExtract: Float: tmp199 << tmp180, 1 V_MOV_B32 vDst(VGPR139) src0(VGPR111) # 201: OpFMul: Float: tmp201 << tmp199, const200 V_MOV_B32 vDst(VGPR140) src0(LITERAL_CONST) const: 0x431d0000 V_MUL_F32 vDst(VGPR141) src0(VGPR139) src1(VGPR140) // VOP2 # 202: OpFAdd: Float: tmp202 << tmp196, tmp201 V_ADD_F32 vDst(VGPR142) src0(VGPR138) src1(VGPR141) // VOP2 # 205: OpAccessChain: Float*: p[2] # 206: OpCompositeExtract: Float: tmp206 << tmp180, 2 V_MOV_B32 vDst(VGPR143) src0(VGPR112) # 207: OpFMul: Float: tmp207 << const203, tmp206 V_MOV_B32 vDst(VGPR144) src0(LITERAL_CONST) const: 0x42e20000 V_MUL_F32 vDst(VGPR145) src0(VGPR144) src1(VGPR143) // VOP2 # 208: OpFAdd: Float: tmp208 << tmp202, tmp207 V_ADD_F32 vDst(VGPR146) src0(VGPR142) src1(VGPR145) // VOP2 # 210: OpFAdd: Float: tmp210 << tmp208, const100 V_MOV_B32 vDst(VGPR147) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR148) src0(VGPR146) src1(VGPR147) // VOP2 # OpStore: : tmp210 >> param211 V_MOV_B32 vDst(VGPR99) src0(VGPR148) # 212: OpFunctionCall: Float: hash(f1;(param211) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x63 # VGPR99 S_MOV_B64 sDst(SGPR72) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0x95 # VGPR149 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR72) # .lbl1 # 214: OpFAdd: Float: tmp214 << tmp208, const106 V_MOV_B32 vDst(VGPR150) src0(1_0_F) V_ADD_F32 vDst(VGPR151) src0(VGPR146) src1(VGPR150) // VOP2 # OpStore: : tmp214 >> param215 V_MOV_B32 vDst(VGPR100) src0(VGPR151) # 216: OpFunctionCall: Float: hash(f1;(param215) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x64 # VGPR100 S_MOV_B64 sDst(SGPR74) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0x98 # VGPR152 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR74) # .lbl2 # 217: OpAccessChain: Float*: f[0] # 218: OpLoad: Float: tmp218 << f[0] V_MOV_B32 vDst(VGPR153) src0(VGPR96) # 219: OpExtInst(FMix): Float: tmp219 << hash(f1;, hash(f1;, tmp218 V_SUBREV_F32 vDst(VGPR154) src0(VGPR153) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR154) src0(VGPR149) src1(VGPR154) // VOP2 V_MAD_F32 vDst(VGPR154) src0(VGPR152) src1(VGPR153) src2(VGPR154) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 221: OpFAdd: Float: tmp221 << tmp208, const200 V_MOV_B32 vDst(VGPR155) src0(LITERAL_CONST) const: 0x431d0000 V_ADD_F32 vDst(VGPR156) src0(VGPR146) src1(VGPR155) // VOP2 # OpStore: : tmp221 >> param222 V_MOV_B32 vDst(VGPR101) src0(VGPR156) # 223: OpFunctionCall: Float: hash(f1;(param222) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x65 # VGPR101 S_MOV_B64 sDst(SGPR76) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0x9d # VGPR157 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR76) # .lbl3 # 226: OpFAdd: Float: tmp226 << tmp208, const225 V_MOV_B32 vDst(VGPR158) src0(LITERAL_CONST) const: 0x431e0000 V_ADD_F32 vDst(VGPR159) src0(VGPR146) src1(VGPR158) // VOP2 # OpStore: : tmp226 >> param227 V_MOV_B32 vDst(VGPR102) src0(VGPR159) # 228: OpFunctionCall: Float: hash(f1;(param227) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x66 # VGPR102 S_MOV_B64 sDst(SGPR78) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xa0 # VGPR160 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR78) # .lbl4 # 229: OpAccessChain: Float*: f[0] # 230: OpLoad: Float: tmp230 << f[0] V_MOV_B32 vDst(VGPR161) src0(VGPR96) # 231: OpExtInst(FMix): Float: tmp231 << hash(f1;, hash(f1;, tmp230 V_SUBREV_F32 vDst(VGPR162) src0(VGPR161) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR162) src0(VGPR157) src1(VGPR162) // VOP2 V_MAD_F32 vDst(VGPR162) src0(VGPR160) src1(VGPR161) src2(VGPR162) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 232: OpAccessChain: Float*: f[1] # 233: OpLoad: Float: tmp233 << f[1] V_MOV_B32 vDst(VGPR163) src0(VGPR97) # 234: OpExtInst(FMix): Float: tmp234 << tmp219, tmp231, tmp233 V_SUBREV_F32 vDst(VGPR164) src0(VGPR163) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR164) src0(VGPR154) src1(VGPR164) // VOP2 V_MAD_F32 vDst(VGPR164) src0(VGPR162) src1(VGPR163) src2(VGPR164) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 236: OpFAdd: Float: tmp236 << tmp208, const203 V_MOV_B32 vDst(VGPR165) src0(LITERAL_CONST) const: 0x42e20000 V_ADD_F32 vDst(VGPR166) src0(VGPR146) src1(VGPR165) // VOP2 # OpStore: : tmp236 >> param237 V_MOV_B32 vDst(VGPR103) src0(VGPR166) # 238: OpFunctionCall: Float: hash(f1;(param237) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x67 # VGPR103 S_MOV_B64 sDst(SGPR80) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xa7 # VGPR167 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR80) # .lbl5 # 241: OpFAdd: Float: tmp241 << tmp208, const240 V_MOV_B32 vDst(VGPR168) src0(LITERAL_CONST) const: 0x42e40000 V_ADD_F32 vDst(VGPR169) src0(VGPR146) src1(VGPR168) // VOP2 # OpStore: : tmp241 >> param242 V_MOV_B32 vDst(VGPR104) src0(VGPR169) # 243: OpFunctionCall: Float: hash(f1;(param242) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x68 # VGPR104 S_MOV_B64 sDst(SGPR82) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xaa # VGPR170 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR82) # .lbl6 # 244: OpAccessChain: Float*: f[0] # 245: OpLoad: Float: tmp245 << f[0] V_MOV_B32 vDst(VGPR171) src0(VGPR96) # 246: OpExtInst(FMix): Float: tmp246 << hash(f1;, hash(f1;, tmp245 V_SUBREV_F32 vDst(VGPR172) src0(VGPR171) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR172) src0(VGPR167) src1(VGPR172) // VOP2 V_MAD_F32 vDst(VGPR172) src0(VGPR170) src1(VGPR171) src2(VGPR172) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 249: OpFAdd: Float: tmp249 << tmp208, const248 V_MOV_B32 vDst(VGPR173) src0(LITERAL_CONST) const: 0x43870000 V_ADD_F32 vDst(VGPR174) src0(VGPR146) src1(VGPR173) // VOP2 # OpStore: : tmp249 >> param250 V_MOV_B32 vDst(VGPR105) src0(VGPR174) # 251: OpFunctionCall: Float: hash(f1;(param250) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x69 # VGPR105 S_MOV_B64 sDst(SGPR84) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xaf # VGPR175 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR84) # .lbl7 # 254: OpFAdd: Float: tmp254 << tmp208, const253 V_MOV_B32 vDst(VGPR176) src0(LITERAL_CONST) const: 0x43878000 V_ADD_F32 vDst(VGPR177) src0(VGPR146) src1(VGPR176) // VOP2 # OpStore: : tmp254 >> param255 V_MOV_B32 vDst(VGPR106) src0(VGPR177) # 256: OpFunctionCall: Float: hash(f1;(param255) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x6a # VGPR106 S_MOV_B64 sDst(SGPR86) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xb2 # VGPR178 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR86) # .lbl8 # 257: OpAccessChain: Float*: f[0] # 258: OpLoad: Float: tmp258 << f[0] V_MOV_B32 vDst(VGPR179) src0(VGPR96) # 259: OpExtInst(FMix): Float: tmp259 << hash(f1;, hash(f1;, tmp258 V_SUBREV_F32 vDst(VGPR180) src0(VGPR179) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR180) src0(VGPR175) src1(VGPR180) // VOP2 V_MAD_F32 vDst(VGPR180) src0(VGPR178) src1(VGPR179) src2(VGPR180) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 260: OpAccessChain: Float*: f[1] # 261: OpLoad: Float: tmp261 << f[1] V_MOV_B32 vDst(VGPR181) src0(VGPR97) # 262: OpExtInst(FMix): Float: tmp262 << tmp246, tmp259, tmp261 V_SUBREV_F32 vDst(VGPR182) src0(VGPR181) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR182) src0(VGPR172) src1(VGPR182) // VOP2 V_MAD_F32 vDst(VGPR182) src0(VGPR180) src1(VGPR181) src2(VGPR182) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 263: OpAccessChain: Float*: f[2] # 264: OpLoad: Float: tmp264 << f[2] V_MOV_B32 vDst(VGPR183) src0(VGPR98) # 265: OpExtInst(FMix): Float: tmp265 << tmp234, tmp262, tmp264 V_SUBREV_F32 vDst(VGPR184) src0(VGPR183) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR184) src0(VGPR164) src1(VGPR184) // VOP2 V_MAD_F32 vDst(VGPR184) src0(VGPR182) src1(VGPR183) src2(VGPR184) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp265 S_MOV_B32 sDst(M0) src0(SGPR68) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR184) S_SETPC_B64 sDst(SGPR66) src0(SGPR66) # Float smN2(vf2;(FloatVector2* p) Function: Float smN2(vf2;() S_MOV_B64 sDst(SGPR92) src0(EXEC) # lb30 Label: lb30 # 268: OpLoad: FloatVector2: tmp268 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR188) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR189) src0(VGPR1) # 269: OpCompositeExtract: Float: tmp269 << tmp268, 0 V_MOV_B32 vDst(VGPR190) src0(VGPR188) # 270: OpCompositeExtract: Float: tmp270 << tmp268, 1 V_MOV_B32 vDst(VGPR191) src0(VGPR189) # 271: OpCompositeConstruct: FloatVector3: tmp271 << tmp269, tmp270, const100 V_MOV_B32 vDst(VGPR192) src0(VGPR190) V_MOV_B32 vDst(VGPR193) src0(VGPR191) V_MOV_B32 vDst(VGPR195) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR194) src0(VGPR195) # OpStore: : tmp271 >> param272 V_MOV_B32 vDst(VGPR185) src0(VGPR192) V_MOV_B32 vDst(VGPR186) src0(VGPR193) V_MOV_B32 vDst(VGPR187) src0(VGPR194) # 273: OpFunctionCall: Float: noise(vf3;(param272) S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0xb9 # VGPR[185:187] S_MOV_B64 sDst(SGPR94) src0(EXEC) S_MOV_B32 sDst(SGPR68) src0(LITERAL_CONST) const: 0xc4 # VGPR196 # Indirect branch to noise(vf3;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR94) # .lbl9 # OpReturnValue: : << noise(vf3; S_MOV_B32 sDst(M0) src0(SGPR90) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR196) S_SETPC_B64 sDst(SGPR88) src0(SGPR88) # Float smN3(vf3;(FloatVector3* p) Function: Float smN3(vf3;() S_MOV_B64 sDst(SGPR100) src0(EXEC) # lb33 Label: lb33 # 277: OpLoad: FloatVector3: tmp277 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR99) const: 0x0 V_MOVRELS_B32 vDst(VGPR200) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR201) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR202) src0(VGPR2) # OpStore: : tmp277 >> param276 V_MOV_B32 vDst(VGPR197) src0(VGPR200) V_MOV_B32 vDst(VGPR198) src0(VGPR201) V_MOV_B32 vDst(VGPR199) src0(VGPR202) # 278: OpFunctionCall: Float: noise(vf3;(param276) S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0xc5 # VGPR[197:199] S_MOV_B64 sDst(SGPR102) src0(EXEC) S_MOV_B32 sDst(SGPR68) src0(LITERAL_CONST) const: 0xcb # VGPR203 # Indirect branch to noise(vf3;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR102) # .lbl10 # OpReturnValue: : << noise(vf3; S_MOV_B32 sDst(M0) src0(SGPR98) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR203) S_SETPC_B64 sDst(SGPR96) src0(SGPR96) # Float fbm3(vf3;(FloatVector3* p) Function: Float fbm3(vf3;() S_MOV_B64 sDst(SGPR108) src0(EXEC) # lb36 Label: lb36 # OpStore: : const100 >> f V_MOV_B32 vDst(VGPR209) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR204) src0(VGPR209) # OpStore: : const285 >> i V_MOV_B32 vDst(VGPR205) src0(1_INT) # OpBranch: to lb286 S_BRANCH ??? lb286 # lb286 Label: lb286 # OpLoopMerge: (merge: lb288, continue: lb289) # CF Block: Merge: lb288, Continue: lb289 S_MOV_B64 sDst(SGPR110) src0(EXEC) S_MOV_B64 sDst(SGPR112) src0(EXEC) S_MOV_B64 sDst(SGPR114) src0(EXEC) Label: lb286Loop # OpBranch: to lb290 S_BRANCH ??? lb290 # lb290 Label: lb290 # 291: OpLoad: Int: tmp291 << i Decorators: RelaxedPrecision # 293: OpSLessThanEqual: Bool: tmp293 << tmp291, const292 V_MOV_B32 vDst(VGPR210) src0(9_INT) V_CMP_LE_I32 dst(SGPR116) src0(VGPR205) src1(VGPR210) // VOP3a # OpBranchConditional: if(tmp293) then branch to lb287, else branch to lb288 # CF Block: Cond Branch: true: lb287, false: lb288 S_AND_B64 sDst(EXEC) src0(SGPR116) src1(EXEC) S_CBRANCH_EXECZ ??? lb288 S_BRANCH ??? lb287 # lb287 Label: lb287 # 295: OpLoad: Int: tmp295 << i Decorators: RelaxedPrecision # 296: OpConvertSToF: Float: tmp296 << tmp295 V_CVT_F32_I32 vDst(VGPR211) src0(VGPR205) # 297: OpExtInst(Exp2): Float: tmp297 << tmp296 V_EXP_F32 vDst(VGPR212) src0(VGPR211) # 298: OpLoad: FloatVector3: tmp298 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR107) const: 0x0 V_MOVRELS_B32 vDst(VGPR213) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR214) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR215) src0(VGPR2) # 300: OpVectorTimesScalar: FloatVector3: tmp300 << tmp298, tmp297 V_MUL_F32 vDst(VGPR216) src0(VGPR212) src1(VGPR213) // VOP2 V_MUL_F32 vDst(VGPR217) src0(VGPR212) src1(VGPR214) // VOP2 V_MUL_F32 vDst(VGPR218) src0(VGPR212) src1(VGPR215) // VOP2 # OpStore: : tmp300 >> param301 V_MOV_B32 vDst(VGPR206) src0(VGPR216) V_MOV_B32 vDst(VGPR207) src0(VGPR217) V_MOV_B32 vDst(VGPR208) src0(VGPR218) # 302: OpFunctionCall: Float: noise(vf3;(param301) S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0xce # VGPR[206:208] S_MOV_B64 sDst(SGPR118) src0(EXEC) S_MOV_B32 sDst(SGPR68) src0(LITERAL_CONST) const: 0xdb # VGPR219 # Indirect branch to noise(vf3;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR118) # .lbl11 # 304: OpFSub: Float: tmp304 << noise(vf3;, const303 V_MOV_B32 vDst(VGPR220) src0(0_5_F) V_SUB_F32 vDst(VGPR221) src0(VGPR219) src1(VGPR220) // VOP2 # 306: OpFDiv: Float: tmp306 << tmp304, tmp297 V_RCP_F32 vDst(VGPR222) src0(VGPR212) V_MUL_F32 vDst(VGPR222) src0(VGPR221) src1(VGPR222) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR222) src0(VGPR222) src1(VGPR212) src2(VGPR221) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 307: OpLoad: Float: tmp307 << f # 308: OpFAdd: Float: tmp308 << tmp307, tmp306 V_ADD_F32 vDst(VGPR223) src0(VGPR204) src1(VGPR222) // VOP2 # OpStore: : tmp308 >> f V_MOV_B32 vDst(VGPR204) src0(VGPR223) # OpBranch: to lb289 S_BRANCH ??? lb289 # lb289 Label: lb289 # 309: OpLoad: Int: tmp309 << i Decorators: RelaxedPrecision # 310: OpIAdd: Int: tmp310 << tmp309, const285 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR224) src0(1_INT) V_ADD_I32 vDst(VGPR225) src0(VGPR205) src1(VGPR224) // VOP2 # OpStore: : tmp310 >> i V_MOV_B32 vDst(VGPR205) src0(VGPR225) # OpBranch: to lb286 S_BRANCH ??? lb286 # lb288 Label: lb288 # 311: OpLoad: Float: tmp311 << f # OpReturnValue: : << tmp311 S_MOV_B32 sDst(M0) src0(SGPR106) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR204) S_SETPC_B64 sDst(SGPR104) src0(SGPR104) # FloatVector2 rotate(f1;vf2;(Float* a, FloatVector2* v) Function: FloatVector2 rotate(f1;vf2;(, FloatVector2 fbm3(vf3;.v) S_MOV_B64 sDst(SGPR126) src0(EXEC) # lb41 Label: lb41 # 314: OpLoad: Float: tmp314 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR123) const: 0x0 V_MOVRELS_B32 vDst(VGPR226) src0(VGPR0) # 315: OpExtInst(Cos): Float: tmp315 << tmp314 V_MUL_F32 vDst(VGPR227) src0(LITERAL_CONST) src1(VGPR226) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR227) src0(VGPR227) V_COS_F32 vDst(VGPR227) src0(VGPR227) # 316: OpAccessChain: Float*: v[0] # 317: OpLoad: Float: tmp317 << v[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELS_B32 vDst(VGPR228) src0(VGPR0) # 318: OpFMul: Float: tmp318 << tmp315, tmp317 V_MUL_F32 vDst(VGPR229) src0(VGPR227) src1(VGPR228) // VOP2 # 319: OpLoad: Float: tmp319 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR123) const: 0x0 V_MOVRELS_B32 vDst(VGPR230) src0(VGPR0) # 320: OpExtInst(Sin): Float: tmp320 << tmp319 V_MUL_F32 vDst(VGPR231) src0(LITERAL_CONST) src1(VGPR230) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR231) src0(VGPR231) V_SIN_F32 vDst(VGPR231) src0(VGPR231) # 321: OpAccessChain: Float*: v[1] # 322: OpLoad: Float: tmp322 << v[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELS_B32 vDst(VGPR232) src0(VGPR1) # 323: OpFMul: Float: tmp323 << tmp320, tmp322 V_MUL_F32 vDst(VGPR233) src0(VGPR231) src1(VGPR232) // VOP2 # 324: OpFAdd: Float: tmp324 << tmp318, tmp323 V_ADD_F32 vDst(VGPR234) src0(VGPR229) src1(VGPR233) // VOP2 # 325: OpLoad: Float: tmp325 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR123) const: 0x0 V_MOVRELS_B32 vDst(VGPR235) src0(VGPR0) # 326: OpExtInst(Cos): Float: tmp326 << tmp325 V_MUL_F32 vDst(VGPR236) src0(LITERAL_CONST) src1(VGPR235) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR236) src0(VGPR236) V_COS_F32 vDst(VGPR236) src0(VGPR236) # 327: OpAccessChain: Float*: v[1] # 328: OpLoad: Float: tmp328 << v[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELS_B32 vDst(VGPR237) src0(VGPR1) # 329: OpFMul: Float: tmp329 << tmp326, tmp328 V_MUL_F32 vDst(VGPR238) src0(VGPR236) src1(VGPR237) // VOP2 # 330: OpLoad: Float: tmp330 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR123) const: 0x0 V_MOVRELS_B32 vDst(VGPR239) src0(VGPR0) # 331: OpExtInst(Sin): Float: tmp331 << tmp330 V_MUL_F32 vDst(VGPR240) src0(LITERAL_CONST) src1(VGPR239) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR240) src0(VGPR240) V_SIN_F32 vDst(VGPR240) src0(VGPR240) # 332: OpAccessChain: Float*: v[0] # 333: OpLoad: Float: tmp333 << v[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELS_B32 vDst(VGPR241) src0(VGPR0) # 334: OpFMul: Float: tmp334 << tmp331, tmp333 V_MUL_F32 vDst(VGPR242) src0(VGPR240) src1(VGPR241) // VOP2 # 335: OpFSub: Float: tmp335 << tmp329, tmp334 V_SUB_F32 vDst(VGPR243) src0(VGPR238) src1(VGPR242) // VOP2 # 336: OpCompositeConstruct: FloatVector2: tmp336 << tmp324, tmp335 V_MOV_B32 vDst(VGPR244) src0(VGPR234) V_MOV_B32 vDst(VGPR245) src0(VGPR243) # OpReturnValue: : << tmp336 S_MOV_B32 sDst(M0) src0(SGPR122) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR244) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR245) S_SETPC_B64 sDst(SGPR120) src0(SGPR120) # Float sugarybit(vf2;(FloatVector2* p) Function: Float sugarybit(vf2;() S_MOV_B64 sDst(SGPR132) src0(EXEC) # lb44 Label: lb44 # 339: OpLoad: FloatVector2: tmp339 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR246) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR247) src0(VGPR1) # 343: OpExtInst(FClamp): FloatVector2: tmp343 << tmp339, const341, const342 V_MOV_B32 vDst(VGPR248) src0(M1_0_F) V_MOV_B32 vDst(VGPR249) src0(M1_0_F) V_MOV_B32 vDst(VGPR250) src0(1_0_F) V_MOV_B32 vDst(VGPR251) src0(1_0_F) V_MAX_F32 vDst(VGPR252) src0(VGPR246) src1(VGPR248) // VOP2 V_MAX_F32 vDst(VGPR253) src0(VGPR247) src1(VGPR249) // VOP2 V_MIN_F32 vDst(VGPR252) src0(VGPR252) src1(VGPR250) // VOP2 V_MIN_F32 vDst(VGPR253) src0(VGPR253) src1(VGPR251) // VOP2 # OpStore: : tmp343 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR252) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR253) # 346: OpAccessChain: Float*: p[0] # 347: OpLoad: Float: tmp347 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 348: OpExtInst(FAbs): Float: tmp348 << tmp347 V_ADD_F32 vDst(VGPR255) src0(VGPR254) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 350: OpExtInst(Pow): Float: tmp350 << tmp348, const349 V_MOV_B32 vDst(VGPR256) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR257) src0(VGPR255) V_MUL_F32 vDst(VGPR257) src0(VGPR256) src1(VGPR257) // VOP2 V_EXP_F32 vDst(VGPR257) src0(VGPR257) # 351: OpFSub: Float: tmp351 << const106, tmp350 V_SUB_F32 vDst(VGPR258) src0(1_0_F) src1(VGPR257) // VOP2 # 352: OpAccessChain: Float*: p[1] # 353: OpLoad: Float: tmp353 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR259) src0(VGPR1) # 354: OpAccessChain: Float*: o[1] # 355: OpCompositeExtract: Float: tmp355 << const101, 1 V_MOV_B32 vDst(VGPR261) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR260) src0(VGPR262) # 356: OpFAdd: Float: tmp356 << tmp353, tmp355 V_ADD_F32 vDst(VGPR262) src0(VGPR259) src1(VGPR260) // VOP2 # 357: OpExtInst(FAbs): Float: tmp357 << tmp356 V_ADD_F32 vDst(VGPR263) src0(VGPR262) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 358: OpExtInst(Pow): Float: tmp358 << tmp357, const349 V_MOV_B32 vDst(VGPR264) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR265) src0(VGPR263) V_MUL_F32 vDst(VGPR265) src0(VGPR264) src1(VGPR265) // VOP2 V_EXP_F32 vDst(VGPR265) src0(VGPR265) # 359: OpFSub: Float: tmp359 << const106, tmp358 V_SUB_F32 vDst(VGPR266) src0(1_0_F) src1(VGPR265) // VOP2 # 360: OpFMul: Float: tmp360 << tmp351, tmp359 V_MUL_F32 vDst(VGPR267) src0(VGPR258) src1(VGPR266) // VOP2 # 362: OpFMul: Float: tmp362 << tmp360, const361 V_MOV_B32 vDst(VGPR268) src0(LITERAL_CONST) const: 0x3f733333 V_MUL_F32 vDst(VGPR269) src0(VGPR267) src1(VGPR268) // VOP2 # 363: OpExtInst(Pow): Float: tmp363 << tmp362, const303 V_MOV_B32 vDst(VGPR270) src0(0_5_F) V_LOG_F32 vDst(VGPR271) src0(VGPR269) V_MUL_F32 vDst(VGPR271) src0(VGPR270) src1(VGPR271) // VOP2 V_EXP_F32 vDst(VGPR271) src0(VGPR271) # 364: OpFSub: Float: tmp364 << const106, tmp363 V_SUB_F32 vDst(VGPR272) src0(1_0_F) src1(VGPR271) // VOP2 # 366: OpAccessChain: Float*: p[0] # 367: OpLoad: Float: tmp367 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR273) src0(VGPR0) # 368: OpExtInst(FAbs): Float: tmp368 << tmp367 V_ADD_F32 vDst(VGPR274) src0(VGPR273) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 369: OpExtInst(Pow): Float: tmp369 << tmp368, const349 V_MOV_B32 vDst(VGPR275) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR276) src0(VGPR274) V_MUL_F32 vDst(VGPR276) src0(VGPR275) src1(VGPR276) // VOP2 V_EXP_F32 vDst(VGPR276) src0(VGPR276) # 370: OpFSub: Float: tmp370 << const106, tmp369 V_SUB_F32 vDst(VGPR277) src0(1_0_F) src1(VGPR276) // VOP2 # 371: OpAccessChain: Float*: p[1] # 372: OpLoad: Float: tmp372 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR278) src0(VGPR1) # 373: OpExtInst(FAbs): Float: tmp373 << tmp372 V_ADD_F32 vDst(VGPR279) src0(VGPR278) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 374: OpExtInst(Pow): Float: tmp374 << tmp373, const349 V_MOV_B32 vDst(VGPR280) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR281) src0(VGPR279) V_MUL_F32 vDst(VGPR281) src0(VGPR280) src1(VGPR281) // VOP2 V_EXP_F32 vDst(VGPR281) src0(VGPR281) # 375: OpFSub: Float: tmp375 << const106, tmp374 V_SUB_F32 vDst(VGPR282) src0(1_0_F) src1(VGPR281) // VOP2 # 376: OpFMul: Float: tmp376 << tmp370, tmp375 V_MUL_F32 vDst(VGPR283) src0(VGPR277) src1(VGPR282) // VOP2 # 378: OpExtInst(Pow): Float: tmp378 << tmp376, const377 V_MOV_B32 vDst(VGPR284) src0(4_0_F) V_LOG_F32 vDst(VGPR285) src0(VGPR283) V_MUL_F32 vDst(VGPR285) src0(VGPR284) src1(VGPR285) // VOP2 V_EXP_F32 vDst(VGPR285) src0(VGPR285) # 381: OpFMul: Float: tmp381 << tmp364, tmp378 V_MUL_F32 vDst(VGPR286) src0(VGPR272) src1(VGPR285) // VOP2 # 382: OpFMul: Float: tmp382 << tmp381, const109 V_MOV_B32 vDst(VGPR287) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR288) src0(VGPR286) src1(VGPR287) // VOP2 # OpReturnValue: : << tmp382 S_MOV_B32 sDst(M0) src0(SGPR130) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR288) S_SETPC_B64 sDst(SGPR128) src0(SGPR128) # Float sugarlayer(vf2;f1;(FloatVector2* t, Float* ndotv) Function: Float sugarlayer(vf2;f1;(, Float sugarybit(vf2;.ndotv) S_MOV_B64 sDst(SGPR140) src0(EXEC) # lb49 Label: lb49 # 386: OpLoad: FloatVector2: tmp386 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR137) const: 0x0 V_MOVRELS_B32 vDst(VGPR300) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR301) src0(VGPR1) # 387: OpVectorTimesScalar: FloatVector2: tmp387 << tmp386, const349 V_MOV_B32 vDst(VGPR304) src0(LITERAL_CONST) const: 0x41000000 V_MUL_F32 vDst(VGPR302) src0(VGPR304) src1(VGPR300) // VOP2 V_MUL_F32 vDst(VGPR303) src0(VGPR304) src1(VGPR301) // VOP2 # 390: OpExtInst(Fract): FloatVector2: tmp390 << tmp387 V_FRACT_F32 vDst(VGPR305) src0(VGPR302) V_FRACT_F32 vDst(VGPR306) src0(VGPR303) # 392: OpFSub: FloatVector2: tmp392 << tmp390, const391 V_MOV_B32 vDst(VGPR307) src0(0_5_F) V_MOV_B32 vDst(VGPR308) src0(0_5_F) V_SUB_F32 vDst(VGPR309) src0(VGPR305) src1(VGPR307) // VOP2 V_SUB_F32 vDst(VGPR310) src0(VGPR306) src1(VGPR308) // VOP2 # 395: OpExtInst(Floor): FloatVector2: tmp395 << tmp387 V_FLOOR_F32 vDst(VGPR311) src0(VGPR302) V_FLOOR_F32 vDst(VGPR312) src0(VGPR303) # 397: OpAccessChain: Float*: c[0] # 398: OpCompositeExtract: Float: tmp398 << tmp395, 0 V_MOV_B32 vDst(VGPR313) src0(VGPR311) # 399: OpAccessChain: Float*: c[1] # 400: OpCompositeExtract: Float: tmp400 << tmp395, 1 V_MOV_B32 vDst(VGPR314) src0(VGPR312) # 402: OpFMul: Float: tmp402 << tmp400, const401 V_MOV_B32 vDst(VGPR315) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR316) src0(VGPR314) src1(VGPR315) // VOP2 # 403: OpFAdd: Float: tmp403 << tmp398, tmp402 V_ADD_F32 vDst(VGPR317) src0(VGPR313) src1(VGPR316) // VOP2 # 405: OpAccessChain: Float*: c[1] # 406: OpCompositeExtract: Float: tmp406 << tmp395, 1 V_MOV_B32 vDst(VGPR318) src0(VGPR312) # 408: OpFMul: Float: tmp408 << tmp406, const407 V_MOV_B32 vDst(VGPR319) src0(LITERAL_CONST) const: 0x42540000 V_MUL_F32 vDst(VGPR320) src0(VGPR318) src1(VGPR319) // VOP2 # 409: OpExtInst(Cos): Float: tmp409 << tmp408 V_MUL_F32 vDst(VGPR321) src0(LITERAL_CONST) src1(VGPR320) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR321) src0(VGPR321) V_COS_F32 vDst(VGPR321) src0(VGPR321) # 410: OpAccessChain: Float*: c[0] # 411: OpCompositeExtract: Float: tmp411 << tmp395, 0 V_MOV_B32 vDst(VGPR322) src0(VGPR311) # 413: OpFMul: Float: tmp413 << tmp411, const412 V_MOV_B32 vDst(VGPR323) src0(LITERAL_CONST) const: 0x42fa0000 V_MUL_F32 vDst(VGPR324) src0(VGPR322) src1(VGPR323) // VOP2 # 414: OpExtInst(Sin): Float: tmp414 << tmp413 V_MUL_F32 vDst(VGPR325) src0(LITERAL_CONST) src1(VGPR324) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR325) src0(VGPR325) V_SIN_F32 vDst(VGPR325) src0(VGPR325) # 415: OpCompositeConstruct: FloatVector2: tmp415 << tmp409, tmp414 V_MOV_B32 vDst(VGPR326) src0(VGPR321) V_MOV_B32 vDst(VGPR327) src0(VGPR325) # 417: OpVectorTimesScalar: FloatVector2: tmp417 << tmp415, const416 V_MOV_B32 vDst(VGPR330) src0(LITERAL_CONST) const: 0x40200000 V_MUL_F32 vDst(VGPR328) src0(VGPR330) src1(VGPR326) // VOP2 V_MUL_F32 vDst(VGPR329) src0(VGPR330) src1(VGPR327) // VOP2 # OpStore: : tmp395 >> param419 V_MOV_B32 vDst(VGPR289) src0(VGPR311) V_MOV_B32 vDst(VGPR290) src0(VGPR312) # 421: OpFunctionCall: Float: smN2(vf2;(param419) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x121 # VGPR[289:290] S_MOV_B64 sDst(SGPR142) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x14b # VGPR331 # Indirect branch to smN2(vf2;: ??? S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_ADD_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR142) # .lbl12 # 425: OpFAdd: FloatVector2: tmp425 << tmp395, const424 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x42c80000 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x42c80000 V_ADD_F32 vDst(VGPR334) src0(VGPR311) src1(VGPR332) // VOP2 V_ADD_F32 vDst(VGPR335) src0(VGPR312) src1(VGPR333) // VOP2 # OpStore: : tmp425 >> param426 V_MOV_B32 vDst(VGPR291) src0(VGPR334) V_MOV_B32 vDst(VGPR292) src0(VGPR335) # 427: OpFunctionCall: Float: smN2(vf2;(param426) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x123 # VGPR[291:292] S_MOV_B64 sDst(SGPR144) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x150 # VGPR336 # Indirect branch to smN2(vf2;: ??? S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_ADD_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR144) # .lbl13 # 428: OpCompositeConstruct: FloatVector2: tmp428 << smN2(vf2;, smN2(vf2; V_MOV_B32 vDst(VGPR337) src0(VGPR331) V_MOV_B32 vDst(VGPR338) src0(VGPR336) # 429: OpCompositeConstruct: FloatVector2: tmp429 << const106, const106 V_MOV_B32 vDst(VGPR339) src0(1_0_F) V_MOV_B32 vDst(VGPR340) src0(1_0_F) # 430: OpFAdd: FloatVector2: tmp430 << tmp429, tmp428 V_ADD_F32 vDst(VGPR341) src0(VGPR339) src1(VGPR337) // VOP2 V_ADD_F32 vDst(VGPR342) src0(VGPR340) src1(VGPR338) // VOP2 # 432: OpLoad: Float: tmp432 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR138) const: 0x0 V_MOVRELS_B32 vDst(VGPR343) src0(VGPR0) # 433: OpFSub: Float: tmp433 << const106, tmp432 V_SUB_F32 vDst(VGPR344) src0(1_0_F) src1(VGPR343) // VOP2 # 434: OpExtInst(Pow): Float: tmp434 << tmp433, const377 V_MOV_B32 vDst(VGPR345) src0(4_0_F) V_LOG_F32 vDst(VGPR346) src0(VGPR344) V_MUL_F32 vDst(VGPR346) src0(VGPR345) src1(VGPR346) // VOP2 V_EXP_F32 vDst(VGPR346) src0(VGPR346) # 436: OpExtInst(FMix): Float: tmp436 << const106, tmp434, const435 V_MOV_B32 vDst(VGPR347) src0(LITERAL_CONST) const: 0x3f666666 V_SUBREV_F32 vDst(VGPR348) src0(VGPR347) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR348) src0(1_0_F) src1(VGPR348) // VOP2 V_MAD_F32 vDst(VGPR348) src0(VGPR346) src1(VGPR347) src2(VGPR348) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 438: OpFMul: Float: tmp438 << tmp436, const437 V_MOV_B32 vDst(VGPR349) src0(LITERAL_CONST) const: 0x41c80000 V_MUL_F32 vDst(VGPR350) src0(VGPR348) src1(VGPR349) // VOP2 # 441: OpFMul: FloatVector2: tmp441 << tmp392, tmp430 V_MUL_F32 vDst(VGPR351) src0(VGPR309) src1(VGPR341) // VOP2 V_MUL_F32 vDst(VGPR352) src0(VGPR310) src1(VGPR342) // VOP2 # 442: OpVectorTimesScalar: FloatVector2: tmp442 << tmp441, const377 V_MOV_B32 vDst(VGPR355) src0(4_0_F) V_MUL_F32 vDst(VGPR353) src0(VGPR355) src1(VGPR351) // VOP2 V_MUL_F32 vDst(VGPR354) src0(VGPR355) src1(VGPR352) // VOP2 # 444: OpFAdd: FloatVector2: tmp444 << tmp442, tmp417 V_ADD_F32 vDst(VGPR356) src0(VGPR353) src1(VGPR328) // VOP2 V_ADD_F32 vDst(VGPR357) src0(VGPR354) src1(VGPR329) // VOP2 # OpStore: : tmp403 >> param445 V_MOV_B32 vDst(VGPR293) src0(VGPR317) # OpStore: : tmp444 >> param447 V_MOV_B32 vDst(VGPR294) src0(VGPR356) V_MOV_B32 vDst(VGPR295) src0(VGPR357) # 448: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param445, param447) S_ADD_U32 sDst(SGPR123) src0(LITERAL_CONST) src1(0) const: 0x125 # VGPR293 S_ADD_U32 sDst(SGPR124) src0(LITERAL_CONST) src1(0) const: 0x126 # VGPR[294:295] S_MOV_B64 sDst(SGPR146) src0(EXEC) S_MOV_B32 sDst(SGPR122) src0(LITERAL_CONST) const: 0x166 # VGPR[358:359] # Indirect branch to rotate(f1;vf2;: ??? S_GETPC_B64 sDst(SGPR120) src0(SGPR120) S_ADD_U32 sDst(SGPR120) src0(SGPR120) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR121) src0(SGPR121) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR120) src0(SGPR120) S_MOV_B64 sDst(EXEC) src0(SGPR146) # .lbl14 # OpStore: : rotate(f1;vf2; >> param449 V_MOV_B32 vDst(VGPR296) src0(VGPR358) V_MOV_B32 vDst(VGPR297) src0(VGPR359) # 450: OpFunctionCall: Float: sugarybit(vf2;(param449) S_ADD_U32 sDst(SGPR131) src0(LITERAL_CONST) src1(0) const: 0x128 # VGPR[296:297] S_MOV_B64 sDst(SGPR148) src0(EXEC) S_MOV_B32 sDst(SGPR130) src0(LITERAL_CONST) const: 0x168 # VGPR360 # Indirect branch to sugarybit(vf2;: ??? S_GETPC_B64 sDst(SGPR128) src0(SGPR128) S_ADD_U32 sDst(SGPR128) src0(SGPR128) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR129) src0(SGPR129) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR128) src0(SGPR128) S_MOV_B64 sDst(EXEC) src0(SGPR148) # .lbl15 # 452: OpVectorTimesScalar: FloatVector2: tmp452 << tmp387, const401 V_MOV_B32 vDst(VGPR363) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR361) src0(VGPR363) src1(VGPR302) // VOP2 V_MUL_F32 vDst(VGPR362) src0(VGPR363) src1(VGPR303) // VOP2 # OpStore: : tmp452 >> param453 V_MOV_B32 vDst(VGPR298) src0(VGPR361) V_MOV_B32 vDst(VGPR299) src0(VGPR362) # 454: OpFunctionCall: Float: smN2(vf2;(param453) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x12a # VGPR[298:299] S_MOV_B64 sDst(SGPR150) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x16c # VGPR364 # Indirect branch to smN2(vf2;: ??? S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_ADD_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR150) # .lbl16 # 455: OpFSub: Float: tmp455 << smN2(vf2;, const303 V_MOV_B32 vDst(VGPR365) src0(0_5_F) V_SUB_F32 vDst(VGPR366) src0(VGPR364) src1(VGPR365) // VOP2 # 456: OpExtInst(FMax): Float: tmp456 << const100, tmp455 V_MOV_B32 vDst(VGPR367) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR368) src0(VGPR367) src1(VGPR366) // VOP2 # 457: OpFMul: Float: tmp457 << sugarybit(vf2;, tmp456 V_MUL_F32 vDst(VGPR369) src0(VGPR360) src1(VGPR368) // VOP2 # 459: OpFMul: Float: tmp459 << tmp457, tmp438 V_MUL_F32 vDst(VGPR370) src0(VGPR369) src1(VGPR350) // VOP2 # OpReturnValue: : << tmp459 S_MOV_B32 sDst(M0) src0(SGPR136) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR370) S_SETPC_B64 sDst(SGPR134) src0(SGPR134) # FloatVector3 saturatecol(vf3;(FloatVector3* c) Function: FloatVector3 saturatecol(vf3;() S_MOV_B64 sDst(SGPR156) src0(EXEC) # lb53 Label: lb53 # 462: OpLoad: FloatVector3: tmp462 << c S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR155) const: 0x0 V_MOVRELS_B32 vDst(VGPR372) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR373) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR374) src0(VGPR2) # 464: OpLoad: Float: tmp464 << colour # OpStore: : tmp464 >> param463 V_MOV_B32 vDst(VGPR371) src0(VGPR30) # 465: OpFunctionCall: FloatVector3: gumRamp(f1;(param463) S_ADD_U32 sDst(SGPR41) src0(LITERAL_CONST) src1(0) const: 0x173 # VGPR371 S_MOV_B64 sDst(SGPR158) src0(EXEC) S_MOV_B32 sDst(SGPR40) src0(LITERAL_CONST) const: 0x177 # VGPR[375:377] # Indirect branch to gumRamp(f1;: ??? S_GETPC_B64 sDst(SGPR38) src0(SGPR38) S_ADD_U32 sDst(SGPR38) src0(SGPR38) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR39) src0(SGPR39) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR38) src0(SGPR38) S_MOV_B64 sDst(EXEC) src0(SGPR158) # .lbl17 # 466: OpExtInst(Pow): FloatVector3: tmp466 << tmp462, gumRamp(f1; V_LOG_F32 vDst(VGPR378) src0(VGPR372) V_LOG_F32 vDst(VGPR379) src0(VGPR373) V_LOG_F32 vDst(VGPR380) src0(VGPR374) V_MUL_F32 vDst(VGPR378) src0(VGPR375) src1(VGPR378) // VOP2 V_MUL_F32 vDst(VGPR379) src0(VGPR376) src1(VGPR379) // VOP2 V_MUL_F32 vDst(VGPR380) src0(VGPR377) src1(VGPR380) // VOP2 V_EXP_F32 vDst(VGPR378) src0(VGPR378) V_EXP_F32 vDst(VGPR379) src0(VGPR379) V_EXP_F32 vDst(VGPR380) src0(VGPR380) # OpReturnValue: : << tmp466 S_MOV_B32 sDst(M0) src0(SGPR154) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR378) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR379) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR380) S_SETPC_B64 sDst(SGPR152) src0(SGPR152) # Float sprinkles2(vf2;f1;(FloatVector2* coord, Float* ndotv) Function: Float sprinkles2(vf2;f1;(, Float saturatecol(vf3;.ndotv) S_MOV_B64 sDst(SGPR166) src0(EXEC) # lb57 Label: lb57 # OpStore: : const100 >> sprinkle V_MOV_B32 vDst(VGPR386) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR381) src0(VGPR386) # OpStore: : const471 >> i V_MOV_B32 vDst(VGPR382) src0(0) # OpBranch: to lb472 S_BRANCH ??? lb472 # lb472 Label: lb472 # OpLoopMerge: (merge: lb474, continue: lb475) # CF Block: Merge: lb474, Continue: lb475 S_MOV_B64 sDst(SGPR168) src0(EXEC) S_MOV_B64 sDst(SGPR170) src0(EXEC) S_MOV_B64 sDst(SGPR172) src0(EXEC) Label: lb472Loop # OpBranch: to lb476 S_BRANCH ??? lb476 # lb476 Label: lb476 # 477: OpLoad: Int: tmp477 << i Decorators: RelaxedPrecision # 479: OpSLessThan: Bool: tmp479 << tmp477, const478 V_MOV_B32 vDst(VGPR387) src0(4_INT) V_CMP_LT_I32 dst(SGPR174) src0(VGPR382) src1(VGPR387) // VOP3a # OpBranchConditional: if(tmp479) then branch to lb473, else branch to lb474 # CF Block: Cond Branch: true: lb473, false: lb474 S_AND_B64 sDst(EXEC) src0(SGPR174) src1(EXEC) S_CBRANCH_EXECZ ??? lb474 S_BRANCH ??? lb473 # lb473 Label: lb473 # 480: OpLoad: FloatVector2: tmp480 << coord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR163) const: 0x0 V_MOVRELS_B32 vDst(VGPR388) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR389) src0(VGPR1) # 481: OpLoad: Int: tmp481 << i Decorators: RelaxedPrecision # 482: OpConvertSToF: Float: tmp482 << tmp481 V_CVT_F32_I32 vDst(VGPR390) src0(VGPR382) # 484: OpFMul: Float: tmp484 << tmp482, const483 V_MOV_B32 vDst(VGPR391) src0(LITERAL_CONST) const: 0x41273333 V_MUL_F32 vDst(VGPR392) src0(VGPR390) src1(VGPR391) // VOP2 # 485: OpCompositeConstruct: FloatVector2: tmp485 << tmp484, tmp484 V_MOV_B32 vDst(VGPR393) src0(VGPR392) V_MOV_B32 vDst(VGPR394) src0(VGPR392) # 486: OpFAdd: FloatVector2: tmp486 << tmp480, tmp485 V_ADD_F32 vDst(VGPR395) src0(VGPR388) src1(VGPR393) // VOP2 V_ADD_F32 vDst(VGPR396) src0(VGPR389) src1(VGPR394) // VOP2 # 487: OpLoad: Int: tmp487 << i Decorators: RelaxedPrecision # 488: OpConvertSToF: Float: tmp488 << tmp487 V_CVT_F32_I32 vDst(VGPR397) src0(VGPR382) # 490: OpFMul: Float: tmp490 << tmp488, const489 V_MOV_B32 vDst(VGPR398) src0(LITERAL_CONST) const: 0x3e4ccccd V_MUL_F32 vDst(VGPR399) src0(VGPR397) src1(VGPR398) // VOP2 # 491: OpFAdd: Float: tmp491 << const106, tmp490 V_ADD_F32 vDst(VGPR400) src0(1_0_F) src1(VGPR399) // VOP2 # 492: OpVectorTimesScalar: FloatVector2: tmp492 << tmp486, tmp491 V_MUL_F32 vDst(VGPR401) src0(VGPR400) src1(VGPR395) // VOP2 V_MUL_F32 vDst(VGPR402) src0(VGPR400) src1(VGPR396) // VOP2 # OpStore: : tmp492 >> param493 V_MOV_B32 vDst(VGPR383) src0(VGPR401) V_MOV_B32 vDst(VGPR384) src0(VGPR402) # 495: OpLoad: Float: tmp495 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR164) const: 0x0 V_MOVRELS_B32 vDst(VGPR403) src0(VGPR0) # OpStore: : tmp495 >> param494 V_MOV_B32 vDst(VGPR385) src0(VGPR403) # 496: OpFunctionCall: Float: sugarlayer(vf2;f1;(param493, param494) S_ADD_U32 sDst(SGPR137) src0(LITERAL_CONST) src1(0) const: 0x17f # VGPR[383:384] S_ADD_U32 sDst(SGPR138) src0(LITERAL_CONST) src1(0) const: 0x181 # VGPR385 S_MOV_B64 sDst(SGPR176) src0(EXEC) S_MOV_B32 sDst(SGPR136) src0(LITERAL_CONST) const: 0x194 # VGPR404 # Indirect branch to sugarlayer(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR134) src0(SGPR134) S_ADD_U32 sDst(SGPR134) src0(SGPR134) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR135) src0(SGPR135) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR134) src0(SGPR134) S_MOV_B64 sDst(EXEC) src0(SGPR176) # .lbl18 # 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision # 498: OpConvertSToF: Float: tmp498 << tmp497 V_CVT_F32_I32 vDst(VGPR405) src0(VGPR382) # 499: OpFDiv: Float: tmp499 << tmp498, const377 V_MOV_B32 vDst(VGPR406) src0(4_0_F) V_RCP_F32 vDst(VGPR407) src0(VGPR406) V_MUL_F32 vDst(VGPR407) src0(VGPR405) src1(VGPR407) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR407) src0(VGPR407) src1(VGPR406) src2(VGPR405) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 500: OpFSub: Float: tmp500 << const106, tmp499 V_SUB_F32 vDst(VGPR408) src0(1_0_F) src1(VGPR407) // VOP2 # 501: OpExtInst(Pow): Float: tmp501 << tmp500, const377 V_MOV_B32 vDst(VGPR409) src0(4_0_F) V_LOG_F32 vDst(VGPR410) src0(VGPR408) V_MUL_F32 vDst(VGPR410) src0(VGPR409) src1(VGPR410) // VOP2 V_EXP_F32 vDst(VGPR410) src0(VGPR410) # 502: OpFMul: Float: tmp502 << sugarlayer(vf2;f1;, tmp501 V_MUL_F32 vDst(VGPR411) src0(VGPR404) src1(VGPR410) // VOP2 # 503: OpLoad: Float: tmp503 << sprinkle # 504: OpFAdd: Float: tmp504 << tmp503, tmp502 V_ADD_F32 vDst(VGPR412) src0(VGPR381) src1(VGPR411) // VOP2 # OpStore: : tmp504 >> sprinkle V_MOV_B32 vDst(VGPR381) src0(VGPR412) # OpBranch: to lb475 S_BRANCH ??? lb475 # lb475 Label: lb475 # 505: OpLoad: Int: tmp505 << i Decorators: RelaxedPrecision # 506: OpIAdd: Int: tmp506 << tmp505, const285 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR413) src0(1_INT) V_ADD_I32 vDst(VGPR414) src0(VGPR382) src1(VGPR413) // VOP2 # OpStore: : tmp506 >> i V_MOV_B32 vDst(VGPR382) src0(VGPR414) # OpBranch: to lb472 S_BRANCH ??? lb472 # lb474 Label: lb474 # 507: OpLoad: Float: tmp507 << sprinkle # OpReturnValue: : << tmp507 S_MOV_B32 sDst(M0) src0(SGPR162) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR381) S_SETPC_B64 sDst(SGPR160) src0(SGPR160) # Float sprinkles(vf2;f1;(FloatVector2* coord, Float* ndotv) Function: Float sprinkles(vf2;f1;(, Float sprinkles2(vf2;f1;.ndotv) S_MOV_B64 sDst(SGPR184) src0(EXEC) # lb61 Label: lb61 # 510: OpLoad: FloatVector2: tmp510 << coord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR181) const: 0x0 V_MOVRELS_B32 vDst(VGPR421) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR422) src0(VGPR1) # 512: OpVectorTimesScalar: FloatVector2: tmp512 << tmp510, const511 V_MOV_B32 vDst(VGPR425) src0(LITERAL_CONST) const: 0x3f400000 V_MUL_F32 vDst(VGPR423) src0(VGPR425) src1(VGPR421) // VOP2 V_MUL_F32 vDst(VGPR424) src0(VGPR425) src1(VGPR422) // VOP2 # OpStore: : tmp512 >> param513 V_MOV_B32 vDst(VGPR415) src0(VGPR423) V_MOV_B32 vDst(VGPR416) src0(VGPR424) # 515: OpLoad: Float: tmp515 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR182) const: 0x0 V_MOVRELS_B32 vDst(VGPR426) src0(VGPR0) # OpStore: : tmp515 >> param514 V_MOV_B32 vDst(VGPR417) src0(VGPR426) # 516: OpFunctionCall: Float: sprinkles2(vf2;f1;(param513, param514) S_ADD_U32 sDst(SGPR163) src0(LITERAL_CONST) src1(0) const: 0x19f # VGPR[415:416] S_ADD_U32 sDst(SGPR164) src0(LITERAL_CONST) src1(0) const: 0x1a1 # VGPR417 S_MOV_B64 sDst(SGPR186) src0(EXEC) S_MOV_B32 sDst(SGPR162) src0(LITERAL_CONST) const: 0x1ab # VGPR427 # Indirect branch to sprinkles2(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR160) src0(SGPR160) S_ADD_U32 sDst(SGPR160) src0(SGPR160) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR161) src0(SGPR161) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR160) src0(SGPR160) S_MOV_B64 sDst(EXEC) src0(SGPR186) # .lbl19 # 517: OpLoad: FloatVector2: tmp517 << coord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR181) const: 0x0 V_MOVRELS_B32 vDst(VGPR428) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR429) src0(VGPR1) # 518: OpVectorTimesScalar: FloatVector2: tmp518 << tmp517, const127 V_MOV_B32 vDst(VGPR432) src0(2_0_F) V_MUL_F32 vDst(VGPR430) src0(VGPR432) src1(VGPR428) // VOP2 V_MUL_F32 vDst(VGPR431) src0(VGPR432) src1(VGPR429) // VOP2 # OpStore: : tmp518 >> param519 V_MOV_B32 vDst(VGPR418) src0(VGPR430) V_MOV_B32 vDst(VGPR419) src0(VGPR431) # 521: OpLoad: Float: tmp521 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR182) const: 0x0 V_MOVRELS_B32 vDst(VGPR433) src0(VGPR0) # OpStore: : tmp521 >> param520 V_MOV_B32 vDst(VGPR420) src0(VGPR433) # 522: OpFunctionCall: Float: sprinkles2(vf2;f1;(param519, param520) S_ADD_U32 sDst(SGPR163) src0(LITERAL_CONST) src1(0) const: 0x1a2 # VGPR[418:419] S_ADD_U32 sDst(SGPR164) src0(LITERAL_CONST) src1(0) const: 0x1a4 # VGPR420 S_MOV_B64 sDst(SGPR188) src0(EXEC) S_MOV_B32 sDst(SGPR162) src0(LITERAL_CONST) const: 0x1b2 # VGPR434 # Indirect branch to sprinkles2(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR160) src0(SGPR160) S_ADD_U32 sDst(SGPR160) src0(SGPR160) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR161) src0(SGPR161) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR160) src0(SGPR160) S_MOV_B64 sDst(EXEC) src0(SGPR188) # .lbl20 # 524: OpFMul: Float: tmp524 << sprinkles2(vf2;f1;, const523 V_MOV_B32 vDst(VGPR435) src0(LITERAL_CONST) const: 0x3e99999a V_MUL_F32 vDst(VGPR436) src0(VGPR434) src1(VGPR435) // VOP2 # 525: OpFAdd: Float: tmp525 << sprinkles2(vf2;f1;, tmp524 V_ADD_F32 vDst(VGPR437) src0(VGPR427) src1(VGPR436) // VOP2 # OpReturnValue: : << tmp525 S_MOV_B32 sDst(M0) src0(SGPR180) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR437) S_SETPC_B64 sDst(SGPR178) src0(SGPR178) # FloatVector3 gummy(vf3;vf3;vf3;(FloatVector3* no, FloatVector3* vo, FloatVector3* v) Function: FloatVector3 gummy(vf3;vf3;vf3;(, FloatVector3 sprinkles(vf2;f1;.vo, FloatVector3 sprinkles(vf2;f1;.v) S_MOV_B64 sDst(SGPR196) src0(EXEC) # lb67 Label: lb67 # 529: OpLoad: FloatVector3: tmp529 << no S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR451) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR452) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR453) src0(VGPR2) # 530: OpLoad: FloatVector3: tmp530 << v S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR195) const: 0x0 V_MOVRELS_B32 vDst(VGPR454) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR455) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR456) src0(VGPR2) # 531: OpFNegate: FloatVector3: tmp531 << tmp530 V_MUL_F32 vDst(VGPR457) src0(M1_0_F) src1(VGPR454) // VOP2 V_MUL_F32 vDst(VGPR458) src0(M1_0_F) src1(VGPR455) // VOP2 V_MUL_F32 vDst(VGPR459) src0(M1_0_F) src1(VGPR456) // VOP2 # 532: OpDot: Float: tmp532 << tmp529, tmp531 V_MUL_F32 vDst(VGPR460) src0(VGPR451) src1(VGPR457) // VOP2 V_MAC_F32 vDst(VGPR460) src0(VGPR452) src1(VGPR458) // VOP2 V_MAC_F32 vDst(VGPR460) src0(VGPR453) src1(VGPR459) // VOP2 # 534: OpAccessChain: Float*: no[2] # 535: OpLoad: Float: tmp535 << no[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR461) src0(VGPR2) # 536: OpAccessChain: Float*: no[0] # 537: OpLoad: Float: tmp537 << no[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR462) src0(VGPR0) # 538: OpExtInst(Atan2): Float: tmp538 << tmp535, tmp537 V_MOV_B32 vDst(VGPR463) src0(LITERAL_CONST) const: 0xbc5cdd30 V_MOV_B32 vDst(VGPR464) src0(LITERAL_CONST) const: 0x3d6b6d55 V_MOV_B32 vDst(VGPR465) src0(LITERAL_CONST) const: 0xbdf84c31 V_MOV_B32 vDst(VGPR466) src0(LITERAL_CONST) const: 0x3e4854c9 V_MOV_B32 vDst(VGPR467) src0(LITERAL_CONST) const: 0xbeaa7e45 V_MOV_B32 vDst(VGPR468) src0(LITERAL_CONST) const: 0x3f7fffb7 V_MOV_B32 vDst(VGPR469) src0(LITERAL_CONST) const: 0x3fc90fdb V_MOV_B32 vDst(VGPR470) src0(LITERAL_CONST) const: 0x40490fdb V_ADD_F32 vDst(VGPR471) src0(VGPR462) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR472) src0(VGPR461) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_MAX_F32 vDst(VGPR473) src0(VGPR471) src1(VGPR472) // VOP2 V_MIN_F32 vDst(VGPR474) src0(VGPR471) src1(VGPR472) // VOP2 V_RCP_F32 vDst(VGPR473) src0(VGPR473) V_MUL_F32 vDst(VGPR473) src0(VGPR473) src1(VGPR474) // VOP2 V_MUL_F32 vDst(VGPR474) src0(VGPR473) src1(VGPR473) // VOP2 V_MAD_F32 vDst(VGPR475) src0(VGPR463) src1(VGPR474) src2(VGPR464) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR465) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR466) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR467) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR468) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR473) // VOP2 V_CMP_GT_F32 src0(VGPR472) src1(VGPR471) # CF Block: Merge: .lbl21 S_MOV_B64 sDst(SGPR198) src0(EXEC) # CF Block: Cond Branch: true: .lbl22, false: .lbl21 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl21 S_BRANCH ??? .lbl22 Label: .lbl22 V_SUB_F32 vDst(VGPR475) src0(VGPR469) src1(VGPR475) // VOP2 S_BRANCH ??? .lbl21 Label: .lbl21 V_CMP_GT_F32 src0(0) src1(VGPR462) # CF Block: Merge: .lbl23 S_MOV_B64 sDst(SGPR200) src0(EXEC) # CF Block: Cond Branch: true: .lbl24, false: .lbl23 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl23 S_BRANCH ??? .lbl24 Label: .lbl24 V_SUB_F32 vDst(VGPR475) src0(VGPR470) src1(VGPR475) // VOP2 S_BRANCH ??? .lbl23 Label: .lbl23 V_CMP_GT_F32 src0(0) src1(VGPR461) # CF Block: Merge: .lbl25 S_MOV_B64 sDst(SGPR202) src0(EXEC) # CF Block: Cond Branch: true: .lbl26, false: .lbl25 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl25 S_BRANCH ??? .lbl26 Label: .lbl26 V_SUB_F32 vDst(VGPR475) src0(0) src1(VGPR475) // VOP2 S_BRANCH ??? .lbl25 Label: .lbl25 # 539: OpAccessChain: Float*: no[1] # 540: OpLoad: Float: tmp540 << no[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR476) src0(VGPR1) # 541: OpExtInst(Asin): Float: tmp541 << tmp540 V_MOV_B32 vDst(VGPR477) src0(LITERAL_CONST) const: 0xbc996e30 V_MOV_B32 vDst(VGPR478) src0(LITERAL_CONST) const: 0x3d981627 V_MOV_B32 vDst(VGPR479) src0(LITERAL_CONST) const: 0xbe593484 V_MOV_B32 vDst(VGPR480) src0(LITERAL_CONST) const: 0x3fc90da4 V_MOV_B32 vDst(VGPR481) src0(LITERAL_CONST) const: 0x3fc90fdb V_ADD_F32 vDst(VGPR482) src0(VGPR476) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR483) src0(VGPR477) src1(VGPR482) src2(VGPR478) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR483) src0(VGPR482) src1(VGPR483) src2(VGPR479) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR483) src0(VGPR482) src1(VGPR483) src2(VGPR480) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUB_F32 vDst(VGPR482) src0(1_0_F) src1(VGPR482) // VOP2 V_SQRT_F32 vDst(VGPR482) src0(VGPR482) V_MAD_F32 vDst(VGPR483) src0(VGPR482) src1(VGPR483) src2(VGPR481) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_CMP_GT_F32 src0(0) src1(VGPR476) # CF Block: Merge: .lbl27 S_MOV_B64 sDst(SGPR204) src0(EXEC) # CF Block: Cond Branch: true: .lbl28, false: .lbl27 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl27 S_BRANCH ??? .lbl28 Label: .lbl28 V_MUL_F32 vDst(VGPR483) src0(M1_0_F) src1(VGPR483) // VOP2 S_BRANCH ??? .lbl27 Label: .lbl27 # 542: OpCompositeConstruct: FloatVector2: tmp542 << tmp538, tmp541 V_MOV_B32 vDst(VGPR484) src0(VGPR475) V_MOV_B32 vDst(VGPR485) src0(VGPR483) # 543: OpVectorTimesScalar: FloatVector2: tmp543 << tmp542, const511 V_MOV_B32 vDst(VGPR488) src0(LITERAL_CONST) const: 0x3f400000 V_MUL_F32 vDst(VGPR486) src0(VGPR488) src1(VGPR484) // VOP2 V_MUL_F32 vDst(VGPR487) src0(VGPR488) src1(VGPR485) // VOP2 # OpStore: : tmp543 >> param544 V_MOV_B32 vDst(VGPR438) src0(VGPR486) V_MOV_B32 vDst(VGPR439) src0(VGPR487) # OpStore: : tmp532 >> param545 V_MOV_B32 vDst(VGPR440) src0(VGPR460) # 547: OpFunctionCall: Float: sprinkles(vf2;f1;(param544, param545) S_ADD_U32 sDst(SGPR181) src0(LITERAL_CONST) src1(0) const: 0x1b6 # VGPR[438:439] S_ADD_U32 sDst(SGPR182) src0(LITERAL_CONST) src1(0) const: 0x1b8 # VGPR440 S_MOV_B64 sDst(SGPR206) src0(EXEC) S_MOV_B32 sDst(SGPR180) src0(LITERAL_CONST) const: 0x1e9 # VGPR489 # Indirect branch to sprinkles(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR178) src0(SGPR178) S_ADD_U32 sDst(SGPR178) src0(SGPR178) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR179) src0(SGPR179) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR178) src0(SGPR178) S_MOV_B64 sDst(EXEC) src0(SGPR206) # .lbl29 # 550: OpLoad: FloatVector3: tmp550 << vo S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR194) const: 0x0 V_MOVRELS_B32 vDst(VGPR490) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR491) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR492) src0(VGPR2) # 551: OpVectorShuffle: FloatVector2: tmp551 << tmp550, tmp550, 0, 2 V_MOV_B32 vDst(VGPR493) src0(VGPR490) V_MOV_B32 vDst(VGPR494) src0(VGPR492) # OpStore: : tmp551 >> param549 V_MOV_B32 vDst(VGPR441) src0(VGPR493) V_MOV_B32 vDst(VGPR442) src0(VGPR494) # OpStore: : tmp532 >> param552 V_MOV_B32 vDst(VGPR443) src0(VGPR460) # 554: OpFunctionCall: Float: sprinkles(vf2;f1;(param549, param552) S_ADD_U32 sDst(SGPR181) src0(LITERAL_CONST) src1(0) const: 0x1b9 # VGPR[441:442] S_ADD_U32 sDst(SGPR182) src0(LITERAL_CONST) src1(0) const: 0x1bb # VGPR443 S_MOV_B64 sDst(SGPR208) src0(EXEC) S_MOV_B32 sDst(SGPR180) src0(LITERAL_CONST) const: 0x1ef # VGPR495 # Indirect branch to sprinkles(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR178) src0(SGPR178) S_ADD_U32 sDst(SGPR178) src0(SGPR178) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR179) src0(SGPR179) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR178) src0(SGPR178) S_MOV_B64 sDst(EXEC) src0(SGPR208) # .lbl30 # 558: OpAccessChain: Float*: no[1] # 559: OpLoad: Float: tmp559 << no[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR496) src0(VGPR1) # 560: OpExtInst(SmoothStep): Float: tmp560 << const523, const303, tmp559 V_MOV_B32 vDst(VGPR497) src0(LITERAL_CONST) const: 0x3e99999a V_MOV_B32 vDst(VGPR498) src0(0_5_F) V_CMP_GE_F32 src0(VGPR497) src1(VGPR496) # CF Block: Merge: .lbl34 S_MOV_B64 sDst(SGPR210) src0(EXEC) # CF Block: Cond Branch: true: .lbl35, false: .lbl31 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl31 S_BRANCH ??? .lbl35 Label: .lbl35 V_MOV_B32 vDst(VGPR499) src0(0) S_BRANCH ??? .lbl34 Label: .lbl31 V_CMP_LE_F32 src0(VGPR498) src1(VGPR496) # CF Block: Merge: .lbl33 S_MOV_B64 sDst(SGPR212) src0(EXEC) # CF Block: Cond Branch: true: .lbl36, false: .lbl32 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl32 S_BRANCH ??? .lbl36 Label: .lbl36 V_MOV_B32 vDst(VGPR499) src0(1_0_F) S_BRANCH ??? .lbl33 Label: .lbl32 V_SUBREV_F32 vDst(VGPR500) src0(VGPR497) src1(VGPR498) // VOP2 V_RCP_F32 vDst(VGPR500) src0(VGPR500) V_SUBREV_F32 vDst(VGPR499) src0(VGPR497) src1(VGPR496) // VOP2 V_MUL_F32 vDst(VGPR500) src0(VGPR499) src1(VGPR500) // VOP2 V_MAX_F32 vDst(VGPR500) src0(0) src1(VGPR500) // VOP2 V_MIN_F32 vDst(VGPR500) src0(1_0_F) src1(VGPR500) // VOP2 V_MOV_B32 vDst(VGPR499) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR499) src0(2_0_F) src1(VGPR500) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR500) src0(VGPR500) src1(VGPR500) // VOP2 V_MUL_F32 vDst(VGPR499) src0(VGPR500) src1(VGPR499) // VOP2 S_BRANCH ??? .lbl33 Label: .lbl33 S_BRANCH ??? .lbl34 Label: .lbl34 # 561: OpExtInst(FMix): Float: tmp561 << sprinkles(vf2;f1;, sprinkles(vf2;f1;, tmp560 V_SUBREV_F32 vDst(VGPR501) src0(VGPR499) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR501) src0(VGPR489) src1(VGPR501) // VOP2 V_MAD_F32 vDst(VGPR501) src0(VGPR495) src1(VGPR499) src2(VGPR501) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 563: OpAccessChain: Float*: no[1] # 564: OpLoad: Float: tmp564 << no[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR502) src0(VGPR1) # 565: OpFSub: Float: tmp565 << tmp564, const523 V_MOV_B32 vDst(VGPR503) src0(LITERAL_CONST) const: 0x3e99999a V_SUB_F32 vDst(VGPR504) src0(VGPR502) src1(VGPR503) // VOP2 # 566: OpFMul: Float: tmp566 << tmp565, const401 V_MOV_B32 vDst(VGPR505) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR506) src0(VGPR504) src1(VGPR505) // VOP2 # 567: OpExtInst(FClamp): Float: tmp567 << tmp566, const100, const106 V_MOV_B32 vDst(VGPR507) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR508) src0(1_0_F) V_MAX_F32 vDst(VGPR509) src0(VGPR506) src1(VGPR507) // VOP2 V_MIN_F32 vDst(VGPR509) src0(VGPR509) src1(VGPR508) // VOP2 # 571: OpLoad: Float: tmp571 << colour # OpStore: : tmp571 >> param570 V_MOV_B32 vDst(VGPR447) src0(VGPR30) # 572: OpFunctionCall: FloatVector3: gumColour(f1;(param570) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x1bf # VGPR447 S_MOV_B64 sDst(SGPR214) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x1fe # VGPR[510:512] # Indirect branch to gumColour(f1;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR214) # .lbl37 # 574: OpCompositeConstruct: FloatVector3: tmp574 << const573, const573, const573 V_MOV_B32 vDst(VGPR516) src0(LITERAL_CONST) const: 0x3f7ae148 V_MOV_B32 vDst(VGPR513) src0(VGPR516) V_MOV_B32 vDst(VGPR517) src0(LITERAL_CONST) const: 0x3f7ae148 V_MOV_B32 vDst(VGPR514) src0(VGPR517) V_MOV_B32 vDst(VGPR518) src0(LITERAL_CONST) const: 0x3f7ae148 V_MOV_B32 vDst(VGPR515) src0(VGPR518) # 575: OpExtInst(FMix): FloatVector3: tmp575 << const569, gumColour(f1;, tmp574 V_MOV_B32 vDst(VGPR519) src0(0_5_F) V_MOV_B32 vDst(VGPR520) src0(0_5_F) V_MOV_B32 vDst(VGPR521) src0(0_5_F) V_SUBREV_F32 vDst(VGPR522) src0(VGPR513) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR522) src0(VGPR519) src1(VGPR522) // VOP2 V_MAD_F32 vDst(VGPR522) src0(VGPR510) src1(VGPR513) src2(VGPR522) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR523) src0(VGPR514) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR523) src0(VGPR520) src1(VGPR523) // VOP2 V_MAD_F32 vDst(VGPR523) src0(VGPR511) src1(VGPR514) src2(VGPR523) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR524) src0(VGPR515) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR524) src0(VGPR521) src1(VGPR524) // VOP2 V_MAD_F32 vDst(VGPR524) src0(VGPR512) src1(VGPR515) src2(VGPR524) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 577: OpAccessChain: Float*: tc[0] # 578: OpLoad: Float: tmp578 << tc[0] V_MOV_B32 vDst(VGPR525) src0(VGPR24) # 579: OpExtInst(FAbs): Float: tmp579 << tmp578 V_ADD_F32 vDst(VGPR526) src0(VGPR525) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 580: OpFSub: Float: tmp580 << const106, tmp579 V_SUB_F32 vDst(VGPR527) src0(1_0_F) src1(VGPR526) // VOP2 # 581: OpFMul: Float: tmp581 << tmp580, const303 V_MOV_B32 vDst(VGPR528) src0(0_5_F) V_MUL_F32 vDst(VGPR529) src0(VGPR527) src1(VGPR528) // VOP2 # 582: OpExtInst(Pow): Float: tmp582 << tmp581, const489 V_MOV_B32 vDst(VGPR530) src0(LITERAL_CONST) const: 0x3e4ccccd V_LOG_F32 vDst(VGPR531) src0(VGPR529) V_MUL_F32 vDst(VGPR531) src0(VGPR530) src1(VGPR531) // VOP2 V_EXP_F32 vDst(VGPR531) src0(VGPR531) # 583: OpFAdd: Float: tmp583 << const576, tmp582 V_MOV_B32 vDst(VGPR532) src0(LITERAL_CONST) const: 0x3dcccccd V_ADD_F32 vDst(VGPR533) src0(VGPR532) src1(VGPR531) // VOP2 # 584: OpVectorTimesScalar: FloatVector3: tmp584 << tmp575, tmp583 V_MUL_F32 vDst(VGPR534) src0(VGPR533) src1(VGPR522) // VOP2 V_MUL_F32 vDst(VGPR535) src0(VGPR533) src1(VGPR523) // VOP2 V_MUL_F32 vDst(VGPR536) src0(VGPR533) src1(VGPR524) // VOP2 # 588: OpFMul: Float: tmp588 << tmp561, tmp567 V_MUL_F32 vDst(VGPR537) src0(VGPR501) src1(VGPR509) // VOP2 # 589: OpCompositeConstruct: FloatVector3: tmp589 << tmp588, tmp588, tmp588 V_MOV_B32 vDst(VGPR538) src0(VGPR537) V_MOV_B32 vDst(VGPR539) src0(VGPR537) V_MOV_B32 vDst(VGPR540) src0(VGPR537) # 590: OpExtInst(FMix): FloatVector3: tmp590 << tmp584, const585, tmp589 V_MOV_B32 vDst(VGPR541) src0(2_0_F) V_MOV_B32 vDst(VGPR542) src0(2_0_F) V_MOV_B32 vDst(VGPR543) src0(2_0_F) V_SUBREV_F32 vDst(VGPR544) src0(VGPR538) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR544) src0(VGPR534) src1(VGPR544) // VOP2 V_MAD_F32 vDst(VGPR544) src0(VGPR541) src1(VGPR538) src2(VGPR544) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR545) src0(VGPR539) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR545) src0(VGPR535) src1(VGPR545) // VOP2 V_MAD_F32 vDst(VGPR545) src0(VGPR542) src1(VGPR539) src2(VGPR545) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR546) src0(VGPR540) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR546) src0(VGPR536) src1(VGPR546) // VOP2 V_MAD_F32 vDst(VGPR546) src0(VGPR543) src1(VGPR540) src2(VGPR546) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp590 >> param591 V_MOV_B32 vDst(VGPR448) src0(VGPR544) V_MOV_B32 vDst(VGPR449) src0(VGPR545) V_MOV_B32 vDst(VGPR450) src0(VGPR546) # 592: OpFunctionCall: FloatVector3: saturatecol(vf3;(param591) S_ADD_U32 sDst(SGPR155) src0(LITERAL_CONST) src1(0) const: 0x1c0 # VGPR[448:450] S_MOV_B64 sDst(SGPR216) src0(EXEC) S_MOV_B32 sDst(SGPR154) src0(LITERAL_CONST) const: 0x223 # VGPR[547:549] # Indirect branch to saturatecol(vf3;: ??? S_GETPC_B64 sDst(SGPR152) src0(SGPR152) S_ADD_U32 sDst(SGPR152) src0(SGPR152) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR153) src0(SGPR153) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR152) src0(SGPR152) S_MOV_B64 sDst(EXEC) src0(SGPR216) # .lbl38 # OpStore: : saturatecol(vf3; >> tex V_MOV_B32 vDst(VGPR444) src0(VGPR547) V_MOV_B32 vDst(VGPR445) src0(VGPR548) V_MOV_B32 vDst(VGPR446) src0(VGPR549) # 595: OpFSub: Float: tmp595 << const593, tmp532 V_MOV_B32 vDst(VGPR550) src0(LITERAL_CONST) const: 0x3f866666 V_SUB_F32 vDst(VGPR551) src0(VGPR550) src1(VGPR460) // VOP2 # 596: OpLoad: FloatVector3: tmp596 << tex # 597: OpVectorTimesScalar: FloatVector3: tmp597 << tmp596, tmp595 V_MUL_F32 vDst(VGPR552) src0(VGPR551) src1(VGPR444) // VOP2 V_MUL_F32 vDst(VGPR553) src0(VGPR551) src1(VGPR445) // VOP2 V_MUL_F32 vDst(VGPR554) src0(VGPR551) src1(VGPR446) // VOP2 # OpStore: : tmp597 >> tex V_MOV_B32 vDst(VGPR444) src0(VGPR552) V_MOV_B32 vDst(VGPR445) src0(VGPR553) V_MOV_B32 vDst(VGPR446) src0(VGPR554) # 599: OpFSub: Float: tmp599 << const106, tmp532 V_SUB_F32 vDst(VGPR555) src0(1_0_F) src1(VGPR460) // VOP2 # 600: OpExtInst(Pow): Float: tmp600 << tmp599, const349 V_MOV_B32 vDst(VGPR556) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR557) src0(VGPR555) V_MUL_F32 vDst(VGPR557) src0(VGPR556) src1(VGPR557) // VOP2 V_EXP_F32 vDst(VGPR557) src0(VGPR557) # 601: OpCompositeConstruct: FloatVector3: tmp601 << tmp600, tmp600, tmp600 V_MOV_B32 vDst(VGPR558) src0(VGPR557) V_MOV_B32 vDst(VGPR559) src0(VGPR557) V_MOV_B32 vDst(VGPR560) src0(VGPR557) # 603: OpVectorTimesScalar: FloatVector3: tmp603 << tmp601, const602 V_MOV_B32 vDst(VGPR564) src0(LITERAL_CONST) const: 0x3c23d70a V_MUL_F32 vDst(VGPR561) src0(VGPR564) src1(VGPR558) // VOP2 V_MUL_F32 vDst(VGPR562) src0(VGPR564) src1(VGPR559) // VOP2 V_MUL_F32 vDst(VGPR563) src0(VGPR564) src1(VGPR560) // VOP2 # 604: OpLoad: FloatVector3: tmp604 << tex # 605: OpFAdd: FloatVector3: tmp605 << tmp604, tmp603 V_ADD_F32 vDst(VGPR565) src0(VGPR444) src1(VGPR561) // VOP2 V_ADD_F32 vDst(VGPR566) src0(VGPR445) src1(VGPR562) // VOP2 V_ADD_F32 vDst(VGPR567) src0(VGPR446) src1(VGPR563) // VOP2 # OpStore: : tmp605 >> tex V_MOV_B32 vDst(VGPR444) src0(VGPR565) V_MOV_B32 vDst(VGPR445) src0(VGPR566) V_MOV_B32 vDst(VGPR446) src0(VGPR567) # 606: OpLoad: FloatVector3: tmp606 << tex # OpReturnValue: : << tmp606 S_MOV_B32 sDst(M0) src0(SGPR192) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR444) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR445) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR446) S_SETPC_B64 sDst(SGPR190) src0(SGPR190) # Float de(vf3;(FloatVector3* p) Function: Float de(vf3;() S_MOV_B64 sDst(SGPR222) src0(EXEC) # lb70 Label: lb70 # 610: OpAccessChain: Float*: p[1] # 611: OpLoad: Float: tmp611 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR574) src0(VGPR1) # 612: OpFMul: Float: tmp612 << tmp611, const609 V_MOV_B32 vDst(VGPR575) src0(LITERAL_CONST) const: 0x3fa66666 V_MUL_F32 vDst(VGPR576) src0(VGPR574) src1(VGPR575) // VOP2 # 613: OpAccessChain: Float*: p[1] # OpStore: : tmp612 >> p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELD_B32 vDst(VGPR1) src0(VGPR576) # 615: OpLoad: FloatVector3: tmp615 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR577) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR578) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR579) src0(VGPR2) # 616: OpCompositeConstruct: FloatVector3: tmp616 << const109, const109, const109 V_MOV_B32 vDst(VGPR583) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR580) src0(VGPR583) V_MOV_B32 vDst(VGPR584) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR581) src0(VGPR584) V_MOV_B32 vDst(VGPR585) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR582) src0(VGPR585) # 617: OpFDiv: FloatVector3: tmp617 << tmp615, tmp616 V_RCP_F32 vDst(VGPR586) src0(VGPR580) V_RCP_F32 vDst(VGPR587) src0(VGPR581) V_RCP_F32 vDst(VGPR588) src0(VGPR582) V_MUL_F32 vDst(VGPR586) src0(VGPR577) src1(VGPR586) // VOP2 V_MUL_F32 vDst(VGPR587) src0(VGPR578) src1(VGPR587) // VOP2 V_MUL_F32 vDst(VGPR588) src0(VGPR579) src1(VGPR588) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR586) src0(VGPR586) src1(VGPR580) src2(VGPR577) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR587) src0(VGPR587) src1(VGPR581) src2(VGPR578) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR588) src0(VGPR588) src1(VGPR582) src2(VGPR579) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 618: OpExtInst(Floor): FloatVector3: tmp618 << tmp617 V_FLOOR_F32 vDst(VGPR589) src0(VGPR586) V_FLOOR_F32 vDst(VGPR590) src0(VGPR587) V_FLOOR_F32 vDst(VGPR591) src0(VGPR588) # 619: OpAccessChain: Float*: fp[0] # 620: OpCompositeExtract: Float: tmp620 << tmp618, 0 V_MOV_B32 vDst(VGPR592) src0(VGPR589) # 622: OpFMul: Float: tmp622 << tmp620, const621 V_MOV_B32 vDst(VGPR593) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR594) src0(VGPR592) src1(VGPR593) // VOP2 # 623: OpAccessChain: Float*: fp[2] # 624: OpCompositeExtract: Float: tmp624 << tmp618, 2 V_MOV_B32 vDst(VGPR595) src0(VGPR591) # 626: OpFMul: Float: tmp626 << tmp624, const625 V_MOV_B32 vDst(VGPR596) src0(LITERAL_CONST) const: 0x42ce0000 V_MUL_F32 vDst(VGPR597) src0(VGPR595) src1(VGPR596) // VOP2 # 627: OpFSub: Float: tmp627 << tmp622, tmp626 V_SUB_F32 vDst(VGPR598) src0(VGPR594) src1(VGPR597) // VOP2 # 628: OpExtInst(Cos): Float: tmp628 << tmp627 V_MUL_F32 vDst(VGPR599) src0(LITERAL_CONST) src1(VGPR598) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR599) src0(VGPR599) V_COS_F32 vDst(VGPR599) src0(VGPR599) # 629: OpFAdd: Float: tmp629 << tmp628, const576 V_MOV_B32 vDst(VGPR600) src0(LITERAL_CONST) const: 0x3dcccccd V_ADD_F32 vDst(VGPR601) src0(VGPR599) src1(VGPR600) // VOP2 # 630: OpExtInst(Step): Float: tmp630 << const100, tmp629 V_MOV_B32 vDst(VGPR602) src0(LITERAL_CONST) const: 0x00000000 V_CMP_GT_F32 src0(VGPR602) src1(VGPR601) # CF Block: Merge: .lbl40 S_MOV_B64 sDst(SGPR224) src0(EXEC) # CF Block: Cond Branch: true: .lbl41, false: .lbl39 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl39 S_BRANCH ??? .lbl41 Label: .lbl41 V_MOV_B32 vDst(VGPR603) src0(0) S_BRANCH ??? .lbl40 Label: .lbl39 V_MOV_B32 vDst(VGPR603) src0(1_0_F) S_BRANCH ??? .lbl40 Label: .lbl40 # OpStore: : tmp630 >> is_choc V_MOV_B32 vDst(VGPR33) src0(VGPR603) # 632: OpLoad: FloatVector3: tmp632 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR604) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR605) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR606) src0(VGPR2) # 634: OpVectorTimesScalar: FloatVector3: tmp634 << tmp632, const633 V_MOV_B32 vDst(VGPR610) src0(LITERAL_CONST) const: 0x41f00000 V_MUL_F32 vDst(VGPR607) src0(VGPR610) src1(VGPR604) // VOP2 V_MUL_F32 vDst(VGPR608) src0(VGPR610) src1(VGPR605) // VOP2 V_MUL_F32 vDst(VGPR609) src0(VGPR610) src1(VGPR606) // VOP2 # OpStore: : tmp634 >> param635 V_MOV_B32 vDst(VGPR568) src0(VGPR607) V_MOV_B32 vDst(VGPR569) src0(VGPR608) V_MOV_B32 vDst(VGPR570) src0(VGPR609) # 636: OpFunctionCall: Float: smN3(vf3;(param635) S_ADD_U32 sDst(SGPR99) src0(LITERAL_CONST) src1(0) const: 0x238 # VGPR[568:570] S_MOV_B64 sDst(SGPR226) src0(EXEC) S_MOV_B32 sDst(SGPR98) src0(LITERAL_CONST) const: 0x263 # VGPR611 # Indirect branch to smN3(vf3;: ??? S_GETPC_B64 sDst(SGPR96) src0(SGPR96) S_ADD_U32 sDst(SGPR96) src0(SGPR96) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR97) src0(SGPR97) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR96) src0(SGPR96) S_MOV_B64 sDst(EXEC) src0(SGPR226) # .lbl42 # 638: OpFMul: Float: tmp638 << smN3(vf3;, const637 V_MOV_B32 vDst(VGPR612) src0(LITERAL_CONST) const: 0x3a83126f V_MUL_F32 vDst(VGPR613) src0(VGPR611) src1(VGPR612) // VOP2 # 639: OpLoad: Float: tmp639 << is_choc # 640: OpFMul: Float: tmp640 << tmp638, tmp639 V_MUL_F32 vDst(VGPR614) src0(VGPR613) src1(VGPR33) // VOP2 # 641: OpLoad: FloatVector3: tmp641 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR615) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR616) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR617) src0(VGPR2) # 642: OpVectorTimesScalar: FloatVector3: tmp642 << tmp641, const401 V_MOV_B32 vDst(VGPR621) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR618) src0(VGPR621) src1(VGPR615) // VOP2 V_MUL_F32 vDst(VGPR619) src0(VGPR621) src1(VGPR616) // VOP2 V_MUL_F32 vDst(VGPR620) src0(VGPR621) src1(VGPR617) // VOP2 # OpStore: : tmp642 >> param643 V_MOV_B32 vDst(VGPR571) src0(VGPR618) V_MOV_B32 vDst(VGPR572) src0(VGPR619) V_MOV_B32 vDst(VGPR573) src0(VGPR620) # 644: OpFunctionCall: Float: smN3(vf3;(param643) S_ADD_U32 sDst(SGPR99) src0(LITERAL_CONST) src1(0) const: 0x23b # VGPR[571:573] S_MOV_B64 sDst(SGPR228) src0(EXEC) S_MOV_B32 sDst(SGPR98) src0(LITERAL_CONST) const: 0x26e # VGPR622 # Indirect branch to smN3(vf3;: ??? S_GETPC_B64 sDst(SGPR96) src0(SGPR96) S_ADD_U32 sDst(SGPR96) src0(SGPR96) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR97) src0(SGPR97) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR96) src0(SGPR96) S_MOV_B64 sDst(EXEC) src0(SGPR228) # .lbl43 # 645: OpExtInst(FMax): Float: tmp645 << const100, smN3(vf3; V_MOV_B32 vDst(VGPR623) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR624) src0(VGPR623) src1(VGPR622) // VOP2 # 646: OpExtInst(Pow): Float: tmp646 << tmp645, const401 V_MOV_B32 vDst(VGPR625) src0(LITERAL_CONST) const: 0x40a00000 V_LOG_F32 vDst(VGPR626) src0(VGPR624) V_MUL_F32 vDst(VGPR626) src0(VGPR625) src1(VGPR626) // VOP2 V_EXP_F32 vDst(VGPR626) src0(VGPR626) # 648: OpLoad: Float: tmp648 << is_choc # 649: OpFSub: Float: tmp649 << const106, tmp648 V_SUB_F32 vDst(VGPR627) src0(1_0_F) src1(VGPR33) // VOP2 # 650: OpFMul: Float: tmp650 << const647, tmp649 V_MOV_B32 vDst(VGPR628) src0(LITERAL_CONST) const: 0x3d4ccccd V_MUL_F32 vDst(VGPR629) src0(VGPR628) src1(VGPR627) // VOP2 # 651: OpFAdd: Float: tmp651 << const602, tmp650 V_MOV_B32 vDst(VGPR630) src0(LITERAL_CONST) const: 0x3c23d70a V_ADD_F32 vDst(VGPR631) src0(VGPR630) src1(VGPR629) // VOP2 # 652: OpFMul: Float: tmp652 << tmp646, tmp651 V_MUL_F32 vDst(VGPR632) src0(VGPR626) src1(VGPR631) // VOP2 # 653: OpFSub: Float: tmp653 << tmp640, tmp652 V_SUB_F32 vDst(VGPR633) src0(VGPR614) src1(VGPR632) // VOP2 # 654: OpAccessChain: Float*: fp[0] # 655: OpCompositeExtract: Float: tmp655 << tmp618, 0 V_MOV_B32 vDst(VGPR634) src0(VGPR589) # 656: OpAccessChain: Float*: fp[2] # 657: OpCompositeExtract: Float: tmp657 << tmp618, 2 V_MOV_B32 vDst(VGPR635) src0(VGPR591) # 658: OpExtInst(Sin): Float: tmp658 << tmp657 V_MUL_F32 vDst(VGPR636) src0(LITERAL_CONST) src1(VGPR635) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR636) src0(VGPR636) V_SIN_F32 vDst(VGPR636) src0(VGPR636) # 659: OpFMul: Float: tmp659 << tmp658, const109 V_MOV_B32 vDst(VGPR637) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR638) src0(VGPR636) src1(VGPR637) // VOP2 # 660: OpFAdd: Float: tmp660 << tmp655, tmp659 V_ADD_F32 vDst(VGPR639) src0(VGPR634) src1(VGPR638) // VOP2 # 661: OpFMod: Float: tmp661 << tmp660, const377 V_MOV_B32 vDst(VGPR640) src0(4_0_F) V_RCP_F32 vDst(VGPR641) src0(VGPR640) V_MUL_F32 vDst(VGPR641) src0(VGPR639) src1(VGPR641) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR641) src0(VGPR641) src1(VGPR640) src2(VGPR639) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR641) src0(VGPR641) V_MAD_F32 vDst(VGPR641) src0(VGPR640) src1(VGPR641) src2(VGPR639) abs(0) clamp(0) omod(0) neg(1) // VOP3a # OpStore: : tmp661 >> colour V_MOV_B32 vDst(VGPR30) src0(VGPR641) # 662: OpLoad: FloatVector3: tmp662 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR642) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR643) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR644) src0(VGPR2) # 663: OpVectorShuffle: FloatVector2: tmp663 << tmp662, tmp662, 0, 2 V_MOV_B32 vDst(VGPR645) src0(VGPR642) V_MOV_B32 vDst(VGPR646) src0(VGPR644) # 665: OpFMod: FloatVector2: tmp665 << tmp663, const664 V_MOV_B32 vDst(VGPR647) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR648) src0(LITERAL_CONST) const: 0x40400000 V_RCP_F32 vDst(VGPR649) src0(VGPR647) V_MUL_F32 vDst(VGPR649) src0(VGPR645) src1(VGPR649) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR649) src0(VGPR649) src1(VGPR647) src2(VGPR645) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR649) src0(VGPR649) V_RCP_F32 vDst(VGPR650) src0(VGPR648) V_MUL_F32 vDst(VGPR650) src0(VGPR646) src1(VGPR650) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR650) src0(VGPR650) src1(VGPR648) src2(VGPR646) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR650) src0(VGPR650) V_MAD_F32 vDst(VGPR649) src0(VGPR647) src1(VGPR649) src2(VGPR645) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR650) src0(VGPR648) src1(VGPR650) src2(VGPR646) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 668: OpFSub: FloatVector2: tmp668 << tmp665, const667 V_MOV_B32 vDst(VGPR651) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR652) src0(LITERAL_CONST) const: 0x3fc00000 V_SUB_F32 vDst(VGPR653) src0(VGPR649) src1(VGPR651) // VOP2 V_SUB_F32 vDst(VGPR654) src0(VGPR650) src1(VGPR652) // VOP2 # 669: OpLoad: FloatVector3: tmp669 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR655) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR656) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR657) src0(VGPR2) # 670: OpVectorShuffle: FloatVector3: tmp670 << tmp669, tmp668, 3, 1, 4 V_MOV_B32 vDst(VGPR658) src0(VGPR653) V_MOV_B32 vDst(VGPR659) src0(VGPR656) V_MOV_B32 vDst(VGPR660) src0(VGPR654) # OpStore: : tmp670 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR658) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR659) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR660) # 672: OpAccessChain: Float*: fp[2] # 673: OpCompositeExtract: Float: tmp673 << tmp618, 2 V_MOV_B32 vDst(VGPR661) src0(VGPR591) # 675: OpFMul: Float: tmp675 << tmp673, const674 V_MOV_B32 vDst(VGPR662) src0(LITERAL_CONST) const: 0x40e00000 V_MUL_F32 vDst(VGPR663) src0(VGPR661) src1(VGPR662) // VOP2 # 676: OpAccessChain: Float*: fp[0] # 677: OpCompositeExtract: Float: tmp677 << tmp618, 0 V_MOV_B32 vDst(VGPR664) src0(VGPR589) # 679: OpFMul: Float: tmp679 << tmp677, const678 V_MOV_B32 vDst(VGPR665) src0(LITERAL_CONST) const: 0x41100000 V_MUL_F32 vDst(VGPR666) src0(VGPR664) src1(VGPR665) // VOP2 # 680: OpFAdd: Float: tmp680 << tmp675, tmp679 V_ADD_F32 vDst(VGPR667) src0(VGPR663) src1(VGPR666) // VOP2 # 681: OpExtInst(Cos): Float: tmp681 << tmp680 V_MUL_F32 vDst(VGPR668) src0(LITERAL_CONST) src1(VGPR667) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR668) src0(VGPR668) V_COS_F32 vDst(VGPR668) src0(VGPR668) # 682: OpFMul: Float: tmp682 << const303, tmp681 V_MUL_F32 vDst(VGPR669) src0(0_5_F) src1(VGPR668) // VOP2 # 683: OpFAdd: Float: tmp683 << const303, tmp682 V_ADD_F32 vDst(VGPR670) src0(0_5_F) src1(VGPR669) // VOP2 # 684: OpExtInst(FMix): Float: tmp684 << const671, const106, tmp683 V_MOV_B32 vDst(VGPR671) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR672) src0(1_0_F) V_SUBREV_F32 vDst(VGPR673) src0(VGPR670) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR673) src0(VGPR671) src1(VGPR673) // VOP2 V_MAD_F32 vDst(VGPR673) src0(VGPR672) src1(VGPR670) src2(VGPR673) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp684 >> ss V_MOV_B32 vDst(VGPR32) src0(VGPR673) # 686: OpLoad: FloatVector3: tmp686 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR674) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR675) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR676) src0(VGPR2) # 687: OpExtInst(Length): Float: tmp687 << tmp686 V_MUL_F32 vDst(VGPR677) src0(VGPR674) src1(VGPR674) // VOP2 V_MAC_F32 vDst(VGPR677) src0(VGPR675) src1(VGPR675) // VOP2 V_MAC_F32 vDst(VGPR677) src0(VGPR676) src1(VGPR676) // VOP2 V_SQRT_F32 vDst(VGPR677) src0(VGPR677) # 688: OpLoad: Float: tmp688 << ss # 689: OpFSub: Float: tmp689 << tmp687, tmp688 V_SUB_F32 vDst(VGPR678) src0(VGPR677) src1(VGPR32) // VOP2 # 691: OpAccessChain: Float*: p[1] # 692: OpLoad: Float: tmp692 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR679) src0(VGPR1) # 693: OpFNegate: Float: tmp693 << tmp692 V_MUL_F32 vDst(VGPR680) src0(M1_0_F) src1(VGPR679) // VOP2 # 696: OpExtInst(FMax): Float: tmp696 << const100, tmp689 V_MOV_B32 vDst(VGPR681) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR682) src0(VGPR681) src1(VGPR678) // VOP2 # 698: OpExtInst(FMax): Float: tmp698 << const100, tmp693 V_MOV_B32 vDst(VGPR683) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR684) src0(VGPR683) src1(VGPR680) // VOP2 # 699: OpCompositeConstruct: FloatVector2: tmp699 << tmp696, tmp698 V_MOV_B32 vDst(VGPR685) src0(VGPR682) V_MOV_B32 vDst(VGPR686) src0(VGPR684) # 700: OpExtInst(Length): Float: tmp700 << tmp699 V_MUL_F32 vDst(VGPR687) src0(VGPR685) src1(VGPR685) // VOP2 V_MAC_F32 vDst(VGPR687) src0(VGPR686) src1(VGPR686) // VOP2 V_SQRT_F32 vDst(VGPR687) src0(VGPR687) # 701: OpFSub: Float: tmp701 << tmp700, const576 V_MOV_B32 vDst(VGPR688) src0(LITERAL_CONST) const: 0x3dcccccd V_SUB_F32 vDst(VGPR689) src0(VGPR687) src1(VGPR688) // VOP2 # 703: OpFAdd: Float: tmp703 << tmp701, tmp653 V_ADD_F32 vDst(VGPR690) src0(VGPR689) src1(VGPR633) // VOP2 # 705: OpFMul: Float: tmp705 << tmp703, const704 V_MOV_B32 vDst(VGPR691) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR692) src0(VGPR690) src1(VGPR691) // VOP2 # OpReturnValue: : << tmp705 S_MOV_B32 sDst(M0) src0(SGPR220) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR692) S_SETPC_B64 sDst(SGPR218) src0(SGPR218) # FloatVector3 marble(vf2;(FloatVector2* p) Function: FloatVector3 marble(vf2;() S_MOV_B64 sDst(SGPR234) src0(EXEC) # lb74 Label: lb74 # 709: OpAccessChain: Float*: p[0] # 710: OpLoad: Float: tmp710 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR705) src0(VGPR0) # 711: OpFAdd: Float: tmp711 << tmp710, const127 V_MOV_B32 vDst(VGPR706) src0(2_0_F) V_ADD_F32 vDst(VGPR707) src0(VGPR705) src1(VGPR706) // VOP2 # 712: OpAccessChain: Float*: p[0] # OpStore: : tmp711 >> p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR707) # 717: OpLoad: FloatVector2: tmp717 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR708) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR709) src0(VGPR1) # 718: OpExtInst(Floor): FloatVector2: tmp718 << tmp717 V_FLOOR_F32 vDst(VGPR710) src0(VGPR708) V_FLOOR_F32 vDst(VGPR711) src0(VGPR709) # 720: OpLoad: FloatVector2: tmp720 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR712) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR713) src0(VGPR1) # 722: OpFSub: FloatVector2: tmp722 << tmp720, tmp718 V_SUB_F32 vDst(VGPR714) src0(VGPR712) src1(VGPR710) // VOP2 V_SUB_F32 vDst(VGPR715) src0(VGPR713) src1(VGPR711) // VOP2 # 723: OpFSub: FloatVector2: tmp723 << tmp722, const391 V_MOV_B32 vDst(VGPR716) src0(0_5_F) V_MOV_B32 vDst(VGPR717) src0(0_5_F) V_SUB_F32 vDst(VGPR718) src0(VGPR714) src1(VGPR716) // VOP2 V_SUB_F32 vDst(VGPR719) src0(VGPR715) src1(VGPR717) // VOP2 # 725: OpAccessChain: Float*: c1[0] # 726: OpCompositeExtract: Float: tmp726 << tmp723, 0 V_MOV_B32 vDst(VGPR720) src0(VGPR718) # 727: OpVectorTimesScalar: FloatVector2: tmp727 << const342, tmp726 V_MOV_B32 vDst(VGPR723) src0(1_0_F) V_MOV_B32 vDst(VGPR724) src0(1_0_F) V_MUL_F32 vDst(VGPR721) src0(VGPR720) src1(VGPR723) // VOP2 V_MUL_F32 vDst(VGPR722) src0(VGPR720) src1(VGPR724) // VOP2 # 728: OpAccessChain: Float*: c1[1] # 729: OpCompositeExtract: Float: tmp729 << tmp723, 1 V_MOV_B32 vDst(VGPR725) src0(VGPR719) # 731: OpVectorTimesScalar: FloatVector2: tmp731 << const730, tmp729 V_MOV_B32 vDst(VGPR728) src0(1_0_F) V_MOV_B32 vDst(VGPR729) src0(M1_0_F) V_MUL_F32 vDst(VGPR726) src0(VGPR725) src1(VGPR728) // VOP2 V_MUL_F32 vDst(VGPR727) src0(VGPR725) src1(VGPR729) // VOP2 # 732: OpFAdd: FloatVector2: tmp732 << tmp727, tmp731 V_ADD_F32 vDst(VGPR730) src0(VGPR721) src1(VGPR726) // VOP2 V_ADD_F32 vDst(VGPR731) src0(VGPR722) src1(VGPR727) // VOP2 # 733: OpVectorTimesScalar: FloatVector2: tmp733 << tmp732, const704 V_MOV_B32 vDst(VGPR734) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR732) src0(VGPR734) src1(VGPR730) // VOP2 V_MUL_F32 vDst(VGPR733) src0(VGPR734) src1(VGPR731) // VOP2 # 736: OpLoad: FloatVector2: tmp736 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR735) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR736) src0(VGPR1) # 737: OpCompositeExtract: Float: tmp737 << tmp736, 0 V_MOV_B32 vDst(VGPR737) src0(VGPR735) # 738: OpCompositeExtract: Float: tmp738 << tmp736, 1 V_MOV_B32 vDst(VGPR738) src0(VGPR736) # 739: OpCompositeConstruct: FloatVector3: tmp739 << tmp737, tmp738, const100 V_MOV_B32 vDst(VGPR739) src0(VGPR737) V_MOV_B32 vDst(VGPR740) src0(VGPR738) V_MOV_B32 vDst(VGPR742) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR741) src0(VGPR742) # OpStore: : tmp739 >> param740 V_MOV_B32 vDst(VGPR693) src0(VGPR739) V_MOV_B32 vDst(VGPR694) src0(VGPR740) V_MOV_B32 vDst(VGPR695) src0(VGPR741) # 741: OpFunctionCall: Float: fbm3(vf3;(param740) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x2b5 # VGPR[693:695] S_MOV_B64 sDst(SGPR236) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x2e7 # VGPR743 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR236) # .lbl44 # 742: OpFMul: Float: tmp742 << fbm3(vf3;, const303 V_MOV_B32 vDst(VGPR744) src0(0_5_F) V_MUL_F32 vDst(VGPR745) src0(VGPR743) src1(VGPR744) // VOP2 # 743: OpExtInst(FMax): Float: tmp743 << const100, tmp742 V_MOV_B32 vDst(VGPR746) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR747) src0(VGPR746) src1(VGPR745) // VOP2 # 744: OpCompositeConstruct: FloatVector3: tmp744 << tmp743, tmp743, tmp743 V_MOV_B32 vDst(VGPR748) src0(VGPR747) V_MOV_B32 vDst(VGPR749) src0(VGPR747) V_MOV_B32 vDst(VGPR750) src0(VGPR747) # 745: OpCompositeConstruct: FloatVector3: tmp745 << const511, const511, const511 V_MOV_B32 vDst(VGPR754) src0(LITERAL_CONST) const: 0x3f400000 V_MOV_B32 vDst(VGPR751) src0(VGPR754) V_MOV_B32 vDst(VGPR755) src0(LITERAL_CONST) const: 0x3f400000 V_MOV_B32 vDst(VGPR752) src0(VGPR755) V_MOV_B32 vDst(VGPR756) src0(LITERAL_CONST) const: 0x3f400000 V_MOV_B32 vDst(VGPR753) src0(VGPR756) # 746: OpExtInst(FMix): FloatVector3: tmp746 << const735, tmp744, tmp745 V_MOV_B32 vDst(VGPR757) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR758) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR759) src0(LITERAL_CONST) const: 0x3d4ccccd V_SUBREV_F32 vDst(VGPR760) src0(VGPR751) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR760) src0(VGPR757) src1(VGPR760) // VOP2 V_MAD_F32 vDst(VGPR760) src0(VGPR748) src1(VGPR751) src2(VGPR760) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR761) src0(VGPR752) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR761) src0(VGPR758) src1(VGPR761) // VOP2 V_MAD_F32 vDst(VGPR761) src0(VGPR749) src1(VGPR752) src2(VGPR761) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR762) src0(VGPR753) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR762) src0(VGPR759) src1(VGPR762) // VOP2 V_MAD_F32 vDst(VGPR762) src0(VGPR750) src1(VGPR753) src2(VGPR762) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 754: OpVectorTimesScalar: FloatVector2: tmp754 << tmp718, const127 V_MOV_B32 vDst(VGPR765) src0(2_0_F) V_MUL_F32 vDst(VGPR763) src0(VGPR765) src1(VGPR710) // VOP2 V_MUL_F32 vDst(VGPR764) src0(VGPR765) src1(VGPR711) // VOP2 # 755: OpLoad: FloatVector2: tmp755 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR766) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR767) src0(VGPR1) # 756: OpVectorTimesScalar: FloatVector2: tmp756 << tmp755, const106 V_MOV_B32 vDst(VGPR770) src0(1_0_F) V_MUL_F32 vDst(VGPR768) src0(VGPR770) src1(VGPR766) // VOP2 V_MUL_F32 vDst(VGPR769) src0(VGPR770) src1(VGPR767) // VOP2 # 757: OpFAdd: FloatVector2: tmp757 << tmp754, tmp756 V_ADD_F32 vDst(VGPR771) src0(VGPR763) src1(VGPR768) // VOP2 V_ADD_F32 vDst(VGPR772) src0(VGPR764) src1(VGPR769) // VOP2 # 758: OpLoad: FloatVector2: tmp758 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR773) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR774) src0(VGPR1) # 759: OpVectorShuffle: FloatVector2: tmp759 << tmp758, tmp758, 1, 0 V_MOV_B32 vDst(VGPR775) src0(VGPR774) V_MOV_B32 vDst(VGPR776) src0(VGPR773) # 760: OpVectorTimesScalar: FloatVector2: tmp760 << tmp759, const127 V_MOV_B32 vDst(VGPR779) src0(2_0_F) V_MUL_F32 vDst(VGPR777) src0(VGPR779) src1(VGPR775) // VOP2 V_MUL_F32 vDst(VGPR778) src0(VGPR779) src1(VGPR776) // VOP2 # 761: OpExtInst(Cos): FloatVector2: tmp761 << tmp760 V_MUL_F32 vDst(VGPR780) src0(LITERAL_CONST) src1(VGPR777) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR780) src0(VGPR780) V_MUL_F32 vDst(VGPR781) src0(LITERAL_CONST) src1(VGPR778) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR781) src0(VGPR781) V_COS_F32 vDst(VGPR780) src0(VGPR780) V_COS_F32 vDst(VGPR781) src0(VGPR781) # 762: OpVectorTimesScalar: FloatVector2: tmp762 << tmp761, const748 V_MOV_B32 vDst(VGPR784) src0(LITERAL_CONST) const: 0x3ecccccd V_MUL_F32 vDst(VGPR782) src0(VGPR784) src1(VGPR780) // VOP2 V_MUL_F32 vDst(VGPR783) src0(VGPR784) src1(VGPR781) // VOP2 # 763: OpFAdd: FloatVector2: tmp763 << tmp757, tmp762 V_ADD_F32 vDst(VGPR785) src0(VGPR771) src1(VGPR782) // VOP2 V_ADD_F32 vDst(VGPR786) src0(VGPR772) src1(VGPR783) // VOP2 # 764: OpCompositeExtract: Float: tmp764 << tmp763, 0 V_MOV_B32 vDst(VGPR787) src0(VGPR785) # 765: OpCompositeExtract: Float: tmp765 << tmp763, 1 V_MOV_B32 vDst(VGPR788) src0(VGPR786) # 766: OpCompositeConstruct: FloatVector3: tmp766 << tmp764, tmp765, const100 V_MOV_B32 vDst(VGPR789) src0(VGPR787) V_MOV_B32 vDst(VGPR790) src0(VGPR788) V_MOV_B32 vDst(VGPR792) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR791) src0(VGPR792) # OpStore: : tmp766 >> param767 V_MOV_B32 vDst(VGPR696) src0(VGPR789) V_MOV_B32 vDst(VGPR697) src0(VGPR790) V_MOV_B32 vDst(VGPR698) src0(VGPR791) # 768: OpFunctionCall: Float: fbm3(vf3;(param767) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x2b8 # VGPR[696:698] S_MOV_B64 sDst(SGPR238) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x319 # VGPR793 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR238) # .lbl45 # 769: OpFAdd: Float: tmp769 << const303, fbm3(vf3; V_ADD_F32 vDst(VGPR794) src0(0_5_F) src1(VGPR793) // VOP2 # 770: OpExtInst(SmoothStep): Float: tmp770 << const748, const151, tmp769 V_MOV_B32 vDst(VGPR795) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR796) src0(LITERAL_CONST) const: 0x3f4ccccd V_CMP_GE_F32 src0(VGPR795) src1(VGPR794) # CF Block: Merge: .lbl49 S_MOV_B64 sDst(SGPR240) src0(EXEC) # CF Block: Cond Branch: true: .lbl50, false: .lbl46 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl46 S_BRANCH ??? .lbl50 Label: .lbl50 V_MOV_B32 vDst(VGPR797) src0(0) S_BRANCH ??? .lbl49 Label: .lbl46 V_CMP_LE_F32 src0(VGPR796) src1(VGPR794) # CF Block: Merge: .lbl48 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl51, false: .lbl47 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl47 S_BRANCH ??? .lbl51 Label: .lbl51 V_MOV_B32 vDst(VGPR797) src0(1_0_F) S_BRANCH ??? .lbl48 Label: .lbl47 V_SUBREV_F32 vDst(VGPR798) src0(VGPR795) src1(VGPR796) // VOP2 V_RCP_F32 vDst(VGPR798) src0(VGPR798) V_SUBREV_F32 vDst(VGPR797) src0(VGPR795) src1(VGPR794) // VOP2 V_MUL_F32 vDst(VGPR798) src0(VGPR797) src1(VGPR798) // VOP2 V_MAX_F32 vDst(VGPR798) src0(0) src1(VGPR798) // VOP2 V_MIN_F32 vDst(VGPR798) src0(1_0_F) src1(VGPR798) // VOP2 V_MOV_B32 vDst(VGPR797) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR797) src0(2_0_F) src1(VGPR798) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR798) src0(VGPR798) src1(VGPR798) // VOP2 V_MUL_F32 vDst(VGPR797) src0(VGPR798) src1(VGPR797) // VOP2 S_BRANCH ??? .lbl48 Label: .lbl48 S_BRANCH ??? .lbl49 Label: .lbl49 # 771: OpFSub: Float: tmp771 << const106, tmp770 V_SUB_F32 vDst(VGPR799) src0(1_0_F) src1(VGPR797) // VOP2 # 772: OpCompositeConstruct: FloatVector3: tmp772 << tmp771, tmp771, tmp771 V_MOV_B32 vDst(VGPR800) src0(VGPR799) V_MOV_B32 vDst(VGPR801) src0(VGPR799) V_MOV_B32 vDst(VGPR802) src0(VGPR799) # 773: OpExtInst(FMix): FloatVector3: tmp773 << const750, const752, tmp772 V_MOV_B32 vDst(VGPR803) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR804) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR805) src0(LITERAL_CONST) const: 0x3e75c28f V_MOV_B32 vDst(VGPR806) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR807) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR808) src0(LITERAL_CONST) const: 0x3f0f5c29 V_SUBREV_F32 vDst(VGPR809) src0(VGPR800) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR809) src0(VGPR803) src1(VGPR809) // VOP2 V_MAD_F32 vDst(VGPR809) src0(VGPR806) src1(VGPR800) src2(VGPR809) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR810) src0(VGPR801) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR810) src0(VGPR804) src1(VGPR810) // VOP2 V_MAD_F32 vDst(VGPR810) src0(VGPR807) src1(VGPR801) src2(VGPR810) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR811) src0(VGPR802) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR811) src0(VGPR805) src1(VGPR811) // VOP2 V_MAD_F32 vDst(VGPR811) src0(VGPR808) src1(VGPR802) src2(VGPR811) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 774: OpLoad: FloatVector2: tmp774 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR812) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR813) src0(VGPR1) # 775: OpVectorTimesScalar: FloatVector2: tmp775 << tmp774, const671 V_MOV_B32 vDst(VGPR816) src0(LITERAL_CONST) const: 0x3f333333 V_MUL_F32 vDst(VGPR814) src0(VGPR816) src1(VGPR812) // VOP2 V_MUL_F32 vDst(VGPR815) src0(VGPR816) src1(VGPR813) // VOP2 # 776: OpCompositeExtract: Float: tmp776 << tmp775, 0 V_MOV_B32 vDst(VGPR817) src0(VGPR814) # 777: OpCompositeExtract: Float: tmp777 << tmp775, 1 V_MOV_B32 vDst(VGPR818) src0(VGPR815) # 778: OpCompositeConstruct: FloatVector3: tmp778 << tmp776, tmp777, const100 V_MOV_B32 vDst(VGPR819) src0(VGPR817) V_MOV_B32 vDst(VGPR820) src0(VGPR818) V_MOV_B32 vDst(VGPR822) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR821) src0(VGPR822) # OpStore: : tmp778 >> param779 V_MOV_B32 vDst(VGPR699) src0(VGPR819) V_MOV_B32 vDst(VGPR700) src0(VGPR820) V_MOV_B32 vDst(VGPR701) src0(VGPR821) # 780: OpFunctionCall: Float: fbm3(vf3;(param779) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x2bb # VGPR[699:701] S_MOV_B64 sDst(SGPR244) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x337 # VGPR823 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR244) # .lbl52 # 781: OpFMul: Float: tmp781 << fbm3(vf3;, const106 V_MOV_B32 vDst(VGPR824) src0(1_0_F) V_MUL_F32 vDst(VGPR825) src0(VGPR823) src1(VGPR824) // VOP2 # 782: OpExtInst(FMax): Float: tmp782 << const100, tmp781 V_MOV_B32 vDst(VGPR826) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR827) src0(VGPR826) src1(VGPR825) // VOP2 # 783: OpCompositeConstruct: FloatVector3: tmp783 << tmp782, tmp782, tmp782 V_MOV_B32 vDst(VGPR828) src0(VGPR827) V_MOV_B32 vDst(VGPR829) src0(VGPR827) V_MOV_B32 vDst(VGPR830) src0(VGPR827) # 784: OpFAdd: FloatVector3: tmp784 << tmp773, tmp783 V_ADD_F32 vDst(VGPR831) src0(VGPR809) src1(VGPR828) // VOP2 V_ADD_F32 vDst(VGPR832) src0(VGPR810) src1(VGPR829) // VOP2 V_ADD_F32 vDst(VGPR833) src0(VGPR811) src1(VGPR830) // VOP2 # 785: OpLoad: FloatVector2: tmp785 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR834) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR835) src0(VGPR1) # 786: OpFNegate: FloatVector2: tmp786 << tmp785 V_MUL_F32 vDst(VGPR836) src0(M1_0_F) src1(VGPR834) // VOP2 V_MUL_F32 vDst(VGPR837) src0(M1_0_F) src1(VGPR835) // VOP2 # 787: OpCompositeExtract: Float: tmp787 << tmp786, 0 V_MOV_B32 vDst(VGPR838) src0(VGPR836) # 788: OpCompositeExtract: Float: tmp788 << tmp786, 1 V_MOV_B32 vDst(VGPR839) src0(VGPR837) # 789: OpCompositeConstruct: FloatVector3: tmp789 << tmp787, tmp788, const100 V_MOV_B32 vDst(VGPR840) src0(VGPR838) V_MOV_B32 vDst(VGPR841) src0(VGPR839) V_MOV_B32 vDst(VGPR843) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR842) src0(VGPR843) # OpStore: : tmp789 >> param790 V_MOV_B32 vDst(VGPR702) src0(VGPR840) V_MOV_B32 vDst(VGPR703) src0(VGPR841) V_MOV_B32 vDst(VGPR704) src0(VGPR842) # 791: OpFunctionCall: Float: fbm3(vf3;(param790) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x2be # VGPR[702:704] S_MOV_B64 sDst(SGPR246) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x34c # VGPR844 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR246) # .lbl53 # 792: OpExtInst(SmoothStep): Float: tmp792 << const489, const523, fbm3(vf3; V_MOV_B32 vDst(VGPR845) src0(LITERAL_CONST) const: 0x3e4ccccd V_MOV_B32 vDst(VGPR846) src0(LITERAL_CONST) const: 0x3e99999a V_CMP_GE_F32 src0(VGPR845) src1(VGPR844) # CF Block: Merge: .lbl57 S_MOV_B64 sDst(SGPR248) src0(EXEC) # CF Block: Cond Branch: true: .lbl58, false: .lbl54 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl54 S_BRANCH ??? .lbl58 Label: .lbl58 V_MOV_B32 vDst(VGPR847) src0(0) S_BRANCH ??? .lbl57 Label: .lbl54 V_CMP_LE_F32 src0(VGPR846) src1(VGPR844) # CF Block: Merge: .lbl56 S_MOV_B64 sDst(SGPR250) src0(EXEC) # CF Block: Cond Branch: true: .lbl59, false: .lbl55 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl55 S_BRANCH ??? .lbl59 Label: .lbl59 V_MOV_B32 vDst(VGPR847) src0(1_0_F) S_BRANCH ??? .lbl56 Label: .lbl55 V_SUBREV_F32 vDst(VGPR848) src0(VGPR845) src1(VGPR846) // VOP2 V_RCP_F32 vDst(VGPR848) src0(VGPR848) V_SUBREV_F32 vDst(VGPR847) src0(VGPR845) src1(VGPR844) // VOP2 V_MUL_F32 vDst(VGPR848) src0(VGPR847) src1(VGPR848) // VOP2 V_MAX_F32 vDst(VGPR848) src0(0) src1(VGPR848) // VOP2 V_MIN_F32 vDst(VGPR848) src0(1_0_F) src1(VGPR848) // VOP2 V_MOV_B32 vDst(VGPR847) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR847) src0(2_0_F) src1(VGPR848) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR848) src0(VGPR848) src1(VGPR848) // VOP2 V_MUL_F32 vDst(VGPR847) src0(VGPR848) src1(VGPR847) // VOP2 S_BRANCH ??? .lbl56 Label: .lbl56 S_BRANCH ??? .lbl57 Label: .lbl57 # 793: OpCompositeConstruct: FloatVector3: tmp793 << tmp792, tmp792, tmp792 V_MOV_B32 vDst(VGPR849) src0(VGPR847) V_MOV_B32 vDst(VGPR850) src0(VGPR847) V_MOV_B32 vDst(VGPR851) src0(VGPR847) # 794: OpVectorTimesScalar: FloatVector3: tmp794 << tmp793, const489 V_MOV_B32 vDst(VGPR855) src0(LITERAL_CONST) const: 0x3e4ccccd V_MUL_F32 vDst(VGPR852) src0(VGPR855) src1(VGPR849) // VOP2 V_MUL_F32 vDst(VGPR853) src0(VGPR855) src1(VGPR850) // VOP2 V_MUL_F32 vDst(VGPR854) src0(VGPR855) src1(VGPR851) // VOP2 # 795: OpFAdd: FloatVector3: tmp795 << tmp784, tmp794 V_ADD_F32 vDst(VGPR856) src0(VGPR831) src1(VGPR852) // VOP2 V_ADD_F32 vDst(VGPR857) src0(VGPR832) src1(VGPR853) // VOP2 V_ADD_F32 vDst(VGPR858) src0(VGPR833) src1(VGPR854) // VOP2 # 798: OpCompositeConstruct: FloatVector3: tmp798 << const303, const303, const303 V_MOV_B32 vDst(VGPR859) src0(0_5_F) V_MOV_B32 vDst(VGPR860) src0(0_5_F) V_MOV_B32 vDst(VGPR861) src0(0_5_F) # 799: OpExtInst(FMix): FloatVector3: tmp799 << tmp795, const735, tmp798 V_MOV_B32 vDst(VGPR862) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR863) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR864) src0(LITERAL_CONST) const: 0x3d4ccccd V_SUBREV_F32 vDst(VGPR865) src0(VGPR859) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR865) src0(VGPR856) src1(VGPR865) // VOP2 V_MAD_F32 vDst(VGPR865) src0(VGPR862) src1(VGPR859) src2(VGPR865) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR866) src0(VGPR860) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR866) src0(VGPR857) src1(VGPR866) // VOP2 V_MAD_F32 vDst(VGPR866) src0(VGPR863) src1(VGPR860) src2(VGPR866) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR867) src0(VGPR861) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR867) src0(VGPR858) src1(VGPR867) // VOP2 V_MAD_F32 vDst(VGPR867) src0(VGPR864) src1(VGPR861) src2(VGPR867) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 802: OpFSub: Float: tmp802 << const303, const714 V_MOV_B32 vDst(VGPR868) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR869) src0(0_5_F) src1(VGPR868) // VOP2 # 803: OpAccessChain: Float*: c1[1] # 804: OpCompositeExtract: Float: tmp804 << tmp723, 1 V_MOV_B32 vDst(VGPR870) src0(VGPR719) # 805: OpExtInst(FAbs): Float: tmp805 << tmp804 V_ADD_F32 vDst(VGPR871) src0(VGPR870) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 806: OpExtInst(SmoothStep): Float: tmp806 << tmp802, const303, tmp805 V_MOV_B32 vDst(VGPR872) src0(0_5_F) V_CMP_GE_F32 src0(VGPR869) src1(VGPR871) # CF Block: Merge: .lbl63 S_MOV_B64 sDst(SGPR252) src0(EXEC) # CF Block: Cond Branch: true: .lbl64, false: .lbl60 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl60 S_BRANCH ??? .lbl64 Label: .lbl64 V_MOV_B32 vDst(VGPR873) src0(0) S_BRANCH ??? .lbl63 Label: .lbl60 V_CMP_LE_F32 src0(VGPR872) src1(VGPR871) # CF Block: Merge: .lbl62 S_MOV_B64 sDst(SGPR254) src0(EXEC) # CF Block: Cond Branch: true: .lbl65, false: .lbl61 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl61 S_BRANCH ??? .lbl65 Label: .lbl65 V_MOV_B32 vDst(VGPR873) src0(1_0_F) S_BRANCH ??? .lbl62 Label: .lbl61 V_SUBREV_F32 vDst(VGPR874) src0(VGPR869) src1(VGPR872) // VOP2 V_RCP_F32 vDst(VGPR874) src0(VGPR874) V_SUBREV_F32 vDst(VGPR873) src0(VGPR869) src1(VGPR871) // VOP2 V_MUL_F32 vDst(VGPR874) src0(VGPR873) src1(VGPR874) // VOP2 V_MAX_F32 vDst(VGPR874) src0(0) src1(VGPR874) // VOP2 V_MIN_F32 vDst(VGPR874) src0(1_0_F) src1(VGPR874) // VOP2 V_MOV_B32 vDst(VGPR873) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR873) src0(2_0_F) src1(VGPR874) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR874) src0(VGPR874) src1(VGPR874) // VOP2 V_MUL_F32 vDst(VGPR873) src0(VGPR874) src1(VGPR873) // VOP2 S_BRANCH ??? .lbl62 Label: .lbl62 S_BRANCH ??? .lbl63 Label: .lbl63 # 808: OpFSub: Float: tmp808 << const303, const714 V_MOV_B32 vDst(VGPR875) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR876) src0(0_5_F) src1(VGPR875) // VOP2 # 809: OpAccessChain: Float*: c1[0] # 810: OpCompositeExtract: Float: tmp810 << tmp723, 0 V_MOV_B32 vDst(VGPR877) src0(VGPR718) # 811: OpExtInst(FAbs): Float: tmp811 << tmp810 V_ADD_F32 vDst(VGPR878) src0(VGPR877) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 812: OpExtInst(SmoothStep): Float: tmp812 << tmp808, const303, tmp811 V_MOV_B32 vDst(VGPR879) src0(0_5_F) V_CMP_GE_F32 src0(VGPR876) src1(VGPR878) # CF Block: Merge: .lbl69 S_MOV_B64 sDst(SGPR256) src0(EXEC) # CF Block: Cond Branch: true: .lbl70, false: .lbl66 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl66 S_BRANCH ??? .lbl70 Label: .lbl70 V_MOV_B32 vDst(VGPR880) src0(0) S_BRANCH ??? .lbl69 Label: .lbl66 V_CMP_LE_F32 src0(VGPR879) src1(VGPR878) # CF Block: Merge: .lbl68 S_MOV_B64 sDst(SGPR258) src0(EXEC) # CF Block: Cond Branch: true: .lbl71, false: .lbl67 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl67 S_BRANCH ??? .lbl71 Label: .lbl71 V_MOV_B32 vDst(VGPR880) src0(1_0_F) S_BRANCH ??? .lbl68 Label: .lbl67 V_SUBREV_F32 vDst(VGPR881) src0(VGPR876) src1(VGPR879) // VOP2 V_RCP_F32 vDst(VGPR881) src0(VGPR881) V_SUBREV_F32 vDst(VGPR880) src0(VGPR876) src1(VGPR878) // VOP2 V_MUL_F32 vDst(VGPR881) src0(VGPR880) src1(VGPR881) // VOP2 V_MAX_F32 vDst(VGPR881) src0(0) src1(VGPR881) // VOP2 V_MIN_F32 vDst(VGPR881) src0(1_0_F) src1(VGPR881) // VOP2 V_MOV_B32 vDst(VGPR880) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR880) src0(2_0_F) src1(VGPR881) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR881) src0(VGPR881) src1(VGPR881) // VOP2 V_MUL_F32 vDst(VGPR880) src0(VGPR881) src1(VGPR880) // VOP2 S_BRANCH ??? .lbl68 Label: .lbl68 S_BRANCH ??? .lbl69 Label: .lbl69 # 813: OpExtInst(FMax): Float: tmp813 << tmp806, tmp812 V_MAX_F32 vDst(VGPR882) src0(VGPR873) src1(VGPR880) // VOP2 # 816: OpFSub: Float: tmp816 << const303, const714 V_MOV_B32 vDst(VGPR883) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR884) src0(0_5_F) src1(VGPR883) // VOP2 # 817: OpAccessChain: Float*: rc1[1] # 818: OpCompositeExtract: Float: tmp818 << tmp733, 1 V_MOV_B32 vDst(VGPR885) src0(VGPR733) # 819: OpExtInst(FAbs): Float: tmp819 << tmp818 V_ADD_F32 vDst(VGPR886) src0(VGPR885) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 820: OpExtInst(SmoothStep): Float: tmp820 << tmp816, const303, tmp819 V_MOV_B32 vDst(VGPR887) src0(0_5_F) V_CMP_GE_F32 src0(VGPR884) src1(VGPR886) # CF Block: Merge: .lbl75 S_MOV_B64 sDst(SGPR260) src0(EXEC) # CF Block: Cond Branch: true: .lbl76, false: .lbl72 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl72 S_BRANCH ??? .lbl76 Label: .lbl76 V_MOV_B32 vDst(VGPR888) src0(0) S_BRANCH ??? .lbl75 Label: .lbl72 V_CMP_LE_F32 src0(VGPR887) src1(VGPR886) # CF Block: Merge: .lbl74 S_MOV_B64 sDst(SGPR262) src0(EXEC) # CF Block: Cond Branch: true: .lbl77, false: .lbl73 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl73 S_BRANCH ??? .lbl77 Label: .lbl77 V_MOV_B32 vDst(VGPR888) src0(1_0_F) S_BRANCH ??? .lbl74 Label: .lbl73 V_SUBREV_F32 vDst(VGPR889) src0(VGPR884) src1(VGPR887) // VOP2 V_RCP_F32 vDst(VGPR889) src0(VGPR889) V_SUBREV_F32 vDst(VGPR888) src0(VGPR884) src1(VGPR886) // VOP2 V_MUL_F32 vDst(VGPR889) src0(VGPR888) src1(VGPR889) // VOP2 V_MAX_F32 vDst(VGPR889) src0(0) src1(VGPR889) // VOP2 V_MIN_F32 vDst(VGPR889) src0(1_0_F) src1(VGPR889) // VOP2 V_MOV_B32 vDst(VGPR888) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR888) src0(2_0_F) src1(VGPR889) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR889) src0(VGPR889) src1(VGPR889) // VOP2 V_MUL_F32 vDst(VGPR888) src0(VGPR889) src1(VGPR888) // VOP2 S_BRANCH ??? .lbl74 Label: .lbl74 S_BRANCH ??? .lbl75 Label: .lbl75 # 822: OpFSub: Float: tmp822 << const303, const714 V_MOV_B32 vDst(VGPR890) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR891) src0(0_5_F) src1(VGPR890) // VOP2 # 823: OpAccessChain: Float*: rc1[0] # 824: OpCompositeExtract: Float: tmp824 << tmp733, 0 V_MOV_B32 vDst(VGPR892) src0(VGPR732) # 825: OpExtInst(FAbs): Float: tmp825 << tmp824 V_ADD_F32 vDst(VGPR893) src0(VGPR892) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 826: OpExtInst(SmoothStep): Float: tmp826 << tmp822, const303, tmp825 V_MOV_B32 vDst(VGPR894) src0(0_5_F) V_CMP_GE_F32 src0(VGPR891) src1(VGPR893) # CF Block: Merge: .lbl81 S_MOV_B64 sDst(SGPR264) src0(EXEC) # CF Block: Cond Branch: true: .lbl82, false: .lbl78 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl78 S_BRANCH ??? .lbl82 Label: .lbl82 V_MOV_B32 vDst(VGPR895) src0(0) S_BRANCH ??? .lbl81 Label: .lbl78 V_CMP_LE_F32 src0(VGPR894) src1(VGPR893) # CF Block: Merge: .lbl80 S_MOV_B64 sDst(SGPR266) src0(EXEC) # CF Block: Cond Branch: true: .lbl83, false: .lbl79 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl79 S_BRANCH ??? .lbl83 Label: .lbl83 V_MOV_B32 vDst(VGPR895) src0(1_0_F) S_BRANCH ??? .lbl80 Label: .lbl79 V_SUBREV_F32 vDst(VGPR896) src0(VGPR891) src1(VGPR894) // VOP2 V_RCP_F32 vDst(VGPR896) src0(VGPR896) V_SUBREV_F32 vDst(VGPR895) src0(VGPR891) src1(VGPR893) // VOP2 V_MUL_F32 vDst(VGPR896) src0(VGPR895) src1(VGPR896) // VOP2 V_MAX_F32 vDst(VGPR896) src0(0) src1(VGPR896) // VOP2 V_MIN_F32 vDst(VGPR896) src0(1_0_F) src1(VGPR896) // VOP2 V_MOV_B32 vDst(VGPR895) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR895) src0(2_0_F) src1(VGPR896) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR896) src0(VGPR896) src1(VGPR896) // VOP2 V_MUL_F32 vDst(VGPR895) src0(VGPR896) src1(VGPR895) // VOP2 S_BRANCH ??? .lbl80 Label: .lbl80 S_BRANCH ??? .lbl81 Label: .lbl81 # 827: OpExtInst(FMax): Float: tmp827 << tmp820, tmp826 V_MAX_F32 vDst(VGPR897) src0(VGPR888) src1(VGPR895) // VOP2 # 832: OpCompositeConstruct: FloatVector3: tmp832 << tmp827, tmp827, tmp827 V_MOV_B32 vDst(VGPR898) src0(VGPR897) V_MOV_B32 vDst(VGPR899) src0(VGPR897) V_MOV_B32 vDst(VGPR900) src0(VGPR897) # 833: OpExtInst(FMix): FloatVector3: tmp833 << tmp799, tmp746, tmp832 V_SUBREV_F32 vDst(VGPR901) src0(VGPR898) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR901) src0(VGPR865) src1(VGPR901) // VOP2 V_MAD_F32 vDst(VGPR901) src0(VGPR760) src1(VGPR898) src2(VGPR901) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR902) src0(VGPR899) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR902) src0(VGPR866) src1(VGPR902) // VOP2 V_MAD_F32 vDst(VGPR902) src0(VGPR761) src1(VGPR899) src2(VGPR902) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR903) src0(VGPR900) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR903) src0(VGPR867) src1(VGPR903) // VOP2 V_MAD_F32 vDst(VGPR903) src0(VGPR762) src1(VGPR900) src2(VGPR903) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 836: OpExtInst(FMax): Float: tmp836 << tmp827, tmp813 V_MAX_F32 vDst(VGPR904) src0(VGPR897) src1(VGPR882) // VOP2 # 837: OpCompositeConstruct: FloatVector3: tmp837 << tmp836, tmp836, tmp836 V_MOV_B32 vDst(VGPR905) src0(VGPR904) V_MOV_B32 vDst(VGPR906) src0(VGPR904) V_MOV_B32 vDst(VGPR907) src0(VGPR904) # 838: OpExtInst(FMix): FloatVector3: tmp838 << tmp795, tmp833, tmp837 V_SUBREV_F32 vDst(VGPR908) src0(VGPR905) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR908) src0(VGPR856) src1(VGPR908) // VOP2 V_MAD_F32 vDst(VGPR908) src0(VGPR901) src1(VGPR905) src2(VGPR908) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR909) src0(VGPR906) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR909) src0(VGPR857) src1(VGPR909) // VOP2 V_MAD_F32 vDst(VGPR909) src0(VGPR902) src1(VGPR906) src2(VGPR909) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR910) src0(VGPR907) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR910) src0(VGPR858) src1(VGPR910) // VOP2 V_MAD_F32 vDst(VGPR910) src0(VGPR903) src1(VGPR907) src2(VGPR910) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 839: OpVectorTimesScalar: FloatVector3: tmp839 << tmp838, const151 V_MOV_B32 vDst(VGPR914) src0(LITERAL_CONST) const: 0x3f4ccccd V_MUL_F32 vDst(VGPR911) src0(VGPR914) src1(VGPR908) // VOP2 V_MUL_F32 vDst(VGPR912) src0(VGPR914) src1(VGPR909) // VOP2 V_MUL_F32 vDst(VGPR913) src0(VGPR914) src1(VGPR910) // VOP2 # OpReturnValue: : << tmp839 S_MOV_B32 sDst(M0) src0(SGPR232) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR911) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR912) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR913) S_SETPC_B64 sDst(SGPR230) src0(SGPR230) # FloatVector3 cameraPos(f1;(Float* t) Function: FloatVector3 cameraPos(f1;() S_MOV_B64 sDst(SGPR272) src0(EXEC) # lb77 Label: lb77 # 842: OpLoad: Float: tmp842 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR271) const: 0x0 V_MOVRELS_B32 vDst(VGPR915) src0(VGPR0) # 843: OpFMul: Float: tmp843 << tmp842, const704 V_MOV_B32 vDst(VGPR916) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR917) src0(VGPR915) src1(VGPR916) // VOP2 # 845: OpLoad: Float: tmp845 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR271) const: 0x0 V_MOVRELS_B32 vDst(VGPR918) src0(VGPR0) # 846: OpFMul: Float: tmp846 << tmp845, const377 V_MOV_B32 vDst(VGPR919) src0(4_0_F) V_MUL_F32 vDst(VGPR920) src0(VGPR918) src1(VGPR919) // VOP2 # 847: OpExtInst(Cos): Float: tmp847 << tmp846 V_MUL_F32 vDst(VGPR921) src0(LITERAL_CONST) src1(VGPR920) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR921) src0(VGPR921) V_COS_F32 vDst(VGPR921) src0(VGPR921) # 849: OpFMul: Float: tmp849 << tmp847, const848 V_MOV_B32 vDst(VGPR922) src0(LITERAL_CONST) const: 0x3cf5c28f V_MUL_F32 vDst(VGPR923) src0(VGPR921) src1(VGPR922) // VOP2 # 850: OpFAdd: Float: tmp850 << const844, tmp849 V_MOV_B32 vDst(VGPR924) src0(LITERAL_CONST) const: 0x40c00000 V_ADD_F32 vDst(VGPR925) src0(VGPR924) src1(VGPR923) // VOP2 # 851: OpCompositeConstruct: FloatVector3: tmp851 << tmp843, tmp850, const100 V_MOV_B32 vDst(VGPR926) src0(VGPR917) V_MOV_B32 vDst(VGPR927) src0(VGPR925) V_MOV_B32 vDst(VGPR929) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR928) src0(VGPR929) # OpReturnValue: : << tmp851 S_MOV_B32 sDst(M0) src0(SGPR270) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR926) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR927) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR928) S_SETPC_B64 sDst(SGPR268) src0(SGPR268) # FloatVector3 targetPos(f1;(Float* ti) Function: FloatVector3 targetPos(f1;() S_MOV_B64 sDst(SGPR278) src0(EXEC) # lb80 Label: lb80 # 855: OpLoad: Float: tmp855 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR277) const: 0x0 V_MOVRELS_B32 vDst(VGPR934) src0(VGPR0) # 856: OpLoad: Float: tmp856 << t_per_target # 857: OpFMul: Float: tmp857 << tmp855, tmp856 V_MUL_F32 vDst(VGPR935) src0(VGPR934) src1(VGPR35) // VOP2 # OpStore: : tmp857 >> param858 V_MOV_B32 vDst(VGPR933) src0(VGPR935) # 859: OpFunctionCall: FloatVector3: cameraPos(f1;(param858) S_ADD_U32 sDst(SGPR271) src0(LITERAL_CONST) src1(0) const: 0x3a5 # VGPR933 S_MOV_B64 sDst(SGPR280) src0(EXEC) S_MOV_B32 sDst(SGPR270) src0(LITERAL_CONST) const: 0x3a8 # VGPR[936:938] # Indirect branch to cameraPos(f1;: ??? S_GETPC_B64 sDst(SGPR268) src0(SGPR268) S_ADD_U32 sDst(SGPR268) src0(SGPR268) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR269) src0(SGPR269) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR268) src0(SGPR268) S_MOV_B64 sDst(EXEC) src0(SGPR280) # .lbl84 # 861: OpFMul: FloatVector3: tmp861 << cameraPos(f1;, const860 V_MOV_B32 vDst(VGPR939) src0(1_0_F) V_MOV_B32 vDst(VGPR940) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR941) src0(LITERAL_CONST) const: 0x00000000 V_MUL_F32 vDst(VGPR942) src0(VGPR936) src1(VGPR939) // VOP2 V_MUL_F32 vDst(VGPR943) src0(VGPR937) src1(VGPR940) // VOP2 V_MUL_F32 vDst(VGPR944) src0(VGPR938) src1(VGPR941) // VOP2 # 862: OpLoad: Float: tmp862 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR277) const: 0x0 V_MOVRELS_B32 vDst(VGPR945) src0(VGPR0) # 864: OpFMul: Float: tmp864 << tmp862, const863 V_MOV_B32 vDst(VGPR946) src0(LITERAL_CONST) const: 0x41a00000 V_MUL_F32 vDst(VGPR947) src0(VGPR945) src1(VGPR946) // VOP2 # 865: OpExtInst(Cos): Float: tmp865 << tmp864 V_MUL_F32 vDst(VGPR948) src0(LITERAL_CONST) src1(VGPR947) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR948) src0(VGPR948) V_COS_F32 vDst(VGPR948) src0(VGPR948) # 866: OpFMul: Float: tmp866 << tmp865, const377 V_MOV_B32 vDst(VGPR949) src0(4_0_F) V_MUL_F32 vDst(VGPR950) src0(VGPR948) src1(VGPR949) // VOP2 # 868: OpLoad: Float: tmp868 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR277) const: 0x0 V_MOVRELS_B32 vDst(VGPR951) src0(VGPR0) # 870: OpFMul: Float: tmp870 << tmp868, const869 V_MOV_B32 vDst(VGPR952) src0(LITERAL_CONST) const: 0x41600000 V_MUL_F32 vDst(VGPR953) src0(VGPR951) src1(VGPR952) // VOP2 # 871: OpExtInst(Cos): Float: tmp871 << tmp870 V_MUL_F32 vDst(VGPR954) src0(LITERAL_CONST) src1(VGPR953) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR954) src0(VGPR954) V_COS_F32 vDst(VGPR954) src0(VGPR954) # 872: OpFMul: Float: tmp872 << tmp871, const109 V_MOV_B32 vDst(VGPR955) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR956) src0(VGPR954) src1(VGPR955) // VOP2 # 873: OpFAdd: Float: tmp873 << const867, tmp872 V_MOV_B32 vDst(VGPR957) src0(LITERAL_CONST) const: 0xc0e00000 V_ADD_F32 vDst(VGPR958) src0(VGPR957) src1(VGPR956) // VOP2 # 874: OpCompositeConstruct: FloatVector3: tmp874 << tmp866, const100, tmp873 V_MOV_B32 vDst(VGPR959) src0(VGPR950) V_MOV_B32 vDst(VGPR962) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR960) src0(VGPR962) V_MOV_B32 vDst(VGPR961) src0(VGPR958) # 875: OpFAdd: FloatVector3: tmp875 << tmp861, tmp874 V_ADD_F32 vDst(VGPR963) src0(VGPR942) src1(VGPR959) // VOP2 V_ADD_F32 vDst(VGPR964) src0(VGPR943) src1(VGPR960) // VOP2 V_ADD_F32 vDst(VGPR965) src0(VGPR944) src1(VGPR961) // VOP2 # OpStore: : tmp875 >> target V_MOV_B32 vDst(VGPR930) src0(VGPR963) V_MOV_B32 vDst(VGPR931) src0(VGPR964) V_MOV_B32 vDst(VGPR932) src0(VGPR965) # 876: OpLoad: FloatVector3: tmp876 << target # 877: OpVectorShuffle: FloatVector2: tmp877 << tmp876, tmp876, 0, 2 V_MOV_B32 vDst(VGPR966) src0(VGPR930) V_MOV_B32 vDst(VGPR967) src0(VGPR932) # 878: OpCompositeConstruct: FloatVector2: tmp878 << const109, const109 V_MOV_B32 vDst(VGPR970) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR968) src0(VGPR970) V_MOV_B32 vDst(VGPR971) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR969) src0(VGPR971) # 879: OpFDiv: FloatVector2: tmp879 << tmp877, tmp878 V_RCP_F32 vDst(VGPR972) src0(VGPR968) V_RCP_F32 vDst(VGPR973) src0(VGPR969) V_MUL_F32 vDst(VGPR972) src0(VGPR966) src1(VGPR972) // VOP2 V_MUL_F32 vDst(VGPR973) src0(VGPR967) src1(VGPR973) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR972) src0(VGPR972) src1(VGPR968) src2(VGPR966) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR973) src0(VGPR973) src1(VGPR969) src2(VGPR967) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 880: OpExtInst(Floor): FloatVector2: tmp880 << tmp879 V_FLOOR_F32 vDst(VGPR974) src0(VGPR972) V_FLOOR_F32 vDst(VGPR975) src0(VGPR973) # 881: OpVectorTimesScalar: FloatVector2: tmp881 << tmp880, const109 V_MOV_B32 vDst(VGPR978) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR976) src0(VGPR978) src1(VGPR974) // VOP2 V_MUL_F32 vDst(VGPR977) src0(VGPR978) src1(VGPR975) // VOP2 # 882: OpFAdd: FloatVector2: tmp882 << tmp881, const667 V_MOV_B32 vDst(VGPR979) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR980) src0(LITERAL_CONST) const: 0x3fc00000 V_ADD_F32 vDst(VGPR981) src0(VGPR976) src1(VGPR979) // VOP2 V_ADD_F32 vDst(VGPR982) src0(VGPR977) src1(VGPR980) // VOP2 # 883: OpLoad: FloatVector3: tmp883 << target # 884: OpVectorShuffle: FloatVector3: tmp884 << tmp883, tmp882, 3, 1, 4 V_MOV_B32 vDst(VGPR983) src0(VGPR981) V_MOV_B32 vDst(VGPR984) src0(VGPR931) V_MOV_B32 vDst(VGPR985) src0(VGPR982) # OpStore: : tmp884 >> target V_MOV_B32 vDst(VGPR930) src0(VGPR983) V_MOV_B32 vDst(VGPR931) src0(VGPR984) V_MOV_B32 vDst(VGPR932) src0(VGPR985) # 885: OpLoad: FloatVector3: tmp885 << target # OpReturnValue: : << tmp885 S_MOV_B32 sDst(M0) src0(SGPR276) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR930) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR931) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR932) S_SETPC_B64 sDst(SGPR274) src0(SGPR274) # Float cameraZoom(f1;(Float* ti) Function: Float cameraZoom(f1;() S_MOV_B64 sDst(SGPR286) src0(EXEC) # lb83 Label: lb83 # 889: OpLoad: Float: tmp889 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR285) const: 0x0 V_MOVRELS_B32 vDst(VGPR986) src0(VGPR0) # 890: OpFMul: Float: tmp890 << tmp889, const633 V_MOV_B32 vDst(VGPR987) src0(LITERAL_CONST) const: 0x41f00000 V_MUL_F32 vDst(VGPR988) src0(VGPR986) src1(VGPR987) // VOP2 # 891: OpExtInst(Cos): Float: tmp891 << tmp890 V_MUL_F32 vDst(VGPR989) src0(LITERAL_CONST) src1(VGPR988) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR989) src0(VGPR989) V_COS_F32 vDst(VGPR989) src0(VGPR989) # 892: OpFMul: Float: tmp892 << const303, tmp891 V_MUL_F32 vDst(VGPR990) src0(0_5_F) src1(VGPR989) // VOP2 # 893: OpFAdd: Float: tmp893 << const303, tmp892 V_ADD_F32 vDst(VGPR991) src0(0_5_F) src1(VGPR990) // VOP2 # 894: OpExtInst(FMix): Float: tmp894 << const109, const888, tmp893 V_MOV_B32 vDst(VGPR992) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR993) src0(LITERAL_CONST) const: 0x40600000 V_SUBREV_F32 vDst(VGPR994) src0(VGPR991) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR994) src0(VGPR992) src1(VGPR994) // VOP2 V_MAD_F32 vDst(VGPR994) src0(VGPR993) src1(VGPR991) src2(VGPR994) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 896: OpFMul: Float: tmp896 << tmp894, const895 V_MOV_B32 vDst(VGPR995) src0(LITERAL_CONST) const: 0x3fb33333 V_MUL_F32 vDst(VGPR996) src0(VGPR994) src1(VGPR995) // VOP2 # OpReturnValue: : << tmp896 S_MOV_B32 sDst(M0) src0(SGPR284) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR996) S_SETPC_B64 sDst(SGPR282) src0(SGPR282) # FloatVector3 trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* t, Float* max_t) Function: FloatVector3 trace(vf3;vf3;f1;f1;(, FloatVector3 cameraZoom(f1;.rd, Float cameraZoom(f1;.t, Float cameraZoom(f1;.max_t) S_MOV_B64 sDst(SGPR296) src0(EXEC) # lb90 Label: lb90 # OpStore: : const471 >> i V_MOV_B32 vDst(VGPR997) src0(0) # OpBranch: to lb900 S_BRANCH ??? lb900 # lb900 Label: lb900 # OpLoopMerge: (merge: lb902, continue: lb903) # CF Block: Merge: lb902, Continue: lb903 S_MOV_B64 sDst(SGPR298) src0(EXEC) S_MOV_B64 sDst(SGPR300) src0(EXEC) S_MOV_B64 sDst(SGPR302) src0(EXEC) Label: lb900Loop # OpBranch: to lb904 S_BRANCH ??? lb904 # lb904 Label: lb904 # 905: OpLoad: Int: tmp905 << i Decorators: RelaxedPrecision # 907: OpSLessThan: Bool: tmp907 << tmp905, const906 V_MOV_B32 vDst(VGPR1031) src0(LITERAL_CONST) const: 0x00000064 V_CMP_LT_I32 dst(SGPR304) src0(VGPR997) src1(VGPR1031) // VOP3a # OpBranchConditional: if(tmp907) then branch to lb901, else branch to lb902 # CF Block: Cond Branch: true: lb901, false: lb902 S_AND_B64 sDst(EXEC) src0(SGPR304) src1(EXEC) S_CBRANCH_EXECZ ??? lb902 S_BRANCH ??? lb901 # lb901 Label: lb901 # 909: OpLoad: FloatVector3: tmp909 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR291) const: 0x0 V_MOVRELS_B32 vDst(VGPR1032) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1033) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1034) src0(VGPR2) # 910: OpLoad: FloatVector3: tmp910 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1035) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1036) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1037) src0(VGPR2) # 911: OpLoad: Float: tmp911 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELS_B32 vDst(VGPR1038) src0(VGPR0) # 912: OpVectorTimesScalar: FloatVector3: tmp912 << tmp910, tmp911 V_MUL_F32 vDst(VGPR1039) src0(VGPR1038) src1(VGPR1035) // VOP2 V_MUL_F32 vDst(VGPR1040) src0(VGPR1038) src1(VGPR1036) // VOP2 V_MUL_F32 vDst(VGPR1041) src0(VGPR1038) src1(VGPR1037) // VOP2 # 913: OpFAdd: FloatVector3: tmp913 << tmp909, tmp912 V_ADD_F32 vDst(VGPR1042) src0(VGPR1032) src1(VGPR1039) // VOP2 V_ADD_F32 vDst(VGPR1043) src0(VGPR1033) src1(VGPR1040) // VOP2 V_ADD_F32 vDst(VGPR1044) src0(VGPR1034) src1(VGPR1041) // VOP2 # OpStore: : tmp913 >> param914 V_MOV_B32 vDst(VGPR998) src0(VGPR1042) V_MOV_B32 vDst(VGPR999) src0(VGPR1043) V_MOV_B32 vDst(VGPR1000) src0(VGPR1044) # 915: OpFunctionCall: Float: de(vf3;(param914) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3e6 # VGPR[998:1000] S_MOV_B64 sDst(SGPR306) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x415 # VGPR1045 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR306) # .lbl85 # 916: OpLoad: Float: tmp916 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELS_B32 vDst(VGPR1046) src0(VGPR0) # 917: OpLoad: Float: tmp917 << max_t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR294) const: 0x0 V_MOVRELS_B32 vDst(VGPR1047) src0(VGPR0) # 918: OpFOrdGreaterThan: Bool: tmp918 << tmp916, tmp917 V_CMP_GT_F32 dst(SGPR308) src0(VGPR1046) src1(VGPR1047) // VOP3a # OpSelectionMerge: (merge: lb920) # CF Block: Merge: lb920 S_MOV_B64 sDst(SGPR310) src0(EXEC) # OpBranchConditional: if(tmp918) then branch to lb919, else branch to lb920 # CF Block: Cond Branch: true: lb919, false: lb920 S_AND_B64 sDst(EXEC) src0(SGPR308) src1(EXEC) S_CBRANCH_EXECZ ??? lb920 S_BRANCH ??? lb919 # lb919 Label: lb919 # OpReturnValue: : << const921 V_MOV_B32 vDst(VGPR1048) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1049) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1050) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR290) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1048) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1049) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1050) S_SETPC_B64 sDst(SGPR288) src0(SGPR288) # lb920 Label: lb920 # 924: OpExtInst(FAbs): Float: tmp924 << de(vf3; V_ADD_F32 vDst(VGPR1051) src0(VGPR1045) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 926: OpFOrdLessThan: Bool: tmp926 << tmp924, const925 V_MOV_B32 vDst(VGPR1052) src0(LITERAL_CONST) const: 0x38d1b717 V_CMP_LT_F32 dst(SGPR312) src0(VGPR1051) src1(VGPR1052) // VOP3a # OpSelectionMerge: (merge: lb928) # CF Block: Merge: lb928 S_MOV_B64 sDst(SGPR314) src0(EXEC) # OpBranchConditional: if(tmp926) then branch to lb927, else branch to lb928 # CF Block: Cond Branch: true: lb927, false: lb928 S_AND_B64 sDst(EXEC) src0(SGPR312) src1(EXEC) S_CBRANCH_EXECZ ??? lb928 S_BRANCH ??? lb927 # lb927 Label: lb927 # OpBranch: to lb902 S_BRANCH ??? lb902 # lb928 Label: lb928 # 930: OpLoad: Float: tmp930 << max_t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR294) const: 0x0 V_MOVRELS_B32 vDst(VGPR1053) src0(VGPR0) # 931: OpFAdd: Float: tmp931 << tmp930, const637 V_MOV_B32 vDst(VGPR1054) src0(LITERAL_CONST) const: 0x3a83126f V_ADD_F32 vDst(VGPR1055) src0(VGPR1053) src1(VGPR1054) // VOP2 # 932: OpLoad: Float: tmp932 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELS_B32 vDst(VGPR1056) src0(VGPR0) # 934: OpFAdd: Float: tmp934 << tmp932, de(vf3; V_ADD_F32 vDst(VGPR1057) src0(VGPR1056) src1(VGPR1045) // VOP2 # 935: OpExtInst(FMin): Float: tmp935 << tmp931, tmp934 V_MIN_F32 vDst(VGPR1058) src0(VGPR1055) src1(VGPR1057) // VOP2 # OpStore: : tmp935 >> t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1058) # OpBranch: to lb903 S_BRANCH ??? lb903 # lb903 Label: lb903 # 936: OpLoad: Int: tmp936 << i Decorators: RelaxedPrecision # 937: OpIAdd: Int: tmp937 << tmp936, const285 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR1059) src0(1_INT) V_ADD_I32 vDst(VGPR1060) src0(VGPR997) src1(VGPR1059) // VOP2 # OpStore: : tmp937 >> i V_MOV_B32 vDst(VGPR997) src0(VGPR1060) # OpBranch: to lb900 S_BRANCH ??? lb900 # lb902 Label: lb902 # 939: OpLoad: FloatVector3: tmp939 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR291) const: 0x0 V_MOVRELS_B32 vDst(VGPR1061) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1062) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1063) src0(VGPR2) # 940: OpLoad: FloatVector3: tmp940 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1064) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1065) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1066) src0(VGPR2) # 941: OpLoad: Float: tmp941 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELS_B32 vDst(VGPR1067) src0(VGPR0) # 942: OpVectorTimesScalar: FloatVector3: tmp942 << tmp940, tmp941 V_MUL_F32 vDst(VGPR1068) src0(VGPR1067) src1(VGPR1064) // VOP2 V_MUL_F32 vDst(VGPR1069) src0(VGPR1067) src1(VGPR1065) // VOP2 V_MUL_F32 vDst(VGPR1070) src0(VGPR1067) src1(VGPR1066) // VOP2 # 943: OpFAdd: FloatVector3: tmp943 << tmp939, tmp942 V_ADD_F32 vDst(VGPR1071) src0(VGPR1061) src1(VGPR1068) // VOP2 V_ADD_F32 vDst(VGPR1072) src0(VGPR1062) src1(VGPR1069) // VOP2 V_ADD_F32 vDst(VGPR1073) src0(VGPR1063) src1(VGPR1070) // VOP2 # OpStore: : const946 >> col V_MOV_B32 vDst(VGPR1074) src0(LITERAL_CONST) const: 0x3ca3d70a V_MOV_B32 vDst(VGPR1075) src0(LITERAL_CONST) const: 0x3c23d70a V_MOV_B32 vDst(VGPR1076) src0(LITERAL_CONST) const: 0x3ba3d70a V_MOV_B32 vDst(VGPR1001) src0(VGPR1074) V_MOV_B32 vDst(VGPR1002) src0(VGPR1075) V_MOV_B32 vDst(VGPR1003) src0(VGPR1076) # OpStore: : tmp943 >> param949 V_MOV_B32 vDst(VGPR1004) src0(VGPR1071) V_MOV_B32 vDst(VGPR1005) src0(VGPR1072) V_MOV_B32 vDst(VGPR1006) src0(VGPR1073) # 951: OpFunctionCall: Float: de(vf3;(param949) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3ec # VGPR[1004:1006] S_MOV_B64 sDst(SGPR316) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x435 # VGPR1077 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR316) # .lbl86 # 955: OpCompositeConstruct: FloatVector3: tmp955 << const637, const100, const100 V_MOV_B32 vDst(VGPR1081) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR1078) src0(VGPR1081) V_MOV_B32 vDst(VGPR1082) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1079) src0(VGPR1082) V_MOV_B32 vDst(VGPR1083) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1080) src0(VGPR1083) # 956: OpFAdd: FloatVector3: tmp956 << tmp943, tmp955 V_ADD_F32 vDst(VGPR1084) src0(VGPR1071) src1(VGPR1078) // VOP2 V_ADD_F32 vDst(VGPR1085) src0(VGPR1072) src1(VGPR1079) // VOP2 V_ADD_F32 vDst(VGPR1086) src0(VGPR1073) src1(VGPR1080) // VOP2 # OpStore: : tmp956 >> param957 V_MOV_B32 vDst(VGPR1007) src0(VGPR1084) V_MOV_B32 vDst(VGPR1008) src0(VGPR1085) V_MOV_B32 vDst(VGPR1009) src0(VGPR1086) # 958: OpFunctionCall: Float: de(vf3;(param957) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3ef # VGPR[1007:1009] S_MOV_B64 sDst(SGPR318) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x43f # VGPR1087 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR318) # .lbl87 # 960: OpFSub: Float: tmp960 << de(vf3;, de(vf3; V_SUB_F32 vDst(VGPR1088) src0(VGPR1087) src1(VGPR1077) // VOP2 # 963: OpCompositeConstruct: FloatVector3: tmp963 << const100, const637, const100 V_MOV_B32 vDst(VGPR1092) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1089) src0(VGPR1092) V_MOV_B32 vDst(VGPR1093) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR1090) src0(VGPR1093) V_MOV_B32 vDst(VGPR1094) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1091) src0(VGPR1094) # 964: OpFAdd: FloatVector3: tmp964 << tmp943, tmp963 V_ADD_F32 vDst(VGPR1095) src0(VGPR1071) src1(VGPR1089) // VOP2 V_ADD_F32 vDst(VGPR1096) src0(VGPR1072) src1(VGPR1090) // VOP2 V_ADD_F32 vDst(VGPR1097) src0(VGPR1073) src1(VGPR1091) // VOP2 # OpStore: : tmp964 >> param965 V_MOV_B32 vDst(VGPR1010) src0(VGPR1095) V_MOV_B32 vDst(VGPR1011) src0(VGPR1096) V_MOV_B32 vDst(VGPR1012) src0(VGPR1097) # 966: OpFunctionCall: Float: de(vf3;(param965) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3f2 # VGPR[1010:1012] S_MOV_B64 sDst(SGPR320) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x44a # VGPR1098 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR320) # .lbl88 # 968: OpFSub: Float: tmp968 << de(vf3;, de(vf3; V_SUB_F32 vDst(VGPR1099) src0(VGPR1098) src1(VGPR1077) // VOP2 # 971: OpCompositeConstruct: FloatVector3: tmp971 << const100, const100, const637 V_MOV_B32 vDst(VGPR1103) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1100) src0(VGPR1103) V_MOV_B32 vDst(VGPR1104) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1101) src0(VGPR1104) V_MOV_B32 vDst(VGPR1105) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR1102) src0(VGPR1105) # 972: OpFAdd: FloatVector3: tmp972 << tmp943, tmp971 V_ADD_F32 vDst(VGPR1106) src0(VGPR1071) src1(VGPR1100) // VOP2 V_ADD_F32 vDst(VGPR1107) src0(VGPR1072) src1(VGPR1101) // VOP2 V_ADD_F32 vDst(VGPR1108) src0(VGPR1073) src1(VGPR1102) // VOP2 # OpStore: : tmp972 >> param973 V_MOV_B32 vDst(VGPR1013) src0(VGPR1106) V_MOV_B32 vDst(VGPR1014) src0(VGPR1107) V_MOV_B32 vDst(VGPR1015) src0(VGPR1108) # 974: OpFunctionCall: Float: de(vf3;(param973) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3f5 # VGPR[1013:1015] S_MOV_B64 sDst(SGPR322) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x455 # VGPR1109 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR322) # .lbl89 # 976: OpFSub: Float: tmp976 << de(vf3;, de(vf3; V_SUB_F32 vDst(VGPR1110) src0(VGPR1109) src1(VGPR1077) // VOP2 # 977: OpCompositeConstruct: FloatVector3: tmp977 << tmp960, tmp968, tmp976 V_MOV_B32 vDst(VGPR1111) src0(VGPR1088) V_MOV_B32 vDst(VGPR1112) src0(VGPR1099) V_MOV_B32 vDst(VGPR1113) src0(VGPR1110) # 978: OpExtInst(Normalize): FloatVector3: tmp978 << tmp977 V_MUL_F32 vDst(VGPR1114) src0(VGPR1111) src1(VGPR1111) // VOP2 V_MAC_F32 vDst(VGPR1114) src0(VGPR1112) src1(VGPR1112) // VOP2 V_MAC_F32 vDst(VGPR1114) src0(VGPR1113) src1(VGPR1113) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1114) src0(VGPR1114) V_MUL_F32 vDst(VGPR1115) src0(VGPR1111) src1(VGPR1114) // VOP2 V_MUL_F32 vDst(VGPR1116) src0(VGPR1112) src1(VGPR1114) // VOP2 V_MUL_F32 vDst(VGPR1117) src0(VGPR1113) src1(VGPR1114) // VOP2 # 980: OpLoad: FloatVector3: tmp980 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1118) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1119) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1120) src0(VGPR2) # 982: OpLoad: FloatVector3: tmp982 << l # 983: OpLoad: FloatVector3: tmp983 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1121) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1122) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1123) src0(VGPR2) # 984: OpFSub: FloatVector3: tmp984 << tmp982, tmp983 V_SUB_F32 vDst(VGPR1124) src0(VGPR37) src1(VGPR1121) // VOP2 V_SUB_F32 vDst(VGPR1125) src0(VGPR38) src1(VGPR1122) // VOP2 V_SUB_F32 vDst(VGPR1126) src0(VGPR39) src1(VGPR1123) // VOP2 # 985: OpExtInst(Normalize): FloatVector3: tmp985 << tmp984 V_MUL_F32 vDst(VGPR1127) src0(VGPR1124) src1(VGPR1124) // VOP2 V_MAC_F32 vDst(VGPR1127) src0(VGPR1125) src1(VGPR1125) // VOP2 V_MAC_F32 vDst(VGPR1127) src0(VGPR1126) src1(VGPR1126) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1127) src0(VGPR1127) V_MUL_F32 vDst(VGPR1128) src0(VGPR1124) src1(VGPR1127) // VOP2 V_MUL_F32 vDst(VGPR1129) src0(VGPR1125) src1(VGPR1127) // VOP2 V_MUL_F32 vDst(VGPR1130) src0(VGPR1126) src1(VGPR1127) // VOP2 # 986: OpLoad: Float: tmp986 << is_choc # 987: OpFOrdLessThan: Bool: tmp987 << tmp986, const303 V_MOV_B32 vDst(VGPR1131) src0(0_5_F) V_CMP_LT_F32 dst(SGPR324) src0(VGPR33) src1(VGPR1131) // VOP3a # OpSelectionMerge: (merge: lb989) # CF Block: Merge: lb989 S_MOV_B64 sDst(SGPR326) src0(EXEC) # OpBranchConditional: if(tmp987) then branch to lb988, else branch to lb1078 # CF Block: Cond Branch: true: lb988, false: lb1078 S_AND_B64 sDst(EXEC) src0(SGPR324) src1(EXEC) S_CBRANCH_EXECZ ??? lb1078 S_BRANCH ??? lb988 # lb988 Label: lb988 # 990: OpAccessChain: Float*: rp[0] # 991: OpCompositeExtract: Float: tmp991 << tmp943, 0 V_MOV_B32 vDst(VGPR1132) src0(VGPR1071) # 992: OpFDiv: Float: tmp992 << tmp991, const109 V_MOV_B32 vDst(VGPR1133) src0(LITERAL_CONST) const: 0x40400000 V_RCP_F32 vDst(VGPR1134) src0(VGPR1133) V_MUL_F32 vDst(VGPR1134) src0(VGPR1132) src1(VGPR1134) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1134) src0(VGPR1134) src1(VGPR1133) src2(VGPR1132) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 993: OpExtInst(Floor): Float: tmp993 << tmp992 V_FLOOR_F32 vDst(VGPR1135) src0(VGPR1134) # 994: OpFMod: Float: tmp994 << tmp993, const127 V_MOV_B32 vDst(VGPR1136) src0(2_0_F) V_RCP_F32 vDst(VGPR1137) src0(VGPR1136) V_MUL_F32 vDst(VGPR1137) src0(VGPR1135) src1(VGPR1137) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1137) src0(VGPR1137) src1(VGPR1136) src2(VGPR1135) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR1137) src0(VGPR1137) V_MAD_F32 vDst(VGPR1137) src0(VGPR1136) src1(VGPR1137) src2(VGPR1135) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 995: OpFOrdGreaterThan: Bool: tmp995 << tmp994, const303 V_MOV_B32 vDst(VGPR1138) src0(0_5_F) V_CMP_GT_F32 dst(SGPR328) src0(VGPR1137) src1(VGPR1138) // VOP3a # OpSelectionMerge: (merge: lb997) # CF Block: Merge: lb997 S_MOV_B64 sDst(SGPR330) src0(EXEC) # OpBranchConditional: if(tmp995) then branch to lb996, else branch to lb1034 # CF Block: Cond Branch: true: lb996, false: lb1034 S_AND_B64 sDst(EXEC) src0(SGPR328) src1(EXEC) S_CBRANCH_EXECZ ??? lb1034 S_BRANCH ??? lb996 # lb996 Label: lb996 # 1000: OpVectorShuffle: FloatVector2: tmp1000 << tmp943, tmp943, 0, 2 V_MOV_B32 vDst(VGPR1139) src0(VGPR1071) V_MOV_B32 vDst(VGPR1140) src0(VGPR1073) # 1002: OpVectorShuffle: FloatVector2: tmp1002 << tmp943, tmp943, 0, 2 V_MOV_B32 vDst(VGPR1141) src0(VGPR1071) V_MOV_B32 vDst(VGPR1142) src0(VGPR1073) # 1003: OpCompositeConstruct: FloatVector2: tmp1003 << const109, const109 V_MOV_B32 vDst(VGPR1145) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR1143) src0(VGPR1145) V_MOV_B32 vDst(VGPR1146) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR1144) src0(VGPR1146) # 1004: OpFDiv: FloatVector2: tmp1004 << tmp1002, tmp1003 V_RCP_F32 vDst(VGPR1147) src0(VGPR1143) V_RCP_F32 vDst(VGPR1148) src0(VGPR1144) V_MUL_F32 vDst(VGPR1147) src0(VGPR1141) src1(VGPR1147) // VOP2 V_MUL_F32 vDst(VGPR1148) src0(VGPR1142) src1(VGPR1148) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1147) src0(VGPR1147) src1(VGPR1143) src2(VGPR1141) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR1148) src0(VGPR1148) src1(VGPR1144) src2(VGPR1142) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1005: OpExtInst(Floor): FloatVector2: tmp1005 << tmp1004 V_FLOOR_F32 vDst(VGPR1149) src0(VGPR1147) V_FLOOR_F32 vDst(VGPR1150) src0(VGPR1148) # 1006: OpVectorTimesScalar: FloatVector2: tmp1006 << tmp1005, const109 V_MOV_B32 vDst(VGPR1153) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR1151) src0(VGPR1153) src1(VGPR1149) // VOP2 V_MUL_F32 vDst(VGPR1152) src0(VGPR1153) src1(VGPR1150) // VOP2 # 1007: OpFAdd: FloatVector2: tmp1007 << tmp1006, const667 V_MOV_B32 vDst(VGPR1154) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR1155) src0(LITERAL_CONST) const: 0x3fc00000 V_ADD_F32 vDst(VGPR1156) src0(VGPR1151) src1(VGPR1154) // VOP2 V_ADD_F32 vDst(VGPR1157) src0(VGPR1152) src1(VGPR1155) // VOP2 # 1008: OpExtInst(Distance): Float: tmp1008 << tmp1000, tmp1007 V_SUB_F32 vDst(VGPR1158) src0(VGPR1139) src1(VGPR1156) // VOP2 V_SUB_F32 vDst(VGPR1159) src0(VGPR1140) src1(VGPR1157) // VOP2 V_MUL_F32 vDst(VGPR1160) src0(VGPR1158) src1(VGPR1158) // VOP2 V_MAC_F32 vDst(VGPR1160) src0(VGPR1159) src1(VGPR1159) // VOP2 V_SQRT_F32 vDst(VGPR1160) src0(VGPR1160) # 1009: OpFMul: Float: tmp1009 << tmp1008, const704 V_MOV_B32 vDst(VGPR1161) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR1162) src0(VGPR1160) src1(VGPR1161) // VOP2 # 1010: OpExtInst(Pow): Float: tmp1010 << tmp1009, const127 V_MOV_B32 vDst(VGPR1163) src0(2_0_F) V_LOG_F32 vDst(VGPR1164) src0(VGPR1162) V_MUL_F32 vDst(VGPR1164) src0(VGPR1163) src1(VGPR1164) // VOP2 V_EXP_F32 vDst(VGPR1164) src0(VGPR1164) # 1019: OpFAdd: Float: tmp1019 << const303, tmp1010 V_ADD_F32 vDst(VGPR1165) src0(0_5_F) src1(VGPR1164) // VOP2 # 1021: OpFAdd: Float: tmp1021 << const704, tmp1010 V_MOV_B32 vDst(VGPR1166) src0(LITERAL_CONST) const: 0x3f19999a V_ADD_F32 vDst(VGPR1167) src0(VGPR1166) src1(VGPR1164) // VOP2 # 1023: OpVectorShuffle: FloatVector2: tmp1023 << tmp943, tmp943, 0, 2 V_MOV_B32 vDst(VGPR1168) src0(VGPR1071) V_MOV_B32 vDst(VGPR1169) src0(VGPR1073) # 1024: OpVectorTimesScalar: FloatVector2: tmp1024 << tmp1023, const621 V_MOV_B32 vDst(VGPR1172) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR1170) src0(VGPR1172) src1(VGPR1168) // VOP2 V_MUL_F32 vDst(VGPR1171) src0(VGPR1172) src1(VGPR1169) // VOP2 # 1025: OpCompositeExtract: Float: tmp1025 << tmp1024, 0 V_MOV_B32 vDst(VGPR1173) src0(VGPR1170) # 1026: OpCompositeExtract: Float: tmp1026 << tmp1024, 1 V_MOV_B32 vDst(VGPR1174) src0(VGPR1171) # 1027: OpCompositeConstruct: FloatVector3: tmp1027 << tmp1025, tmp1026, const100 V_MOV_B32 vDst(VGPR1175) src0(VGPR1173) V_MOV_B32 vDst(VGPR1176) src0(VGPR1174) V_MOV_B32 vDst(VGPR1178) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1177) src0(VGPR1178) # OpStore: : tmp1027 >> param1028 V_MOV_B32 vDst(VGPR1019) src0(VGPR1175) V_MOV_B32 vDst(VGPR1020) src0(VGPR1176) V_MOV_B32 vDst(VGPR1021) src0(VGPR1177) # 1029: OpFunctionCall: Float: fbm3(vf3;(param1028) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x3fb # VGPR[1019:1021] S_MOV_B64 sDst(SGPR332) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x49b # VGPR1179 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR332) # .lbl90 # 1030: OpFAdd: Float: tmp1030 << const748, fbm3(vf3; V_MOV_B32 vDst(VGPR1180) src0(LITERAL_CONST) const: 0x3ecccccd V_ADD_F32 vDst(VGPR1181) src0(VGPR1180) src1(VGPR1179) // VOP2 # 1031: OpExtInst(SmoothStep): Float: tmp1031 << tmp1019, tmp1021, tmp1030 V_CMP_GE_F32 src0(VGPR1165) src1(VGPR1181) # CF Block: Merge: .lbl94 S_MOV_B64 sDst(SGPR334) src0(EXEC) # CF Block: Cond Branch: true: .lbl95, false: .lbl91 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl91 S_BRANCH ??? .lbl95 Label: .lbl95 V_MOV_B32 vDst(VGPR1182) src0(0) S_BRANCH ??? .lbl94 Label: .lbl91 V_CMP_LE_F32 src0(VGPR1167) src1(VGPR1181) # CF Block: Merge: .lbl93 S_MOV_B64 sDst(SGPR336) src0(EXEC) # CF Block: Cond Branch: true: .lbl96, false: .lbl92 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl92 S_BRANCH ??? .lbl96 Label: .lbl96 V_MOV_B32 vDst(VGPR1182) src0(1_0_F) S_BRANCH ??? .lbl93 Label: .lbl92 V_SUBREV_F32 vDst(VGPR1183) src0(VGPR1165) src1(VGPR1167) // VOP2 V_RCP_F32 vDst(VGPR1183) src0(VGPR1183) V_SUBREV_F32 vDst(VGPR1182) src0(VGPR1165) src1(VGPR1181) // VOP2 V_MUL_F32 vDst(VGPR1183) src0(VGPR1182) src1(VGPR1183) // VOP2 V_MAX_F32 vDst(VGPR1183) src0(0) src1(VGPR1183) // VOP2 V_MIN_F32 vDst(VGPR1183) src0(1_0_F) src1(VGPR1183) // VOP2 V_MOV_B32 vDst(VGPR1182) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1182) src0(2_0_F) src1(VGPR1183) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1183) src0(VGPR1183) src1(VGPR1183) // VOP2 V_MUL_F32 vDst(VGPR1182) src0(VGPR1183) src1(VGPR1182) // VOP2 S_BRANCH ??? .lbl93 Label: .lbl93 S_BRANCH ??? .lbl94 Label: .lbl94 # 1032: OpCompositeConstruct: FloatVector3: tmp1032 << tmp1031, tmp1031, tmp1031 V_MOV_B32 vDst(VGPR1184) src0(VGPR1182) V_MOV_B32 vDst(VGPR1185) src0(VGPR1182) V_MOV_B32 vDst(VGPR1186) src0(VGPR1182) # 1033: OpExtInst(FMix): FloatVector3: tmp1033 << const1013, const1017, tmp1032 V_MOV_B32 vDst(VGPR1187) src0(4_0_F) V_MOV_B32 vDst(VGPR1188) src0(4_0_F) V_MOV_B32 vDst(VGPR1189) src0(LITERAL_CONST) const: 0x40266666 V_MOV_B32 vDst(VGPR1190) src0(LITERAL_CONST) const: 0x3f47ae14 V_MOV_B32 vDst(VGPR1191) src0(LITERAL_CONST) const: 0x3eb851ec V_MOV_B32 vDst(VGPR1192) src0(LITERAL_CONST) const: 0x3df5c28f V_SUBREV_F32 vDst(VGPR1193) src0(VGPR1184) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1193) src0(VGPR1187) src1(VGPR1193) // VOP2 V_MAD_F32 vDst(VGPR1193) src0(VGPR1190) src1(VGPR1184) src2(VGPR1193) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1194) src0(VGPR1185) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1194) src0(VGPR1188) src1(VGPR1194) // VOP2 V_MAD_F32 vDst(VGPR1194) src0(VGPR1191) src1(VGPR1185) src2(VGPR1194) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1195) src0(VGPR1186) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1195) src0(VGPR1189) src1(VGPR1195) // VOP2 V_MAD_F32 vDst(VGPR1195) src0(VGPR1192) src1(VGPR1186) src2(VGPR1195) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1033 >> chocolour V_MOV_B32 vDst(VGPR1016) src0(VGPR1193) V_MOV_B32 vDst(VGPR1017) src0(VGPR1194) V_MOV_B32 vDst(VGPR1018) src0(VGPR1195) # OpBranch: to lb997 S_BRANCH ??? lb997 # lb1034 Label: lb1034 # 1036: OpAccessChain: Float*: rp[0] # 1037: OpCompositeExtract: Float: tmp1037 << tmp943, 0 V_MOV_B32 vDst(VGPR1196) src0(VGPR1071) # 1038: OpFMul: Float: tmp1038 << tmp1037, const621 V_MOV_B32 vDst(VGPR1197) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR1198) src0(VGPR1196) src1(VGPR1197) // VOP2 # 1039: OpAccessChain: Float*: rp[2] # 1040: OpCompositeExtract: Float: tmp1040 << tmp943, 2 V_MOV_B32 vDst(VGPR1199) src0(VGPR1073) # 1041: OpFMul: Float: tmp1041 << tmp1040, const401 V_MOV_B32 vDst(VGPR1200) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR1201) src0(VGPR1199) src1(VGPR1200) // VOP2 # 1042: OpExtInst(Sin): Float: tmp1042 << tmp1041 V_MUL_F32 vDst(VGPR1202) src0(LITERAL_CONST) src1(VGPR1201) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR1202) src0(VGPR1202) V_SIN_F32 vDst(VGPR1202) src0(VGPR1202) # 1043: OpFAdd: Float: tmp1043 << tmp1038, tmp1042 V_ADD_F32 vDst(VGPR1203) src0(VGPR1198) src1(VGPR1202) // VOP2 # 1044: OpExtInst(Cos): Float: tmp1044 << tmp1043 V_MUL_F32 vDst(VGPR1204) src0(LITERAL_CONST) src1(VGPR1203) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR1204) src0(VGPR1204) V_COS_F32 vDst(VGPR1204) src0(VGPR1204) # 1045: OpFMul: Float: tmp1045 << const303, tmp1044 V_MUL_F32 vDst(VGPR1205) src0(0_5_F) src1(VGPR1204) // VOP2 # 1046: OpFAdd: Float: tmp1046 << const303, tmp1045 V_ADD_F32 vDst(VGPR1206) src0(0_5_F) src1(VGPR1205) // VOP2 # 1047: OpExtInst(SmoothStep): Float: tmp1047 << const671, const435, tmp1046 V_MOV_B32 vDst(VGPR1207) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR1208) src0(LITERAL_CONST) const: 0x3f666666 V_CMP_GE_F32 src0(VGPR1207) src1(VGPR1206) # CF Block: Merge: .lbl100 S_MOV_B64 sDst(SGPR338) src0(EXEC) # CF Block: Cond Branch: true: .lbl101, false: .lbl97 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl97 S_BRANCH ??? .lbl101 Label: .lbl101 V_MOV_B32 vDst(VGPR1209) src0(0) S_BRANCH ??? .lbl100 Label: .lbl97 V_CMP_LE_F32 src0(VGPR1208) src1(VGPR1206) # CF Block: Merge: .lbl99 S_MOV_B64 sDst(SGPR340) src0(EXEC) # CF Block: Cond Branch: true: .lbl102, false: .lbl98 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl98 S_BRANCH ??? .lbl102 Label: .lbl102 V_MOV_B32 vDst(VGPR1209) src0(1_0_F) S_BRANCH ??? .lbl99 Label: .lbl98 V_SUBREV_F32 vDst(VGPR1210) src0(VGPR1207) src1(VGPR1208) // VOP2 V_RCP_F32 vDst(VGPR1210) src0(VGPR1210) V_SUBREV_F32 vDst(VGPR1209) src0(VGPR1207) src1(VGPR1206) // VOP2 V_MUL_F32 vDst(VGPR1210) src0(VGPR1209) src1(VGPR1210) // VOP2 V_MAX_F32 vDst(VGPR1210) src0(0) src1(VGPR1210) // VOP2 V_MIN_F32 vDst(VGPR1210) src0(1_0_F) src1(VGPR1210) // VOP2 V_MOV_B32 vDst(VGPR1209) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1209) src0(2_0_F) src1(VGPR1210) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1210) src0(VGPR1210) src1(VGPR1210) // VOP2 V_MUL_F32 vDst(VGPR1209) src0(VGPR1210) src1(VGPR1209) // VOP2 S_BRANCH ??? .lbl99 Label: .lbl99 S_BRANCH ??? .lbl100 Label: .lbl100 # 1048: OpCompositeConstruct: FloatVector3: tmp1048 << tmp1047, tmp1047, tmp1047 V_MOV_B32 vDst(VGPR1211) src0(VGPR1209) V_MOV_B32 vDst(VGPR1212) src0(VGPR1209) V_MOV_B32 vDst(VGPR1213) src0(VGPR1209) # 1049: OpExtInst(FMix): FloatVector3: tmp1049 << const1035, const1013, tmp1048 V_MOV_B32 vDst(VGPR1214) src0(LITERAL_CONST) const: 0x3fa66666 V_MOV_B32 vDst(VGPR1215) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR1216) src0(LITERAL_CONST) const: 0x3e4ccccd V_MOV_B32 vDst(VGPR1217) src0(4_0_F) V_MOV_B32 vDst(VGPR1218) src0(4_0_F) V_MOV_B32 vDst(VGPR1219) src0(LITERAL_CONST) const: 0x40266666 V_SUBREV_F32 vDst(VGPR1220) src0(VGPR1211) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1220) src0(VGPR1214) src1(VGPR1220) // VOP2 V_MAD_F32 vDst(VGPR1220) src0(VGPR1217) src1(VGPR1211) src2(VGPR1220) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1221) src0(VGPR1212) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1221) src0(VGPR1215) src1(VGPR1221) // VOP2 V_MAD_F32 vDst(VGPR1221) src0(VGPR1218) src1(VGPR1212) src2(VGPR1221) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1222) src0(VGPR1213) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1222) src0(VGPR1216) src1(VGPR1222) // VOP2 V_MAD_F32 vDst(VGPR1222) src0(VGPR1219) src1(VGPR1213) src2(VGPR1222) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1049 >> chocolour V_MOV_B32 vDst(VGPR1016) src0(VGPR1220) V_MOV_B32 vDst(VGPR1017) src0(VGPR1221) V_MOV_B32 vDst(VGPR1018) src0(VGPR1222) # OpBranch: to lb997 S_BRANCH ??? lb997 # lb997 Label: lb997 # 1050: OpLoad: FloatVector3: tmp1050 << chocolour # 1051: OpVectorTimesScalar: FloatVector3: tmp1051 << tmp1050, const576 V_MOV_B32 vDst(VGPR1226) src0(LITERAL_CONST) const: 0x3dcccccd V_MUL_F32 vDst(VGPR1223) src0(VGPR1226) src1(VGPR1016) // VOP2 V_MUL_F32 vDst(VGPR1224) src0(VGPR1226) src1(VGPR1017) // VOP2 V_MUL_F32 vDst(VGPR1225) src0(VGPR1226) src1(VGPR1018) // VOP2 # 1053: OpLoad: FloatVector3: tmp1053 << l # 1054: OpDot: Float: tmp1054 << tmp978, tmp1053 V_MUL_F32 vDst(VGPR1227) src0(VGPR1115) src1(VGPR37) // VOP2 V_MAC_F32 vDst(VGPR1227) src0(VGPR1116) src1(VGPR38) // VOP2 V_MAC_F32 vDst(VGPR1227) src0(VGPR1117) src1(VGPR39) // VOP2 # 1055: OpFMul: Float: tmp1055 << const303, tmp1054 V_MUL_F32 vDst(VGPR1228) src0(0_5_F) src1(VGPR1227) // VOP2 # 1056: OpFAdd: Float: tmp1056 << const303, tmp1055 V_ADD_F32 vDst(VGPR1229) src0(0_5_F) src1(VGPR1228) // VOP2 # 1057: OpCompositeConstruct: FloatVector3: tmp1057 << tmp1056, tmp1056, tmp1056 V_MOV_B32 vDst(VGPR1230) src0(VGPR1229) V_MOV_B32 vDst(VGPR1231) src0(VGPR1229) V_MOV_B32 vDst(VGPR1232) src0(VGPR1229) # 1058: OpFMul: FloatVector3: tmp1058 << tmp1051, tmp1057 V_MUL_F32 vDst(VGPR1233) src0(VGPR1223) src1(VGPR1230) // VOP2 V_MUL_F32 vDst(VGPR1234) src0(VGPR1224) src1(VGPR1231) // VOP2 V_MUL_F32 vDst(VGPR1235) src0(VGPR1225) src1(VGPR1232) // VOP2 # 1062: OpDot: Float: tmp1062 << tmp985, tmp978 V_MUL_F32 vDst(VGPR1236) src0(VGPR1128) src1(VGPR1115) // VOP2 V_MAC_F32 vDst(VGPR1236) src0(VGPR1129) src1(VGPR1116) // VOP2 V_MAC_F32 vDst(VGPR1236) src0(VGPR1130) src1(VGPR1117) // VOP2 # 1063: OpFMul: Float: tmp1063 << const303, tmp1062 V_MUL_F32 vDst(VGPR1237) src0(0_5_F) src1(VGPR1236) // VOP2 # 1064: OpFAdd: Float: tmp1064 << const303, tmp1063 V_ADD_F32 vDst(VGPR1238) src0(0_5_F) src1(VGPR1237) // VOP2 # 1065: OpExtInst(FClamp): Float: tmp1065 << tmp1064, const100, const106 V_MOV_B32 vDst(VGPR1239) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1240) src0(1_0_F) V_MAX_F32 vDst(VGPR1241) src0(VGPR1238) src1(VGPR1239) // VOP2 V_MIN_F32 vDst(VGPR1241) src0(VGPR1241) src1(VGPR1240) // VOP2 # 1066: OpExtInst(Pow): Float: tmp1066 << tmp1065, const863 V_MOV_B32 vDst(VGPR1242) src0(LITERAL_CONST) const: 0x41a00000 V_LOG_F32 vDst(VGPR1243) src0(VGPR1241) V_MUL_F32 vDst(VGPR1243) src0(VGPR1242) src1(VGPR1243) // VOP2 V_EXP_F32 vDst(VGPR1243) src0(VGPR1243) # 1067: OpCompositeConstruct: FloatVector3: tmp1067 << tmp1066, tmp1066, tmp1066 V_MOV_B32 vDst(VGPR1244) src0(VGPR1243) V_MOV_B32 vDst(VGPR1245) src0(VGPR1243) V_MOV_B32 vDst(VGPR1246) src0(VGPR1243) # 1068: OpFMul: FloatVector3: tmp1068 << const1059, tmp1067 V_MOV_B32 vDst(VGPR1247) src0(LITERAL_CONST) const: 0x3d75c28f V_MOV_B32 vDst(VGPR1248) src0(LITERAL_CONST) const: 0x3d75c28f V_MOV_B32 vDst(VGPR1249) src0(LITERAL_CONST) const: 0x3cf5c28f V_MUL_F32 vDst(VGPR1250) src0(VGPR1247) src1(VGPR1244) // VOP2 V_MUL_F32 vDst(VGPR1251) src0(VGPR1248) src1(VGPR1245) // VOP2 V_MUL_F32 vDst(VGPR1252) src0(VGPR1249) src1(VGPR1246) // VOP2 # 1069: OpFAdd: FloatVector3: tmp1069 << tmp1058, tmp1068 V_ADD_F32 vDst(VGPR1253) src0(VGPR1233) src1(VGPR1250) // VOP2 V_ADD_F32 vDst(VGPR1254) src0(VGPR1234) src1(VGPR1251) // VOP2 V_ADD_F32 vDst(VGPR1255) src0(VGPR1235) src1(VGPR1252) // VOP2 # 1071: OpLoad: FloatVector3: tmp1071 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1257) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1258) src0(VGPR2) # 1072: OpFNegate: FloatVector3: tmp1072 << tmp1071 V_MUL_F32 vDst(VGPR1259) src0(M1_0_F) src1(VGPR1256) // VOP2 V_MUL_F32 vDst(VGPR1260) src0(M1_0_F) src1(VGPR1257) // VOP2 V_MUL_F32 vDst(VGPR1261) src0(M1_0_F) src1(VGPR1258) // VOP2 # 1073: OpDot: Float: tmp1073 << tmp978, tmp1072 V_MUL_F32 vDst(VGPR1262) src0(VGPR1115) src1(VGPR1259) // VOP2 V_MAC_F32 vDst(VGPR1262) src0(VGPR1116) src1(VGPR1260) // VOP2 V_MAC_F32 vDst(VGPR1262) src0(VGPR1117) src1(VGPR1261) // VOP2 # 1074: OpExtInst(Pow): Float: tmp1074 << tmp1073, const127 V_MOV_B32 vDst(VGPR1263) src0(2_0_F) V_LOG_F32 vDst(VGPR1264) src0(VGPR1262) V_MUL_F32 vDst(VGPR1264) src0(VGPR1263) src1(VGPR1264) // VOP2 V_EXP_F32 vDst(VGPR1264) src0(VGPR1264) # 1075: OpFMul: Float: tmp1075 << const704, tmp1074 V_MOV_B32 vDst(VGPR1265) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR1266) src0(VGPR1265) src1(VGPR1264) // VOP2 # 1076: OpFAdd: Float: tmp1076 << const106, tmp1075 V_ADD_F32 vDst(VGPR1267) src0(1_0_F) src1(VGPR1266) // VOP2 # 1077: OpVectorTimesScalar: FloatVector3: tmp1077 << tmp1069, tmp1076 V_MUL_F32 vDst(VGPR1268) src0(VGPR1267) src1(VGPR1253) // VOP2 V_MUL_F32 vDst(VGPR1269) src0(VGPR1267) src1(VGPR1254) // VOP2 V_MUL_F32 vDst(VGPR1270) src0(VGPR1267) src1(VGPR1255) // VOP2 # OpStore: : tmp1077 >> col V_MOV_B32 vDst(VGPR1001) src0(VGPR1268) V_MOV_B32 vDst(VGPR1002) src0(VGPR1269) V_MOV_B32 vDst(VGPR1003) src0(VGPR1270) # OpBranch: to lb989 S_BRANCH ??? lb989 # lb1078 Label: lb1078 # OpStore: : tmp978 >> param1079 V_MOV_B32 vDst(VGPR1022) src0(VGPR1115) V_MOV_B32 vDst(VGPR1023) src0(VGPR1116) V_MOV_B32 vDst(VGPR1024) src0(VGPR1117) # OpStore: : tmp943 >> param1081 V_MOV_B32 vDst(VGPR1025) src0(VGPR1071) V_MOV_B32 vDst(VGPR1026) src0(VGPR1072) V_MOV_B32 vDst(VGPR1027) src0(VGPR1073) # OpStore: : tmp980 >> param1083 V_MOV_B32 vDst(VGPR1028) src0(VGPR1118) V_MOV_B32 vDst(VGPR1029) src0(VGPR1119) V_MOV_B32 vDst(VGPR1030) src0(VGPR1120) # 1085: OpFunctionCall: FloatVector3: gummy(vf3;vf3;vf3;(param1079, param1081, param1083) S_ADD_U32 sDst(SGPR193) src0(LITERAL_CONST) src1(0) const: 0x3fe # VGPR[1022:1024] S_ADD_U32 sDst(SGPR194) src0(LITERAL_CONST) src1(0) const: 0x401 # VGPR[1025:1027] S_ADD_U32 sDst(SGPR195) src0(LITERAL_CONST) src1(0) const: 0x404 # VGPR[1028:1030] S_MOV_B64 sDst(SGPR342) src0(EXEC) S_MOV_B32 sDst(SGPR192) src0(LITERAL_CONST) const: 0x4f7 # VGPR[1271:1273] # Indirect branch to gummy(vf3;vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR190) src0(SGPR190) S_ADD_U32 sDst(SGPR190) src0(SGPR190) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR191) src0(SGPR191) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR190) src0(SGPR190) S_MOV_B64 sDst(EXEC) src0(SGPR342) # .lbl103 # 1086: OpVectorTimesScalar: FloatVector3: tmp1086 << gummy(vf3;vf3;vf3;, const401 V_MOV_B32 vDst(VGPR1277) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR1274) src0(VGPR1277) src1(VGPR1271) // VOP2 V_MUL_F32 vDst(VGPR1275) src0(VGPR1277) src1(VGPR1272) // VOP2 V_MUL_F32 vDst(VGPR1276) src0(VGPR1277) src1(VGPR1273) // VOP2 # 1089: OpDot: Float: tmp1089 << tmp985, tmp978 V_MUL_F32 vDst(VGPR1278) src0(VGPR1128) src1(VGPR1115) // VOP2 V_MAC_F32 vDst(VGPR1278) src0(VGPR1129) src1(VGPR1116) // VOP2 V_MAC_F32 vDst(VGPR1278) src0(VGPR1130) src1(VGPR1117) // VOP2 # 1090: OpFMul: Float: tmp1090 << const303, tmp1089 V_MUL_F32 vDst(VGPR1279) src0(0_5_F) src1(VGPR1278) // VOP2 # 1091: OpFAdd: Float: tmp1091 << const303, tmp1090 V_ADD_F32 vDst(VGPR1280) src0(0_5_F) src1(VGPR1279) // VOP2 # 1092: OpExtInst(FClamp): Float: tmp1092 << tmp1091, const100, const106 V_MOV_B32 vDst(VGPR1281) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1282) src0(1_0_F) V_MAX_F32 vDst(VGPR1283) src0(VGPR1280) src1(VGPR1281) // VOP2 V_MIN_F32 vDst(VGPR1283) src0(VGPR1283) src1(VGPR1282) // VOP2 # 1094: OpExtInst(Pow): Float: tmp1094 << tmp1092, const1093 V_MOV_B32 vDst(VGPR1284) src0(LITERAL_CONST) const: 0x43800000 V_LOG_F32 vDst(VGPR1285) src0(VGPR1283) V_MUL_F32 vDst(VGPR1285) src0(VGPR1284) src1(VGPR1285) // VOP2 V_EXP_F32 vDst(VGPR1285) src0(VGPR1285) # 1095: OpExtInst(SmoothStep): Float: tmp1095 << const303, const704, tmp1094 V_MOV_B32 vDst(VGPR1286) src0(LITERAL_CONST) const: 0x3f19999a V_CMP_GE_F32 src0(0_5_F) src1(VGPR1285) # CF Block: Merge: .lbl107 S_MOV_B64 sDst(SGPR344) src0(EXEC) # CF Block: Cond Branch: true: .lbl108, false: .lbl104 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl104 S_BRANCH ??? .lbl108 Label: .lbl108 V_MOV_B32 vDst(VGPR1287) src0(0) S_BRANCH ??? .lbl107 Label: .lbl104 V_CMP_LE_F32 src0(VGPR1286) src1(VGPR1285) # CF Block: Merge: .lbl106 S_MOV_B64 sDst(SGPR346) src0(EXEC) # CF Block: Cond Branch: true: .lbl109, false: .lbl105 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl105 S_BRANCH ??? .lbl109 Label: .lbl109 V_MOV_B32 vDst(VGPR1287) src0(1_0_F) S_BRANCH ??? .lbl106 Label: .lbl105 V_SUBREV_F32 vDst(VGPR1288) src0(0_5_F) src1(VGPR1286) // VOP2 V_RCP_F32 vDst(VGPR1288) src0(VGPR1288) V_SUBREV_F32 vDst(VGPR1287) src0(0_5_F) src1(VGPR1285) // VOP2 V_MUL_F32 vDst(VGPR1288) src0(VGPR1287) src1(VGPR1288) // VOP2 V_MAX_F32 vDst(VGPR1288) src0(0) src1(VGPR1288) // VOP2 V_MIN_F32 vDst(VGPR1288) src0(1_0_F) src1(VGPR1288) // VOP2 V_MOV_B32 vDst(VGPR1287) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1287) src0(2_0_F) src1(VGPR1288) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1288) src0(VGPR1288) src1(VGPR1288) // VOP2 V_MUL_F32 vDst(VGPR1287) src0(VGPR1288) src1(VGPR1287) // VOP2 S_BRANCH ??? .lbl106 Label: .lbl106 S_BRANCH ??? .lbl107 Label: .lbl107 # 1096: OpCompositeConstruct: FloatVector3: tmp1096 << tmp1095, tmp1095, tmp1095 V_MOV_B32 vDst(VGPR1289) src0(VGPR1287) V_MOV_B32 vDst(VGPR1290) src0(VGPR1287) V_MOV_B32 vDst(VGPR1291) src0(VGPR1287) # 1097: OpVectorTimesScalar: FloatVector3: tmp1097 << tmp1096, const576 V_MOV_B32 vDst(VGPR1295) src0(LITERAL_CONST) const: 0x3dcccccd V_MUL_F32 vDst(VGPR1292) src0(VGPR1295) src1(VGPR1289) // VOP2 V_MUL_F32 vDst(VGPR1293) src0(VGPR1295) src1(VGPR1290) // VOP2 V_MUL_F32 vDst(VGPR1294) src0(VGPR1295) src1(VGPR1291) // VOP2 # 1098: OpFAdd: FloatVector3: tmp1098 << tmp1086, tmp1097 V_ADD_F32 vDst(VGPR1296) src0(VGPR1274) src1(VGPR1292) // VOP2 V_ADD_F32 vDst(VGPR1297) src0(VGPR1275) src1(VGPR1293) // VOP2 V_ADD_F32 vDst(VGPR1298) src0(VGPR1276) src1(VGPR1294) // VOP2 # OpStore: : tmp1098 >> col V_MOV_B32 vDst(VGPR1001) src0(VGPR1296) V_MOV_B32 vDst(VGPR1002) src0(VGPR1297) V_MOV_B32 vDst(VGPR1003) src0(VGPR1298) # OpBranch: to lb989 S_BRANCH ??? lb989 # lb989 Label: lb989 # 1099: OpAccessChain: Float*: rp[1] # 1100: OpCompositeExtract: Float: tmp1100 << tmp943, 1 V_MOV_B32 vDst(VGPR1299) src0(VGPR1072) # 1101: OpExtInst(FMax): Float: tmp1101 << const100, tmp1100 V_MOV_B32 vDst(VGPR1300) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR1301) src0(VGPR1300) src1(VGPR1299) // VOP2 # 1102: OpExtInst(Pow): Float: tmp1102 << tmp1101, const303 V_MOV_B32 vDst(VGPR1302) src0(0_5_F) V_LOG_F32 vDst(VGPR1303) src0(VGPR1301) V_MUL_F32 vDst(VGPR1303) src0(VGPR1302) src1(VGPR1303) // VOP2 V_EXP_F32 vDst(VGPR1303) src0(VGPR1303) # 1103: OpExtInst(FMix): Float: tmp1103 << const106, tmp1102, const704 V_MOV_B32 vDst(VGPR1304) src0(LITERAL_CONST) const: 0x3f19999a V_SUBREV_F32 vDst(VGPR1305) src0(VGPR1304) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1305) src0(1_0_F) src1(VGPR1305) // VOP2 V_MAD_F32 vDst(VGPR1305) src0(VGPR1303) src1(VGPR1304) src2(VGPR1305) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1104: OpLoad: FloatVector3: tmp1104 << col # 1105: OpVectorTimesScalar: FloatVector3: tmp1105 << tmp1104, tmp1103 V_MUL_F32 vDst(VGPR1306) src0(VGPR1305) src1(VGPR1001) // VOP2 V_MUL_F32 vDst(VGPR1307) src0(VGPR1305) src1(VGPR1002) // VOP2 V_MUL_F32 vDst(VGPR1308) src0(VGPR1305) src1(VGPR1003) // VOP2 # OpStore: : tmp1105 >> col V_MOV_B32 vDst(VGPR1001) src0(VGPR1306) V_MOV_B32 vDst(VGPR1002) src0(VGPR1307) V_MOV_B32 vDst(VGPR1003) src0(VGPR1308) # 1106: OpLoad: FloatVector3: tmp1106 << col # OpReturnValue: : << tmp1106 S_MOV_B32 sDst(M0) src0(SGPR290) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1001) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1002) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1003) S_SETPC_B64 sDst(SGPR288) src0(SGPR288) # Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) Function: Void mainImage(vf4;vf2;(, FloatVector2 main.fragCoord) S_MOV_B64 sDst(SGPR348) src0(EXEC) # lb97 Label: lb97 # 1111: OpLoad: Float: tmp1111 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR350) S_WAITCNT 0 # OpStore: : tmp1111 >> time V_MOV_B32 vDst(VGPR28) src0(SGPR350) # 1112: OpLoad: FloatVector2: tmp1112 << fragCoord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR13) const: 0x0 V_MOVRELS_B32 vDst(VGPR1350) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1351) src0(VGPR1) # 1115: OpLoad: FloatVector3: tmp1115 << iResolution S_LOAD_DWORDX2_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR[352:353]) S_WAITCNT 0 S_LOAD_DWORD_IMM offset(12) sBase(SGPR[0:1]) sDst(SGPR354) S_WAITCNT 0 # 1116: OpVectorShuffle: FloatVector2: tmp1116 << tmp1115, tmp1115, 0, 1 V_MOV_B32 vDst(VGPR1352) src0(SGPR352) V_MOV_B32 vDst(VGPR1353) src0(SGPR353) # 1117: OpFDiv: FloatVector2: tmp1117 << tmp1112, tmp1116 V_RCP_F32 vDst(VGPR1354) src0(VGPR1352) V_RCP_F32 vDst(VGPR1355) src0(VGPR1353) V_MUL_F32 vDst(VGPR1354) src0(VGPR1350) src1(VGPR1354) // VOP2 V_MUL_F32 vDst(VGPR1355) src0(VGPR1351) src1(VGPR1355) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1354) src0(VGPR1354) src1(VGPR1352) src2(VGPR1350) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR1355) src0(VGPR1355) src1(VGPR1353) src2(VGPR1351) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1118: OpVectorTimesScalar: FloatVector2: tmp1118 << tmp1117, const127 V_MOV_B32 vDst(VGPR1358) src0(2_0_F) V_MUL_F32 vDst(VGPR1356) src0(VGPR1358) src1(VGPR1354) // VOP2 V_MUL_F32 vDst(VGPR1357) src0(VGPR1358) src1(VGPR1355) // VOP2 # 1119: OpFSub: FloatVector2: tmp1119 << tmp1118, const342 V_MOV_B32 vDst(VGPR1359) src0(1_0_F) V_MOV_B32 vDst(VGPR1360) src0(1_0_F) V_SUB_F32 vDst(VGPR1361) src0(VGPR1356) src1(VGPR1359) // VOP2 V_SUB_F32 vDst(VGPR1362) src0(VGPR1357) src1(VGPR1360) // VOP2 # OpStore: : tmp1119 >> tc V_MOV_B32 vDst(VGPR24) src0(VGPR1361) V_MOV_B32 vDst(VGPR25) src0(VGPR1362) # 1121: OpLoad: Float: tmp1121 << time # 1122: OpLoad: Float: tmp1122 << t_per_target # 1123: OpFDiv: Float: tmp1123 << tmp1121, tmp1122 V_RCP_F32 vDst(VGPR1363) src0(VGPR35) V_MUL_F32 vDst(VGPR1363) src0(VGPR28) src1(VGPR1363) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1363) src0(VGPR1363) src1(VGPR35) src2(VGPR28) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1124: OpExtInst(Floor): Float: tmp1124 << tmp1123 V_FLOOR_F32 vDst(VGPR1364) src0(VGPR1363) # 1126: OpLoad: Float: tmp1126 << time # 1127: OpLoad: Float: tmp1127 << t_per_target # 1128: OpFDiv: Float: tmp1128 << tmp1126, tmp1127 V_RCP_F32 vDst(VGPR1365) src0(VGPR35) V_MUL_F32 vDst(VGPR1365) src0(VGPR28) src1(VGPR1365) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1365) src0(VGPR1365) src1(VGPR35) src2(VGPR28) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1129: OpExtInst(Fract): Float: tmp1129 << tmp1128 V_FRACT_F32 vDst(VGPR1366) src0(VGPR1365) # 1132: OpLoad: Float: tmp1132 << time # OpStore: : tmp1132 >> param1131 V_MOV_B32 vDst(VGPR1309) src0(VGPR28) # 1133: OpFunctionCall: FloatVector3: cameraPos(f1;(param1131) S_ADD_U32 sDst(SGPR271) src0(LITERAL_CONST) src1(0) const: 0x51d # VGPR1309 S_MOV_B64 sDst(SGPR356) src0(EXEC) S_MOV_B32 sDst(SGPR270) src0(LITERAL_CONST) const: 0x557 # VGPR[1367:1369] # Indirect branch to cameraPos(f1;: ??? S_GETPC_B64 sDst(SGPR268) src0(SGPR268) S_ADD_U32 sDst(SGPR268) src0(SGPR268) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR269) src0(SGPR269) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR268) src0(SGPR268) S_MOV_B64 sDst(EXEC) src0(SGPR356) # .lbl110 # 1136: OpFSub: Float: tmp1136 << tmp1124, const106 V_MOV_B32 vDst(VGPR1370) src0(1_0_F) V_SUB_F32 vDst(VGPR1371) src0(VGPR1364) src1(VGPR1370) // VOP2 # OpStore: : tmp1136 >> param1137 V_MOV_B32 vDst(VGPR1310) src0(VGPR1371) # 1138: OpFunctionCall: FloatVector3: targetPos(f1;(param1137) S_ADD_U32 sDst(SGPR277) src0(LITERAL_CONST) src1(0) const: 0x51e # VGPR1310 S_MOV_B64 sDst(SGPR358) src0(EXEC) S_MOV_B32 sDst(SGPR276) src0(LITERAL_CONST) const: 0x55c # VGPR[1372:1374] # Indirect branch to targetPos(f1;: ??? S_GETPC_B64 sDst(SGPR274) src0(SGPR274) S_ADD_U32 sDst(SGPR274) src0(SGPR274) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR275) src0(SGPR275) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR274) src0(SGPR274) S_MOV_B64 sDst(EXEC) src0(SGPR358) # .lbl111 # OpStore: : tmp1124 >> param1139 V_MOV_B32 vDst(VGPR1311) src0(VGPR1364) # 1141: OpFunctionCall: FloatVector3: targetPos(f1;(param1139) S_ADD_U32 sDst(SGPR277) src0(LITERAL_CONST) src1(0) const: 0x51f # VGPR1311 S_MOV_B64 sDst(SGPR360) src0(EXEC) S_MOV_B32 sDst(SGPR276) src0(LITERAL_CONST) const: 0x55f # VGPR[1375:1377] # Indirect branch to targetPos(f1;: ??? S_GETPC_B64 sDst(SGPR274) src0(SGPR274) S_ADD_U32 sDst(SGPR274) src0(SGPR274) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR275) src0(SGPR275) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR274) src0(SGPR274) S_MOV_B64 sDst(EXEC) src0(SGPR360) # .lbl112 # 1143: OpExtInst(SmoothStep): Float: tmp1143 << const523, const671, tmp1129 V_MOV_B32 vDst(VGPR1378) src0(LITERAL_CONST) const: 0x3e99999a V_MOV_B32 vDst(VGPR1379) src0(LITERAL_CONST) const: 0x3f333333 V_CMP_GE_F32 src0(VGPR1378) src1(VGPR1366) # CF Block: Merge: .lbl116 S_MOV_B64 sDst(SGPR362) src0(EXEC) # CF Block: Cond Branch: true: .lbl117, false: .lbl113 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl113 S_BRANCH ??? .lbl117 Label: .lbl117 V_MOV_B32 vDst(VGPR1380) src0(0) S_BRANCH ??? .lbl116 Label: .lbl113 V_CMP_LE_F32 src0(VGPR1379) src1(VGPR1366) # CF Block: Merge: .lbl115 S_MOV_B64 sDst(SGPR364) src0(EXEC) # CF Block: Cond Branch: true: .lbl118, false: .lbl114 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl114 S_BRANCH ??? .lbl118 Label: .lbl118 V_MOV_B32 vDst(VGPR1380) src0(1_0_F) S_BRANCH ??? .lbl115 Label: .lbl114 V_SUBREV_F32 vDst(VGPR1381) src0(VGPR1378) src1(VGPR1379) // VOP2 V_RCP_F32 vDst(VGPR1381) src0(VGPR1381) V_SUBREV_F32 vDst(VGPR1380) src0(VGPR1378) src1(VGPR1366) // VOP2 V_MUL_F32 vDst(VGPR1381) src0(VGPR1380) src1(VGPR1381) // VOP2 V_MAX_F32 vDst(VGPR1381) src0(0) src1(VGPR1381) // VOP2 V_MIN_F32 vDst(VGPR1381) src0(1_0_F) src1(VGPR1381) // VOP2 V_MOV_B32 vDst(VGPR1380) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1380) src0(2_0_F) src1(VGPR1381) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1381) src0(VGPR1381) src1(VGPR1381) // VOP2 V_MUL_F32 vDst(VGPR1380) src0(VGPR1381) src1(VGPR1380) // VOP2 S_BRANCH ??? .lbl115 Label: .lbl115 S_BRANCH ??? .lbl116 Label: .lbl116 # 1144: OpCompositeConstruct: FloatVector3: tmp1144 << tmp1143, tmp1143, tmp1143 V_MOV_B32 vDst(VGPR1382) src0(VGPR1380) V_MOV_B32 vDst(VGPR1383) src0(VGPR1380) V_MOV_B32 vDst(VGPR1384) src0(VGPR1380) # 1145: OpExtInst(FMix): FloatVector3: tmp1145 << targetPos(f1;, targetPos(f1;, tmp1144 V_SUBREV_F32 vDst(VGPR1385) src0(VGPR1382) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1385) src0(VGPR1372) src1(VGPR1385) // VOP2 V_MAD_F32 vDst(VGPR1385) src0(VGPR1375) src1(VGPR1382) src2(VGPR1385) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1386) src0(VGPR1383) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1386) src0(VGPR1373) src1(VGPR1386) // VOP2 V_MAD_F32 vDst(VGPR1386) src0(VGPR1376) src1(VGPR1383) src2(VGPR1386) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1387) src0(VGPR1384) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1387) src0(VGPR1374) src1(VGPR1387) // VOP2 V_MAD_F32 vDst(VGPR1387) src0(VGPR1377) src1(VGPR1384) src2(VGPR1387) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1149: OpFSub: FloatVector3: tmp1149 << tmp1145, cameraPos(f1; V_SUB_F32 vDst(VGPR1388) src0(VGPR1385) src1(VGPR1367) // VOP2 V_SUB_F32 vDst(VGPR1389) src0(VGPR1386) src1(VGPR1368) // VOP2 V_SUB_F32 vDst(VGPR1390) src0(VGPR1387) src1(VGPR1369) // VOP2 # 1150: OpExtInst(Normalize): FloatVector3: tmp1150 << tmp1149 V_MUL_F32 vDst(VGPR1391) src0(VGPR1388) src1(VGPR1388) // VOP2 V_MAC_F32 vDst(VGPR1391) src0(VGPR1389) src1(VGPR1389) // VOP2 V_MAC_F32 vDst(VGPR1391) src0(VGPR1390) src1(VGPR1390) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1391) src0(VGPR1391) V_MUL_F32 vDst(VGPR1392) src0(VGPR1388) src1(VGPR1391) // VOP2 V_MUL_F32 vDst(VGPR1393) src0(VGPR1389) src1(VGPR1391) // VOP2 V_MUL_F32 vDst(VGPR1394) src0(VGPR1390) src1(VGPR1391) // VOP2 # 1154: OpExtInst(Cross): FloatVector3: tmp1154 << tmp1150, const1153 V_MOV_B32 vDst(VGPR1395) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1396) src0(1_0_F) V_MOV_B32 vDst(VGPR1397) src0(LITERAL_CONST) const: 0x00000000 V_MUL_F32 vDst(VGPR1398) src0(VGPR1393) src1(VGPR1397) // VOP2 V_MUL_F32 vDst(VGPR1399) src0(VGPR1394) src1(VGPR1395) // VOP2 V_MUL_F32 vDst(VGPR1400) src0(VGPR1392) src1(VGPR1396) // VOP2 V_MAC_F32 vDst(VGPR1398) src0(VGPR1394) src1(VGPR1396) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1399) src0(VGPR1392) src1(VGPR1397) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1400) src0(VGPR1393) src1(VGPR1395) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 1155: OpExtInst(Normalize): FloatVector3: tmp1155 << tmp1154 V_MUL_F32 vDst(VGPR1401) src0(VGPR1398) src1(VGPR1398) // VOP2 V_MAC_F32 vDst(VGPR1401) src0(VGPR1399) src1(VGPR1399) // VOP2 V_MAC_F32 vDst(VGPR1401) src0(VGPR1400) src1(VGPR1400) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1401) src0(VGPR1401) V_MUL_F32 vDst(VGPR1402) src0(VGPR1398) src1(VGPR1401) // VOP2 V_MUL_F32 vDst(VGPR1403) src0(VGPR1399) src1(VGPR1401) // VOP2 V_MUL_F32 vDst(VGPR1404) src0(VGPR1400) src1(VGPR1401) // VOP2 # OpStore: : tmp1155 >> camu V_MOV_B32 vDst(VGPR1312) src0(VGPR1402) V_MOV_B32 vDst(VGPR1313) src0(VGPR1403) V_MOV_B32 vDst(VGPR1314) src0(VGPR1404) # 1157: OpLoad: FloatVector3: tmp1157 << camu # 1159: OpExtInst(Cross): FloatVector3: tmp1159 << tmp1157, tmp1150 V_MUL_F32 vDst(VGPR1405) src0(VGPR1313) src1(VGPR1394) // VOP2 V_MUL_F32 vDst(VGPR1406) src0(VGPR1314) src1(VGPR1392) // VOP2 V_MUL_F32 vDst(VGPR1407) src0(VGPR1312) src1(VGPR1393) // VOP2 V_MAC_F32 vDst(VGPR1405) src0(VGPR1314) src1(VGPR1393) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1406) src0(VGPR1312) src1(VGPR1394) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1407) src0(VGPR1313) src1(VGPR1392) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 1160: OpExtInst(Normalize): FloatVector3: tmp1160 << tmp1159 V_MUL_F32 vDst(VGPR1408) src0(VGPR1405) src1(VGPR1405) // VOP2 V_MAC_F32 vDst(VGPR1408) src0(VGPR1406) src1(VGPR1406) // VOP2 V_MAC_F32 vDst(VGPR1408) src0(VGPR1407) src1(VGPR1407) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1408) src0(VGPR1408) V_MUL_F32 vDst(VGPR1409) src0(VGPR1405) src1(VGPR1408) // VOP2 V_MUL_F32 vDst(VGPR1410) src0(VGPR1406) src1(VGPR1408) // VOP2 V_MUL_F32 vDst(VGPR1411) src0(VGPR1407) src1(VGPR1408) // VOP2 # 1163: OpExtInst(Cross): FloatVector3: tmp1163 << tmp1150, tmp1160 V_MUL_F32 vDst(VGPR1412) src0(VGPR1393) src1(VGPR1411) // VOP2 V_MUL_F32 vDst(VGPR1413) src0(VGPR1394) src1(VGPR1409) // VOP2 V_MUL_F32 vDst(VGPR1414) src0(VGPR1392) src1(VGPR1410) // VOP2 V_MAC_F32 vDst(VGPR1412) src0(VGPR1394) src1(VGPR1410) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1413) src0(VGPR1392) src1(VGPR1411) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1414) src0(VGPR1393) src1(VGPR1409) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 1164: OpExtInst(Normalize): FloatVector3: tmp1164 << tmp1163 V_MUL_F32 vDst(VGPR1415) src0(VGPR1412) src1(VGPR1412) // VOP2 V_MAC_F32 vDst(VGPR1415) src0(VGPR1413) src1(VGPR1413) // VOP2 V_MAC_F32 vDst(VGPR1415) src0(VGPR1414) src1(VGPR1414) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1415) src0(VGPR1415) V_MUL_F32 vDst(VGPR1416) src0(VGPR1412) src1(VGPR1415) // VOP2 V_MUL_F32 vDst(VGPR1417) src0(VGPR1413) src1(VGPR1415) // VOP2 V_MUL_F32 vDst(VGPR1418) src0(VGPR1414) src1(VGPR1415) // VOP2 # OpStore: : tmp1164 >> camu V_MOV_B32 vDst(VGPR1312) src0(VGPR1416) V_MOV_B32 vDst(VGPR1313) src0(VGPR1417) V_MOV_B32 vDst(VGPR1314) src0(VGPR1418) # 1168: OpLoad: FloatVector3: tmp1168 << camu # 1171: OpCompositeExtract: Float: tmp1171 << tmp1168, 0 V_MOV_B32 vDst(VGPR1419) src0(VGPR1312) # 1172: OpCompositeExtract: Float: tmp1172 << tmp1168, 1 V_MOV_B32 vDst(VGPR1420) src0(VGPR1313) # 1173: OpCompositeExtract: Float: tmp1173 << tmp1168, 2 V_MOV_B32 vDst(VGPR1421) src0(VGPR1314) # 1174: OpCompositeExtract: Float: tmp1174 << tmp1160, 0 V_MOV_B32 vDst(VGPR1422) src0(VGPR1409) # 1175: OpCompositeExtract: Float: tmp1175 << tmp1160, 1 V_MOV_B32 vDst(VGPR1423) src0(VGPR1410) # 1176: OpCompositeExtract: Float: tmp1176 << tmp1160, 2 V_MOV_B32 vDst(VGPR1424) src0(VGPR1411) # 1177: OpCompositeExtract: Float: tmp1177 << tmp1150, 0 V_MOV_B32 vDst(VGPR1425) src0(VGPR1392) # 1178: OpCompositeExtract: Float: tmp1178 << tmp1150, 1 V_MOV_B32 vDst(VGPR1426) src0(VGPR1393) # 1179: OpCompositeExtract: Float: tmp1179 << tmp1150, 2 V_MOV_B32 vDst(VGPR1427) src0(VGPR1394) # 1180: OpCompositeConstruct: FloatVector3: tmp1180 << tmp1171, tmp1172, tmp1173 V_MOV_B32 vDst(VGPR1428) src0(VGPR1419) V_MOV_B32 vDst(VGPR1429) src0(VGPR1420) V_MOV_B32 vDst(VGPR1430) src0(VGPR1421) # 1181: OpCompositeConstruct: FloatVector3: tmp1181 << tmp1174, tmp1175, tmp1176 V_MOV_B32 vDst(VGPR1431) src0(VGPR1422) V_MOV_B32 vDst(VGPR1432) src0(VGPR1423) V_MOV_B32 vDst(VGPR1433) src0(VGPR1424) # 1182: OpCompositeConstruct: FloatVector3: tmp1182 << tmp1177, tmp1178, tmp1179 V_MOV_B32 vDst(VGPR1434) src0(VGPR1425) V_MOV_B32 vDst(VGPR1435) src0(VGPR1426) V_MOV_B32 vDst(VGPR1436) src0(VGPR1427) # 1183: OpCompositeConstruct: FloatMatrix3x3: tmp1183 << tmp1180, tmp1181, tmp1182 V_MOV_B32 vDst(VGPR1437) src0(VGPR1428) V_MOV_B32 vDst(VGPR1438) src0(VGPR1429) V_MOV_B32 vDst(VGPR1439) src0(VGPR1430) V_MOV_B32 vDst(VGPR1440) src0(VGPR1431) V_MOV_B32 vDst(VGPR1441) src0(VGPR1432) V_MOV_B32 vDst(VGPR1442) src0(VGPR1433) V_MOV_B32 vDst(VGPR1443) src0(VGPR1434) V_MOV_B32 vDst(VGPR1444) src0(VGPR1435) V_MOV_B32 vDst(VGPR1445) src0(VGPR1436) # 1185: OpLoad: FloatVector2: tmp1185 << tc # 1186: OpVectorTimesScalar: FloatVector2: tmp1186 << tmp1185, const303 V_MOV_B32 vDst(VGPR1448) src0(0_5_F) V_MUL_F32 vDst(VGPR1446) src0(VGPR1448) src1(VGPR24) // VOP2 V_MUL_F32 vDst(VGPR1447) src0(VGPR1448) src1(VGPR25) // VOP2 # 1187: OpFAdd: FloatVector2: tmp1187 << tmp1186, const391 V_MOV_B32 vDst(VGPR1449) src0(0_5_F) V_MOV_B32 vDst(VGPR1450) src0(0_5_F) V_ADD_F32 vDst(VGPR1451) src0(VGPR1446) src1(VGPR1449) // VOP2 V_ADD_F32 vDst(VGPR1452) src0(VGPR1447) src1(VGPR1450) // VOP2 # 1189: OpLoad: FloatVector2: tmp1189 << tc # OpStore: : tmp1189 >> p V_MOV_B32 vDst(VGPR1315) src0(VGPR24) V_MOV_B32 vDst(VGPR1316) src0(VGPR25) # 1192: OpAccessChain: Float*: iResolution[0] # 1193: OpLoad: Float: tmp1193 << iResolution[0] S_LOAD_DWORD_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR366) S_WAITCNT 0 # 1194: OpAccessChain: Float*: iResolution[1] # 1195: OpLoad: Float: tmp1195 << iResolution[1] S_LOAD_DWORD_IMM offset(8) sBase(SGPR[0:1]) sDst(SGPR367) S_WAITCNT 0 # 1196: OpFDiv: Float: tmp1196 << tmp1193, tmp1195 V_MOV_B32 vDst(VGPR1453) src0(SGPR367) V_RCP_F32 vDst(VGPR1454) src0(VGPR1453) V_MUL_F32 vDst(VGPR1454) src0(SGPR366) src1(VGPR1454) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1454) src0(VGPR1454) src1(VGPR1453) src2(SGPR366) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1197: OpAccessChain: Float*: p[0] # 1198: OpLoad: Float: tmp1198 << p[0] V_MOV_B32 vDst(VGPR1455) src0(VGPR1315) # 1199: OpFMul: Float: tmp1199 << tmp1198, tmp1196 V_MUL_F32 vDst(VGPR1456) src0(VGPR1455) src1(VGPR1454) // VOP2 # 1200: OpAccessChain: Float*: p[0] # OpStore: : tmp1199 >> p[0] V_MOV_B32 vDst(VGPR1315) src0(VGPR1456) # 1203: OpFSub: Float: tmp1203 << tmp1124, const106 V_MOV_B32 vDst(VGPR1457) src0(1_0_F) V_SUB_F32 vDst(VGPR1458) src0(VGPR1364) src1(VGPR1457) // VOP2 # OpStore: : tmp1203 >> param1204 V_MOV_B32 vDst(VGPR1317) src0(VGPR1458) # 1205: OpFunctionCall: Float: cameraZoom(f1;(param1204) S_ADD_U32 sDst(SGPR285) src0(LITERAL_CONST) src1(0) const: 0x525 # VGPR1317 S_MOV_B64 sDst(SGPR368) src0(EXEC) S_MOV_B32 sDst(SGPR284) src0(LITERAL_CONST) const: 0x5b3 # VGPR1459 # Indirect branch to cameraZoom(f1;: ??? S_GETPC_B64 sDst(SGPR282) src0(SGPR282) S_ADD_U32 sDst(SGPR282) src0(SGPR282) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR283) src0(SGPR283) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR282) src0(SGPR282) S_MOV_B64 sDst(EXEC) src0(SGPR368) # .lbl119 # OpStore: : tmp1124 >> param1206 V_MOV_B32 vDst(VGPR1318) src0(VGPR1364) # 1208: OpFunctionCall: Float: cameraZoom(f1;(param1206) S_ADD_U32 sDst(SGPR285) src0(LITERAL_CONST) src1(0) const: 0x526 # VGPR1318 S_MOV_B64 sDst(SGPR370) src0(EXEC) S_MOV_B32 sDst(SGPR284) src0(LITERAL_CONST) const: 0x5b4 # VGPR1460 # Indirect branch to cameraZoom(f1;: ??? S_GETPC_B64 sDst(SGPR282) src0(SGPR282) S_ADD_U32 sDst(SGPR282) src0(SGPR282) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR283) src0(SGPR283) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR282) src0(SGPR282) S_MOV_B64 sDst(EXEC) src0(SGPR370) # .lbl120 # 1210: OpExtInst(SmoothStep): Float: tmp1210 << const671, const435, tmp1129 V_MOV_B32 vDst(VGPR1461) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR1462) src0(LITERAL_CONST) const: 0x3f666666 V_CMP_GE_F32 src0(VGPR1461) src1(VGPR1366) # CF Block: Merge: .lbl124 S_MOV_B64 sDst(SGPR372) src0(EXEC) # CF Block: Cond Branch: true: .lbl125, false: .lbl121 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl121 S_BRANCH ??? .lbl125 Label: .lbl125 V_MOV_B32 vDst(VGPR1463) src0(0) S_BRANCH ??? .lbl124 Label: .lbl121 V_CMP_LE_F32 src0(VGPR1462) src1(VGPR1366) # CF Block: Merge: .lbl123 S_MOV_B64 sDst(SGPR374) src0(EXEC) # CF Block: Cond Branch: true: .lbl126, false: .lbl122 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl122 S_BRANCH ??? .lbl126 Label: .lbl126 V_MOV_B32 vDst(VGPR1463) src0(1_0_F) S_BRANCH ??? .lbl123 Label: .lbl122 V_SUBREV_F32 vDst(VGPR1464) src0(VGPR1461) src1(VGPR1462) // VOP2 V_RCP_F32 vDst(VGPR1464) src0(VGPR1464) V_SUBREV_F32 vDst(VGPR1463) src0(VGPR1461) src1(VGPR1366) // VOP2 V_MUL_F32 vDst(VGPR1464) src0(VGPR1463) src1(VGPR1464) // VOP2 V_MAX_F32 vDst(VGPR1464) src0(0) src1(VGPR1464) // VOP2 V_MIN_F32 vDst(VGPR1464) src0(1_0_F) src1(VGPR1464) // VOP2 V_MOV_B32 vDst(VGPR1463) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1463) src0(2_0_F) src1(VGPR1464) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1464) src0(VGPR1464) src1(VGPR1464) // VOP2 V_MUL_F32 vDst(VGPR1463) src0(VGPR1464) src1(VGPR1463) // VOP2 S_BRANCH ??? .lbl123 Label: .lbl123 S_BRANCH ??? .lbl124 Label: .lbl124 # 1211: OpExtInst(FMix): Float: tmp1211 << cameraZoom(f1;, cameraZoom(f1;, tmp1210 V_SUBREV_F32 vDst(VGPR1465) src0(VGPR1463) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1465) src0(VGPR1459) src1(VGPR1465) // VOP2 V_MAD_F32 vDst(VGPR1465) src0(VGPR1460) src1(VGPR1463) src2(VGPR1465) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1214: OpLoad: FloatVector2: tmp1214 << p # 1216: OpCompositeExtract: Float: tmp1216 << tmp1214, 0 V_MOV_B32 vDst(VGPR1466) src0(VGPR1315) # 1217: OpCompositeExtract: Float: tmp1217 << tmp1214, 1 V_MOV_B32 vDst(VGPR1467) src0(VGPR1316) # 1218: OpCompositeConstruct: FloatVector3: tmp1218 << tmp1216, tmp1217, tmp1211 V_MOV_B32 vDst(VGPR1468) src0(VGPR1466) V_MOV_B32 vDst(VGPR1469) src0(VGPR1467) V_MOV_B32 vDst(VGPR1470) src0(VGPR1465) # 1219: OpExtInst(Normalize): FloatVector3: tmp1219 << tmp1218 V_MUL_F32 vDst(VGPR1471) src0(VGPR1468) src1(VGPR1468) // VOP2 V_MAC_F32 vDst(VGPR1471) src0(VGPR1469) src1(VGPR1469) // VOP2 V_MAC_F32 vDst(VGPR1471) src0(VGPR1470) src1(VGPR1470) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1471) src0(VGPR1471) V_MUL_F32 vDst(VGPR1472) src0(VGPR1468) src1(VGPR1471) // VOP2 V_MUL_F32 vDst(VGPR1473) src0(VGPR1469) src1(VGPR1471) // VOP2 V_MUL_F32 vDst(VGPR1474) src0(VGPR1470) src1(VGPR1471) // VOP2 # 1220: OpMatrixTimesVector: FloatVector3: tmp1220 << tmp1183, tmp1219 V_MUL_F32 vDst(VGPR1475) src0(VGPR1437) src1(VGPR1472) // VOP2 V_MUL_F32 vDst(VGPR1476) src0(VGPR1438) src1(VGPR1472) // VOP2 V_MUL_F32 vDst(VGPR1477) src0(VGPR1439) src1(VGPR1472) // VOP2 V_MAC_F32 vDst(VGPR1475) src0(VGPR1440) src1(VGPR1473) // VOP2 V_MAC_F32 vDst(VGPR1476) src0(VGPR1441) src1(VGPR1473) // VOP2 V_MAC_F32 vDst(VGPR1477) src0(VGPR1442) src1(VGPR1473) // VOP2 V_MAC_F32 vDst(VGPR1475) src0(VGPR1443) src1(VGPR1474) // VOP2 V_MAC_F32 vDst(VGPR1476) src0(VGPR1444) src1(VGPR1474) // VOP2 V_MAC_F32 vDst(VGPR1477) src0(VGPR1445) src1(VGPR1474) // VOP2 # 1222: OpAccessChain: Float*: ro[1] # 1223: OpCompositeExtract: Float: tmp1223 << cameraPos(f1;, 1 V_MOV_B32 vDst(VGPR1478) src0(VGPR1368) # 1224: OpFSub: Float: tmp1224 << const106, tmp1223 V_SUB_F32 vDst(VGPR1479) src0(1_0_F) src1(VGPR1478) // VOP2 # 1225: OpAccessChain: Float*: rd[1] # 1226: OpCompositeExtract: Float: tmp1226 << tmp1220, 1 V_MOV_B32 vDst(VGPR1480) src0(VGPR1476) # 1227: OpFDiv: Float: tmp1227 << tmp1224, tmp1226 V_RCP_F32 vDst(VGPR1481) src0(VGPR1480) V_MUL_F32 vDst(VGPR1481) src0(VGPR1479) src1(VGPR1481) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1481) src0(VGPR1481) src1(VGPR1480) src2(VGPR1479) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1228: OpExtInst(FMax): Float: tmp1228 << const100, tmp1227 V_MOV_B32 vDst(VGPR1482) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR1483) src0(VGPR1482) src1(VGPR1481) // VOP2 # OpStore: : tmp1228 >> t V_MOV_B32 vDst(VGPR1319) src0(VGPR1483) # 1231: OpAccessChain: Float*: ro[1] # 1232: OpCompositeExtract: Float: tmp1232 << cameraPos(f1;, 1 V_MOV_B32 vDst(VGPR1484) src0(VGPR1368) # 1233: OpFSub: Float: tmp1233 << const1230, tmp1232 V_MOV_B32 vDst(VGPR1485) src0(LITERAL_CONST) const: 0xbc23d70a V_SUB_F32 vDst(VGPR1486) src0(VGPR1485) src1(VGPR1484) // VOP2 # 1234: OpAccessChain: Float*: rd[1] # 1235: OpCompositeExtract: Float: tmp1235 << tmp1220, 1 V_MOV_B32 vDst(VGPR1487) src0(VGPR1476) # 1236: OpFDiv: Float: tmp1236 << tmp1233, tmp1235 V_RCP_F32 vDst(VGPR1488) src0(VGPR1487) V_MUL_F32 vDst(VGPR1488) src0(VGPR1486) src1(VGPR1488) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1488) src0(VGPR1488) src1(VGPR1487) src2(VGPR1486) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1237: OpExtInst(FMax): Float: tmp1237 << const100, tmp1236 V_MOV_B32 vDst(VGPR1489) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR1490) src0(VGPR1489) src1(VGPR1488) // VOP2 # OpStore: : cameraPos(f1; >> param1239 V_MOV_B32 vDst(VGPR1323) src0(VGPR1367) V_MOV_B32 vDst(VGPR1324) src0(VGPR1368) V_MOV_B32 vDst(VGPR1325) src0(VGPR1369) # OpStore: : tmp1220 >> param1241 V_MOV_B32 vDst(VGPR1326) src0(VGPR1475) V_MOV_B32 vDst(VGPR1327) src0(VGPR1476) V_MOV_B32 vDst(VGPR1328) src0(VGPR1477) # 1244: OpLoad: Float: tmp1244 << t # OpStore: : tmp1244 >> param1243 V_MOV_B32 vDst(VGPR1329) src0(VGPR1319) # OpStore: : tmp1237 >> param1245 V_MOV_B32 vDst(VGPR1330) src0(VGPR1490) # 1247: OpFunctionCall: FloatVector3: trace(vf3;vf3;f1;f1;(param1239, param1241, param1243, param1245) S_ADD_U32 sDst(SGPR291) src0(LITERAL_CONST) src1(0) const: 0x52b # VGPR[1323:1325] S_ADD_U32 sDst(SGPR292) src0(LITERAL_CONST) src1(0) const: 0x52e # VGPR[1326:1328] S_ADD_U32 sDst(SGPR293) src0(LITERAL_CONST) src1(0) const: 0x531 # VGPR1329 S_ADD_U32 sDst(SGPR294) src0(LITERAL_CONST) src1(0) const: 0x532 # VGPR1330 S_MOV_B64 sDst(SGPR376) src0(EXEC) S_MOV_B32 sDst(SGPR290) src0(LITERAL_CONST) const: 0x5d3 # VGPR[1491:1493] # Indirect branch to trace(vf3;vf3;f1;f1;: ??? S_GETPC_B64 sDst(SGPR288) src0(SGPR288) S_ADD_U32 sDst(SGPR288) src0(SGPR288) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR289) src0(SGPR289) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR288) src0(SGPR288) S_MOV_B64 sDst(EXEC) src0(SGPR376) # .lbl127 # 1248: OpLoad: Float: tmp1248 << param1243 # OpStore: : tmp1248 >> t V_MOV_B32 vDst(VGPR1319) src0(VGPR1329) # OpStore: : trace(vf3;vf3;f1;f1; >> col V_MOV_B32 vDst(VGPR1320) src0(VGPR1491) V_MOV_B32 vDst(VGPR1321) src0(VGPR1492) V_MOV_B32 vDst(VGPR1322) src0(VGPR1493) # 1252: OpLoad: Float: tmp1252 << t # 1253: OpVectorTimesScalar: FloatVector3: tmp1253 << tmp1220, tmp1252 V_MUL_F32 vDst(VGPR1494) src0(VGPR1319) src1(VGPR1475) // VOP2 V_MUL_F32 vDst(VGPR1495) src0(VGPR1319) src1(VGPR1476) // VOP2 V_MUL_F32 vDst(VGPR1496) src0(VGPR1319) src1(VGPR1477) // VOP2 # 1254: OpFAdd: FloatVector3: tmp1254 << cameraPos(f1;, tmp1253 V_ADD_F32 vDst(VGPR1497) src0(VGPR1367) src1(VGPR1494) // VOP2 V_ADD_F32 vDst(VGPR1498) src0(VGPR1368) src1(VGPR1495) // VOP2 V_ADD_F32 vDst(VGPR1499) src0(VGPR1369) src1(VGPR1496) // VOP2 # 1255: OpAccessChain: Float*: rp[1] # 1256: OpCompositeExtract: Float: tmp1256 << tmp1254, 1 V_MOV_B32 vDst(VGPR1500) src0(VGPR1498) # 1257: OpFMul: Float: tmp1257 << tmp1256, const127 V_MOV_B32 vDst(VGPR1501) src0(2_0_F) V_MUL_F32 vDst(VGPR1502) src0(VGPR1500) src1(VGPR1501) // VOP2 # 1258: OpExtInst(FClamp): Float: tmp1258 << tmp1257, const100, const106 V_MOV_B32 vDst(VGPR1503) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1504) src0(1_0_F) V_MAX_F32 vDst(VGPR1505) src0(VGPR1502) src1(VGPR1503) // VOP2 V_MIN_F32 vDst(VGPR1505) src0(VGPR1505) src1(VGPR1504) // VOP2 # OpStore: : tmp1258 >> icing_factor V_MOV_B32 vDst(VGPR43) src0(VGPR1505) # 1259: OpLoad: Float: tmp1259 << t # 1260: OpFOrdGreaterThan: Bool: tmp1260 << tmp1259, const100 V_MOV_B32 vDst(VGPR1506) src0(LITERAL_CONST) const: 0x00000000 V_CMP_GT_F32 dst(SGPR378) src0(VGPR1319) src1(VGPR1506) // VOP3a # 1262: OpLoad: Float: tmp1262 << t # 1263: OpFOrdLessThan: Bool: tmp1263 << tmp1237, tmp1262 V_CMP_LT_F32 dst(SGPR380) src0(VGPR1490) src1(VGPR1319) // VOP3a # 1264: OpLogicalAnd: Bool: tmp1264 << tmp1260, tmp1263 S_AND_B64 sDst(SGPR382) src0(SGPR378) src1(SGPR380) # OpSelectionMerge: (merge: lb1266) # CF Block: Merge: lb1266 S_MOV_B64 sDst(SGPR384) src0(EXEC) # OpBranchConditional: if(tmp1264) then branch to lb1265, else branch to lb1266 # CF Block: Cond Branch: true: lb1265, false: lb1266 S_AND_B64 sDst(EXEC) src0(SGPR382) src1(EXEC) S_CBRANCH_EXECZ ??? lb1266 S_BRANCH ??? lb1265 # lb1265 Label: lb1265 # 1269: OpVectorShuffle: FloatVector2: tmp1269 << cameraPos(f1;, cameraPos(f1;, 0, 2 V_MOV_B32 vDst(VGPR1507) src0(VGPR1367) V_MOV_B32 vDst(VGPR1508) src0(VGPR1369) # 1271: OpVectorShuffle: FloatVector2: tmp1271 << tmp1220, tmp1220, 0, 2 V_MOV_B32 vDst(VGPR1509) src0(VGPR1475) V_MOV_B32 vDst(VGPR1510) src0(VGPR1477) # 1273: OpVectorTimesScalar: FloatVector2: tmp1273 << tmp1271, tmp1237 V_MUL_F32 vDst(VGPR1511) src0(VGPR1490) src1(VGPR1509) // VOP2 V_MUL_F32 vDst(VGPR1512) src0(VGPR1490) src1(VGPR1510) // VOP2 # 1274: OpFAdd: FloatVector2: tmp1274 << tmp1269, tmp1273 V_ADD_F32 vDst(VGPR1513) src0(VGPR1507) src1(VGPR1511) // VOP2 V_ADD_F32 vDst(VGPR1514) src0(VGPR1508) src1(VGPR1512) // VOP2 # OpStore: : tmp1274 >> c V_MOV_B32 vDst(VGPR1331) src0(VGPR1513) V_MOV_B32 vDst(VGPR1332) src0(VGPR1514) # 1276: OpLoad: FloatVector2: tmp1276 << c # 1277: OpVectorTimesScalar: FloatVector2: tmp1277 << tmp1276, const151 V_MOV_B32 vDst(VGPR1517) src0(LITERAL_CONST) const: 0x3f4ccccd V_MUL_F32 vDst(VGPR1515) src0(VGPR1517) src1(VGPR1331) // VOP2 V_MUL_F32 vDst(VGPR1516) src0(VGPR1517) src1(VGPR1332) // VOP2 # 1279: OpAccessChain: Float*: xc[0] # 1280: OpCompositeExtract: Float: tmp1280 << tmp1277, 0 V_MOV_B32 vDst(VGPR1518) src0(VGPR1515) # 1281: OpAccessChain: Float*: xc[1] # 1282: OpCompositeExtract: Float: tmp1282 << tmp1277, 1 V_MOV_B32 vDst(VGPR1519) src0(VGPR1516) # 1283: OpExtInst(Fract): Float: tmp1283 << tmp1282 V_FRACT_F32 vDst(VGPR1520) src0(VGPR1519) # 1284: OpExtInst(Step): Float: tmp1284 << const303, tmp1283 V_CMP_GT_F32 src0(0_5_F) src1(VGPR1520) # CF Block: Merge: .lbl129 S_MOV_B64 sDst(SGPR386) src0(EXEC) # CF Block: Cond Branch: true: .lbl130, false: .lbl128 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl128 S_BRANCH ??? .lbl130 Label: .lbl130 V_MOV_B32 vDst(VGPR1521) src0(0) S_BRANCH ??? .lbl129 Label: .lbl128 V_MOV_B32 vDst(VGPR1521) src0(1_0_F) S_BRANCH ??? .lbl129 Label: .lbl129 # 1285: OpFMul: Float: tmp1285 << const303, tmp1284 V_MUL_F32 vDst(VGPR1522) src0(0_5_F) src1(VGPR1521) // VOP2 # 1286: OpFAdd: Float: tmp1286 << tmp1280, tmp1285 V_ADD_F32 vDst(VGPR1523) src0(VGPR1518) src1(VGPR1522) // VOP2 # 1287: OpExtInst(Fract): Float: tmp1287 << tmp1286 V_FRACT_F32 vDst(VGPR1524) src0(VGPR1523) # 1288: OpExtInst(Step): Float: tmp1288 << const303, tmp1287 V_CMP_GT_F32 src0(0_5_F) src1(VGPR1524) # CF Block: Merge: .lbl132 S_MOV_B64 sDst(SGPR388) src0(EXEC) # CF Block: Cond Branch: true: .lbl133, false: .lbl131 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl131 S_BRANCH ??? .lbl133 Label: .lbl133 V_MOV_B32 vDst(VGPR1525) src0(0) S_BRANCH ??? .lbl132 Label: .lbl131 V_MOV_B32 vDst(VGPR1525) src0(1_0_F) S_BRANCH ??? .lbl132 Label: .lbl132 # 1294: OpCompositeConstruct: FloatVector3: tmp1294 << tmp1288, tmp1288, tmp1288 V_MOV_B32 vDst(VGPR1526) src0(VGPR1525) V_MOV_B32 vDst(VGPR1527) src0(VGPR1525) V_MOV_B32 vDst(VGPR1528) src0(VGPR1525) # 1295: OpExtInst(FMix): FloatVector3: tmp1295 << const1290, const1292, tmp1294 V_MOV_B32 vDst(VGPR1529) src0(1_0_F) V_MOV_B32 vDst(VGPR1530) src0(1_0_F) V_MOV_B32 vDst(VGPR1531) src0(1_0_F) V_MOV_B32 vDst(VGPR1532) src0(0_5_F) V_MOV_B32 vDst(VGPR1533) src0(0_5_F) V_MOV_B32 vDst(VGPR1534) src0(LITERAL_CONST) const: 0x3e800000 V_SUBREV_F32 vDst(VGPR1535) src0(VGPR1526) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1535) src0(VGPR1529) src1(VGPR1535) // VOP2 V_MAD_F32 vDst(VGPR1535) src0(VGPR1532) src1(VGPR1526) src2(VGPR1535) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1536) src0(VGPR1527) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1536) src0(VGPR1530) src1(VGPR1536) // VOP2 V_MAD_F32 vDst(VGPR1536) src0(VGPR1533) src1(VGPR1527) src2(VGPR1536) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1537) src0(VGPR1528) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1537) src0(VGPR1531) src1(VGPR1537) // VOP2 V_MAD_F32 vDst(VGPR1537) src0(VGPR1534) src1(VGPR1528) src2(VGPR1537) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1295 >> cc V_MOV_B32 vDst(VGPR1333) src0(VGPR1535) V_MOV_B32 vDst(VGPR1334) src0(VGPR1536) V_MOV_B32 vDst(VGPR1335) src0(VGPR1537) # 1296: OpLoad: FloatVector3: tmp1296 << cc # 1299: OpVectorTimesScalar: FloatVector2: tmp1299 << tmp1277, const621 V_MOV_B32 vDst(VGPR1540) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR1538) src0(VGPR1540) src1(VGPR1515) // VOP2 V_MUL_F32 vDst(VGPR1539) src0(VGPR1540) src1(VGPR1516) // VOP2 # 1300: OpAccessChain: Float*: xc[1] # 1301: OpCompositeExtract: Float: tmp1301 << tmp1277, 1 V_MOV_B32 vDst(VGPR1541) src0(VGPR1516) # 1302: OpFMul: Float: tmp1302 << tmp1301, const127 V_MOV_B32 vDst(VGPR1542) src0(2_0_F) V_MUL_F32 vDst(VGPR1543) src0(VGPR1541) src1(VGPR1542) // VOP2 # 1303: OpExtInst(Cos): Float: tmp1303 << tmp1302 V_MUL_F32 vDst(VGPR1544) src0(LITERAL_CONST) src1(VGPR1543) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR1544) src0(VGPR1544) V_COS_F32 vDst(VGPR1544) src0(VGPR1544) # 1304: OpFMul: Float: tmp1304 << tmp1303, const109 V_MOV_B32 vDst(VGPR1545) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR1546) src0(VGPR1544) src1(VGPR1545) // VOP2 # 1305: OpAccessChain: Float*: xc[0] # 1306: OpCompositeExtract: Float: tmp1306 << tmp1277, 0 V_MOV_B32 vDst(VGPR1547) src0(VGPR1515) # 1307: OpFMul: Float: tmp1307 << tmp1306, const106 V_MOV_B32 vDst(VGPR1548) src0(1_0_F) V_MUL_F32 vDst(VGPR1549) src0(VGPR1547) src1(VGPR1548) // VOP2 # 1308: OpExtInst(Cos): Float: tmp1308 << tmp1307 V_MUL_F32 vDst(VGPR1550) src0(LITERAL_CONST) src1(VGPR1549) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR1550) src0(VGPR1550) V_COS_F32 vDst(VGPR1550) src0(VGPR1550) # 1309: OpFMul: Float: tmp1309 << tmp1308, const377 V_MOV_B32 vDst(VGPR1551) src0(4_0_F) V_MUL_F32 vDst(VGPR1552) src0(VGPR1550) src1(VGPR1551) // VOP2 # 1310: OpCompositeConstruct: FloatVector2: tmp1310 << tmp1304, tmp1309 V_MOV_B32 vDst(VGPR1553) src0(VGPR1546) V_MOV_B32 vDst(VGPR1554) src0(VGPR1552) # 1311: OpFAdd: FloatVector2: tmp1311 << tmp1299, tmp1310 V_ADD_F32 vDst(VGPR1555) src0(VGPR1538) src1(VGPR1553) // VOP2 V_ADD_F32 vDst(VGPR1556) src0(VGPR1539) src1(VGPR1554) // VOP2 # OpStore: : tmp1311 >> param1312 V_MOV_B32 vDst(VGPR1336) src0(VGPR1555) V_MOV_B32 vDst(VGPR1337) src0(VGPR1556) # 1313: OpFunctionCall: Float: smN2(vf2;(param1312) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x538 # VGPR[1336:1337] S_MOV_B64 sDst(SGPR390) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x615 # VGPR1557 # Indirect branch to smN2(vf2;: ??? S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_ADD_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR390) # .lbl134 # 1314: OpFMul: Float: tmp1314 << const303, smN2(vf2; V_MUL_F32 vDst(VGPR1558) src0(0_5_F) src1(VGPR1557) // VOP2 # 1315: OpFAdd: Float: tmp1315 << const523, tmp1314 V_MOV_B32 vDst(VGPR1559) src0(LITERAL_CONST) const: 0x3e99999a V_ADD_F32 vDst(VGPR1560) src0(VGPR1559) src1(VGPR1558) // VOP2 # 1316: OpExtInst(Pow): Float: tmp1316 << tmp1315, const377 V_MOV_B32 vDst(VGPR1561) src0(4_0_F) V_LOG_F32 vDst(VGPR1562) src0(VGPR1560) V_MUL_F32 vDst(VGPR1562) src0(VGPR1561) src1(VGPR1562) // VOP2 V_EXP_F32 vDst(VGPR1562) src0(VGPR1562) # 1317: OpCompositeConstruct: FloatVector3: tmp1317 << tmp1316, tmp1316, tmp1316 V_MOV_B32 vDst(VGPR1563) src0(VGPR1562) V_MOV_B32 vDst(VGPR1564) src0(VGPR1562) V_MOV_B32 vDst(VGPR1565) src0(VGPR1562) # 1318: OpExtInst(FMix): FloatVector3: tmp1318 << tmp1296, const1297, tmp1317 V_MOV_B32 vDst(VGPR1566) src0(LITERAL_CONST) const: 0x3f666666 V_MOV_B32 vDst(VGPR1567) src0(LITERAL_CONST) const: 0x3f666666 V_MOV_B32 vDst(VGPR1568) src0(0_5_F) V_SUBREV_F32 vDst(VGPR1569) src0(VGPR1563) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1569) src0(VGPR1333) src1(VGPR1569) // VOP2 V_MAD_F32 vDst(VGPR1569) src0(VGPR1566) src1(VGPR1563) src2(VGPR1569) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1570) src0(VGPR1564) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1570) src0(VGPR1334) src1(VGPR1570) // VOP2 V_MAD_F32 vDst(VGPR1570) src0(VGPR1567) src1(VGPR1564) src2(VGPR1570) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1571) src0(VGPR1565) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1571) src0(VGPR1335) src1(VGPR1571) // VOP2 V_MAD_F32 vDst(VGPR1571) src0(VGPR1568) src1(VGPR1565) src2(VGPR1571) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1318 >> cc V_MOV_B32 vDst(VGPR1333) src0(VGPR1569) V_MOV_B32 vDst(VGPR1334) src0(VGPR1570) V_MOV_B32 vDst(VGPR1335) src0(VGPR1571) # 1320: OpLoad: FloatVector3: tmp1320 << l # 1322: OpFSub: FloatVector3: tmp1322 << tmp1320, tmp1220 V_SUB_F32 vDst(VGPR1572) src0(VGPR37) src1(VGPR1475) // VOP2 V_SUB_F32 vDst(VGPR1573) src0(VGPR38) src1(VGPR1476) // VOP2 V_SUB_F32 vDst(VGPR1574) src0(VGPR39) src1(VGPR1477) // VOP2 # 1323: OpExtInst(Normalize): FloatVector3: tmp1323 << tmp1322 V_MUL_F32 vDst(VGPR1575) src0(VGPR1572) src1(VGPR1572) // VOP2 V_MAC_F32 vDst(VGPR1575) src0(VGPR1573) src1(VGPR1573) // VOP2 V_MAC_F32 vDst(VGPR1575) src0(VGPR1574) src1(VGPR1574) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1575) src0(VGPR1575) V_MUL_F32 vDst(VGPR1576) src0(VGPR1572) src1(VGPR1575) // VOP2 V_MUL_F32 vDst(VGPR1577) src0(VGPR1573) src1(VGPR1575) // VOP2 V_MUL_F32 vDst(VGPR1578) src0(VGPR1574) src1(VGPR1575) // VOP2 # 1326: OpExtInst(Reflect): FloatVector3: tmp1326 << tmp1220, const1153 V_MOV_B32 vDst(VGPR1579) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1580) src0(1_0_F) V_MOV_B32 vDst(VGPR1581) src0(LITERAL_CONST) const: 0x00000000 V_MUL_F32 vDst(VGPR1585) src0(VGPR1475) src1(VGPR1579) // VOP2 V_MAC_F32 vDst(VGPR1585) src0(VGPR1476) src1(VGPR1580) // VOP2 V_MAC_F32 vDst(VGPR1585) src0(VGPR1477) src1(VGPR1581) // VOP2 V_MUL_F32 vDst(VGPR1585) src0(2_0_F) src1(VGPR1585) // VOP2 V_MUL_F32 vDst(VGPR1582) src0(VGPR1579) src1(VGPR1585) // VOP2 V_MUL_F32 vDst(VGPR1583) src0(VGPR1580) src1(VGPR1585) // VOP2 V_MUL_F32 vDst(VGPR1584) src0(VGPR1581) src1(VGPR1585) // VOP2 V_SUB_F32 vDst(VGPR1582) src0(VGPR1475) src1(VGPR1582) // VOP2 V_SUB_F32 vDst(VGPR1583) src0(VGPR1476) src1(VGPR1583) // VOP2 V_SUB_F32 vDst(VGPR1584) src0(VGPR1477) src1(VGPR1584) // VOP2 # 1329: OpVectorTimesScalar: FloatVector2: tmp1329 << tmp1277, const303 V_MOV_B32 vDst(VGPR1588) src0(0_5_F) V_MUL_F32 vDst(VGPR1586) src0(VGPR1588) src1(VGPR1515) // VOP2 V_MUL_F32 vDst(VGPR1587) src0(VGPR1588) src1(VGPR1516) // VOP2 # OpStore: : const127 >> param1330 V_MOV_B32 vDst(VGPR1338) src0(2_0_F) # OpStore: : tmp1329 >> param1331 V_MOV_B32 vDst(VGPR1339) src0(VGPR1586) V_MOV_B32 vDst(VGPR1340) src0(VGPR1587) # 1332: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param1330, param1331) S_ADD_U32 sDst(SGPR123) src0(LITERAL_CONST) src1(0) const: 0x53a # VGPR1338 S_ADD_U32 sDst(SGPR124) src0(LITERAL_CONST) src1(0) const: 0x53b # VGPR[1339:1340] S_MOV_B64 sDst(SGPR392) src0(EXEC) S_MOV_B32 sDst(SGPR122) src0(LITERAL_CONST) const: 0x635 # VGPR[1589:1590] # Indirect branch to rotate(f1;vf2;: ??? S_GETPC_B64 sDst(SGPR120) src0(SGPR120) S_ADD_U32 sDst(SGPR120) src0(SGPR120) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR121) src0(SGPR121) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR120) src0(SGPR120) S_MOV_B64 sDst(EXEC) src0(SGPR392) # .lbl135 # OpStore: : rotate(f1;vf2; >> param1333 V_MOV_B32 vDst(VGPR1341) src0(VGPR1589) V_MOV_B32 vDst(VGPR1342) src0(VGPR1590) # 1334: OpFunctionCall: FloatVector3: marble(vf2;(param1333) S_ADD_U32 sDst(SGPR233) src0(LITERAL_CONST) src1(0) const: 0x53d # VGPR[1341:1342] S_MOV_B64 sDst(SGPR394) src0(EXEC) S_MOV_B32 sDst(SGPR232) src0(LITERAL_CONST) const: 0x637 # VGPR[1591:1593] # Indirect branch to marble(vf2;: ??? S_GETPC_B64 sDst(SGPR230) src0(SGPR230) S_ADD_U32 sDst(SGPR230) src0(SGPR230) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR231) src0(SGPR231) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR230) src0(SGPR230) S_MOV_B64 sDst(EXEC) src0(SGPR394) # .lbl136 # OpStore: : marble(vf2; >> cc V_MOV_B32 vDst(VGPR1333) src0(VGPR1591) V_MOV_B32 vDst(VGPR1334) src0(VGPR1592) V_MOV_B32 vDst(VGPR1335) src0(VGPR1593) # 1335: OpLoad: FloatVector2: tmp1335 << c # 1336: OpCompositeConstruct: FloatVector2: tmp1336 << const109, const109 V_MOV_B32 vDst(VGPR1596) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR1594) src0(VGPR1596) V_MOV_B32 vDst(VGPR1597) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR1595) src0(VGPR1597) # 1337: OpFDiv: FloatVector2: tmp1337 << tmp1335, tmp1336 V_RCP_F32 vDst(VGPR1598) src0(VGPR1594) V_RCP_F32 vDst(VGPR1599) src0(VGPR1595) V_MUL_F32 vDst(VGPR1598) src0(VGPR1331) src1(VGPR1598) // VOP2 V_MUL_F32 vDst(VGPR1599) src0(VGPR1332) src1(VGPR1599) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1598) src0(VGPR1598) src1(VGPR1594) src2(VGPR1331) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR1599) src0(VGPR1599) src1(VGPR1595) src2(VGPR1332) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1338: OpExtInst(Fract): FloatVector2: tmp1338 << tmp1337 V_FRACT_F32 vDst(VGPR1600) src0(VGPR1598) V_FRACT_F32 vDst(VGPR1601) src0(VGPR1599) # OpStore: : tmp1338 >> c V_MOV_B32 vDst(VGPR1331) src0(VGPR1600) V_MOV_B32 vDst(VGPR1332) src0(VGPR1601) # 1339: OpLoad: FloatVector3: tmp1339 << cc # 1340: OpVectorTimesScalar: FloatVector3: tmp1340 << tmp1339, const151 V_MOV_B32 vDst(VGPR1605) src0(LITERAL_CONST) const: 0x3f4ccccd V_MUL_F32 vDst(VGPR1602) src0(VGPR1605) src1(VGPR1333) // VOP2 V_MUL_F32 vDst(VGPR1603) src0(VGPR1605) src1(VGPR1334) // VOP2 V_MUL_F32 vDst(VGPR1604) src0(VGPR1605) src1(VGPR1335) // VOP2 # 1342: OpLoad: Float: tmp1342 << colour # OpStore: : tmp1342 >> param1341 V_MOV_B32 vDst(VGPR1343) src0(VGPR30) # 1343: OpFunctionCall: FloatVector3: gumColour(f1;(param1341) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x53f # VGPR1343 S_MOV_B64 sDst(SGPR396) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x646 # VGPR[1606:1608] # Indirect branch to gumColour(f1;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR396) # .lbl137 # 1344: OpVectorTimesScalar: FloatVector3: tmp1344 << gumColour(f1;, const127 V_MOV_B32 vDst(VGPR1612) src0(2_0_F) V_MUL_F32 vDst(VGPR1609) src0(VGPR1612) src1(VGPR1606) // VOP2 V_MUL_F32 vDst(VGPR1610) src0(VGPR1612) src1(VGPR1607) // VOP2 V_MUL_F32 vDst(VGPR1611) src0(VGPR1612) src1(VGPR1608) // VOP2 # 1345: OpLoad: Float: tmp1345 << is_choc # 1346: OpVectorTimesScalar: FloatVector3: tmp1346 << tmp1344, tmp1345 V_MUL_F32 vDst(VGPR1613) src0(VGPR33) src1(VGPR1609) // VOP2 V_MUL_F32 vDst(VGPR1614) src0(VGPR33) src1(VGPR1610) // VOP2 V_MUL_F32 vDst(VGPR1615) src0(VGPR33) src1(VGPR1611) // VOP2 # 1349: OpLoad: FloatVector2: tmp1349 << c # 1350: OpExtInst(Distance): Float: tmp1350 << const391, tmp1349 V_MOV_B32 vDst(VGPR1616) src0(0_5_F) V_MOV_B32 vDst(VGPR1617) src0(0_5_F) V_SUB_F32 vDst(VGPR1618) src0(VGPR1616) src1(VGPR1331) // VOP2 V_SUB_F32 vDst(VGPR1619) src0(VGPR1617) src1(VGPR1332) // VOP2 V_MUL_F32 vDst(VGPR1620) src0(VGPR1618) src1(VGPR1618) // VOP2 V_MAC_F32 vDst(VGPR1620) src0(VGPR1619) src1(VGPR1619) // VOP2 V_SQRT_F32 vDst(VGPR1620) src0(VGPR1620) # 1351: OpLoad: Float: tmp1351 << ss # 1352: OpFDiv: Float: tmp1352 << tmp1350, tmp1351 V_RCP_F32 vDst(VGPR1621) src0(VGPR32) V_MUL_F32 vDst(VGPR1621) src0(VGPR1620) src1(VGPR1621) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1621) src0(VGPR1621) src1(VGPR32) src2(VGPR1620) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1353: OpExtInst(SmoothStep): Float: tmp1353 << const1347, const1348, tmp1352 V_MOV_B32 vDst(VGPR1622) src0(LITERAL_CONST) const: 0x3ea8f5c3 V_MOV_B32 vDst(VGPR1623) src0(LITERAL_CONST) const: 0x3f07ae14 V_CMP_GE_F32 src0(VGPR1622) src1(VGPR1621) # CF Block: Merge: .lbl141 S_MOV_B64 sDst(SGPR398) src0(EXEC) # CF Block: Cond Branch: true: .lbl142, false: .lbl138 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl138 S_BRANCH ??? .lbl142 Label: .lbl142 V_MOV_B32 vDst(VGPR1624) src0(0) S_BRANCH ??? .lbl141 Label: .lbl138 V_CMP_LE_F32 src0(VGPR1623) src1(VGPR1621) # CF Block: Merge: .lbl140 S_MOV_B64 sDst(SGPR400) src0(EXEC) # CF Block: Cond Branch: true: .lbl143, false: .lbl139 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl139 S_BRANCH ??? .lbl143 Label: .lbl143 V_MOV_B32 vDst(VGPR1624) src0(1_0_F) S_BRANCH ??? .lbl140 Label: .lbl139 V_SUBREV_F32 vDst(VGPR1625) src0(VGPR1622) src1(VGPR1623) // VOP2 V_RCP_F32 vDst(VGPR1625) src0(VGPR1625) V_SUBREV_F32 vDst(VGPR1624) src0(VGPR1622) src1(VGPR1621) // VOP2 V_MUL_F32 vDst(VGPR1625) src0(VGPR1624) src1(VGPR1625) // VOP2 V_MAX_F32 vDst(VGPR1625) src0(0) src1(VGPR1625) // VOP2 V_MIN_F32 vDst(VGPR1625) src0(1_0_F) src1(VGPR1625) // VOP2 V_MOV_B32 vDst(VGPR1624) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1624) src0(2_0_F) src1(VGPR1625) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1625) src0(VGPR1625) src1(VGPR1625) // VOP2 V_MUL_F32 vDst(VGPR1624) src0(VGPR1625) src1(VGPR1624) // VOP2 S_BRANCH ??? .lbl140 Label: .lbl140 S_BRANCH ??? .lbl141 Label: .lbl141 # 1354: OpCompositeConstruct: FloatVector3: tmp1354 << tmp1353, tmp1353, tmp1353 V_MOV_B32 vDst(VGPR1626) src0(VGPR1624) V_MOV_B32 vDst(VGPR1627) src0(VGPR1624) V_MOV_B32 vDst(VGPR1628) src0(VGPR1624) # 1355: OpExtInst(FMix): FloatVector3: tmp1355 << tmp1346, const1290, tmp1354 V_MOV_B32 vDst(VGPR1629) src0(1_0_F) V_MOV_B32 vDst(VGPR1630) src0(1_0_F) V_MOV_B32 vDst(VGPR1631) src0(1_0_F) V_SUBREV_F32 vDst(VGPR1632) src0(VGPR1626) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1632) src0(VGPR1613) src1(VGPR1632) // VOP2 V_MAD_F32 vDst(VGPR1632) src0(VGPR1629) src1(VGPR1626) src2(VGPR1632) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1633) src0(VGPR1627) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1633) src0(VGPR1614) src1(VGPR1633) // VOP2 V_MAD_F32 vDst(VGPR1633) src0(VGPR1630) src1(VGPR1627) src2(VGPR1633) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1634) src0(VGPR1628) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1634) src0(VGPR1615) src1(VGPR1634) // VOP2 V_MAD_F32 vDst(VGPR1634) src0(VGPR1631) src1(VGPR1628) src2(VGPR1634) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1356: OpFMul: FloatVector3: tmp1356 << tmp1340, tmp1355 V_MUL_F32 vDst(VGPR1635) src0(VGPR1602) src1(VGPR1632) // VOP2 V_MUL_F32 vDst(VGPR1636) src0(VGPR1603) src1(VGPR1633) // VOP2 V_MUL_F32 vDst(VGPR1637) src0(VGPR1604) src1(VGPR1634) // VOP2 # OpStore: : tmp1356 >> col V_MOV_B32 vDst(VGPR1320) src0(VGPR1635) V_MOV_B32 vDst(VGPR1321) src0(VGPR1636) V_MOV_B32 vDst(VGPR1322) src0(VGPR1637) # OpStore: : const106 >> icing_factor V_MOV_B32 vDst(VGPR43) src0(1_0_F) # OpBranch: to lb1266 S_BRANCH ??? lb1266 # lb1266 Label: lb1266 # 1360: OpAccessChain: Float*: iMouse[0] # 1361: OpLoad: Float: tmp1361 << iMouse[0] S_LOAD_DWORD_IMM offset(16) sBase(SGPR[0:1]) sDst(SGPR402) S_WAITCNT 0 # 1362: OpAccessChain: Float*: iResolution[0] # 1363: OpLoad: Float: tmp1363 << iResolution[0] S_LOAD_DWORD_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR403) S_WAITCNT 0 # 1364: OpFDiv: Float: tmp1364 << tmp1361, tmp1363 V_MOV_B32 vDst(VGPR1638) src0(SGPR403) V_RCP_F32 vDst(VGPR1639) src0(VGPR1638) V_MUL_F32 vDst(VGPR1639) src0(SGPR402) src1(VGPR1639) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1639) src0(VGPR1639) src1(VGPR1638) src2(SGPR402) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1365: OpLoad: Float: tmp1365 << icing_factor # 1366: OpFMul: Float: tmp1366 << tmp1364, tmp1365 V_MUL_F32 vDst(VGPR1640) src0(VGPR1639) src1(VGPR43) // VOP2 # 1367: OpFSub: Float: tmp1367 << const106, tmp1366 V_SUB_F32 vDst(VGPR1641) src0(1_0_F) src1(VGPR1640) // VOP2 # 1368: OpLoad: FloatVector3: tmp1368 << col # 1371: OpFMul: Float: tmp1371 << const1369, tmp1367 V_MOV_B32 vDst(VGPR1642) src0(LITERAL_CONST) const: 0xbe800000 V_MUL_F32 vDst(VGPR1643) src0(VGPR1642) src1(VGPR1641) // VOP2 # 1373: OpFAdd: Float: tmp1373 << tmp1371, const1372 V_MOV_B32 vDst(VGPR1644) src0(LITERAL_CONST) const: 0x3eb33333 V_ADD_F32 vDst(VGPR1645) src0(VGPR1643) src1(VGPR1644) // VOP2 # 1375: OpVectorShuffle: FloatVector2: tmp1375 << tmp1254, tmp1254, 0, 2 V_MOV_B32 vDst(VGPR1646) src0(VGPR1497) V_MOV_B32 vDst(VGPR1647) src0(VGPR1499) # 1377: OpVectorTimesScalar: FloatVector2: tmp1377 << tmp1375, const1376 V_MOV_B32 vDst(VGPR1650) src0(LITERAL_CONST) const: 0x40866666 V_MUL_F32 vDst(VGPR1648) src0(VGPR1650) src1(VGPR1646) // VOP2 V_MUL_F32 vDst(VGPR1649) src0(VGPR1650) src1(VGPR1647) // VOP2 # 1378: OpCompositeExtract: Float: tmp1378 << tmp1377, 0 V_MOV_B32 vDst(VGPR1651) src0(VGPR1648) # 1379: OpCompositeExtract: Float: tmp1379 << tmp1377, 1 V_MOV_B32 vDst(VGPR1652) src0(VGPR1649) # 1380: OpCompositeConstruct: FloatVector3: tmp1380 << tmp1378, tmp1379, const100 V_MOV_B32 vDst(VGPR1653) src0(VGPR1651) V_MOV_B32 vDst(VGPR1654) src0(VGPR1652) V_MOV_B32 vDst(VGPR1656) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1655) src0(VGPR1656) # OpStore: : tmp1380 >> param1381 V_MOV_B32 vDst(VGPR1344) src0(VGPR1653) V_MOV_B32 vDst(VGPR1345) src0(VGPR1654) V_MOV_B32 vDst(VGPR1346) src0(VGPR1655) # 1382: OpFunctionCall: Float: fbm3(vf3;(param1381) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x540 # VGPR[1344:1346] S_MOV_B64 sDst(SGPR404) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x679 # VGPR1657 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR404) # .lbl144 # 1383: OpFAdd: Float: tmp1383 << tmp1373, fbm3(vf3; V_ADD_F32 vDst(VGPR1658) src0(VGPR1645) src1(VGPR1657) // VOP2 # 1384: OpExtInst(SmoothStep): Float: tmp1384 << const303, const671, tmp1383 V_MOV_B32 vDst(VGPR1659) src0(LITERAL_CONST) const: 0x3f333333 V_CMP_GE_F32 src0(0_5_F) src1(VGPR1658) # CF Block: Merge: .lbl148 S_MOV_B64 sDst(SGPR406) src0(EXEC) # CF Block: Cond Branch: true: .lbl149, false: .lbl145 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl145 S_BRANCH ??? .lbl149 Label: .lbl149 V_MOV_B32 vDst(VGPR1660) src0(0) S_BRANCH ??? .lbl148 Label: .lbl145 V_CMP_LE_F32 src0(VGPR1659) src1(VGPR1658) # CF Block: Merge: .lbl147 S_MOV_B64 sDst(SGPR408) src0(EXEC) # CF Block: Cond Branch: true: .lbl150, false: .lbl146 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl146 S_BRANCH ??? .lbl150 Label: .lbl150 V_MOV_B32 vDst(VGPR1660) src0(1_0_F) S_BRANCH ??? .lbl147 Label: .lbl146 V_SUBREV_F32 vDst(VGPR1661) src0(0_5_F) src1(VGPR1659) // VOP2 V_RCP_F32 vDst(VGPR1661) src0(VGPR1661) V_SUBREV_F32 vDst(VGPR1660) src0(0_5_F) src1(VGPR1658) // VOP2 V_MUL_F32 vDst(VGPR1661) src0(VGPR1660) src1(VGPR1661) // VOP2 V_MAX_F32 vDst(VGPR1661) src0(0) src1(VGPR1661) // VOP2 V_MIN_F32 vDst(VGPR1661) src0(1_0_F) src1(VGPR1661) // VOP2 V_MOV_B32 vDst(VGPR1660) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1660) src0(2_0_F) src1(VGPR1661) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1661) src0(VGPR1661) src1(VGPR1661) // VOP2 V_MUL_F32 vDst(VGPR1660) src0(VGPR1661) src1(VGPR1660) // VOP2 S_BRANCH ??? .lbl147 Label: .lbl147 S_BRANCH ??? .lbl148 Label: .lbl148 # 1385: OpFMul: Float: tmp1385 << const435, tmp1384 V_MOV_B32 vDst(VGPR1662) src0(LITERAL_CONST) const: 0x3f666666 V_MUL_F32 vDst(VGPR1663) src0(VGPR1662) src1(VGPR1660) // VOP2 # 1387: OpFMul: Float: tmp1387 << const1369, tmp1367 V_MOV_B32 vDst(VGPR1664) src0(LITERAL_CONST) const: 0xbe800000 V_MUL_F32 vDst(VGPR1665) src0(VGPR1664) src1(VGPR1641) // VOP2 # 1388: OpFAdd: Float: tmp1388 << tmp1387, const523 V_MOV_B32 vDst(VGPR1666) src0(LITERAL_CONST) const: 0x3e99999a V_ADD_F32 vDst(VGPR1667) src0(VGPR1665) src1(VGPR1666) // VOP2 # 1390: OpVectorShuffle: FloatVector2: tmp1390 << tmp1254, tmp1254, 0, 2 V_MOV_B32 vDst(VGPR1668) src0(VGPR1497) V_MOV_B32 vDst(VGPR1669) src0(VGPR1499) # 1392: OpVectorTimesScalar: FloatVector2: tmp1392 << tmp1390, const1391 V_MOV_B32 vDst(VGPR1672) src0(LITERAL_CONST) const: 0x4121999a V_MUL_F32 vDst(VGPR1670) src0(VGPR1672) src1(VGPR1668) // VOP2 V_MUL_F32 vDst(VGPR1671) src0(VGPR1672) src1(VGPR1669) // VOP2 # 1393: OpCompositeExtract: Float: tmp1393 << tmp1392, 0 V_MOV_B32 vDst(VGPR1673) src0(VGPR1670) # 1394: OpCompositeExtract: Float: tmp1394 << tmp1392, 1 V_MOV_B32 vDst(VGPR1674) src0(VGPR1671) # 1395: OpCompositeConstruct: FloatVector3: tmp1395 << tmp1393, tmp1394, const100 V_MOV_B32 vDst(VGPR1675) src0(VGPR1673) V_MOV_B32 vDst(VGPR1676) src0(VGPR1674) V_MOV_B32 vDst(VGPR1678) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1677) src0(VGPR1678) # OpStore: : tmp1395 >> param1396 V_MOV_B32 vDst(VGPR1347) src0(VGPR1675) V_MOV_B32 vDst(VGPR1348) src0(VGPR1676) V_MOV_B32 vDst(VGPR1349) src0(VGPR1677) # 1397: OpFunctionCall: Float: fbm3(vf3;(param1396) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x543 # VGPR[1347:1349] S_MOV_B64 sDst(SGPR410) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x68f # VGPR1679 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR410) # .lbl151 # 1398: OpFAdd: Float: tmp1398 << tmp1388, fbm3(vf3; V_ADD_F32 vDst(VGPR1680) src0(VGPR1667) src1(VGPR1679) // VOP2 # 1399: OpExtInst(SmoothStep): Float: tmp1399 << const303, const671, tmp1398 V_MOV_B32 vDst(VGPR1681) src0(LITERAL_CONST) const: 0x3f333333 V_CMP_GE_F32 src0(0_5_F) src1(VGPR1680) # CF Block: Merge: .lbl155 S_MOV_B64 sDst(SGPR412) src0(EXEC) # CF Block: Cond Branch: true: .lbl156, false: .lbl152 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl152 S_BRANCH ??? .lbl156 Label: .lbl156 V_MOV_B32 vDst(VGPR1682) src0(0) S_BRANCH ??? .lbl155 Label: .lbl152 V_CMP_LE_F32 src0(VGPR1681) src1(VGPR1680) # CF Block: Merge: .lbl154 S_MOV_B64 sDst(SGPR414) src0(EXEC) # CF Block: Cond Branch: true: .lbl157, false: .lbl153 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl153 S_BRANCH ??? .lbl157 Label: .lbl157 V_MOV_B32 vDst(VGPR1682) src0(1_0_F) S_BRANCH ??? .lbl154 Label: .lbl153 V_SUBREV_F32 vDst(VGPR1683) src0(0_5_F) src1(VGPR1681) // VOP2 V_RCP_F32 vDst(VGPR1683) src0(VGPR1683) V_SUBREV_F32 vDst(VGPR1682) src0(0_5_F) src1(VGPR1680) // VOP2 V_MUL_F32 vDst(VGPR1683) src0(VGPR1682) src1(VGPR1683) // VOP2 V_MAX_F32 vDst(VGPR1683) src0(0) src1(VGPR1683) // VOP2 V_MIN_F32 vDst(VGPR1683) src0(1_0_F) src1(VGPR1683) // VOP2 V_MOV_B32 vDst(VGPR1682) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1682) src0(2_0_F) src1(VGPR1683) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1683) src0(VGPR1683) src1(VGPR1683) // VOP2 V_MUL_F32 vDst(VGPR1682) src0(VGPR1683) src1(VGPR1682) // VOP2 S_BRANCH ??? .lbl154 Label: .lbl154 S_BRANCH ??? .lbl155 Label: .lbl155 # 1400: OpFMul: Float: tmp1400 << const435, tmp1399 V_MOV_B32 vDst(VGPR1684) src0(LITERAL_CONST) const: 0x3f666666 V_MUL_F32 vDst(VGPR1685) src0(VGPR1684) src1(VGPR1682) // VOP2 # 1401: OpFAdd: Float: tmp1401 << tmp1385, tmp1400 V_ADD_F32 vDst(VGPR1686) src0(VGPR1663) src1(VGPR1685) // VOP2 # 1402: OpCompositeConstruct: FloatVector3: tmp1402 << tmp1401, tmp1401, tmp1401 V_MOV_B32 vDst(VGPR1687) src0(VGPR1686) V_MOV_B32 vDst(VGPR1688) src0(VGPR1686) V_MOV_B32 vDst(VGPR1689) src0(VGPR1686) # 1403: OpExtInst(FMix): FloatVector3: tmp1403 << tmp1368, const1290, tmp1402 V_MOV_B32 vDst(VGPR1690) src0(1_0_F) V_MOV_B32 vDst(VGPR1691) src0(1_0_F) V_MOV_B32 vDst(VGPR1692) src0(1_0_F) V_SUBREV_F32 vDst(VGPR1693) src0(VGPR1687) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1693) src0(VGPR1320) src1(VGPR1693) // VOP2 V_MAD_F32 vDst(VGPR1693) src0(VGPR1690) src1(VGPR1687) src2(VGPR1693) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1694) src0(VGPR1688) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1694) src0(VGPR1321) src1(VGPR1694) // VOP2 V_MAD_F32 vDst(VGPR1694) src0(VGPR1691) src1(VGPR1688) src2(VGPR1694) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1695) src0(VGPR1689) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1695) src0(VGPR1322) src1(VGPR1695) // VOP2 V_MAD_F32 vDst(VGPR1695) src0(VGPR1692) src1(VGPR1689) src2(VGPR1695) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1403 >> col V_MOV_B32 vDst(VGPR1320) src0(VGPR1693) V_MOV_B32 vDst(VGPR1321) src0(VGPR1694) V_MOV_B32 vDst(VGPR1322) src0(VGPR1695) # 1404: OpLoad: FloatVector3: tmp1404 << col # 1405: OpVectorTimesScalar: FloatVector3: tmp1405 << tmp1404, const895 V_MOV_B32 vDst(VGPR1699) src0(LITERAL_CONST) const: 0x3fb33333 V_MUL_F32 vDst(VGPR1696) src0(VGPR1699) src1(VGPR1320) // VOP2 V_MUL_F32 vDst(VGPR1697) src0(VGPR1699) src1(VGPR1321) // VOP2 V_MUL_F32 vDst(VGPR1698) src0(VGPR1699) src1(VGPR1322) // VOP2 # 1406: OpExtInst(Sqrt): FloatVector3: tmp1406 << tmp1405 V_SQRT_F32 vDst(VGPR1700) src0(VGPR1696) V_SQRT_F32 vDst(VGPR1701) src0(VGPR1697) V_SQRT_F32 vDst(VGPR1702) src0(VGPR1698) # 1407: OpLoad: FloatVector4: tmp1407 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1703) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1704) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1705) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1706) src0(VGPR3) # 1408: OpVectorShuffle: FloatVector4: tmp1408 << tmp1407, tmp1406, 4, 5, 6, 3 V_MOV_B32 vDst(VGPR1707) src0(VGPR1700) V_MOV_B32 vDst(VGPR1708) src0(VGPR1701) V_MOV_B32 vDst(VGPR1709) src0(VGPR1702) V_MOV_B32 vDst(VGPR1710) src0(VGPR1706) # OpStore: : tmp1408 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1707) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1708) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1709) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1710) # 1410: OpAccessChain: Float*: q[0] # 1411: OpCompositeExtract: Float: tmp1411 << tmp1187, 0 V_MOV_B32 vDst(VGPR1711) src0(VGPR1451) # 1412: OpFMul: Float: tmp1412 << const1409, tmp1411 V_MOV_B32 vDst(VGPR1712) src0(LITERAL_CONST) const: 0x41800000 V_MUL_F32 vDst(VGPR1713) src0(VGPR1712) src1(VGPR1711) // VOP2 # 1413: OpAccessChain: Float*: q[1] # 1414: OpCompositeExtract: Float: tmp1414 << tmp1187, 1 V_MOV_B32 vDst(VGPR1714) src0(VGPR1452) # 1415: OpFMul: Float: tmp1415 << tmp1412, tmp1414 V_MUL_F32 vDst(VGPR1715) src0(VGPR1713) src1(VGPR1714) // VOP2 # 1416: OpAccessChain: Float*: q[0] # 1417: OpCompositeExtract: Float: tmp1417 << tmp1187, 0 V_MOV_B32 vDst(VGPR1716) src0(VGPR1451) # 1418: OpFSub: Float: tmp1418 << const106, tmp1417 V_SUB_F32 vDst(VGPR1717) src0(1_0_F) src1(VGPR1716) // VOP2 # 1419: OpFMul: Float: tmp1419 << tmp1415, tmp1418 V_MUL_F32 vDst(VGPR1718) src0(VGPR1715) src1(VGPR1717) // VOP2 # 1420: OpAccessChain: Float*: q[1] # 1421: OpCompositeExtract: Float: tmp1421 << tmp1187, 1 V_MOV_B32 vDst(VGPR1719) src0(VGPR1452) # 1422: OpFSub: Float: tmp1422 << const106, tmp1421 V_SUB_F32 vDst(VGPR1720) src0(1_0_F) src1(VGPR1719) // VOP2 # 1423: OpFMul: Float: tmp1423 << tmp1419, tmp1422 V_MUL_F32 vDst(VGPR1721) src0(VGPR1718) src1(VGPR1720) // VOP2 # 1424: OpExtInst(Pow): Float: tmp1424 << tmp1423, const576 V_MOV_B32 vDst(VGPR1722) src0(LITERAL_CONST) const: 0x3dcccccd V_LOG_F32 vDst(VGPR1723) src0(VGPR1721) V_MUL_F32 vDst(VGPR1723) src0(VGPR1722) src1(VGPR1723) // VOP2 V_EXP_F32 vDst(VGPR1723) src0(VGPR1723) # 1425: OpLoad: FloatVector4: tmp1425 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1724) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1725) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1726) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1727) src0(VGPR3) # 1426: OpVectorShuffle: FloatVector3: tmp1426 << tmp1425, tmp1425, 0, 1, 2 V_MOV_B32 vDst(VGPR1728) src0(VGPR1724) V_MOV_B32 vDst(VGPR1729) src0(VGPR1725) V_MOV_B32 vDst(VGPR1730) src0(VGPR1726) # 1427: OpVectorTimesScalar: FloatVector3: tmp1427 << tmp1426, tmp1424 V_MUL_F32 vDst(VGPR1731) src0(VGPR1723) src1(VGPR1728) // VOP2 V_MUL_F32 vDst(VGPR1732) src0(VGPR1723) src1(VGPR1729) // VOP2 V_MUL_F32 vDst(VGPR1733) src0(VGPR1723) src1(VGPR1730) // VOP2 # 1428: OpLoad: FloatVector4: tmp1428 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1734) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1735) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1736) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1737) src0(VGPR3) # 1429: OpVectorShuffle: FloatVector4: tmp1429 << tmp1428, tmp1427, 4, 5, 6, 3 V_MOV_B32 vDst(VGPR1738) src0(VGPR1731) V_MOV_B32 vDst(VGPR1739) src0(VGPR1732) V_MOV_B32 vDst(VGPR1740) src0(VGPR1733) V_MOV_B32 vDst(VGPR1741) src0(VGPR1737) # OpStore: : tmp1429 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1738) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1739) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1740) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1741) # OpReturn: S_SETPC_B64 sDst(SGPR10) src0(SGPR10) Performing GPU-specific optimization... Pre register allocation control-flow processing... Intermediate disassembly (pre register allocation): Program Type: Fragment Special Input Variables: offset: unset, size: 16, FloatVector4 gl_FragCoord BuiltIn(FragCoord) Textures: offset: 0, size: 4, Float iChannel0 offset: 1, size: 4, Float iChannel1 offset: 2, size: 4, Float iChannel2 offset: 3, size: 4, Float iChannel3 Output Variables: offset: 0, size: 16, FloatVector4 finalColor Uniform Constants: offset: 0, size: 4, Float iTime offset: 4, size: 12, FloatVector3 iResolution offset: 16, size: 16, FloatVector4 iMouse offset: 32, size: 16, FloatVector4 iDate offset: 48, size: 4, Float iFrame offset: 52, size: 48, FloatVector3 iChannelResolution[4] Private Global Variables: offset: unset, size: 8, FloatVector2 tc offset: unset, size: 4, Float time offset: unset, size: 4, Float colour offset: unset, size: 4, Float ss offset: unset, size: 4, Float is_choc offset: unset, size: 4, Float t_per_target offset: unset, size: 12, FloatVector3 l offset: unset, size: 4, Float icing_factor offset: unset, size: 48, FloatVector3 gum_colours[4] offset: unset, size: 48, FloatVector3 gum_ramps[4] Constants: Float const100: 0 FloatVector2 const101: {0, 0} Float const106: 1 Float const109: 3 Float const112: 0.316228 Float const113: 0.948683 FloatVector3 const114: {0.316228, 0.948683, 0} Float const121: 0.11 Float const122: 0.002 FloatVector3 const123: {0.11, 0, 0.002} Float const127: 2 Float const131: 0.06 FloatVector3 const132: {0.002, 0.06, 0} Float const139: 0.02 FloatVector3 const140: {0, 0.02, 0.11} Float const143: 0.012 FloatVector3 const144: {0.11, 0.012, 0} Float const151: 0.8 FloatVector3 const152: {0.8, 1, 1} FloatVector3 const159: {0.8, 0.8, 1} FloatVector3 const166: {1, 0.8, 1} Float const173: 43758.5 UInt32 const194: 0 UInt32 const197: 1 Float const200: 157 Float const203: 113 UInt32 const204: 2 Float const225: 158 Float const240: 114 Float const248: 270 Float const253: 271 Int32 const285: 1 Int32 const292: 9 Float const303: 0.5 Float const340: -1 FloatVector2 const341: {-1, -1} FloatVector2 const342: {1, 1} Float const349: 8 Float const361: 0.95 Float const377: 4 FloatVector2 const391: {0.5, 0.5} Float const401: 5 Float const407: 53 Float const412: 125 Float const416: 2.5 Float const423: 100 FloatVector2 const424: {100, 100} Float const435: 0.9 Float const437: 25 Int32 const471: 0 Int32 const478: 4 Float const483: 10.45 Float const489: 0.2 Float const511: 0.75 Float const523: 0.3 FloatVector3 const569: {0.5, 0.5, 0.5} Float const573: 0.98 Float const576: 0.1 FloatVector3 const585: {2, 2, 2} Float const593: 1.05 Float const602: 0.01 Float const609: 1.3 Float const621: 10 Float const625: 103 Float const633: 30 Float const637: 0.001 Float const647: 0.05 FloatVector2 const664: {3, 3} Float const666: 1.5 FloatVector2 const667: {1.5, 1.5} Float const671: 0.7 Float const674: 7 Float const678: 9 Float const704: 0.6 Float const714: 0.015 FloatVector2 const730: {1, -1} FloatVector3 const735: {0.1, 0.1, 0.05} Float const748: 0.4 Float const749: 0.24 FloatVector3 const750: {0.4, 0.4, 0.24} Float const751: 0.56 FloatVector3 const752: {0.7, 0.7, 0.56} Float const844: 6 Float const848: 0.03 FloatVector3 const860: {1, 0, 0} Float const863: 20 Float const867: -7 Float const869: 14 Float const888: 3.5 Float const895: 1.4 Int32 const906: 100 FloatVector3 const921: {0, 0, 0} Float const925: 0.0001 Float const945: 0.005 FloatVector3 const946: {0.02, 0.01, 0.005} Float const1012: 2.6 FloatVector3 const1013: {4, 4, 2.6} Float const1014: 0.78 Float const1015: 0.36 Float const1016: 0.12 FloatVector3 const1017: {0.78, 0.36, 0.12} FloatVector3 const1035: {1.3, 0.6, 0.2} FloatVector3 const1059: {0.06, 0.06, 0.03} Float const1093: 256 FloatVector3 const1153: {0, 1, 0} Float const1230: -0.01 FloatVector3 const1290: {1, 1, 1} Float const1291: 0.25 FloatVector3 const1292: {0.5, 0.5, 0.25} FloatVector3 const1297: {0.9, 0.9, 0.5} Float const1347: 0.33 Float const1348: 0.53 Float const1369: -0.25 Float const1372: 0.35 Float const1376: 4.2 Float const1391: 10.1 Float const1409: 16 UInt32 const1444: 4 Function Local Variables: offset: unset, size: 16, FloatVector4 main.param1433 offset: unset, size: 8, FloatVector2 main.param1434 offset: unset, size: 16, FloatVector4 main.fragColor offset: unset, size: 8, FloatVector2 main.fragCoord offset: unset, size: 4, Float main.i offset: unset, size: 4, Float gumColour(f1;.i offset: unset, size: 4, Float gumRamp(f1;.n offset: unset, size: 12, FloatVector3 hash(f1;.x offset: unset, size: 12, FloatVector3 noise(vf3;.f offset: unset, size: 4, Float noise(vf3;.param211 offset: unset, size: 4, Float noise(vf3;.param215 offset: unset, size: 4, Float noise(vf3;.param222 offset: unset, size: 4, Float noise(vf3;.param227 offset: unset, size: 4, Float noise(vf3;.param237 offset: unset, size: 4, Float noise(vf3;.param242 offset: unset, size: 4, Float noise(vf3;.param250 offset: unset, size: 4, Float noise(vf3;.param255 offset: unset, size: 8, FloatVector2 noise(vf3;.p offset: unset, size: 12, FloatVector3 smN2(vf2;.param272 offset: unset, size: 12, FloatVector3 smN2(vf2;.p offset: unset, size: 12, FloatVector3 smN3(vf3;.param276 offset: unset, size: 12, FloatVector3 smN3(vf3;.p offset: unset, size: 4, Float fbm3(vf3;.f offset: unset, size: 4, Int32 fbm3(vf3;.i offset: unset, size: 12, FloatVector3 fbm3(vf3;.param301 offset: unset, size: 4, Float fbm3(vf3;.a offset: unset, size: 8, FloatVector2 fbm3(vf3;.v offset: unset, size: 8, FloatVector2 rotate(f1;vf2;.p offset: unset, size: 8, FloatVector2 sugarybit(vf2;.t offset: unset, size: 4, Float sugarybit(vf2;.ndotv offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param419 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param426 offset: unset, size: 4, Float sugarlayer(vf2;f1;.param445 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param447 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param449 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param453 offset: unset, size: 12, FloatVector3 sugarlayer(vf2;f1;.c offset: unset, size: 4, Float saturatecol(vf3;.param463 offset: unset, size: 8, FloatVector2 saturatecol(vf3;.coord offset: unset, size: 4, Float saturatecol(vf3;.ndotv offset: unset, size: 4, Float sprinkles2(vf2;f1;.sprinkle offset: unset, size: 4, Int32 sprinkles2(vf2;f1;.i offset: unset, size: 8, FloatVector2 sprinkles2(vf2;f1;.param493 offset: unset, size: 4, Float sprinkles2(vf2;f1;.param494 offset: unset, size: 8, FloatVector2 sprinkles2(vf2;f1;.coord offset: unset, size: 4, Float sprinkles2(vf2;f1;.ndotv offset: unset, size: 8, FloatVector2 sprinkles(vf2;f1;.param513 offset: unset, size: 4, Float sprinkles(vf2;f1;.param514 offset: unset, size: 8, FloatVector2 sprinkles(vf2;f1;.param519 offset: unset, size: 4, Float sprinkles(vf2;f1;.param520 offset: unset, size: 12, FloatVector3 sprinkles(vf2;f1;.no offset: unset, size: 12, FloatVector3 sprinkles(vf2;f1;.vo offset: unset, size: 12, FloatVector3 sprinkles(vf2;f1;.v offset: unset, size: 8, FloatVector2 gummy(vf3;vf3;vf3;.param544 offset: unset, size: 4, Float gummy(vf3;vf3;vf3;.param545 offset: unset, size: 8, FloatVector2 gummy(vf3;vf3;vf3;.param549 offset: unset, size: 4, Float gummy(vf3;vf3;vf3;.param552 offset: unset, size: 12, FloatVector3 gummy(vf3;vf3;vf3;.tex offset: unset, size: 4, Float gummy(vf3;vf3;vf3;.param570 offset: unset, size: 12, FloatVector3 gummy(vf3;vf3;vf3;.param591 offset: unset, size: 12, FloatVector3 gummy(vf3;vf3;vf3;.p offset: unset, size: 12, FloatVector3 de(vf3;.param635 offset: unset, size: 12, FloatVector3 de(vf3;.param643 offset: unset, size: 8, FloatVector2 de(vf3;.p offset: unset, size: 12, FloatVector3 marble(vf2;.param740 offset: unset, size: 12, FloatVector3 marble(vf2;.param767 offset: unset, size: 12, FloatVector3 marble(vf2;.param779 offset: unset, size: 12, FloatVector3 marble(vf2;.param790 offset: unset, size: 4, Float marble(vf2;.t offset: unset, size: 4, Float cameraPos(f1;.ti offset: unset, size: 12, FloatVector3 targetPos(f1;.target offset: unset, size: 4, Float targetPos(f1;.param858 offset: unset, size: 4, Float targetPos(f1;.ti offset: unset, size: 12, FloatVector3 cameraZoom(f1;.ro offset: unset, size: 12, FloatVector3 cameraZoom(f1;.rd offset: unset, size: 4, Float cameraZoom(f1;.t offset: unset, size: 4, Float cameraZoom(f1;.max_t offset: unset, size: 4, Int32 trace(vf3;vf3;f1;f1;.i offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param914 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.col offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param949 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param957 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param965 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param973 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.chocolour offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1028 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1079 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1081 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1083 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1131 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1137 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1139 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.camu offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.p offset: unset, size: 4, Float mainImage(vf4;vf2;.param1204 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1206 offset: unset, size: 4, Float mainImage(vf4;vf2;.t offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.col offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1239 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1241 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1243 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1245 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.c offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.cc offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param1312 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1330 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param1331 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param1333 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1341 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1381 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1396 Instructions: V_SUB_F32 vDst(VGPR14) src0(SGPR2) src1(VGPR14) // VOP2 # Void main() Function: Void main() # lb5 Label: lb5 # OpStore: : const101 >> tc V_MOV_B32 vDst(VGPR26) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR27) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR24) src0(VGPR26) V_MOV_B32 vDst(VGPR25) src0(VGPR27) # OpStore: : const100 >> time V_MOV_B32 vDst(VGPR29) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR28) src0(VGPR29) # OpStore: : const100 >> colour V_MOV_B32 vDst(VGPR31) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR30) src0(VGPR31) # OpStore: : const106 >> ss V_MOV_B32 vDst(VGPR32) src0(1_0_F) # OpStore: : const100 >> is_choc V_MOV_B32 vDst(VGPR34) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR33) src0(VGPR34) # OpStore: : const109 >> t_per_target V_MOV_B32 vDst(VGPR36) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR35) src0(VGPR36) # OpStore: : const114 >> l V_MOV_B32 vDst(VGPR40) src0(LITERAL_CONST) const: 0x3ea1e89b V_MOV_B32 vDst(VGPR41) src0(LITERAL_CONST) const: 0x3f72dce9 V_MOV_B32 vDst(VGPR42) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR37) src0(VGPR40) V_MOV_B32 vDst(VGPR38) src0(VGPR41) V_MOV_B32 vDst(VGPR39) src0(VGPR42) # OpStore: : const100 >> icing_factor V_MOV_B32 vDst(VGPR44) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR43) src0(VGPR44) # 1435: OpLoad: FloatVector4: tmp1435 << gl_FragCoord V_MOV_B32 vDst(VGPR45) src0(VGPR13) V_MOV_B32 vDst(VGPR46) src0(VGPR14) V_MOV_B32 vDst(VGPR47) src0(VGPR15) V_MOV_B32 vDst(VGPR48) src0(VGPR16) # 1436: OpVectorShuffle: FloatVector2: tmp1436 << tmp1435, tmp1435, 0, 1 V_MOV_B32 vDst(VGPR49) src0(VGPR45) V_MOV_B32 vDst(VGPR50) src0(VGPR46) # OpStore: : tmp1436 >> param1434 V_MOV_B32 vDst(VGPR22) src0(VGPR49) V_MOV_B32 vDst(VGPR23) src0(VGPR50) # 1437: OpFunctionCall: Void: mainImage(vf4;vf2;(param1433, param1434) S_ADD_U32 sDst(SGPR12) src0(LITERAL_CONST) src1(0) const: 0x12 # VGPR[18:21] S_ADD_U32 sDst(SGPR13) src0(LITERAL_CONST) src1(0) const: 0x16 # VGPR[22:23] S_MOV_B64 sDst(SGPR14) src0(EXEC) # Indirect branch to mainImage(vf4;vf2;: ??? S_GETPC_B64 sDst(SGPR10) src0(SGPR10) S_ADD_U32 sDst(SGPR10) src0(SGPR10) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR11) src0(SGPR11) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR10) src0(SGPR10) S_MOV_B64 sDst(EXEC) src0(SGPR14) # .lbl0 # 1438: OpLoad: FloatVector4: tmp1438 << param1433 # OpStore: : tmp1438 >> finalColor V_MOV_B32 vDst(VGPR51) src0(VGPR18) V_MOV_B32 vDst(VGPR52) src0(VGPR19) V_MOV_B32 vDst(VGPR53) src0(VGPR20) V_MOV_B32 vDst(VGPR54) src0(VGPR21) # OpReturn: V_CVT_PKRTZ_F16_F32 vDst(VGPR51) src0(VGPR51) src1(VGPR52) // VOP2 V_CVT_PKRTZ_F16_F32 vDst(VGPR52) src0(VGPR53) src1(VGPR54) // VOP2 EXP en(0xf) tgt(0) compr(1) done(1) vm(1) vsrc0(VGPR51) vsrc1(VGPR52) vsrc2(VGPR53) vsrc3(VGPR54) S_WAITCNT 0 S_ENDPGM 0 # FloatVector3 gumColour(f1;(Float* i) Function: FloatVector3 gumColour(f1;() S_MOV_B64 sDst(SGPR20) src0(EXEC) # lb12 Label: lb12 # 116: OpLoad: Float: tmp116 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR55) src0(VGPR0) # 118: OpFOrdLessThan: Bool: tmp118 << tmp116, const106 V_MOV_B32 vDst(VGPR56) src0(1_0_F) V_CMP_LT_F32 dst(SGPR22) src0(VGPR55) src1(VGPR56) // VOP3a # OpSelectionMerge: (merge: lb120) # CF Block: Merge: lb120 S_MOV_B64 sDst(SGPR24) src0(EXEC) # OpBranchConditional: if(tmp118) then branch to lb119, else branch to lb125 # CF Block: Cond Branch: true: lb119, false: lb125 S_AND_B64 sDst(EXEC) src0(SGPR22) src1(EXEC) S_CBRANCH_EXECZ ??? lb125 # lb119 Label: lb119 # OpReturnValue: : << const123 V_MOV_B32 vDst(VGPR57) src0(LITERAL_CONST) const: 0x3de147ae V_MOV_B32 vDst(VGPR58) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR59) src0(LITERAL_CONST) const: 0x3b03126f S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR57) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR58) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR59) S_ANDN2_B64 sDst(SGPR20) src0(SGPR20) src1(EXEC) # lb125 Label: lb125 S_ANDN2_B64 sDst(EXEC) src0(SGPR24) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR20) src1(EXEC) S_CBRANCH_EXECZ ??? lb120 # 126: OpLoad: Float: tmp126 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR60) src0(VGPR0) # 128: OpFOrdLessThan: Bool: tmp128 << tmp126, const127 V_MOV_B32 vDst(VGPR61) src0(2_0_F) V_CMP_LT_F32 dst(SGPR26) src0(VGPR60) src1(VGPR61) // VOP3a # OpSelectionMerge: (merge: lb130) # CF Block: Merge: lb130 S_MOV_B64 sDst(SGPR28) src0(EXEC) # OpBranchConditional: if(tmp128) then branch to lb129, else branch to lb134 # CF Block: Cond Branch: true: lb129, false: lb134 S_AND_B64 sDst(EXEC) src0(SGPR26) src1(EXEC) S_CBRANCH_EXECZ ??? lb134 # lb129 Label: lb129 # OpReturnValue: : << const132 V_MOV_B32 vDst(VGPR62) src0(LITERAL_CONST) const: 0x3b03126f V_MOV_B32 vDst(VGPR63) src0(LITERAL_CONST) const: 0x3d75c28f V_MOV_B32 vDst(VGPR64) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR62) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR63) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR64) S_ANDN2_B64 sDst(SGPR20) src0(SGPR20) src1(EXEC) # lb134 Label: lb134 S_ANDN2_B64 sDst(EXEC) src0(SGPR28) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR20) src1(EXEC) S_CBRANCH_EXECZ ??? lb130 # 135: OpLoad: Float: tmp135 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR65) src0(VGPR0) # 136: OpFOrdLessThan: Bool: tmp136 << tmp135, const109 V_MOV_B32 vDst(VGPR66) src0(LITERAL_CONST) const: 0x40400000 V_CMP_LT_F32 dst(SGPR30) src0(VGPR65) src1(VGPR66) // VOP3a # OpSelectionMerge: (merge: lb138) # CF Block: Merge: lb138 S_MOV_B64 sDst(SGPR32) src0(EXEC) # OpBranchConditional: if(tmp136) then branch to lb137, else branch to lb142 # CF Block: Cond Branch: true: lb137, false: lb142 S_AND_B64 sDst(EXEC) src0(SGPR30) src1(EXEC) S_CBRANCH_EXECZ ??? lb142 # lb137 Label: lb137 # OpReturnValue: : << const140 V_MOV_B32 vDst(VGPR67) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR68) src0(LITERAL_CONST) const: 0x3ca3d70a V_MOV_B32 vDst(VGPR69) src0(LITERAL_CONST) const: 0x3de147ae S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR67) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR68) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR69) S_ANDN2_B64 sDst(SGPR20) src0(SGPR20) src1(EXEC) # lb142 Label: lb142 S_ANDN2_B64 sDst(EXEC) src0(SGPR32) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR20) src1(EXEC) S_CBRANCH_EXECZ ??? lb138 # OpReturnValue: : << const144 V_MOV_B32 vDst(VGPR70) src0(LITERAL_CONST) const: 0x3de147ae V_MOV_B32 vDst(VGPR71) src0(LITERAL_CONST) const: 0x3c449ba6 V_MOV_B32 vDst(VGPR72) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR70) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR71) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR72) S_ANDN2_B64 sDst(SGPR20) src0(SGPR20) src1(EXEC) # lb138 Label: lb138 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR32) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR20) # OpBranch: to lb130 # lb130 Label: lb130 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR28) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR20) # OpBranch: to lb120 # lb120 Label: lb120 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR24) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR20) # 146: OpUndef: FloatVector3: tmp146 << # OpReturnValue: : << tmp146 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR34) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR35) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR36) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # FloatVector3 gumRamp(f1;(Float* i) Function: FloatVector3 gumRamp(f1;() S_MOV_B64 sDst(SGPR42) src0(EXEC) # lb15 Label: lb15 # 147: OpLoad: Float: tmp147 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR41) const: 0x0 V_MOVRELS_B32 vDst(VGPR73) src0(VGPR0) # 148: OpFOrdLessThan: Bool: tmp148 << tmp147, const106 V_MOV_B32 vDst(VGPR74) src0(1_0_F) V_CMP_LT_F32 dst(SGPR44) src0(VGPR73) src1(VGPR74) // VOP3a # OpSelectionMerge: (merge: lb150) # CF Block: Merge: lb150 S_MOV_B64 sDst(SGPR46) src0(EXEC) # OpBranchConditional: if(tmp148) then branch to lb149, else branch to lb154 # CF Block: Cond Branch: true: lb149, false: lb154 S_AND_B64 sDst(EXEC) src0(SGPR44) src1(EXEC) S_CBRANCH_EXECZ ??? lb154 # lb149 Label: lb149 # OpReturnValue: : << const152 V_MOV_B32 vDst(VGPR75) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR76) src0(1_0_F) V_MOV_B32 vDst(VGPR77) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR75) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR76) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR77) S_ANDN2_B64 sDst(SGPR42) src0(SGPR42) src1(EXEC) # lb154 Label: lb154 S_ANDN2_B64 sDst(EXEC) src0(SGPR46) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR42) src1(EXEC) S_CBRANCH_EXECZ ??? lb150 # 155: OpLoad: Float: tmp155 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR41) const: 0x0 V_MOVRELS_B32 vDst(VGPR78) src0(VGPR0) # 156: OpFOrdLessThan: Bool: tmp156 << tmp155, const127 V_MOV_B32 vDst(VGPR79) src0(2_0_F) V_CMP_LT_F32 dst(SGPR48) src0(VGPR78) src1(VGPR79) // VOP3a # OpSelectionMerge: (merge: lb158) # CF Block: Merge: lb158 S_MOV_B64 sDst(SGPR50) src0(EXEC) # OpBranchConditional: if(tmp156) then branch to lb157, else branch to lb161 # CF Block: Cond Branch: true: lb157, false: lb161 S_AND_B64 sDst(EXEC) src0(SGPR48) src1(EXEC) S_CBRANCH_EXECZ ??? lb161 # lb157 Label: lb157 # OpReturnValue: : << const159 V_MOV_B32 vDst(VGPR80) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR81) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR82) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR80) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR81) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR82) S_ANDN2_B64 sDst(SGPR42) src0(SGPR42) src1(EXEC) # lb161 Label: lb161 S_ANDN2_B64 sDst(EXEC) src0(SGPR50) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR42) src1(EXEC) S_CBRANCH_EXECZ ??? lb158 # 162: OpLoad: Float: tmp162 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR41) const: 0x0 V_MOVRELS_B32 vDst(VGPR83) src0(VGPR0) # 163: OpFOrdLessThan: Bool: tmp163 << tmp162, const109 V_MOV_B32 vDst(VGPR84) src0(LITERAL_CONST) const: 0x40400000 V_CMP_LT_F32 dst(SGPR52) src0(VGPR83) src1(VGPR84) // VOP3a # OpSelectionMerge: (merge: lb165) # CF Block: Merge: lb165 S_MOV_B64 sDst(SGPR54) src0(EXEC) # OpBranchConditional: if(tmp163) then branch to lb164, else branch to lb168 # CF Block: Cond Branch: true: lb164, false: lb168 S_AND_B64 sDst(EXEC) src0(SGPR52) src1(EXEC) S_CBRANCH_EXECZ ??? lb168 # lb164 Label: lb164 # OpReturnValue: : << const166 V_MOV_B32 vDst(VGPR85) src0(1_0_F) V_MOV_B32 vDst(VGPR86) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR87) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR85) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR86) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR87) S_ANDN2_B64 sDst(SGPR42) src0(SGPR42) src1(EXEC) # lb168 Label: lb168 S_ANDN2_B64 sDst(EXEC) src0(SGPR54) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR42) src1(EXEC) S_CBRANCH_EXECZ ??? lb165 # OpReturnValue: : << const159 V_MOV_B32 vDst(VGPR88) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR89) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR90) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR88) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR89) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR90) S_ANDN2_B64 sDst(SGPR42) src0(SGPR42) src1(EXEC) # lb165 Label: lb165 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR54) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR42) # OpBranch: to lb158 # lb158 Label: lb158 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR50) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR42) # OpBranch: to lb150 # lb150 Label: lb150 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR46) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR42) # 170: OpUndef: FloatVector3: tmp170 << # OpReturnValue: : << tmp170 S_MOV_B32 sDst(M0) src0(SGPR40) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR56) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR57) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR58) S_SETPC_B64 sDst(SGPR38) src0(SGPR38) # Float hash(f1;(Float* n) Function: Float hash(f1;() S_MOV_B64 sDst(SGPR64) src0(EXEC) # lb19 Label: lb19 # 171: OpLoad: Float: tmp171 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR63) const: 0x0 V_MOVRELS_B32 vDst(VGPR91) src0(VGPR0) # 172: OpExtInst(Sin): Float: tmp172 << tmp171 V_MUL_F32 vDst(VGPR92) src0(LITERAL_CONST) src1(VGPR91) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR92) src0(VGPR92) V_SIN_F32 vDst(VGPR92) src0(VGPR92) # 174: OpFMul: Float: tmp174 << tmp172, const173 V_MOV_B32 vDst(VGPR93) src0(LITERAL_CONST) const: 0x472aee8c V_MUL_F32 vDst(VGPR94) src0(VGPR92) src1(VGPR93) // VOP2 # 175: OpExtInst(Fract): Float: tmp175 << tmp174 V_FRACT_F32 vDst(VGPR95) src0(VGPR94) # OpReturnValue: : << tmp175 S_MOV_B32 sDst(M0) src0(SGPR62) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR95) S_SETPC_B64 sDst(SGPR60) src0(SGPR60) # Float noise(vf3;(FloatVector3* x) Function: Float noise(vf3;() S_MOV_B64 sDst(SGPR70) src0(EXEC) # lb24 Label: lb24 # 179: OpLoad: FloatVector3: tmp179 << x S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR69) const: 0x0 V_MOVRELS_B32 vDst(VGPR107) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR108) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR109) src0(VGPR2) # 180: OpExtInst(Floor): FloatVector3: tmp180 << tmp179 V_FLOOR_F32 vDst(VGPR110) src0(VGPR107) V_FLOOR_F32 vDst(VGPR111) src0(VGPR108) V_FLOOR_F32 vDst(VGPR112) src0(VGPR109) # 182: OpLoad: FloatVector3: tmp182 << x S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR69) const: 0x0 V_MOVRELS_B32 vDst(VGPR113) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR114) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR115) src0(VGPR2) # 183: OpExtInst(Fract): FloatVector3: tmp183 << tmp182 V_FRACT_F32 vDst(VGPR116) src0(VGPR113) V_FRACT_F32 vDst(VGPR117) src0(VGPR114) V_FRACT_F32 vDst(VGPR118) src0(VGPR115) # OpStore: : tmp183 >> f V_MOV_B32 vDst(VGPR96) src0(VGPR116) V_MOV_B32 vDst(VGPR97) src0(VGPR117) V_MOV_B32 vDst(VGPR98) src0(VGPR118) # 184: OpLoad: FloatVector3: tmp184 << f # 185: OpLoad: FloatVector3: tmp185 << f # 186: OpFMul: FloatVector3: tmp186 << tmp184, tmp185 V_MUL_F32 vDst(VGPR119) src0(VGPR96) src1(VGPR96) // VOP2 V_MUL_F32 vDst(VGPR120) src0(VGPR97) src1(VGPR97) // VOP2 V_MUL_F32 vDst(VGPR121) src0(VGPR98) src1(VGPR98) // VOP2 # 187: OpLoad: FloatVector3: tmp187 << f # 188: OpVectorTimesScalar: FloatVector3: tmp188 << tmp187, const127 V_MOV_B32 vDst(VGPR125) src0(2_0_F) V_MUL_F32 vDst(VGPR122) src0(VGPR125) src1(VGPR96) // VOP2 V_MUL_F32 vDst(VGPR123) src0(VGPR125) src1(VGPR97) // VOP2 V_MUL_F32 vDst(VGPR124) src0(VGPR125) src1(VGPR98) // VOP2 # 189: OpCompositeConstruct: FloatVector3: tmp189 << const109, const109, const109 V_MOV_B32 vDst(VGPR129) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR126) src0(VGPR129) V_MOV_B32 vDst(VGPR130) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR127) src0(VGPR130) V_MOV_B32 vDst(VGPR131) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR128) src0(VGPR131) # 190: OpFSub: FloatVector3: tmp190 << tmp189, tmp188 V_SUB_F32 vDst(VGPR132) src0(VGPR126) src1(VGPR122) // VOP2 V_SUB_F32 vDst(VGPR133) src0(VGPR127) src1(VGPR123) // VOP2 V_SUB_F32 vDst(VGPR134) src0(VGPR128) src1(VGPR124) // VOP2 # 191: OpFMul: FloatVector3: tmp191 << tmp186, tmp190 V_MUL_F32 vDst(VGPR135) src0(VGPR119) src1(VGPR132) // VOP2 V_MUL_F32 vDst(VGPR136) src0(VGPR120) src1(VGPR133) // VOP2 V_MUL_F32 vDst(VGPR137) src0(VGPR121) src1(VGPR134) // VOP2 # OpStore: : tmp191 >> f V_MOV_B32 vDst(VGPR96) src0(VGPR135) V_MOV_B32 vDst(VGPR97) src0(VGPR136) V_MOV_B32 vDst(VGPR98) src0(VGPR137) # 195: OpAccessChain: Float*: p[0] # 196: OpCompositeExtract: Float: tmp196 << tmp180, 0 V_MOV_B32 vDst(VGPR138) src0(VGPR110) # 198: OpAccessChain: Float*: p[1] # 199: OpCompositeExtract: Float: tmp199 << tmp180, 1 V_MOV_B32 vDst(VGPR139) src0(VGPR111) # 201: OpFMul: Float: tmp201 << tmp199, const200 V_MOV_B32 vDst(VGPR140) src0(LITERAL_CONST) const: 0x431d0000 V_MUL_F32 vDst(VGPR141) src0(VGPR139) src1(VGPR140) // VOP2 # 202: OpFAdd: Float: tmp202 << tmp196, tmp201 V_ADD_F32 vDst(VGPR142) src0(VGPR138) src1(VGPR141) // VOP2 # 205: OpAccessChain: Float*: p[2] # 206: OpCompositeExtract: Float: tmp206 << tmp180, 2 V_MOV_B32 vDst(VGPR143) src0(VGPR112) # 207: OpFMul: Float: tmp207 << const203, tmp206 V_MOV_B32 vDst(VGPR144) src0(LITERAL_CONST) const: 0x42e20000 V_MUL_F32 vDst(VGPR145) src0(VGPR144) src1(VGPR143) // VOP2 # 208: OpFAdd: Float: tmp208 << tmp202, tmp207 V_ADD_F32 vDst(VGPR146) src0(VGPR142) src1(VGPR145) // VOP2 # 210: OpFAdd: Float: tmp210 << tmp208, const100 V_MOV_B32 vDst(VGPR147) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR148) src0(VGPR146) src1(VGPR147) // VOP2 # OpStore: : tmp210 >> param211 V_MOV_B32 vDst(VGPR99) src0(VGPR148) # 212: OpFunctionCall: Float: hash(f1;(param211) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x63 # VGPR99 S_MOV_B64 sDst(SGPR72) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0x95 # VGPR149 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR72) # .lbl1 # 214: OpFAdd: Float: tmp214 << tmp208, const106 V_MOV_B32 vDst(VGPR150) src0(1_0_F) V_ADD_F32 vDst(VGPR151) src0(VGPR146) src1(VGPR150) // VOP2 # OpStore: : tmp214 >> param215 V_MOV_B32 vDst(VGPR100) src0(VGPR151) # 216: OpFunctionCall: Float: hash(f1;(param215) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x64 # VGPR100 S_MOV_B64 sDst(SGPR74) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0x98 # VGPR152 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR74) # .lbl2 # 217: OpAccessChain: Float*: f[0] # 218: OpLoad: Float: tmp218 << f[0] V_MOV_B32 vDst(VGPR153) src0(VGPR96) # 219: OpExtInst(FMix): Float: tmp219 << hash(f1;, hash(f1;, tmp218 V_SUBREV_F32 vDst(VGPR154) src0(VGPR153) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR154) src0(VGPR149) src1(VGPR154) // VOP2 V_MAD_F32 vDst(VGPR154) src0(VGPR152) src1(VGPR153) src2(VGPR154) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 221: OpFAdd: Float: tmp221 << tmp208, const200 V_MOV_B32 vDst(VGPR155) src0(LITERAL_CONST) const: 0x431d0000 V_ADD_F32 vDst(VGPR156) src0(VGPR146) src1(VGPR155) // VOP2 # OpStore: : tmp221 >> param222 V_MOV_B32 vDst(VGPR101) src0(VGPR156) # 223: OpFunctionCall: Float: hash(f1;(param222) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x65 # VGPR101 S_MOV_B64 sDst(SGPR76) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0x9d # VGPR157 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR76) # .lbl3 # 226: OpFAdd: Float: tmp226 << tmp208, const225 V_MOV_B32 vDst(VGPR158) src0(LITERAL_CONST) const: 0x431e0000 V_ADD_F32 vDst(VGPR159) src0(VGPR146) src1(VGPR158) // VOP2 # OpStore: : tmp226 >> param227 V_MOV_B32 vDst(VGPR102) src0(VGPR159) # 228: OpFunctionCall: Float: hash(f1;(param227) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x66 # VGPR102 S_MOV_B64 sDst(SGPR78) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xa0 # VGPR160 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR78) # .lbl4 # 229: OpAccessChain: Float*: f[0] # 230: OpLoad: Float: tmp230 << f[0] V_MOV_B32 vDst(VGPR161) src0(VGPR96) # 231: OpExtInst(FMix): Float: tmp231 << hash(f1;, hash(f1;, tmp230 V_SUBREV_F32 vDst(VGPR162) src0(VGPR161) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR162) src0(VGPR157) src1(VGPR162) // VOP2 V_MAD_F32 vDst(VGPR162) src0(VGPR160) src1(VGPR161) src2(VGPR162) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 232: OpAccessChain: Float*: f[1] # 233: OpLoad: Float: tmp233 << f[1] V_MOV_B32 vDst(VGPR163) src0(VGPR97) # 234: OpExtInst(FMix): Float: tmp234 << tmp219, tmp231, tmp233 V_SUBREV_F32 vDst(VGPR164) src0(VGPR163) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR164) src0(VGPR154) src1(VGPR164) // VOP2 V_MAD_F32 vDst(VGPR164) src0(VGPR162) src1(VGPR163) src2(VGPR164) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 236: OpFAdd: Float: tmp236 << tmp208, const203 V_MOV_B32 vDst(VGPR165) src0(LITERAL_CONST) const: 0x42e20000 V_ADD_F32 vDst(VGPR166) src0(VGPR146) src1(VGPR165) // VOP2 # OpStore: : tmp236 >> param237 V_MOV_B32 vDst(VGPR103) src0(VGPR166) # 238: OpFunctionCall: Float: hash(f1;(param237) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x67 # VGPR103 S_MOV_B64 sDst(SGPR80) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xa7 # VGPR167 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR80) # .lbl5 # 241: OpFAdd: Float: tmp241 << tmp208, const240 V_MOV_B32 vDst(VGPR168) src0(LITERAL_CONST) const: 0x42e40000 V_ADD_F32 vDst(VGPR169) src0(VGPR146) src1(VGPR168) // VOP2 # OpStore: : tmp241 >> param242 V_MOV_B32 vDst(VGPR104) src0(VGPR169) # 243: OpFunctionCall: Float: hash(f1;(param242) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x68 # VGPR104 S_MOV_B64 sDst(SGPR82) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xaa # VGPR170 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR82) # .lbl6 # 244: OpAccessChain: Float*: f[0] # 245: OpLoad: Float: tmp245 << f[0] V_MOV_B32 vDst(VGPR171) src0(VGPR96) # 246: OpExtInst(FMix): Float: tmp246 << hash(f1;, hash(f1;, tmp245 V_SUBREV_F32 vDst(VGPR172) src0(VGPR171) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR172) src0(VGPR167) src1(VGPR172) // VOP2 V_MAD_F32 vDst(VGPR172) src0(VGPR170) src1(VGPR171) src2(VGPR172) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 249: OpFAdd: Float: tmp249 << tmp208, const248 V_MOV_B32 vDst(VGPR173) src0(LITERAL_CONST) const: 0x43870000 V_ADD_F32 vDst(VGPR174) src0(VGPR146) src1(VGPR173) // VOP2 # OpStore: : tmp249 >> param250 V_MOV_B32 vDst(VGPR105) src0(VGPR174) # 251: OpFunctionCall: Float: hash(f1;(param250) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x69 # VGPR105 S_MOV_B64 sDst(SGPR84) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xaf # VGPR175 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR84) # .lbl7 # 254: OpFAdd: Float: tmp254 << tmp208, const253 V_MOV_B32 vDst(VGPR176) src0(LITERAL_CONST) const: 0x43878000 V_ADD_F32 vDst(VGPR177) src0(VGPR146) src1(VGPR176) // VOP2 # OpStore: : tmp254 >> param255 V_MOV_B32 vDst(VGPR106) src0(VGPR177) # 256: OpFunctionCall: Float: hash(f1;(param255) S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x6a # VGPR106 S_MOV_B64 sDst(SGPR86) src0(EXEC) S_MOV_B32 sDst(SGPR62) src0(LITERAL_CONST) const: 0xb2 # VGPR178 # Indirect branch to hash(f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR86) # .lbl8 # 257: OpAccessChain: Float*: f[0] # 258: OpLoad: Float: tmp258 << f[0] V_MOV_B32 vDst(VGPR179) src0(VGPR96) # 259: OpExtInst(FMix): Float: tmp259 << hash(f1;, hash(f1;, tmp258 V_SUBREV_F32 vDst(VGPR180) src0(VGPR179) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR180) src0(VGPR175) src1(VGPR180) // VOP2 V_MAD_F32 vDst(VGPR180) src0(VGPR178) src1(VGPR179) src2(VGPR180) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 260: OpAccessChain: Float*: f[1] # 261: OpLoad: Float: tmp261 << f[1] V_MOV_B32 vDst(VGPR181) src0(VGPR97) # 262: OpExtInst(FMix): Float: tmp262 << tmp246, tmp259, tmp261 V_SUBREV_F32 vDst(VGPR182) src0(VGPR181) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR182) src0(VGPR172) src1(VGPR182) // VOP2 V_MAD_F32 vDst(VGPR182) src0(VGPR180) src1(VGPR181) src2(VGPR182) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 263: OpAccessChain: Float*: f[2] # 264: OpLoad: Float: tmp264 << f[2] V_MOV_B32 vDst(VGPR183) src0(VGPR98) # 265: OpExtInst(FMix): Float: tmp265 << tmp234, tmp262, tmp264 V_SUBREV_F32 vDst(VGPR184) src0(VGPR183) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR184) src0(VGPR164) src1(VGPR184) // VOP2 V_MAD_F32 vDst(VGPR184) src0(VGPR182) src1(VGPR183) src2(VGPR184) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp265 S_MOV_B32 sDst(M0) src0(SGPR68) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR184) S_SETPC_B64 sDst(SGPR66) src0(SGPR66) # Float smN2(vf2;(FloatVector2* p) Function: Float smN2(vf2;() S_MOV_B64 sDst(SGPR92) src0(EXEC) # lb30 Label: lb30 # 268: OpLoad: FloatVector2: tmp268 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR188) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR189) src0(VGPR1) # 269: OpCompositeExtract: Float: tmp269 << tmp268, 0 V_MOV_B32 vDst(VGPR190) src0(VGPR188) # 270: OpCompositeExtract: Float: tmp270 << tmp268, 1 V_MOV_B32 vDst(VGPR191) src0(VGPR189) # 271: OpCompositeConstruct: FloatVector3: tmp271 << tmp269, tmp270, const100 V_MOV_B32 vDst(VGPR192) src0(VGPR190) V_MOV_B32 vDst(VGPR193) src0(VGPR191) V_MOV_B32 vDst(VGPR195) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR194) src0(VGPR195) # OpStore: : tmp271 >> param272 V_MOV_B32 vDst(VGPR185) src0(VGPR192) V_MOV_B32 vDst(VGPR186) src0(VGPR193) V_MOV_B32 vDst(VGPR187) src0(VGPR194) # 273: OpFunctionCall: Float: noise(vf3;(param272) S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0xb9 # VGPR[185:187] S_MOV_B64 sDst(SGPR94) src0(EXEC) S_MOV_B32 sDst(SGPR68) src0(LITERAL_CONST) const: 0xc4 # VGPR196 # Indirect branch to noise(vf3;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR94) # .lbl9 # OpReturnValue: : << noise(vf3; S_MOV_B32 sDst(M0) src0(SGPR90) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR196) S_SETPC_B64 sDst(SGPR88) src0(SGPR88) # Float smN3(vf3;(FloatVector3* p) Function: Float smN3(vf3;() S_MOV_B64 sDst(SGPR100) src0(EXEC) # lb33 Label: lb33 # 277: OpLoad: FloatVector3: tmp277 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR99) const: 0x0 V_MOVRELS_B32 vDst(VGPR200) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR201) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR202) src0(VGPR2) # OpStore: : tmp277 >> param276 V_MOV_B32 vDst(VGPR197) src0(VGPR200) V_MOV_B32 vDst(VGPR198) src0(VGPR201) V_MOV_B32 vDst(VGPR199) src0(VGPR202) # 278: OpFunctionCall: Float: noise(vf3;(param276) S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0xc5 # VGPR[197:199] S_MOV_B64 sDst(SGPR102) src0(EXEC) S_MOV_B32 sDst(SGPR68) src0(LITERAL_CONST) const: 0xcb # VGPR203 # Indirect branch to noise(vf3;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR102) # .lbl10 # OpReturnValue: : << noise(vf3; S_MOV_B32 sDst(M0) src0(SGPR98) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR203) S_SETPC_B64 sDst(SGPR96) src0(SGPR96) # Float fbm3(vf3;(FloatVector3* p) Function: Float fbm3(vf3;() S_MOV_B64 sDst(SGPR108) src0(EXEC) # lb36 Label: lb36 # OpStore: : const100 >> f V_MOV_B32 vDst(VGPR209) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR204) src0(VGPR209) # OpStore: : const285 >> i V_MOV_B32 vDst(VGPR205) src0(1_INT) # OpBranch: to lb286 # lb286 Label: lb286 # OpLoopMerge: (merge: lb288, continue: lb289) # CF Block: Merge: lb288, Continue: lb289 S_MOV_B64 sDst(SGPR110) src0(EXEC) S_MOV_B64 sDst(SGPR112) src0(EXEC) S_MOV_B64 sDst(SGPR114) src0(EXEC) Label: lb286Loop # OpBranch: to lb290 # lb290 Label: lb290 # 291: OpLoad: Int: tmp291 << i Decorators: RelaxedPrecision # 293: OpSLessThanEqual: Bool: tmp293 << tmp291, const292 V_MOV_B32 vDst(VGPR210) src0(9_INT) V_CMP_LE_I32 dst(SGPR116) src0(VGPR205) src1(VGPR210) // VOP3a # OpBranchConditional: if(tmp293) then branch to lb287, else branch to lb288 # CF Block: Cond Branch: true: lb287, false: lb288 S_AND_B64 sDst(EXEC) src0(SGPR116) src1(EXEC) S_CBRANCH_EXECZ ??? lb288 # lb287 Label: lb287 S_MOV_B64 sDst(SGPR112) src0(EXEC) S_MOV_B64 sDst(SGPR114) src0(EXEC) # 295: OpLoad: Int: tmp295 << i Decorators: RelaxedPrecision # 296: OpConvertSToF: Float: tmp296 << tmp295 V_CVT_F32_I32 vDst(VGPR211) src0(VGPR205) # 297: OpExtInst(Exp2): Float: tmp297 << tmp296 V_EXP_F32 vDst(VGPR212) src0(VGPR211) # 298: OpLoad: FloatVector3: tmp298 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR107) const: 0x0 V_MOVRELS_B32 vDst(VGPR213) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR214) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR215) src0(VGPR2) # 300: OpVectorTimesScalar: FloatVector3: tmp300 << tmp298, tmp297 V_MUL_F32 vDst(VGPR216) src0(VGPR212) src1(VGPR213) // VOP2 V_MUL_F32 vDst(VGPR217) src0(VGPR212) src1(VGPR214) // VOP2 V_MUL_F32 vDst(VGPR218) src0(VGPR212) src1(VGPR215) // VOP2 # OpStore: : tmp300 >> param301 V_MOV_B32 vDst(VGPR206) src0(VGPR216) V_MOV_B32 vDst(VGPR207) src0(VGPR217) V_MOV_B32 vDst(VGPR208) src0(VGPR218) # 302: OpFunctionCall: Float: noise(vf3;(param301) S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0xce # VGPR[206:208] S_MOV_B64 sDst(SGPR118) src0(EXEC) S_MOV_B32 sDst(SGPR68) src0(LITERAL_CONST) const: 0xdb # VGPR219 # Indirect branch to noise(vf3;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR118) # .lbl11 # 304: OpFSub: Float: tmp304 << noise(vf3;, const303 V_MOV_B32 vDst(VGPR220) src0(0_5_F) V_SUB_F32 vDst(VGPR221) src0(VGPR219) src1(VGPR220) // VOP2 # 306: OpFDiv: Float: tmp306 << tmp304, tmp297 V_RCP_F32 vDst(VGPR222) src0(VGPR212) V_MUL_F32 vDst(VGPR222) src0(VGPR221) src1(VGPR222) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR222) src0(VGPR222) src1(VGPR212) src2(VGPR221) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 307: OpLoad: Float: tmp307 << f # 308: OpFAdd: Float: tmp308 << tmp307, tmp306 V_ADD_F32 vDst(VGPR223) src0(VGPR204) src1(VGPR222) // VOP2 # OpStore: : tmp308 >> f V_MOV_B32 vDst(VGPR204) src0(VGPR223) # OpBranch: to lb289 # lb289 Label: lb289 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR112) # 309: OpLoad: Int: tmp309 << i Decorators: RelaxedPrecision # 310: OpIAdd: Int: tmp310 << tmp309, const285 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR224) src0(1_INT) V_ADD_I32 vDst(VGPR225) src0(VGPR205) src1(VGPR224) // VOP2 # OpStore: : tmp310 >> i V_MOV_B32 vDst(VGPR205) src0(VGPR225) # OpBranch: to lb286 S_BRANCH ??? lb286Loop # lb288 Label: lb288 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR110) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR108) # 311: OpLoad: Float: tmp311 << f # OpReturnValue: : << tmp311 S_MOV_B32 sDst(M0) src0(SGPR106) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR204) S_SETPC_B64 sDst(SGPR104) src0(SGPR104) # FloatVector2 rotate(f1;vf2;(Float* a, FloatVector2* v) Function: FloatVector2 rotate(f1;vf2;(, FloatVector2 fbm3(vf3;.v) S_MOV_B64 sDst(SGPR126) src0(EXEC) # lb41 Label: lb41 # 314: OpLoad: Float: tmp314 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR123) const: 0x0 V_MOVRELS_B32 vDst(VGPR226) src0(VGPR0) # 315: OpExtInst(Cos): Float: tmp315 << tmp314 V_MUL_F32 vDst(VGPR227) src0(LITERAL_CONST) src1(VGPR226) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR227) src0(VGPR227) V_COS_F32 vDst(VGPR227) src0(VGPR227) # 316: OpAccessChain: Float*: v[0] # 317: OpLoad: Float: tmp317 << v[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELS_B32 vDst(VGPR228) src0(VGPR0) # 318: OpFMul: Float: tmp318 << tmp315, tmp317 V_MUL_F32 vDst(VGPR229) src0(VGPR227) src1(VGPR228) // VOP2 # 319: OpLoad: Float: tmp319 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR123) const: 0x0 V_MOVRELS_B32 vDst(VGPR230) src0(VGPR0) # 320: OpExtInst(Sin): Float: tmp320 << tmp319 V_MUL_F32 vDst(VGPR231) src0(LITERAL_CONST) src1(VGPR230) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR231) src0(VGPR231) V_SIN_F32 vDst(VGPR231) src0(VGPR231) # 321: OpAccessChain: Float*: v[1] # 322: OpLoad: Float: tmp322 << v[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELS_B32 vDst(VGPR232) src0(VGPR1) # 323: OpFMul: Float: tmp323 << tmp320, tmp322 V_MUL_F32 vDst(VGPR233) src0(VGPR231) src1(VGPR232) // VOP2 # 324: OpFAdd: Float: tmp324 << tmp318, tmp323 V_ADD_F32 vDst(VGPR234) src0(VGPR229) src1(VGPR233) // VOP2 # 325: OpLoad: Float: tmp325 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR123) const: 0x0 V_MOVRELS_B32 vDst(VGPR235) src0(VGPR0) # 326: OpExtInst(Cos): Float: tmp326 << tmp325 V_MUL_F32 vDst(VGPR236) src0(LITERAL_CONST) src1(VGPR235) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR236) src0(VGPR236) V_COS_F32 vDst(VGPR236) src0(VGPR236) # 327: OpAccessChain: Float*: v[1] # 328: OpLoad: Float: tmp328 << v[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELS_B32 vDst(VGPR237) src0(VGPR1) # 329: OpFMul: Float: tmp329 << tmp326, tmp328 V_MUL_F32 vDst(VGPR238) src0(VGPR236) src1(VGPR237) // VOP2 # 330: OpLoad: Float: tmp330 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR123) const: 0x0 V_MOVRELS_B32 vDst(VGPR239) src0(VGPR0) # 331: OpExtInst(Sin): Float: tmp331 << tmp330 V_MUL_F32 vDst(VGPR240) src0(LITERAL_CONST) src1(VGPR239) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR240) src0(VGPR240) V_SIN_F32 vDst(VGPR240) src0(VGPR240) # 332: OpAccessChain: Float*: v[0] # 333: OpLoad: Float: tmp333 << v[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELS_B32 vDst(VGPR241) src0(VGPR0) # 334: OpFMul: Float: tmp334 << tmp331, tmp333 V_MUL_F32 vDst(VGPR242) src0(VGPR240) src1(VGPR241) // VOP2 # 335: OpFSub: Float: tmp335 << tmp329, tmp334 V_SUB_F32 vDst(VGPR243) src0(VGPR238) src1(VGPR242) // VOP2 # 336: OpCompositeConstruct: FloatVector2: tmp336 << tmp324, tmp335 V_MOV_B32 vDst(VGPR244) src0(VGPR234) V_MOV_B32 vDst(VGPR245) src0(VGPR243) # OpReturnValue: : << tmp336 S_MOV_B32 sDst(M0) src0(SGPR122) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR244) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR245) S_SETPC_B64 sDst(SGPR120) src0(SGPR120) # Float sugarybit(vf2;(FloatVector2* p) Function: Float sugarybit(vf2;() S_MOV_B64 sDst(SGPR132) src0(EXEC) # lb44 Label: lb44 # 339: OpLoad: FloatVector2: tmp339 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR246) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR247) src0(VGPR1) # 343: OpExtInst(FClamp): FloatVector2: tmp343 << tmp339, const341, const342 V_MOV_B32 vDst(VGPR248) src0(M1_0_F) V_MOV_B32 vDst(VGPR249) src0(M1_0_F) V_MOV_B32 vDst(VGPR250) src0(1_0_F) V_MOV_B32 vDst(VGPR251) src0(1_0_F) V_MAX_F32 vDst(VGPR252) src0(VGPR246) src1(VGPR248) // VOP2 V_MAX_F32 vDst(VGPR253) src0(VGPR247) src1(VGPR249) // VOP2 V_MIN_F32 vDst(VGPR252) src0(VGPR252) src1(VGPR250) // VOP2 V_MIN_F32 vDst(VGPR253) src0(VGPR253) src1(VGPR251) // VOP2 # OpStore: : tmp343 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR252) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR253) # 346: OpAccessChain: Float*: p[0] # 347: OpLoad: Float: tmp347 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 348: OpExtInst(FAbs): Float: tmp348 << tmp347 V_ADD_F32 vDst(VGPR255) src0(VGPR254) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 350: OpExtInst(Pow): Float: tmp350 << tmp348, const349 V_MOV_B32 vDst(VGPR256) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR257) src0(VGPR255) V_MUL_F32 vDst(VGPR257) src0(VGPR256) src1(VGPR257) // VOP2 V_EXP_F32 vDst(VGPR257) src0(VGPR257) # 351: OpFSub: Float: tmp351 << const106, tmp350 V_SUB_F32 vDst(VGPR258) src0(1_0_F) src1(VGPR257) // VOP2 # 352: OpAccessChain: Float*: p[1] # 353: OpLoad: Float: tmp353 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR259) src0(VGPR1) # 354: OpAccessChain: Float*: o[1] # 355: OpCompositeExtract: Float: tmp355 << const101, 1 V_MOV_B32 vDst(VGPR261) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR260) src0(VGPR262) # 356: OpFAdd: Float: tmp356 << tmp353, tmp355 V_ADD_F32 vDst(VGPR262) src0(VGPR259) src1(VGPR260) // VOP2 # 357: OpExtInst(FAbs): Float: tmp357 << tmp356 V_ADD_F32 vDst(VGPR263) src0(VGPR262) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 358: OpExtInst(Pow): Float: tmp358 << tmp357, const349 V_MOV_B32 vDst(VGPR264) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR265) src0(VGPR263) V_MUL_F32 vDst(VGPR265) src0(VGPR264) src1(VGPR265) // VOP2 V_EXP_F32 vDst(VGPR265) src0(VGPR265) # 359: OpFSub: Float: tmp359 << const106, tmp358 V_SUB_F32 vDst(VGPR266) src0(1_0_F) src1(VGPR265) // VOP2 # 360: OpFMul: Float: tmp360 << tmp351, tmp359 V_MUL_F32 vDst(VGPR267) src0(VGPR258) src1(VGPR266) // VOP2 # 362: OpFMul: Float: tmp362 << tmp360, const361 V_MOV_B32 vDst(VGPR268) src0(LITERAL_CONST) const: 0x3f733333 V_MUL_F32 vDst(VGPR269) src0(VGPR267) src1(VGPR268) // VOP2 # 363: OpExtInst(Pow): Float: tmp363 << tmp362, const303 V_MOV_B32 vDst(VGPR270) src0(0_5_F) V_LOG_F32 vDst(VGPR271) src0(VGPR269) V_MUL_F32 vDst(VGPR271) src0(VGPR270) src1(VGPR271) // VOP2 V_EXP_F32 vDst(VGPR271) src0(VGPR271) # 364: OpFSub: Float: tmp364 << const106, tmp363 V_SUB_F32 vDst(VGPR272) src0(1_0_F) src1(VGPR271) // VOP2 # 366: OpAccessChain: Float*: p[0] # 367: OpLoad: Float: tmp367 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR273) src0(VGPR0) # 368: OpExtInst(FAbs): Float: tmp368 << tmp367 V_ADD_F32 vDst(VGPR274) src0(VGPR273) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 369: OpExtInst(Pow): Float: tmp369 << tmp368, const349 V_MOV_B32 vDst(VGPR275) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR276) src0(VGPR274) V_MUL_F32 vDst(VGPR276) src0(VGPR275) src1(VGPR276) // VOP2 V_EXP_F32 vDst(VGPR276) src0(VGPR276) # 370: OpFSub: Float: tmp370 << const106, tmp369 V_SUB_F32 vDst(VGPR277) src0(1_0_F) src1(VGPR276) // VOP2 # 371: OpAccessChain: Float*: p[1] # 372: OpLoad: Float: tmp372 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR278) src0(VGPR1) # 373: OpExtInst(FAbs): Float: tmp373 << tmp372 V_ADD_F32 vDst(VGPR279) src0(VGPR278) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 374: OpExtInst(Pow): Float: tmp374 << tmp373, const349 V_MOV_B32 vDst(VGPR280) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR281) src0(VGPR279) V_MUL_F32 vDst(VGPR281) src0(VGPR280) src1(VGPR281) // VOP2 V_EXP_F32 vDst(VGPR281) src0(VGPR281) # 375: OpFSub: Float: tmp375 << const106, tmp374 V_SUB_F32 vDst(VGPR282) src0(1_0_F) src1(VGPR281) // VOP2 # 376: OpFMul: Float: tmp376 << tmp370, tmp375 V_MUL_F32 vDst(VGPR283) src0(VGPR277) src1(VGPR282) // VOP2 # 378: OpExtInst(Pow): Float: tmp378 << tmp376, const377 V_MOV_B32 vDst(VGPR284) src0(4_0_F) V_LOG_F32 vDst(VGPR285) src0(VGPR283) V_MUL_F32 vDst(VGPR285) src0(VGPR284) src1(VGPR285) // VOP2 V_EXP_F32 vDst(VGPR285) src0(VGPR285) # 381: OpFMul: Float: tmp381 << tmp364, tmp378 V_MUL_F32 vDst(VGPR286) src0(VGPR272) src1(VGPR285) // VOP2 # 382: OpFMul: Float: tmp382 << tmp381, const109 V_MOV_B32 vDst(VGPR287) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR288) src0(VGPR286) src1(VGPR287) // VOP2 # OpReturnValue: : << tmp382 S_MOV_B32 sDst(M0) src0(SGPR130) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR288) S_SETPC_B64 sDst(SGPR128) src0(SGPR128) # Float sugarlayer(vf2;f1;(FloatVector2* t, Float* ndotv) Function: Float sugarlayer(vf2;f1;(, Float sugarybit(vf2;.ndotv) S_MOV_B64 sDst(SGPR140) src0(EXEC) # lb49 Label: lb49 # 386: OpLoad: FloatVector2: tmp386 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR137) const: 0x0 V_MOVRELS_B32 vDst(VGPR300) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR301) src0(VGPR1) # 387: OpVectorTimesScalar: FloatVector2: tmp387 << tmp386, const349 V_MOV_B32 vDst(VGPR304) src0(LITERAL_CONST) const: 0x41000000 V_MUL_F32 vDst(VGPR302) src0(VGPR304) src1(VGPR300) // VOP2 V_MUL_F32 vDst(VGPR303) src0(VGPR304) src1(VGPR301) // VOP2 # 390: OpExtInst(Fract): FloatVector2: tmp390 << tmp387 V_FRACT_F32 vDst(VGPR305) src0(VGPR302) V_FRACT_F32 vDst(VGPR306) src0(VGPR303) # 392: OpFSub: FloatVector2: tmp392 << tmp390, const391 V_MOV_B32 vDst(VGPR307) src0(0_5_F) V_MOV_B32 vDst(VGPR308) src0(0_5_F) V_SUB_F32 vDst(VGPR309) src0(VGPR305) src1(VGPR307) // VOP2 V_SUB_F32 vDst(VGPR310) src0(VGPR306) src1(VGPR308) // VOP2 # 395: OpExtInst(Floor): FloatVector2: tmp395 << tmp387 V_FLOOR_F32 vDst(VGPR311) src0(VGPR302) V_FLOOR_F32 vDst(VGPR312) src0(VGPR303) # 397: OpAccessChain: Float*: c[0] # 398: OpCompositeExtract: Float: tmp398 << tmp395, 0 V_MOV_B32 vDst(VGPR313) src0(VGPR311) # 399: OpAccessChain: Float*: c[1] # 400: OpCompositeExtract: Float: tmp400 << tmp395, 1 V_MOV_B32 vDst(VGPR314) src0(VGPR312) # 402: OpFMul: Float: tmp402 << tmp400, const401 V_MOV_B32 vDst(VGPR315) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR316) src0(VGPR314) src1(VGPR315) // VOP2 # 403: OpFAdd: Float: tmp403 << tmp398, tmp402 V_ADD_F32 vDst(VGPR317) src0(VGPR313) src1(VGPR316) // VOP2 # 405: OpAccessChain: Float*: c[1] # 406: OpCompositeExtract: Float: tmp406 << tmp395, 1 V_MOV_B32 vDst(VGPR318) src0(VGPR312) # 408: OpFMul: Float: tmp408 << tmp406, const407 V_MOV_B32 vDst(VGPR319) src0(LITERAL_CONST) const: 0x42540000 V_MUL_F32 vDst(VGPR320) src0(VGPR318) src1(VGPR319) // VOP2 # 409: OpExtInst(Cos): Float: tmp409 << tmp408 V_MUL_F32 vDst(VGPR321) src0(LITERAL_CONST) src1(VGPR320) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR321) src0(VGPR321) V_COS_F32 vDst(VGPR321) src0(VGPR321) # 410: OpAccessChain: Float*: c[0] # 411: OpCompositeExtract: Float: tmp411 << tmp395, 0 V_MOV_B32 vDst(VGPR322) src0(VGPR311) # 413: OpFMul: Float: tmp413 << tmp411, const412 V_MOV_B32 vDst(VGPR323) src0(LITERAL_CONST) const: 0x42fa0000 V_MUL_F32 vDst(VGPR324) src0(VGPR322) src1(VGPR323) // VOP2 # 414: OpExtInst(Sin): Float: tmp414 << tmp413 V_MUL_F32 vDst(VGPR325) src0(LITERAL_CONST) src1(VGPR324) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR325) src0(VGPR325) V_SIN_F32 vDst(VGPR325) src0(VGPR325) # 415: OpCompositeConstruct: FloatVector2: tmp415 << tmp409, tmp414 V_MOV_B32 vDst(VGPR326) src0(VGPR321) V_MOV_B32 vDst(VGPR327) src0(VGPR325) # 417: OpVectorTimesScalar: FloatVector2: tmp417 << tmp415, const416 V_MOV_B32 vDst(VGPR330) src0(LITERAL_CONST) const: 0x40200000 V_MUL_F32 vDst(VGPR328) src0(VGPR330) src1(VGPR326) // VOP2 V_MUL_F32 vDst(VGPR329) src0(VGPR330) src1(VGPR327) // VOP2 # OpStore: : tmp395 >> param419 V_MOV_B32 vDst(VGPR289) src0(VGPR311) V_MOV_B32 vDst(VGPR290) src0(VGPR312) # 421: OpFunctionCall: Float: smN2(vf2;(param419) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x121 # VGPR[289:290] S_MOV_B64 sDst(SGPR142) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x14b # VGPR331 # Indirect branch to smN2(vf2;: ??? S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_ADD_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR142) # .lbl12 # 425: OpFAdd: FloatVector2: tmp425 << tmp395, const424 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x42c80000 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x42c80000 V_ADD_F32 vDst(VGPR334) src0(VGPR311) src1(VGPR332) // VOP2 V_ADD_F32 vDst(VGPR335) src0(VGPR312) src1(VGPR333) // VOP2 # OpStore: : tmp425 >> param426 V_MOV_B32 vDst(VGPR291) src0(VGPR334) V_MOV_B32 vDst(VGPR292) src0(VGPR335) # 427: OpFunctionCall: Float: smN2(vf2;(param426) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x123 # VGPR[291:292] S_MOV_B64 sDst(SGPR144) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x150 # VGPR336 # Indirect branch to smN2(vf2;: ??? S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_ADD_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR144) # .lbl13 # 428: OpCompositeConstruct: FloatVector2: tmp428 << smN2(vf2;, smN2(vf2; V_MOV_B32 vDst(VGPR337) src0(VGPR331) V_MOV_B32 vDst(VGPR338) src0(VGPR336) # 429: OpCompositeConstruct: FloatVector2: tmp429 << const106, const106 V_MOV_B32 vDst(VGPR339) src0(1_0_F) V_MOV_B32 vDst(VGPR340) src0(1_0_F) # 430: OpFAdd: FloatVector2: tmp430 << tmp429, tmp428 V_ADD_F32 vDst(VGPR341) src0(VGPR339) src1(VGPR337) // VOP2 V_ADD_F32 vDst(VGPR342) src0(VGPR340) src1(VGPR338) // VOP2 # 432: OpLoad: Float: tmp432 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR138) const: 0x0 V_MOVRELS_B32 vDst(VGPR343) src0(VGPR0) # 433: OpFSub: Float: tmp433 << const106, tmp432 V_SUB_F32 vDst(VGPR344) src0(1_0_F) src1(VGPR343) // VOP2 # 434: OpExtInst(Pow): Float: tmp434 << tmp433, const377 V_MOV_B32 vDst(VGPR345) src0(4_0_F) V_LOG_F32 vDst(VGPR346) src0(VGPR344) V_MUL_F32 vDst(VGPR346) src0(VGPR345) src1(VGPR346) // VOP2 V_EXP_F32 vDst(VGPR346) src0(VGPR346) # 436: OpExtInst(FMix): Float: tmp436 << const106, tmp434, const435 V_MOV_B32 vDst(VGPR347) src0(LITERAL_CONST) const: 0x3f666666 V_SUBREV_F32 vDst(VGPR348) src0(VGPR347) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR348) src0(1_0_F) src1(VGPR348) // VOP2 V_MAD_F32 vDst(VGPR348) src0(VGPR346) src1(VGPR347) src2(VGPR348) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 438: OpFMul: Float: tmp438 << tmp436, const437 V_MOV_B32 vDst(VGPR349) src0(LITERAL_CONST) const: 0x41c80000 V_MUL_F32 vDst(VGPR350) src0(VGPR348) src1(VGPR349) // VOP2 # 441: OpFMul: FloatVector2: tmp441 << tmp392, tmp430 V_MUL_F32 vDst(VGPR351) src0(VGPR309) src1(VGPR341) // VOP2 V_MUL_F32 vDst(VGPR352) src0(VGPR310) src1(VGPR342) // VOP2 # 442: OpVectorTimesScalar: FloatVector2: tmp442 << tmp441, const377 V_MOV_B32 vDst(VGPR355) src0(4_0_F) V_MUL_F32 vDst(VGPR353) src0(VGPR355) src1(VGPR351) // VOP2 V_MUL_F32 vDst(VGPR354) src0(VGPR355) src1(VGPR352) // VOP2 # 444: OpFAdd: FloatVector2: tmp444 << tmp442, tmp417 V_ADD_F32 vDst(VGPR356) src0(VGPR353) src1(VGPR328) // VOP2 V_ADD_F32 vDst(VGPR357) src0(VGPR354) src1(VGPR329) // VOP2 # OpStore: : tmp403 >> param445 V_MOV_B32 vDst(VGPR293) src0(VGPR317) # OpStore: : tmp444 >> param447 V_MOV_B32 vDst(VGPR294) src0(VGPR356) V_MOV_B32 vDst(VGPR295) src0(VGPR357) # 448: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param445, param447) S_ADD_U32 sDst(SGPR123) src0(LITERAL_CONST) src1(0) const: 0x125 # VGPR293 S_ADD_U32 sDst(SGPR124) src0(LITERAL_CONST) src1(0) const: 0x126 # VGPR[294:295] S_MOV_B64 sDst(SGPR146) src0(EXEC) S_MOV_B32 sDst(SGPR122) src0(LITERAL_CONST) const: 0x166 # VGPR[358:359] # Indirect branch to rotate(f1;vf2;: ??? S_GETPC_B64 sDst(SGPR120) src0(SGPR120) S_ADD_U32 sDst(SGPR120) src0(SGPR120) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR121) src0(SGPR121) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR120) src0(SGPR120) S_MOV_B64 sDst(EXEC) src0(SGPR146) # .lbl14 # OpStore: : rotate(f1;vf2; >> param449 V_MOV_B32 vDst(VGPR296) src0(VGPR358) V_MOV_B32 vDst(VGPR297) src0(VGPR359) # 450: OpFunctionCall: Float: sugarybit(vf2;(param449) S_ADD_U32 sDst(SGPR131) src0(LITERAL_CONST) src1(0) const: 0x128 # VGPR[296:297] S_MOV_B64 sDst(SGPR148) src0(EXEC) S_MOV_B32 sDst(SGPR130) src0(LITERAL_CONST) const: 0x168 # VGPR360 # Indirect branch to sugarybit(vf2;: ??? S_GETPC_B64 sDst(SGPR128) src0(SGPR128) S_ADD_U32 sDst(SGPR128) src0(SGPR128) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR129) src0(SGPR129) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR128) src0(SGPR128) S_MOV_B64 sDst(EXEC) src0(SGPR148) # .lbl15 # 452: OpVectorTimesScalar: FloatVector2: tmp452 << tmp387, const401 V_MOV_B32 vDst(VGPR363) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR361) src0(VGPR363) src1(VGPR302) // VOP2 V_MUL_F32 vDst(VGPR362) src0(VGPR363) src1(VGPR303) // VOP2 # OpStore: : tmp452 >> param453 V_MOV_B32 vDst(VGPR298) src0(VGPR361) V_MOV_B32 vDst(VGPR299) src0(VGPR362) # 454: OpFunctionCall: Float: smN2(vf2;(param453) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x12a # VGPR[298:299] S_MOV_B64 sDst(SGPR150) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x16c # VGPR364 # Indirect branch to smN2(vf2;: ??? S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_ADD_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR150) # .lbl16 # 455: OpFSub: Float: tmp455 << smN2(vf2;, const303 V_MOV_B32 vDst(VGPR365) src0(0_5_F) V_SUB_F32 vDst(VGPR366) src0(VGPR364) src1(VGPR365) // VOP2 # 456: OpExtInst(FMax): Float: tmp456 << const100, tmp455 V_MOV_B32 vDst(VGPR367) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR368) src0(VGPR367) src1(VGPR366) // VOP2 # 457: OpFMul: Float: tmp457 << sugarybit(vf2;, tmp456 V_MUL_F32 vDst(VGPR369) src0(VGPR360) src1(VGPR368) // VOP2 # 459: OpFMul: Float: tmp459 << tmp457, tmp438 V_MUL_F32 vDst(VGPR370) src0(VGPR369) src1(VGPR350) // VOP2 # OpReturnValue: : << tmp459 S_MOV_B32 sDst(M0) src0(SGPR136) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR370) S_SETPC_B64 sDst(SGPR134) src0(SGPR134) # FloatVector3 saturatecol(vf3;(FloatVector3* c) Function: FloatVector3 saturatecol(vf3;() S_MOV_B64 sDst(SGPR156) src0(EXEC) # lb53 Label: lb53 # 462: OpLoad: FloatVector3: tmp462 << c S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR155) const: 0x0 V_MOVRELS_B32 vDst(VGPR372) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR373) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR374) src0(VGPR2) # 464: OpLoad: Float: tmp464 << colour # OpStore: : tmp464 >> param463 V_MOV_B32 vDst(VGPR371) src0(VGPR30) # 465: OpFunctionCall: FloatVector3: gumRamp(f1;(param463) S_ADD_U32 sDst(SGPR41) src0(LITERAL_CONST) src1(0) const: 0x173 # VGPR371 S_MOV_B64 sDst(SGPR158) src0(EXEC) S_MOV_B32 sDst(SGPR40) src0(LITERAL_CONST) const: 0x177 # VGPR[375:377] # Indirect branch to gumRamp(f1;: ??? S_GETPC_B64 sDst(SGPR38) src0(SGPR38) S_ADD_U32 sDst(SGPR38) src0(SGPR38) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR39) src0(SGPR39) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR38) src0(SGPR38) S_MOV_B64 sDst(EXEC) src0(SGPR158) # .lbl17 # 466: OpExtInst(Pow): FloatVector3: tmp466 << tmp462, gumRamp(f1; V_LOG_F32 vDst(VGPR378) src0(VGPR372) V_LOG_F32 vDst(VGPR379) src0(VGPR373) V_LOG_F32 vDst(VGPR380) src0(VGPR374) V_MUL_F32 vDst(VGPR378) src0(VGPR375) src1(VGPR378) // VOP2 V_MUL_F32 vDst(VGPR379) src0(VGPR376) src1(VGPR379) // VOP2 V_MUL_F32 vDst(VGPR380) src0(VGPR377) src1(VGPR380) // VOP2 V_EXP_F32 vDst(VGPR378) src0(VGPR378) V_EXP_F32 vDst(VGPR379) src0(VGPR379) V_EXP_F32 vDst(VGPR380) src0(VGPR380) # OpReturnValue: : << tmp466 S_MOV_B32 sDst(M0) src0(SGPR154) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR378) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR379) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR380) S_SETPC_B64 sDst(SGPR152) src0(SGPR152) # Float sprinkles2(vf2;f1;(FloatVector2* coord, Float* ndotv) Function: Float sprinkles2(vf2;f1;(, Float saturatecol(vf3;.ndotv) S_MOV_B64 sDst(SGPR166) src0(EXEC) # lb57 Label: lb57 # OpStore: : const100 >> sprinkle V_MOV_B32 vDst(VGPR386) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR381) src0(VGPR386) # OpStore: : const471 >> i V_MOV_B32 vDst(VGPR382) src0(0) # OpBranch: to lb472 # lb472 Label: lb472 # OpLoopMerge: (merge: lb474, continue: lb475) # CF Block: Merge: lb474, Continue: lb475 S_MOV_B64 sDst(SGPR168) src0(EXEC) S_MOV_B64 sDst(SGPR170) src0(EXEC) S_MOV_B64 sDst(SGPR172) src0(EXEC) Label: lb472Loop # OpBranch: to lb476 # lb476 Label: lb476 # 477: OpLoad: Int: tmp477 << i Decorators: RelaxedPrecision # 479: OpSLessThan: Bool: tmp479 << tmp477, const478 V_MOV_B32 vDst(VGPR387) src0(4_INT) V_CMP_LT_I32 dst(SGPR174) src0(VGPR382) src1(VGPR387) // VOP3a # OpBranchConditional: if(tmp479) then branch to lb473, else branch to lb474 # CF Block: Cond Branch: true: lb473, false: lb474 S_AND_B64 sDst(EXEC) src0(SGPR174) src1(EXEC) S_CBRANCH_EXECZ ??? lb474 # lb473 Label: lb473 S_MOV_B64 sDst(SGPR170) src0(EXEC) S_MOV_B64 sDst(SGPR172) src0(EXEC) # 480: OpLoad: FloatVector2: tmp480 << coord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR163) const: 0x0 V_MOVRELS_B32 vDst(VGPR388) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR389) src0(VGPR1) # 481: OpLoad: Int: tmp481 << i Decorators: RelaxedPrecision # 482: OpConvertSToF: Float: tmp482 << tmp481 V_CVT_F32_I32 vDst(VGPR390) src0(VGPR382) # 484: OpFMul: Float: tmp484 << tmp482, const483 V_MOV_B32 vDst(VGPR391) src0(LITERAL_CONST) const: 0x41273333 V_MUL_F32 vDst(VGPR392) src0(VGPR390) src1(VGPR391) // VOP2 # 485: OpCompositeConstruct: FloatVector2: tmp485 << tmp484, tmp484 V_MOV_B32 vDst(VGPR393) src0(VGPR392) V_MOV_B32 vDst(VGPR394) src0(VGPR392) # 486: OpFAdd: FloatVector2: tmp486 << tmp480, tmp485 V_ADD_F32 vDst(VGPR395) src0(VGPR388) src1(VGPR393) // VOP2 V_ADD_F32 vDst(VGPR396) src0(VGPR389) src1(VGPR394) // VOP2 # 487: OpLoad: Int: tmp487 << i Decorators: RelaxedPrecision # 488: OpConvertSToF: Float: tmp488 << tmp487 V_CVT_F32_I32 vDst(VGPR397) src0(VGPR382) # 490: OpFMul: Float: tmp490 << tmp488, const489 V_MOV_B32 vDst(VGPR398) src0(LITERAL_CONST) const: 0x3e4ccccd V_MUL_F32 vDst(VGPR399) src0(VGPR397) src1(VGPR398) // VOP2 # 491: OpFAdd: Float: tmp491 << const106, tmp490 V_ADD_F32 vDst(VGPR400) src0(1_0_F) src1(VGPR399) // VOP2 # 492: OpVectorTimesScalar: FloatVector2: tmp492 << tmp486, tmp491 V_MUL_F32 vDst(VGPR401) src0(VGPR400) src1(VGPR395) // VOP2 V_MUL_F32 vDst(VGPR402) src0(VGPR400) src1(VGPR396) // VOP2 # OpStore: : tmp492 >> param493 V_MOV_B32 vDst(VGPR383) src0(VGPR401) V_MOV_B32 vDst(VGPR384) src0(VGPR402) # 495: OpLoad: Float: tmp495 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR164) const: 0x0 V_MOVRELS_B32 vDst(VGPR403) src0(VGPR0) # OpStore: : tmp495 >> param494 V_MOV_B32 vDst(VGPR385) src0(VGPR403) # 496: OpFunctionCall: Float: sugarlayer(vf2;f1;(param493, param494) S_ADD_U32 sDst(SGPR137) src0(LITERAL_CONST) src1(0) const: 0x17f # VGPR[383:384] S_ADD_U32 sDst(SGPR138) src0(LITERAL_CONST) src1(0) const: 0x181 # VGPR385 S_MOV_B64 sDst(SGPR176) src0(EXEC) S_MOV_B32 sDst(SGPR136) src0(LITERAL_CONST) const: 0x194 # VGPR404 # Indirect branch to sugarlayer(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR134) src0(SGPR134) S_ADD_U32 sDst(SGPR134) src0(SGPR134) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR135) src0(SGPR135) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR134) src0(SGPR134) S_MOV_B64 sDst(EXEC) src0(SGPR176) # .lbl18 # 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision # 498: OpConvertSToF: Float: tmp498 << tmp497 V_CVT_F32_I32 vDst(VGPR405) src0(VGPR382) # 499: OpFDiv: Float: tmp499 << tmp498, const377 V_MOV_B32 vDst(VGPR406) src0(4_0_F) V_RCP_F32 vDst(VGPR407) src0(VGPR406) V_MUL_F32 vDst(VGPR407) src0(VGPR405) src1(VGPR407) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR407) src0(VGPR407) src1(VGPR406) src2(VGPR405) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 500: OpFSub: Float: tmp500 << const106, tmp499 V_SUB_F32 vDst(VGPR408) src0(1_0_F) src1(VGPR407) // VOP2 # 501: OpExtInst(Pow): Float: tmp501 << tmp500, const377 V_MOV_B32 vDst(VGPR409) src0(4_0_F) V_LOG_F32 vDst(VGPR410) src0(VGPR408) V_MUL_F32 vDst(VGPR410) src0(VGPR409) src1(VGPR410) // VOP2 V_EXP_F32 vDst(VGPR410) src0(VGPR410) # 502: OpFMul: Float: tmp502 << sugarlayer(vf2;f1;, tmp501 V_MUL_F32 vDst(VGPR411) src0(VGPR404) src1(VGPR410) // VOP2 # 503: OpLoad: Float: tmp503 << sprinkle # 504: OpFAdd: Float: tmp504 << tmp503, tmp502 V_ADD_F32 vDst(VGPR412) src0(VGPR381) src1(VGPR411) // VOP2 # OpStore: : tmp504 >> sprinkle V_MOV_B32 vDst(VGPR381) src0(VGPR412) # OpBranch: to lb475 # lb475 Label: lb475 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR170) # 505: OpLoad: Int: tmp505 << i Decorators: RelaxedPrecision # 506: OpIAdd: Int: tmp506 << tmp505, const285 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR413) src0(1_INT) V_ADD_I32 vDst(VGPR414) src0(VGPR382) src1(VGPR413) // VOP2 # OpStore: : tmp506 >> i V_MOV_B32 vDst(VGPR382) src0(VGPR414) # OpBranch: to lb472 S_BRANCH ??? lb472Loop # lb474 Label: lb474 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR168) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR166) # 507: OpLoad: Float: tmp507 << sprinkle # OpReturnValue: : << tmp507 S_MOV_B32 sDst(M0) src0(SGPR162) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR381) S_SETPC_B64 sDst(SGPR160) src0(SGPR160) # Float sprinkles(vf2;f1;(FloatVector2* coord, Float* ndotv) Function: Float sprinkles(vf2;f1;(, Float sprinkles2(vf2;f1;.ndotv) S_MOV_B64 sDst(SGPR184) src0(EXEC) # lb61 Label: lb61 # 510: OpLoad: FloatVector2: tmp510 << coord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR181) const: 0x0 V_MOVRELS_B32 vDst(VGPR421) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR422) src0(VGPR1) # 512: OpVectorTimesScalar: FloatVector2: tmp512 << tmp510, const511 V_MOV_B32 vDst(VGPR425) src0(LITERAL_CONST) const: 0x3f400000 V_MUL_F32 vDst(VGPR423) src0(VGPR425) src1(VGPR421) // VOP2 V_MUL_F32 vDst(VGPR424) src0(VGPR425) src1(VGPR422) // VOP2 # OpStore: : tmp512 >> param513 V_MOV_B32 vDst(VGPR415) src0(VGPR423) V_MOV_B32 vDst(VGPR416) src0(VGPR424) # 515: OpLoad: Float: tmp515 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR182) const: 0x0 V_MOVRELS_B32 vDst(VGPR426) src0(VGPR0) # OpStore: : tmp515 >> param514 V_MOV_B32 vDst(VGPR417) src0(VGPR426) # 516: OpFunctionCall: Float: sprinkles2(vf2;f1;(param513, param514) S_ADD_U32 sDst(SGPR163) src0(LITERAL_CONST) src1(0) const: 0x19f # VGPR[415:416] S_ADD_U32 sDst(SGPR164) src0(LITERAL_CONST) src1(0) const: 0x1a1 # VGPR417 S_MOV_B64 sDst(SGPR186) src0(EXEC) S_MOV_B32 sDst(SGPR162) src0(LITERAL_CONST) const: 0x1ab # VGPR427 # Indirect branch to sprinkles2(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR160) src0(SGPR160) S_ADD_U32 sDst(SGPR160) src0(SGPR160) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR161) src0(SGPR161) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR160) src0(SGPR160) S_MOV_B64 sDst(EXEC) src0(SGPR186) # .lbl19 # 517: OpLoad: FloatVector2: tmp517 << coord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR181) const: 0x0 V_MOVRELS_B32 vDst(VGPR428) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR429) src0(VGPR1) # 518: OpVectorTimesScalar: FloatVector2: tmp518 << tmp517, const127 V_MOV_B32 vDst(VGPR432) src0(2_0_F) V_MUL_F32 vDst(VGPR430) src0(VGPR432) src1(VGPR428) // VOP2 V_MUL_F32 vDst(VGPR431) src0(VGPR432) src1(VGPR429) // VOP2 # OpStore: : tmp518 >> param519 V_MOV_B32 vDst(VGPR418) src0(VGPR430) V_MOV_B32 vDst(VGPR419) src0(VGPR431) # 521: OpLoad: Float: tmp521 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR182) const: 0x0 V_MOVRELS_B32 vDst(VGPR433) src0(VGPR0) # OpStore: : tmp521 >> param520 V_MOV_B32 vDst(VGPR420) src0(VGPR433) # 522: OpFunctionCall: Float: sprinkles2(vf2;f1;(param519, param520) S_ADD_U32 sDst(SGPR163) src0(LITERAL_CONST) src1(0) const: 0x1a2 # VGPR[418:419] S_ADD_U32 sDst(SGPR164) src0(LITERAL_CONST) src1(0) const: 0x1a4 # VGPR420 S_MOV_B64 sDst(SGPR188) src0(EXEC) S_MOV_B32 sDst(SGPR162) src0(LITERAL_CONST) const: 0x1b2 # VGPR434 # Indirect branch to sprinkles2(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR160) src0(SGPR160) S_ADD_U32 sDst(SGPR160) src0(SGPR160) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR161) src0(SGPR161) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR160) src0(SGPR160) S_MOV_B64 sDst(EXEC) src0(SGPR188) # .lbl20 # 524: OpFMul: Float: tmp524 << sprinkles2(vf2;f1;, const523 V_MOV_B32 vDst(VGPR435) src0(LITERAL_CONST) const: 0x3e99999a V_MUL_F32 vDst(VGPR436) src0(VGPR434) src1(VGPR435) // VOP2 # 525: OpFAdd: Float: tmp525 << sprinkles2(vf2;f1;, tmp524 V_ADD_F32 vDst(VGPR437) src0(VGPR427) src1(VGPR436) // VOP2 # OpReturnValue: : << tmp525 S_MOV_B32 sDst(M0) src0(SGPR180) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR437) S_SETPC_B64 sDst(SGPR178) src0(SGPR178) # FloatVector3 gummy(vf3;vf3;vf3;(FloatVector3* no, FloatVector3* vo, FloatVector3* v) Function: FloatVector3 gummy(vf3;vf3;vf3;(, FloatVector3 sprinkles(vf2;f1;.vo, FloatVector3 sprinkles(vf2;f1;.v) S_MOV_B64 sDst(SGPR196) src0(EXEC) # lb67 Label: lb67 # 529: OpLoad: FloatVector3: tmp529 << no S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR451) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR452) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR453) src0(VGPR2) # 530: OpLoad: FloatVector3: tmp530 << v S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR195) const: 0x0 V_MOVRELS_B32 vDst(VGPR454) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR455) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR456) src0(VGPR2) # 531: OpFNegate: FloatVector3: tmp531 << tmp530 V_MUL_F32 vDst(VGPR457) src0(M1_0_F) src1(VGPR454) // VOP2 V_MUL_F32 vDst(VGPR458) src0(M1_0_F) src1(VGPR455) // VOP2 V_MUL_F32 vDst(VGPR459) src0(M1_0_F) src1(VGPR456) // VOP2 # 532: OpDot: Float: tmp532 << tmp529, tmp531 V_MUL_F32 vDst(VGPR460) src0(VGPR451) src1(VGPR457) // VOP2 V_MAC_F32 vDst(VGPR460) src0(VGPR452) src1(VGPR458) // VOP2 V_MAC_F32 vDst(VGPR460) src0(VGPR453) src1(VGPR459) // VOP2 # 534: OpAccessChain: Float*: no[2] # 535: OpLoad: Float: tmp535 << no[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR461) src0(VGPR2) # 536: OpAccessChain: Float*: no[0] # 537: OpLoad: Float: tmp537 << no[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR462) src0(VGPR0) # 538: OpExtInst(Atan2): Float: tmp538 << tmp535, tmp537 V_MOV_B32 vDst(VGPR463) src0(LITERAL_CONST) const: 0xbc5cdd30 V_MOV_B32 vDst(VGPR464) src0(LITERAL_CONST) const: 0x3d6b6d55 V_MOV_B32 vDst(VGPR465) src0(LITERAL_CONST) const: 0xbdf84c31 V_MOV_B32 vDst(VGPR466) src0(LITERAL_CONST) const: 0x3e4854c9 V_MOV_B32 vDst(VGPR467) src0(LITERAL_CONST) const: 0xbeaa7e45 V_MOV_B32 vDst(VGPR468) src0(LITERAL_CONST) const: 0x3f7fffb7 V_MOV_B32 vDst(VGPR469) src0(LITERAL_CONST) const: 0x3fc90fdb V_MOV_B32 vDst(VGPR470) src0(LITERAL_CONST) const: 0x40490fdb V_ADD_F32 vDst(VGPR471) src0(VGPR462) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR472) src0(VGPR461) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_MAX_F32 vDst(VGPR473) src0(VGPR471) src1(VGPR472) // VOP2 V_MIN_F32 vDst(VGPR474) src0(VGPR471) src1(VGPR472) // VOP2 V_RCP_F32 vDst(VGPR473) src0(VGPR473) V_MUL_F32 vDst(VGPR473) src0(VGPR473) src1(VGPR474) // VOP2 V_MUL_F32 vDst(VGPR474) src0(VGPR473) src1(VGPR473) // VOP2 V_MAD_F32 vDst(VGPR475) src0(VGPR463) src1(VGPR474) src2(VGPR464) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR465) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR466) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR467) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR468) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR473) // VOP2 V_CMP_GT_F32 src0(VGPR472) src1(VGPR471) # CF Block: Merge: .lbl21 S_MOV_B64 sDst(SGPR198) src0(EXEC) # CF Block: Cond Branch: true: .lbl22, false: .lbl21 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl21 Label: .lbl22 V_SUB_F32 vDst(VGPR475) src0(VGPR469) src1(VGPR475) // VOP2 Label: .lbl21 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR198) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) V_CMP_GT_F32 src0(0) src1(VGPR462) # CF Block: Merge: .lbl23 S_MOV_B64 sDst(SGPR200) src0(EXEC) # CF Block: Cond Branch: true: .lbl24, false: .lbl23 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl23 Label: .lbl24 V_SUB_F32 vDst(VGPR475) src0(VGPR470) src1(VGPR475) // VOP2 Label: .lbl23 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR200) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) V_CMP_GT_F32 src0(0) src1(VGPR461) # CF Block: Merge: .lbl25 S_MOV_B64 sDst(SGPR202) src0(EXEC) # CF Block: Cond Branch: true: .lbl26, false: .lbl25 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl25 Label: .lbl26 V_SUB_F32 vDst(VGPR475) src0(0) src1(VGPR475) // VOP2 Label: .lbl25 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR202) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) # 539: OpAccessChain: Float*: no[1] # 540: OpLoad: Float: tmp540 << no[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR476) src0(VGPR1) # 541: OpExtInst(Asin): Float: tmp541 << tmp540 V_MOV_B32 vDst(VGPR477) src0(LITERAL_CONST) const: 0xbc996e30 V_MOV_B32 vDst(VGPR478) src0(LITERAL_CONST) const: 0x3d981627 V_MOV_B32 vDst(VGPR479) src0(LITERAL_CONST) const: 0xbe593484 V_MOV_B32 vDst(VGPR480) src0(LITERAL_CONST) const: 0x3fc90da4 V_MOV_B32 vDst(VGPR481) src0(LITERAL_CONST) const: 0x3fc90fdb V_ADD_F32 vDst(VGPR482) src0(VGPR476) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR483) src0(VGPR477) src1(VGPR482) src2(VGPR478) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR483) src0(VGPR482) src1(VGPR483) src2(VGPR479) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR483) src0(VGPR482) src1(VGPR483) src2(VGPR480) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUB_F32 vDst(VGPR482) src0(1_0_F) src1(VGPR482) // VOP2 V_SQRT_F32 vDst(VGPR482) src0(VGPR482) V_MAD_F32 vDst(VGPR483) src0(VGPR482) src1(VGPR483) src2(VGPR481) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_CMP_GT_F32 src0(0) src1(VGPR476) # CF Block: Merge: .lbl27 S_MOV_B64 sDst(SGPR204) src0(EXEC) # CF Block: Cond Branch: true: .lbl28, false: .lbl27 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl27 Label: .lbl28 V_MUL_F32 vDst(VGPR483) src0(M1_0_F) src1(VGPR483) // VOP2 Label: .lbl27 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR204) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) # 542: OpCompositeConstruct: FloatVector2: tmp542 << tmp538, tmp541 V_MOV_B32 vDst(VGPR484) src0(VGPR475) V_MOV_B32 vDst(VGPR485) src0(VGPR483) # 543: OpVectorTimesScalar: FloatVector2: tmp543 << tmp542, const511 V_MOV_B32 vDst(VGPR488) src0(LITERAL_CONST) const: 0x3f400000 V_MUL_F32 vDst(VGPR486) src0(VGPR488) src1(VGPR484) // VOP2 V_MUL_F32 vDst(VGPR487) src0(VGPR488) src1(VGPR485) // VOP2 # OpStore: : tmp543 >> param544 V_MOV_B32 vDst(VGPR438) src0(VGPR486) V_MOV_B32 vDst(VGPR439) src0(VGPR487) # OpStore: : tmp532 >> param545 V_MOV_B32 vDst(VGPR440) src0(VGPR460) # 547: OpFunctionCall: Float: sprinkles(vf2;f1;(param544, param545) S_ADD_U32 sDst(SGPR181) src0(LITERAL_CONST) src1(0) const: 0x1b6 # VGPR[438:439] S_ADD_U32 sDst(SGPR182) src0(LITERAL_CONST) src1(0) const: 0x1b8 # VGPR440 S_MOV_B64 sDst(SGPR206) src0(EXEC) S_MOV_B32 sDst(SGPR180) src0(LITERAL_CONST) const: 0x1e9 # VGPR489 # Indirect branch to sprinkles(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR178) src0(SGPR178) S_ADD_U32 sDst(SGPR178) src0(SGPR178) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR179) src0(SGPR179) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR178) src0(SGPR178) S_MOV_B64 sDst(EXEC) src0(SGPR206) # .lbl29 # 550: OpLoad: FloatVector3: tmp550 << vo S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR194) const: 0x0 V_MOVRELS_B32 vDst(VGPR490) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR491) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR492) src0(VGPR2) # 551: OpVectorShuffle: FloatVector2: tmp551 << tmp550, tmp550, 0, 2 V_MOV_B32 vDst(VGPR493) src0(VGPR490) V_MOV_B32 vDst(VGPR494) src0(VGPR492) # OpStore: : tmp551 >> param549 V_MOV_B32 vDst(VGPR441) src0(VGPR493) V_MOV_B32 vDst(VGPR442) src0(VGPR494) # OpStore: : tmp532 >> param552 V_MOV_B32 vDst(VGPR443) src0(VGPR460) # 554: OpFunctionCall: Float: sprinkles(vf2;f1;(param549, param552) S_ADD_U32 sDst(SGPR181) src0(LITERAL_CONST) src1(0) const: 0x1b9 # VGPR[441:442] S_ADD_U32 sDst(SGPR182) src0(LITERAL_CONST) src1(0) const: 0x1bb # VGPR443 S_MOV_B64 sDst(SGPR208) src0(EXEC) S_MOV_B32 sDst(SGPR180) src0(LITERAL_CONST) const: 0x1ef # VGPR495 # Indirect branch to sprinkles(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR178) src0(SGPR178) S_ADD_U32 sDst(SGPR178) src0(SGPR178) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR179) src0(SGPR179) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR178) src0(SGPR178) S_MOV_B64 sDst(EXEC) src0(SGPR208) # .lbl30 # 558: OpAccessChain: Float*: no[1] # 559: OpLoad: Float: tmp559 << no[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR496) src0(VGPR1) # 560: OpExtInst(SmoothStep): Float: tmp560 << const523, const303, tmp559 V_MOV_B32 vDst(VGPR497) src0(LITERAL_CONST) const: 0x3e99999a V_MOV_B32 vDst(VGPR498) src0(0_5_F) V_CMP_GE_F32 src0(VGPR497) src1(VGPR496) # CF Block: Merge: .lbl34 S_MOV_B64 sDst(SGPR210) src0(EXEC) # CF Block: Cond Branch: true: .lbl35, false: .lbl31 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl31 Label: .lbl35 V_MOV_B32 vDst(VGPR499) src0(0) Label: .lbl31 S_ANDN2_B64 sDst(EXEC) src0(SGPR210) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR196) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl34 V_CMP_LE_F32 src0(VGPR498) src1(VGPR496) # CF Block: Merge: .lbl33 S_MOV_B64 sDst(SGPR212) src0(EXEC) # CF Block: Cond Branch: true: .lbl36, false: .lbl32 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl32 Label: .lbl36 V_MOV_B32 vDst(VGPR499) src0(1_0_F) Label: .lbl32 S_ANDN2_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR196) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl33 V_SUBREV_F32 vDst(VGPR500) src0(VGPR497) src1(VGPR498) // VOP2 V_RCP_F32 vDst(VGPR500) src0(VGPR500) V_SUBREV_F32 vDst(VGPR499) src0(VGPR497) src1(VGPR496) // VOP2 V_MUL_F32 vDst(VGPR500) src0(VGPR499) src1(VGPR500) // VOP2 V_MAX_F32 vDst(VGPR500) src0(0) src1(VGPR500) // VOP2 V_MIN_F32 vDst(VGPR500) src0(1_0_F) src1(VGPR500) // VOP2 V_MOV_B32 vDst(VGPR499) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR499) src0(2_0_F) src1(VGPR500) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR500) src0(VGPR500) src1(VGPR500) // VOP2 V_MUL_F32 vDst(VGPR499) src0(VGPR500) src1(VGPR499) // VOP2 Label: .lbl33 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR212) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) Label: .lbl34 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR210) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) # 561: OpExtInst(FMix): Float: tmp561 << sprinkles(vf2;f1;, sprinkles(vf2;f1;, tmp560 V_SUBREV_F32 vDst(VGPR501) src0(VGPR499) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR501) src0(VGPR489) src1(VGPR501) // VOP2 V_MAD_F32 vDst(VGPR501) src0(VGPR495) src1(VGPR499) src2(VGPR501) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 563: OpAccessChain: Float*: no[1] # 564: OpLoad: Float: tmp564 << no[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR193) const: 0x0 V_MOVRELS_B32 vDst(VGPR502) src0(VGPR1) # 565: OpFSub: Float: tmp565 << tmp564, const523 V_MOV_B32 vDst(VGPR503) src0(LITERAL_CONST) const: 0x3e99999a V_SUB_F32 vDst(VGPR504) src0(VGPR502) src1(VGPR503) // VOP2 # 566: OpFMul: Float: tmp566 << tmp565, const401 V_MOV_B32 vDst(VGPR505) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR506) src0(VGPR504) src1(VGPR505) // VOP2 # 567: OpExtInst(FClamp): Float: tmp567 << tmp566, const100, const106 V_MOV_B32 vDst(VGPR507) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR508) src0(1_0_F) V_MAX_F32 vDst(VGPR509) src0(VGPR506) src1(VGPR507) // VOP2 V_MIN_F32 vDst(VGPR509) src0(VGPR509) src1(VGPR508) // VOP2 # 571: OpLoad: Float: tmp571 << colour # OpStore: : tmp571 >> param570 V_MOV_B32 vDst(VGPR447) src0(VGPR30) # 572: OpFunctionCall: FloatVector3: gumColour(f1;(param570) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x1bf # VGPR447 S_MOV_B64 sDst(SGPR214) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x1fe # VGPR[510:512] # Indirect branch to gumColour(f1;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR214) # .lbl37 # 574: OpCompositeConstruct: FloatVector3: tmp574 << const573, const573, const573 V_MOV_B32 vDst(VGPR516) src0(LITERAL_CONST) const: 0x3f7ae148 V_MOV_B32 vDst(VGPR513) src0(VGPR516) V_MOV_B32 vDst(VGPR517) src0(LITERAL_CONST) const: 0x3f7ae148 V_MOV_B32 vDst(VGPR514) src0(VGPR517) V_MOV_B32 vDst(VGPR518) src0(LITERAL_CONST) const: 0x3f7ae148 V_MOV_B32 vDst(VGPR515) src0(VGPR518) # 575: OpExtInst(FMix): FloatVector3: tmp575 << const569, gumColour(f1;, tmp574 V_MOV_B32 vDst(VGPR519) src0(0_5_F) V_MOV_B32 vDst(VGPR520) src0(0_5_F) V_MOV_B32 vDst(VGPR521) src0(0_5_F) V_SUBREV_F32 vDst(VGPR522) src0(VGPR513) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR522) src0(VGPR519) src1(VGPR522) // VOP2 V_MAD_F32 vDst(VGPR522) src0(VGPR510) src1(VGPR513) src2(VGPR522) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR523) src0(VGPR514) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR523) src0(VGPR520) src1(VGPR523) // VOP2 V_MAD_F32 vDst(VGPR523) src0(VGPR511) src1(VGPR514) src2(VGPR523) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR524) src0(VGPR515) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR524) src0(VGPR521) src1(VGPR524) // VOP2 V_MAD_F32 vDst(VGPR524) src0(VGPR512) src1(VGPR515) src2(VGPR524) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 577: OpAccessChain: Float*: tc[0] # 578: OpLoad: Float: tmp578 << tc[0] V_MOV_B32 vDst(VGPR525) src0(VGPR24) # 579: OpExtInst(FAbs): Float: tmp579 << tmp578 V_ADD_F32 vDst(VGPR526) src0(VGPR525) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 580: OpFSub: Float: tmp580 << const106, tmp579 V_SUB_F32 vDst(VGPR527) src0(1_0_F) src1(VGPR526) // VOP2 # 581: OpFMul: Float: tmp581 << tmp580, const303 V_MOV_B32 vDst(VGPR528) src0(0_5_F) V_MUL_F32 vDst(VGPR529) src0(VGPR527) src1(VGPR528) // VOP2 # 582: OpExtInst(Pow): Float: tmp582 << tmp581, const489 V_MOV_B32 vDst(VGPR530) src0(LITERAL_CONST) const: 0x3e4ccccd V_LOG_F32 vDst(VGPR531) src0(VGPR529) V_MUL_F32 vDst(VGPR531) src0(VGPR530) src1(VGPR531) // VOP2 V_EXP_F32 vDst(VGPR531) src0(VGPR531) # 583: OpFAdd: Float: tmp583 << const576, tmp582 V_MOV_B32 vDst(VGPR532) src0(LITERAL_CONST) const: 0x3dcccccd V_ADD_F32 vDst(VGPR533) src0(VGPR532) src1(VGPR531) // VOP2 # 584: OpVectorTimesScalar: FloatVector3: tmp584 << tmp575, tmp583 V_MUL_F32 vDst(VGPR534) src0(VGPR533) src1(VGPR522) // VOP2 V_MUL_F32 vDst(VGPR535) src0(VGPR533) src1(VGPR523) // VOP2 V_MUL_F32 vDst(VGPR536) src0(VGPR533) src1(VGPR524) // VOP2 # 588: OpFMul: Float: tmp588 << tmp561, tmp567 V_MUL_F32 vDst(VGPR537) src0(VGPR501) src1(VGPR509) // VOP2 # 589: OpCompositeConstruct: FloatVector3: tmp589 << tmp588, tmp588, tmp588 V_MOV_B32 vDst(VGPR538) src0(VGPR537) V_MOV_B32 vDst(VGPR539) src0(VGPR537) V_MOV_B32 vDst(VGPR540) src0(VGPR537) # 590: OpExtInst(FMix): FloatVector3: tmp590 << tmp584, const585, tmp589 V_MOV_B32 vDst(VGPR541) src0(2_0_F) V_MOV_B32 vDst(VGPR542) src0(2_0_F) V_MOV_B32 vDst(VGPR543) src0(2_0_F) V_SUBREV_F32 vDst(VGPR544) src0(VGPR538) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR544) src0(VGPR534) src1(VGPR544) // VOP2 V_MAD_F32 vDst(VGPR544) src0(VGPR541) src1(VGPR538) src2(VGPR544) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR545) src0(VGPR539) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR545) src0(VGPR535) src1(VGPR545) // VOP2 V_MAD_F32 vDst(VGPR545) src0(VGPR542) src1(VGPR539) src2(VGPR545) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR546) src0(VGPR540) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR546) src0(VGPR536) src1(VGPR546) // VOP2 V_MAD_F32 vDst(VGPR546) src0(VGPR543) src1(VGPR540) src2(VGPR546) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp590 >> param591 V_MOV_B32 vDst(VGPR448) src0(VGPR544) V_MOV_B32 vDst(VGPR449) src0(VGPR545) V_MOV_B32 vDst(VGPR450) src0(VGPR546) # 592: OpFunctionCall: FloatVector3: saturatecol(vf3;(param591) S_ADD_U32 sDst(SGPR155) src0(LITERAL_CONST) src1(0) const: 0x1c0 # VGPR[448:450] S_MOV_B64 sDst(SGPR216) src0(EXEC) S_MOV_B32 sDst(SGPR154) src0(LITERAL_CONST) const: 0x223 # VGPR[547:549] # Indirect branch to saturatecol(vf3;: ??? S_GETPC_B64 sDst(SGPR152) src0(SGPR152) S_ADD_U32 sDst(SGPR152) src0(SGPR152) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR153) src0(SGPR153) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR152) src0(SGPR152) S_MOV_B64 sDst(EXEC) src0(SGPR216) # .lbl38 # OpStore: : saturatecol(vf3; >> tex V_MOV_B32 vDst(VGPR444) src0(VGPR547) V_MOV_B32 vDst(VGPR445) src0(VGPR548) V_MOV_B32 vDst(VGPR446) src0(VGPR549) # 595: OpFSub: Float: tmp595 << const593, tmp532 V_MOV_B32 vDst(VGPR550) src0(LITERAL_CONST) const: 0x3f866666 V_SUB_F32 vDst(VGPR551) src0(VGPR550) src1(VGPR460) // VOP2 # 596: OpLoad: FloatVector3: tmp596 << tex # 597: OpVectorTimesScalar: FloatVector3: tmp597 << tmp596, tmp595 V_MUL_F32 vDst(VGPR552) src0(VGPR551) src1(VGPR444) // VOP2 V_MUL_F32 vDst(VGPR553) src0(VGPR551) src1(VGPR445) // VOP2 V_MUL_F32 vDst(VGPR554) src0(VGPR551) src1(VGPR446) // VOP2 # OpStore: : tmp597 >> tex V_MOV_B32 vDst(VGPR444) src0(VGPR552) V_MOV_B32 vDst(VGPR445) src0(VGPR553) V_MOV_B32 vDst(VGPR446) src0(VGPR554) # 599: OpFSub: Float: tmp599 << const106, tmp532 V_SUB_F32 vDst(VGPR555) src0(1_0_F) src1(VGPR460) // VOP2 # 600: OpExtInst(Pow): Float: tmp600 << tmp599, const349 V_MOV_B32 vDst(VGPR556) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR557) src0(VGPR555) V_MUL_F32 vDst(VGPR557) src0(VGPR556) src1(VGPR557) // VOP2 V_EXP_F32 vDst(VGPR557) src0(VGPR557) # 601: OpCompositeConstruct: FloatVector3: tmp601 << tmp600, tmp600, tmp600 V_MOV_B32 vDst(VGPR558) src0(VGPR557) V_MOV_B32 vDst(VGPR559) src0(VGPR557) V_MOV_B32 vDst(VGPR560) src0(VGPR557) # 603: OpVectorTimesScalar: FloatVector3: tmp603 << tmp601, const602 V_MOV_B32 vDst(VGPR564) src0(LITERAL_CONST) const: 0x3c23d70a V_MUL_F32 vDst(VGPR561) src0(VGPR564) src1(VGPR558) // VOP2 V_MUL_F32 vDst(VGPR562) src0(VGPR564) src1(VGPR559) // VOP2 V_MUL_F32 vDst(VGPR563) src0(VGPR564) src1(VGPR560) // VOP2 # 604: OpLoad: FloatVector3: tmp604 << tex # 605: OpFAdd: FloatVector3: tmp605 << tmp604, tmp603 V_ADD_F32 vDst(VGPR565) src0(VGPR444) src1(VGPR561) // VOP2 V_ADD_F32 vDst(VGPR566) src0(VGPR445) src1(VGPR562) // VOP2 V_ADD_F32 vDst(VGPR567) src0(VGPR446) src1(VGPR563) // VOP2 # OpStore: : tmp605 >> tex V_MOV_B32 vDst(VGPR444) src0(VGPR565) V_MOV_B32 vDst(VGPR445) src0(VGPR566) V_MOV_B32 vDst(VGPR446) src0(VGPR567) # 606: OpLoad: FloatVector3: tmp606 << tex # OpReturnValue: : << tmp606 S_MOV_B32 sDst(M0) src0(SGPR192) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR444) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR445) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR446) S_SETPC_B64 sDst(SGPR190) src0(SGPR190) # Float de(vf3;(FloatVector3* p) Function: Float de(vf3;() S_MOV_B64 sDst(SGPR222) src0(EXEC) # lb70 Label: lb70 # 610: OpAccessChain: Float*: p[1] # 611: OpLoad: Float: tmp611 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR574) src0(VGPR1) # 612: OpFMul: Float: tmp612 << tmp611, const609 V_MOV_B32 vDst(VGPR575) src0(LITERAL_CONST) const: 0x3fa66666 V_MUL_F32 vDst(VGPR576) src0(VGPR574) src1(VGPR575) // VOP2 # 613: OpAccessChain: Float*: p[1] # OpStore: : tmp612 >> p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELD_B32 vDst(VGPR1) src0(VGPR576) # 615: OpLoad: FloatVector3: tmp615 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR577) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR578) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR579) src0(VGPR2) # 616: OpCompositeConstruct: FloatVector3: tmp616 << const109, const109, const109 V_MOV_B32 vDst(VGPR583) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR580) src0(VGPR583) V_MOV_B32 vDst(VGPR584) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR581) src0(VGPR584) V_MOV_B32 vDst(VGPR585) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR582) src0(VGPR585) # 617: OpFDiv: FloatVector3: tmp617 << tmp615, tmp616 V_RCP_F32 vDst(VGPR586) src0(VGPR580) V_RCP_F32 vDst(VGPR587) src0(VGPR581) V_RCP_F32 vDst(VGPR588) src0(VGPR582) V_MUL_F32 vDst(VGPR586) src0(VGPR577) src1(VGPR586) // VOP2 V_MUL_F32 vDst(VGPR587) src0(VGPR578) src1(VGPR587) // VOP2 V_MUL_F32 vDst(VGPR588) src0(VGPR579) src1(VGPR588) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR586) src0(VGPR586) src1(VGPR580) src2(VGPR577) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR587) src0(VGPR587) src1(VGPR581) src2(VGPR578) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR588) src0(VGPR588) src1(VGPR582) src2(VGPR579) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 618: OpExtInst(Floor): FloatVector3: tmp618 << tmp617 V_FLOOR_F32 vDst(VGPR589) src0(VGPR586) V_FLOOR_F32 vDst(VGPR590) src0(VGPR587) V_FLOOR_F32 vDst(VGPR591) src0(VGPR588) # 619: OpAccessChain: Float*: fp[0] # 620: OpCompositeExtract: Float: tmp620 << tmp618, 0 V_MOV_B32 vDst(VGPR592) src0(VGPR589) # 622: OpFMul: Float: tmp622 << tmp620, const621 V_MOV_B32 vDst(VGPR593) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR594) src0(VGPR592) src1(VGPR593) // VOP2 # 623: OpAccessChain: Float*: fp[2] # 624: OpCompositeExtract: Float: tmp624 << tmp618, 2 V_MOV_B32 vDst(VGPR595) src0(VGPR591) # 626: OpFMul: Float: tmp626 << tmp624, const625 V_MOV_B32 vDst(VGPR596) src0(LITERAL_CONST) const: 0x42ce0000 V_MUL_F32 vDst(VGPR597) src0(VGPR595) src1(VGPR596) // VOP2 # 627: OpFSub: Float: tmp627 << tmp622, tmp626 V_SUB_F32 vDst(VGPR598) src0(VGPR594) src1(VGPR597) // VOP2 # 628: OpExtInst(Cos): Float: tmp628 << tmp627 V_MUL_F32 vDst(VGPR599) src0(LITERAL_CONST) src1(VGPR598) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR599) src0(VGPR599) V_COS_F32 vDst(VGPR599) src0(VGPR599) # 629: OpFAdd: Float: tmp629 << tmp628, const576 V_MOV_B32 vDst(VGPR600) src0(LITERAL_CONST) const: 0x3dcccccd V_ADD_F32 vDst(VGPR601) src0(VGPR599) src1(VGPR600) // VOP2 # 630: OpExtInst(Step): Float: tmp630 << const100, tmp629 V_MOV_B32 vDst(VGPR602) src0(LITERAL_CONST) const: 0x00000000 V_CMP_GT_F32 src0(VGPR602) src1(VGPR601) # CF Block: Merge: .lbl40 S_MOV_B64 sDst(SGPR224) src0(EXEC) # CF Block: Cond Branch: true: .lbl41, false: .lbl39 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl39 Label: .lbl41 V_MOV_B32 vDst(VGPR603) src0(0) Label: .lbl39 S_ANDN2_B64 sDst(EXEC) src0(SGPR224) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR222) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl40 V_MOV_B32 vDst(VGPR603) src0(1_0_F) Label: .lbl40 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR224) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR222) # OpStore: : tmp630 >> is_choc V_MOV_B32 vDst(VGPR33) src0(VGPR603) # 632: OpLoad: FloatVector3: tmp632 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR604) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR605) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR606) src0(VGPR2) # 634: OpVectorTimesScalar: FloatVector3: tmp634 << tmp632, const633 V_MOV_B32 vDst(VGPR610) src0(LITERAL_CONST) const: 0x41f00000 V_MUL_F32 vDst(VGPR607) src0(VGPR610) src1(VGPR604) // VOP2 V_MUL_F32 vDst(VGPR608) src0(VGPR610) src1(VGPR605) // VOP2 V_MUL_F32 vDst(VGPR609) src0(VGPR610) src1(VGPR606) // VOP2 # OpStore: : tmp634 >> param635 V_MOV_B32 vDst(VGPR568) src0(VGPR607) V_MOV_B32 vDst(VGPR569) src0(VGPR608) V_MOV_B32 vDst(VGPR570) src0(VGPR609) # 636: OpFunctionCall: Float: smN3(vf3;(param635) S_ADD_U32 sDst(SGPR99) src0(LITERAL_CONST) src1(0) const: 0x238 # VGPR[568:570] S_MOV_B64 sDst(SGPR226) src0(EXEC) S_MOV_B32 sDst(SGPR98) src0(LITERAL_CONST) const: 0x263 # VGPR611 # Indirect branch to smN3(vf3;: ??? S_GETPC_B64 sDst(SGPR96) src0(SGPR96) S_ADD_U32 sDst(SGPR96) src0(SGPR96) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR97) src0(SGPR97) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR96) src0(SGPR96) S_MOV_B64 sDst(EXEC) src0(SGPR226) # .lbl42 # 638: OpFMul: Float: tmp638 << smN3(vf3;, const637 V_MOV_B32 vDst(VGPR612) src0(LITERAL_CONST) const: 0x3a83126f V_MUL_F32 vDst(VGPR613) src0(VGPR611) src1(VGPR612) // VOP2 # 639: OpLoad: Float: tmp639 << is_choc # 640: OpFMul: Float: tmp640 << tmp638, tmp639 V_MUL_F32 vDst(VGPR614) src0(VGPR613) src1(VGPR33) // VOP2 # 641: OpLoad: FloatVector3: tmp641 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR615) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR616) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR617) src0(VGPR2) # 642: OpVectorTimesScalar: FloatVector3: tmp642 << tmp641, const401 V_MOV_B32 vDst(VGPR621) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR618) src0(VGPR621) src1(VGPR615) // VOP2 V_MUL_F32 vDst(VGPR619) src0(VGPR621) src1(VGPR616) // VOP2 V_MUL_F32 vDst(VGPR620) src0(VGPR621) src1(VGPR617) // VOP2 # OpStore: : tmp642 >> param643 V_MOV_B32 vDst(VGPR571) src0(VGPR618) V_MOV_B32 vDst(VGPR572) src0(VGPR619) V_MOV_B32 vDst(VGPR573) src0(VGPR620) # 644: OpFunctionCall: Float: smN3(vf3;(param643) S_ADD_U32 sDst(SGPR99) src0(LITERAL_CONST) src1(0) const: 0x23b # VGPR[571:573] S_MOV_B64 sDst(SGPR228) src0(EXEC) S_MOV_B32 sDst(SGPR98) src0(LITERAL_CONST) const: 0x26e # VGPR622 # Indirect branch to smN3(vf3;: ??? S_GETPC_B64 sDst(SGPR96) src0(SGPR96) S_ADD_U32 sDst(SGPR96) src0(SGPR96) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR97) src0(SGPR97) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR96) src0(SGPR96) S_MOV_B64 sDst(EXEC) src0(SGPR228) # .lbl43 # 645: OpExtInst(FMax): Float: tmp645 << const100, smN3(vf3; V_MOV_B32 vDst(VGPR623) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR624) src0(VGPR623) src1(VGPR622) // VOP2 # 646: OpExtInst(Pow): Float: tmp646 << tmp645, const401 V_MOV_B32 vDst(VGPR625) src0(LITERAL_CONST) const: 0x40a00000 V_LOG_F32 vDst(VGPR626) src0(VGPR624) V_MUL_F32 vDst(VGPR626) src0(VGPR625) src1(VGPR626) // VOP2 V_EXP_F32 vDst(VGPR626) src0(VGPR626) # 648: OpLoad: Float: tmp648 << is_choc # 649: OpFSub: Float: tmp649 << const106, tmp648 V_SUB_F32 vDst(VGPR627) src0(1_0_F) src1(VGPR33) // VOP2 # 650: OpFMul: Float: tmp650 << const647, tmp649 V_MOV_B32 vDst(VGPR628) src0(LITERAL_CONST) const: 0x3d4ccccd V_MUL_F32 vDst(VGPR629) src0(VGPR628) src1(VGPR627) // VOP2 # 651: OpFAdd: Float: tmp651 << const602, tmp650 V_MOV_B32 vDst(VGPR630) src0(LITERAL_CONST) const: 0x3c23d70a V_ADD_F32 vDst(VGPR631) src0(VGPR630) src1(VGPR629) // VOP2 # 652: OpFMul: Float: tmp652 << tmp646, tmp651 V_MUL_F32 vDst(VGPR632) src0(VGPR626) src1(VGPR631) // VOP2 # 653: OpFSub: Float: tmp653 << tmp640, tmp652 V_SUB_F32 vDst(VGPR633) src0(VGPR614) src1(VGPR632) // VOP2 # 654: OpAccessChain: Float*: fp[0] # 655: OpCompositeExtract: Float: tmp655 << tmp618, 0 V_MOV_B32 vDst(VGPR634) src0(VGPR589) # 656: OpAccessChain: Float*: fp[2] # 657: OpCompositeExtract: Float: tmp657 << tmp618, 2 V_MOV_B32 vDst(VGPR635) src0(VGPR591) # 658: OpExtInst(Sin): Float: tmp658 << tmp657 V_MUL_F32 vDst(VGPR636) src0(LITERAL_CONST) src1(VGPR635) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR636) src0(VGPR636) V_SIN_F32 vDst(VGPR636) src0(VGPR636) # 659: OpFMul: Float: tmp659 << tmp658, const109 V_MOV_B32 vDst(VGPR637) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR638) src0(VGPR636) src1(VGPR637) // VOP2 # 660: OpFAdd: Float: tmp660 << tmp655, tmp659 V_ADD_F32 vDst(VGPR639) src0(VGPR634) src1(VGPR638) // VOP2 # 661: OpFMod: Float: tmp661 << tmp660, const377 V_MOV_B32 vDst(VGPR640) src0(4_0_F) V_RCP_F32 vDst(VGPR641) src0(VGPR640) V_MUL_F32 vDst(VGPR641) src0(VGPR639) src1(VGPR641) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR641) src0(VGPR641) src1(VGPR640) src2(VGPR639) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR641) src0(VGPR641) V_MAD_F32 vDst(VGPR641) src0(VGPR640) src1(VGPR641) src2(VGPR639) abs(0) clamp(0) omod(0) neg(1) // VOP3a # OpStore: : tmp661 >> colour V_MOV_B32 vDst(VGPR30) src0(VGPR641) # 662: OpLoad: FloatVector3: tmp662 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR642) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR643) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR644) src0(VGPR2) # 663: OpVectorShuffle: FloatVector2: tmp663 << tmp662, tmp662, 0, 2 V_MOV_B32 vDst(VGPR645) src0(VGPR642) V_MOV_B32 vDst(VGPR646) src0(VGPR644) # 665: OpFMod: FloatVector2: tmp665 << tmp663, const664 V_MOV_B32 vDst(VGPR647) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR648) src0(LITERAL_CONST) const: 0x40400000 V_RCP_F32 vDst(VGPR649) src0(VGPR647) V_MUL_F32 vDst(VGPR649) src0(VGPR645) src1(VGPR649) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR649) src0(VGPR649) src1(VGPR647) src2(VGPR645) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR649) src0(VGPR649) V_RCP_F32 vDst(VGPR650) src0(VGPR648) V_MUL_F32 vDst(VGPR650) src0(VGPR646) src1(VGPR650) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR650) src0(VGPR650) src1(VGPR648) src2(VGPR646) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR650) src0(VGPR650) V_MAD_F32 vDst(VGPR649) src0(VGPR647) src1(VGPR649) src2(VGPR645) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR650) src0(VGPR648) src1(VGPR650) src2(VGPR646) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 668: OpFSub: FloatVector2: tmp668 << tmp665, const667 V_MOV_B32 vDst(VGPR651) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR652) src0(LITERAL_CONST) const: 0x3fc00000 V_SUB_F32 vDst(VGPR653) src0(VGPR649) src1(VGPR651) // VOP2 V_SUB_F32 vDst(VGPR654) src0(VGPR650) src1(VGPR652) // VOP2 # 669: OpLoad: FloatVector3: tmp669 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR655) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR656) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR657) src0(VGPR2) # 670: OpVectorShuffle: FloatVector3: tmp670 << tmp669, tmp668, 3, 1, 4 V_MOV_B32 vDst(VGPR658) src0(VGPR653) V_MOV_B32 vDst(VGPR659) src0(VGPR656) V_MOV_B32 vDst(VGPR660) src0(VGPR654) # OpStore: : tmp670 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR658) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR659) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR660) # 672: OpAccessChain: Float*: fp[2] # 673: OpCompositeExtract: Float: tmp673 << tmp618, 2 V_MOV_B32 vDst(VGPR661) src0(VGPR591) # 675: OpFMul: Float: tmp675 << tmp673, const674 V_MOV_B32 vDst(VGPR662) src0(LITERAL_CONST) const: 0x40e00000 V_MUL_F32 vDst(VGPR663) src0(VGPR661) src1(VGPR662) // VOP2 # 676: OpAccessChain: Float*: fp[0] # 677: OpCompositeExtract: Float: tmp677 << tmp618, 0 V_MOV_B32 vDst(VGPR664) src0(VGPR589) # 679: OpFMul: Float: tmp679 << tmp677, const678 V_MOV_B32 vDst(VGPR665) src0(LITERAL_CONST) const: 0x41100000 V_MUL_F32 vDst(VGPR666) src0(VGPR664) src1(VGPR665) // VOP2 # 680: OpFAdd: Float: tmp680 << tmp675, tmp679 V_ADD_F32 vDst(VGPR667) src0(VGPR663) src1(VGPR666) // VOP2 # 681: OpExtInst(Cos): Float: tmp681 << tmp680 V_MUL_F32 vDst(VGPR668) src0(LITERAL_CONST) src1(VGPR667) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR668) src0(VGPR668) V_COS_F32 vDst(VGPR668) src0(VGPR668) # 682: OpFMul: Float: tmp682 << const303, tmp681 V_MUL_F32 vDst(VGPR669) src0(0_5_F) src1(VGPR668) // VOP2 # 683: OpFAdd: Float: tmp683 << const303, tmp682 V_ADD_F32 vDst(VGPR670) src0(0_5_F) src1(VGPR669) // VOP2 # 684: OpExtInst(FMix): Float: tmp684 << const671, const106, tmp683 V_MOV_B32 vDst(VGPR671) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR672) src0(1_0_F) V_SUBREV_F32 vDst(VGPR673) src0(VGPR670) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR673) src0(VGPR671) src1(VGPR673) // VOP2 V_MAD_F32 vDst(VGPR673) src0(VGPR672) src1(VGPR670) src2(VGPR673) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp684 >> ss V_MOV_B32 vDst(VGPR32) src0(VGPR673) # 686: OpLoad: FloatVector3: tmp686 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR674) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR675) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR676) src0(VGPR2) # 687: OpExtInst(Length): Float: tmp687 << tmp686 V_MUL_F32 vDst(VGPR677) src0(VGPR674) src1(VGPR674) // VOP2 V_MAC_F32 vDst(VGPR677) src0(VGPR675) src1(VGPR675) // VOP2 V_MAC_F32 vDst(VGPR677) src0(VGPR676) src1(VGPR676) // VOP2 V_SQRT_F32 vDst(VGPR677) src0(VGPR677) # 688: OpLoad: Float: tmp688 << ss # 689: OpFSub: Float: tmp689 << tmp687, tmp688 V_SUB_F32 vDst(VGPR678) src0(VGPR677) src1(VGPR32) // VOP2 # 691: OpAccessChain: Float*: p[1] # 692: OpLoad: Float: tmp692 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR221) const: 0x0 V_MOVRELS_B32 vDst(VGPR679) src0(VGPR1) # 693: OpFNegate: Float: tmp693 << tmp692 V_MUL_F32 vDst(VGPR680) src0(M1_0_F) src1(VGPR679) // VOP2 # 696: OpExtInst(FMax): Float: tmp696 << const100, tmp689 V_MOV_B32 vDst(VGPR681) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR682) src0(VGPR681) src1(VGPR678) // VOP2 # 698: OpExtInst(FMax): Float: tmp698 << const100, tmp693 V_MOV_B32 vDst(VGPR683) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR684) src0(VGPR683) src1(VGPR680) // VOP2 # 699: OpCompositeConstruct: FloatVector2: tmp699 << tmp696, tmp698 V_MOV_B32 vDst(VGPR685) src0(VGPR682) V_MOV_B32 vDst(VGPR686) src0(VGPR684) # 700: OpExtInst(Length): Float: tmp700 << tmp699 V_MUL_F32 vDst(VGPR687) src0(VGPR685) src1(VGPR685) // VOP2 V_MAC_F32 vDst(VGPR687) src0(VGPR686) src1(VGPR686) // VOP2 V_SQRT_F32 vDst(VGPR687) src0(VGPR687) # 701: OpFSub: Float: tmp701 << tmp700, const576 V_MOV_B32 vDst(VGPR688) src0(LITERAL_CONST) const: 0x3dcccccd V_SUB_F32 vDst(VGPR689) src0(VGPR687) src1(VGPR688) // VOP2 # 703: OpFAdd: Float: tmp703 << tmp701, tmp653 V_ADD_F32 vDst(VGPR690) src0(VGPR689) src1(VGPR633) // VOP2 # 705: OpFMul: Float: tmp705 << tmp703, const704 V_MOV_B32 vDst(VGPR691) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR692) src0(VGPR690) src1(VGPR691) // VOP2 # OpReturnValue: : << tmp705 S_MOV_B32 sDst(M0) src0(SGPR220) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR692) S_SETPC_B64 sDst(SGPR218) src0(SGPR218) # FloatVector3 marble(vf2;(FloatVector2* p) Function: FloatVector3 marble(vf2;() S_MOV_B64 sDst(SGPR234) src0(EXEC) # lb74 Label: lb74 # 709: OpAccessChain: Float*: p[0] # 710: OpLoad: Float: tmp710 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR705) src0(VGPR0) # 711: OpFAdd: Float: tmp711 << tmp710, const127 V_MOV_B32 vDst(VGPR706) src0(2_0_F) V_ADD_F32 vDst(VGPR707) src0(VGPR705) src1(VGPR706) // VOP2 # 712: OpAccessChain: Float*: p[0] # OpStore: : tmp711 >> p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR707) # 717: OpLoad: FloatVector2: tmp717 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR708) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR709) src0(VGPR1) # 718: OpExtInst(Floor): FloatVector2: tmp718 << tmp717 V_FLOOR_F32 vDst(VGPR710) src0(VGPR708) V_FLOOR_F32 vDst(VGPR711) src0(VGPR709) # 720: OpLoad: FloatVector2: tmp720 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR712) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR713) src0(VGPR1) # 722: OpFSub: FloatVector2: tmp722 << tmp720, tmp718 V_SUB_F32 vDst(VGPR714) src0(VGPR712) src1(VGPR710) // VOP2 V_SUB_F32 vDst(VGPR715) src0(VGPR713) src1(VGPR711) // VOP2 # 723: OpFSub: FloatVector2: tmp723 << tmp722, const391 V_MOV_B32 vDst(VGPR716) src0(0_5_F) V_MOV_B32 vDst(VGPR717) src0(0_5_F) V_SUB_F32 vDst(VGPR718) src0(VGPR714) src1(VGPR716) // VOP2 V_SUB_F32 vDst(VGPR719) src0(VGPR715) src1(VGPR717) // VOP2 # 725: OpAccessChain: Float*: c1[0] # 726: OpCompositeExtract: Float: tmp726 << tmp723, 0 V_MOV_B32 vDst(VGPR720) src0(VGPR718) # 727: OpVectorTimesScalar: FloatVector2: tmp727 << const342, tmp726 V_MOV_B32 vDst(VGPR723) src0(1_0_F) V_MOV_B32 vDst(VGPR724) src0(1_0_F) V_MUL_F32 vDst(VGPR721) src0(VGPR720) src1(VGPR723) // VOP2 V_MUL_F32 vDst(VGPR722) src0(VGPR720) src1(VGPR724) // VOP2 # 728: OpAccessChain: Float*: c1[1] # 729: OpCompositeExtract: Float: tmp729 << tmp723, 1 V_MOV_B32 vDst(VGPR725) src0(VGPR719) # 731: OpVectorTimesScalar: FloatVector2: tmp731 << const730, tmp729 V_MOV_B32 vDst(VGPR728) src0(1_0_F) V_MOV_B32 vDst(VGPR729) src0(M1_0_F) V_MUL_F32 vDst(VGPR726) src0(VGPR725) src1(VGPR728) // VOP2 V_MUL_F32 vDst(VGPR727) src0(VGPR725) src1(VGPR729) // VOP2 # 732: OpFAdd: FloatVector2: tmp732 << tmp727, tmp731 V_ADD_F32 vDst(VGPR730) src0(VGPR721) src1(VGPR726) // VOP2 V_ADD_F32 vDst(VGPR731) src0(VGPR722) src1(VGPR727) // VOP2 # 733: OpVectorTimesScalar: FloatVector2: tmp733 << tmp732, const704 V_MOV_B32 vDst(VGPR734) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR732) src0(VGPR734) src1(VGPR730) // VOP2 V_MUL_F32 vDst(VGPR733) src0(VGPR734) src1(VGPR731) // VOP2 # 736: OpLoad: FloatVector2: tmp736 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR735) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR736) src0(VGPR1) # 737: OpCompositeExtract: Float: tmp737 << tmp736, 0 V_MOV_B32 vDst(VGPR737) src0(VGPR735) # 738: OpCompositeExtract: Float: tmp738 << tmp736, 1 V_MOV_B32 vDst(VGPR738) src0(VGPR736) # 739: OpCompositeConstruct: FloatVector3: tmp739 << tmp737, tmp738, const100 V_MOV_B32 vDst(VGPR739) src0(VGPR737) V_MOV_B32 vDst(VGPR740) src0(VGPR738) V_MOV_B32 vDst(VGPR742) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR741) src0(VGPR742) # OpStore: : tmp739 >> param740 V_MOV_B32 vDst(VGPR693) src0(VGPR739) V_MOV_B32 vDst(VGPR694) src0(VGPR740) V_MOV_B32 vDst(VGPR695) src0(VGPR741) # 741: OpFunctionCall: Float: fbm3(vf3;(param740) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x2b5 # VGPR[693:695] S_MOV_B64 sDst(SGPR236) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x2e7 # VGPR743 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR236) # .lbl44 # 742: OpFMul: Float: tmp742 << fbm3(vf3;, const303 V_MOV_B32 vDst(VGPR744) src0(0_5_F) V_MUL_F32 vDst(VGPR745) src0(VGPR743) src1(VGPR744) // VOP2 # 743: OpExtInst(FMax): Float: tmp743 << const100, tmp742 V_MOV_B32 vDst(VGPR746) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR747) src0(VGPR746) src1(VGPR745) // VOP2 # 744: OpCompositeConstruct: FloatVector3: tmp744 << tmp743, tmp743, tmp743 V_MOV_B32 vDst(VGPR748) src0(VGPR747) V_MOV_B32 vDst(VGPR749) src0(VGPR747) V_MOV_B32 vDst(VGPR750) src0(VGPR747) # 745: OpCompositeConstruct: FloatVector3: tmp745 << const511, const511, const511 V_MOV_B32 vDst(VGPR754) src0(LITERAL_CONST) const: 0x3f400000 V_MOV_B32 vDst(VGPR751) src0(VGPR754) V_MOV_B32 vDst(VGPR755) src0(LITERAL_CONST) const: 0x3f400000 V_MOV_B32 vDst(VGPR752) src0(VGPR755) V_MOV_B32 vDst(VGPR756) src0(LITERAL_CONST) const: 0x3f400000 V_MOV_B32 vDst(VGPR753) src0(VGPR756) # 746: OpExtInst(FMix): FloatVector3: tmp746 << const735, tmp744, tmp745 V_MOV_B32 vDst(VGPR757) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR758) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR759) src0(LITERAL_CONST) const: 0x3d4ccccd V_SUBREV_F32 vDst(VGPR760) src0(VGPR751) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR760) src0(VGPR757) src1(VGPR760) // VOP2 V_MAD_F32 vDst(VGPR760) src0(VGPR748) src1(VGPR751) src2(VGPR760) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR761) src0(VGPR752) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR761) src0(VGPR758) src1(VGPR761) // VOP2 V_MAD_F32 vDst(VGPR761) src0(VGPR749) src1(VGPR752) src2(VGPR761) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR762) src0(VGPR753) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR762) src0(VGPR759) src1(VGPR762) // VOP2 V_MAD_F32 vDst(VGPR762) src0(VGPR750) src1(VGPR753) src2(VGPR762) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 754: OpVectorTimesScalar: FloatVector2: tmp754 << tmp718, const127 V_MOV_B32 vDst(VGPR765) src0(2_0_F) V_MUL_F32 vDst(VGPR763) src0(VGPR765) src1(VGPR710) // VOP2 V_MUL_F32 vDst(VGPR764) src0(VGPR765) src1(VGPR711) // VOP2 # 755: OpLoad: FloatVector2: tmp755 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR766) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR767) src0(VGPR1) # 756: OpVectorTimesScalar: FloatVector2: tmp756 << tmp755, const106 V_MOV_B32 vDst(VGPR770) src0(1_0_F) V_MUL_F32 vDst(VGPR768) src0(VGPR770) src1(VGPR766) // VOP2 V_MUL_F32 vDst(VGPR769) src0(VGPR770) src1(VGPR767) // VOP2 # 757: OpFAdd: FloatVector2: tmp757 << tmp754, tmp756 V_ADD_F32 vDst(VGPR771) src0(VGPR763) src1(VGPR768) // VOP2 V_ADD_F32 vDst(VGPR772) src0(VGPR764) src1(VGPR769) // VOP2 # 758: OpLoad: FloatVector2: tmp758 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR773) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR774) src0(VGPR1) # 759: OpVectorShuffle: FloatVector2: tmp759 << tmp758, tmp758, 1, 0 V_MOV_B32 vDst(VGPR775) src0(VGPR774) V_MOV_B32 vDst(VGPR776) src0(VGPR773) # 760: OpVectorTimesScalar: FloatVector2: tmp760 << tmp759, const127 V_MOV_B32 vDst(VGPR779) src0(2_0_F) V_MUL_F32 vDst(VGPR777) src0(VGPR779) src1(VGPR775) // VOP2 V_MUL_F32 vDst(VGPR778) src0(VGPR779) src1(VGPR776) // VOP2 # 761: OpExtInst(Cos): FloatVector2: tmp761 << tmp760 V_MUL_F32 vDst(VGPR780) src0(LITERAL_CONST) src1(VGPR777) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR780) src0(VGPR780) V_MUL_F32 vDst(VGPR781) src0(LITERAL_CONST) src1(VGPR778) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR781) src0(VGPR781) V_COS_F32 vDst(VGPR780) src0(VGPR780) V_COS_F32 vDst(VGPR781) src0(VGPR781) # 762: OpVectorTimesScalar: FloatVector2: tmp762 << tmp761, const748 V_MOV_B32 vDst(VGPR784) src0(LITERAL_CONST) const: 0x3ecccccd V_MUL_F32 vDst(VGPR782) src0(VGPR784) src1(VGPR780) // VOP2 V_MUL_F32 vDst(VGPR783) src0(VGPR784) src1(VGPR781) // VOP2 # 763: OpFAdd: FloatVector2: tmp763 << tmp757, tmp762 V_ADD_F32 vDst(VGPR785) src0(VGPR771) src1(VGPR782) // VOP2 V_ADD_F32 vDst(VGPR786) src0(VGPR772) src1(VGPR783) // VOP2 # 764: OpCompositeExtract: Float: tmp764 << tmp763, 0 V_MOV_B32 vDst(VGPR787) src0(VGPR785) # 765: OpCompositeExtract: Float: tmp765 << tmp763, 1 V_MOV_B32 vDst(VGPR788) src0(VGPR786) # 766: OpCompositeConstruct: FloatVector3: tmp766 << tmp764, tmp765, const100 V_MOV_B32 vDst(VGPR789) src0(VGPR787) V_MOV_B32 vDst(VGPR790) src0(VGPR788) V_MOV_B32 vDst(VGPR792) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR791) src0(VGPR792) # OpStore: : tmp766 >> param767 V_MOV_B32 vDst(VGPR696) src0(VGPR789) V_MOV_B32 vDst(VGPR697) src0(VGPR790) V_MOV_B32 vDst(VGPR698) src0(VGPR791) # 768: OpFunctionCall: Float: fbm3(vf3;(param767) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x2b8 # VGPR[696:698] S_MOV_B64 sDst(SGPR238) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x319 # VGPR793 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR238) # .lbl45 # 769: OpFAdd: Float: tmp769 << const303, fbm3(vf3; V_ADD_F32 vDst(VGPR794) src0(0_5_F) src1(VGPR793) // VOP2 # 770: OpExtInst(SmoothStep): Float: tmp770 << const748, const151, tmp769 V_MOV_B32 vDst(VGPR795) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR796) src0(LITERAL_CONST) const: 0x3f4ccccd V_CMP_GE_F32 src0(VGPR795) src1(VGPR794) # CF Block: Merge: .lbl49 S_MOV_B64 sDst(SGPR240) src0(EXEC) # CF Block: Cond Branch: true: .lbl50, false: .lbl46 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl46 Label: .lbl50 V_MOV_B32 vDst(VGPR797) src0(0) Label: .lbl46 S_ANDN2_B64 sDst(EXEC) src0(SGPR240) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl49 V_CMP_LE_F32 src0(VGPR796) src1(VGPR794) # CF Block: Merge: .lbl48 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl51, false: .lbl47 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl47 Label: .lbl51 V_MOV_B32 vDst(VGPR797) src0(1_0_F) Label: .lbl47 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl48 V_SUBREV_F32 vDst(VGPR798) src0(VGPR795) src1(VGPR796) // VOP2 V_RCP_F32 vDst(VGPR798) src0(VGPR798) V_SUBREV_F32 vDst(VGPR797) src0(VGPR795) src1(VGPR794) // VOP2 V_MUL_F32 vDst(VGPR798) src0(VGPR797) src1(VGPR798) // VOP2 V_MAX_F32 vDst(VGPR798) src0(0) src1(VGPR798) // VOP2 V_MIN_F32 vDst(VGPR798) src0(1_0_F) src1(VGPR798) // VOP2 V_MOV_B32 vDst(VGPR797) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR797) src0(2_0_F) src1(VGPR798) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR798) src0(VGPR798) src1(VGPR798) // VOP2 V_MUL_F32 vDst(VGPR797) src0(VGPR798) src1(VGPR797) // VOP2 Label: .lbl48 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) Label: .lbl49 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR240) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) # 771: OpFSub: Float: tmp771 << const106, tmp770 V_SUB_F32 vDst(VGPR799) src0(1_0_F) src1(VGPR797) // VOP2 # 772: OpCompositeConstruct: FloatVector3: tmp772 << tmp771, tmp771, tmp771 V_MOV_B32 vDst(VGPR800) src0(VGPR799) V_MOV_B32 vDst(VGPR801) src0(VGPR799) V_MOV_B32 vDst(VGPR802) src0(VGPR799) # 773: OpExtInst(FMix): FloatVector3: tmp773 << const750, const752, tmp772 V_MOV_B32 vDst(VGPR803) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR804) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR805) src0(LITERAL_CONST) const: 0x3e75c28f V_MOV_B32 vDst(VGPR806) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR807) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR808) src0(LITERAL_CONST) const: 0x3f0f5c29 V_SUBREV_F32 vDst(VGPR809) src0(VGPR800) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR809) src0(VGPR803) src1(VGPR809) // VOP2 V_MAD_F32 vDst(VGPR809) src0(VGPR806) src1(VGPR800) src2(VGPR809) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR810) src0(VGPR801) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR810) src0(VGPR804) src1(VGPR810) // VOP2 V_MAD_F32 vDst(VGPR810) src0(VGPR807) src1(VGPR801) src2(VGPR810) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR811) src0(VGPR802) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR811) src0(VGPR805) src1(VGPR811) // VOP2 V_MAD_F32 vDst(VGPR811) src0(VGPR808) src1(VGPR802) src2(VGPR811) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 774: OpLoad: FloatVector2: tmp774 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR812) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR813) src0(VGPR1) # 775: OpVectorTimesScalar: FloatVector2: tmp775 << tmp774, const671 V_MOV_B32 vDst(VGPR816) src0(LITERAL_CONST) const: 0x3f333333 V_MUL_F32 vDst(VGPR814) src0(VGPR816) src1(VGPR812) // VOP2 V_MUL_F32 vDst(VGPR815) src0(VGPR816) src1(VGPR813) // VOP2 # 776: OpCompositeExtract: Float: tmp776 << tmp775, 0 V_MOV_B32 vDst(VGPR817) src0(VGPR814) # 777: OpCompositeExtract: Float: tmp777 << tmp775, 1 V_MOV_B32 vDst(VGPR818) src0(VGPR815) # 778: OpCompositeConstruct: FloatVector3: tmp778 << tmp776, tmp777, const100 V_MOV_B32 vDst(VGPR819) src0(VGPR817) V_MOV_B32 vDst(VGPR820) src0(VGPR818) V_MOV_B32 vDst(VGPR822) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR821) src0(VGPR822) # OpStore: : tmp778 >> param779 V_MOV_B32 vDst(VGPR699) src0(VGPR819) V_MOV_B32 vDst(VGPR700) src0(VGPR820) V_MOV_B32 vDst(VGPR701) src0(VGPR821) # 780: OpFunctionCall: Float: fbm3(vf3;(param779) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x2bb # VGPR[699:701] S_MOV_B64 sDst(SGPR244) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x337 # VGPR823 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR244) # .lbl52 # 781: OpFMul: Float: tmp781 << fbm3(vf3;, const106 V_MOV_B32 vDst(VGPR824) src0(1_0_F) V_MUL_F32 vDst(VGPR825) src0(VGPR823) src1(VGPR824) // VOP2 # 782: OpExtInst(FMax): Float: tmp782 << const100, tmp781 V_MOV_B32 vDst(VGPR826) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR827) src0(VGPR826) src1(VGPR825) // VOP2 # 783: OpCompositeConstruct: FloatVector3: tmp783 << tmp782, tmp782, tmp782 V_MOV_B32 vDst(VGPR828) src0(VGPR827) V_MOV_B32 vDst(VGPR829) src0(VGPR827) V_MOV_B32 vDst(VGPR830) src0(VGPR827) # 784: OpFAdd: FloatVector3: tmp784 << tmp773, tmp783 V_ADD_F32 vDst(VGPR831) src0(VGPR809) src1(VGPR828) // VOP2 V_ADD_F32 vDst(VGPR832) src0(VGPR810) src1(VGPR829) // VOP2 V_ADD_F32 vDst(VGPR833) src0(VGPR811) src1(VGPR830) // VOP2 # 785: OpLoad: FloatVector2: tmp785 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR233) const: 0x0 V_MOVRELS_B32 vDst(VGPR834) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR835) src0(VGPR1) # 786: OpFNegate: FloatVector2: tmp786 << tmp785 V_MUL_F32 vDst(VGPR836) src0(M1_0_F) src1(VGPR834) // VOP2 V_MUL_F32 vDst(VGPR837) src0(M1_0_F) src1(VGPR835) // VOP2 # 787: OpCompositeExtract: Float: tmp787 << tmp786, 0 V_MOV_B32 vDst(VGPR838) src0(VGPR836) # 788: OpCompositeExtract: Float: tmp788 << tmp786, 1 V_MOV_B32 vDst(VGPR839) src0(VGPR837) # 789: OpCompositeConstruct: FloatVector3: tmp789 << tmp787, tmp788, const100 V_MOV_B32 vDst(VGPR840) src0(VGPR838) V_MOV_B32 vDst(VGPR841) src0(VGPR839) V_MOV_B32 vDst(VGPR843) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR842) src0(VGPR843) # OpStore: : tmp789 >> param790 V_MOV_B32 vDst(VGPR702) src0(VGPR840) V_MOV_B32 vDst(VGPR703) src0(VGPR841) V_MOV_B32 vDst(VGPR704) src0(VGPR842) # 791: OpFunctionCall: Float: fbm3(vf3;(param790) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x2be # VGPR[702:704] S_MOV_B64 sDst(SGPR246) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x34c # VGPR844 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR246) # .lbl53 # 792: OpExtInst(SmoothStep): Float: tmp792 << const489, const523, fbm3(vf3; V_MOV_B32 vDst(VGPR845) src0(LITERAL_CONST) const: 0x3e4ccccd V_MOV_B32 vDst(VGPR846) src0(LITERAL_CONST) const: 0x3e99999a V_CMP_GE_F32 src0(VGPR845) src1(VGPR844) # CF Block: Merge: .lbl57 S_MOV_B64 sDst(SGPR248) src0(EXEC) # CF Block: Cond Branch: true: .lbl58, false: .lbl54 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl54 Label: .lbl58 V_MOV_B32 vDst(VGPR847) src0(0) Label: .lbl54 S_ANDN2_B64 sDst(EXEC) src0(SGPR248) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl57 V_CMP_LE_F32 src0(VGPR846) src1(VGPR844) # CF Block: Merge: .lbl56 S_MOV_B64 sDst(SGPR250) src0(EXEC) # CF Block: Cond Branch: true: .lbl59, false: .lbl55 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl55 Label: .lbl59 V_MOV_B32 vDst(VGPR847) src0(1_0_F) Label: .lbl55 S_ANDN2_B64 sDst(EXEC) src0(SGPR250) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl56 V_SUBREV_F32 vDst(VGPR848) src0(VGPR845) src1(VGPR846) // VOP2 V_RCP_F32 vDst(VGPR848) src0(VGPR848) V_SUBREV_F32 vDst(VGPR847) src0(VGPR845) src1(VGPR844) // VOP2 V_MUL_F32 vDst(VGPR848) src0(VGPR847) src1(VGPR848) // VOP2 V_MAX_F32 vDst(VGPR848) src0(0) src1(VGPR848) // VOP2 V_MIN_F32 vDst(VGPR848) src0(1_0_F) src1(VGPR848) // VOP2 V_MOV_B32 vDst(VGPR847) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR847) src0(2_0_F) src1(VGPR848) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR848) src0(VGPR848) src1(VGPR848) // VOP2 V_MUL_F32 vDst(VGPR847) src0(VGPR848) src1(VGPR847) // VOP2 Label: .lbl56 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR250) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) Label: .lbl57 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR248) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) # 793: OpCompositeConstruct: FloatVector3: tmp793 << tmp792, tmp792, tmp792 V_MOV_B32 vDst(VGPR849) src0(VGPR847) V_MOV_B32 vDst(VGPR850) src0(VGPR847) V_MOV_B32 vDst(VGPR851) src0(VGPR847) # 794: OpVectorTimesScalar: FloatVector3: tmp794 << tmp793, const489 V_MOV_B32 vDst(VGPR855) src0(LITERAL_CONST) const: 0x3e4ccccd V_MUL_F32 vDst(VGPR852) src0(VGPR855) src1(VGPR849) // VOP2 V_MUL_F32 vDst(VGPR853) src0(VGPR855) src1(VGPR850) // VOP2 V_MUL_F32 vDst(VGPR854) src0(VGPR855) src1(VGPR851) // VOP2 # 795: OpFAdd: FloatVector3: tmp795 << tmp784, tmp794 V_ADD_F32 vDst(VGPR856) src0(VGPR831) src1(VGPR852) // VOP2 V_ADD_F32 vDst(VGPR857) src0(VGPR832) src1(VGPR853) // VOP2 V_ADD_F32 vDst(VGPR858) src0(VGPR833) src1(VGPR854) // VOP2 # 798: OpCompositeConstruct: FloatVector3: tmp798 << const303, const303, const303 V_MOV_B32 vDst(VGPR859) src0(0_5_F) V_MOV_B32 vDst(VGPR860) src0(0_5_F) V_MOV_B32 vDst(VGPR861) src0(0_5_F) # 799: OpExtInst(FMix): FloatVector3: tmp799 << tmp795, const735, tmp798 V_MOV_B32 vDst(VGPR862) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR863) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR864) src0(LITERAL_CONST) const: 0x3d4ccccd V_SUBREV_F32 vDst(VGPR865) src0(VGPR859) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR865) src0(VGPR856) src1(VGPR865) // VOP2 V_MAD_F32 vDst(VGPR865) src0(VGPR862) src1(VGPR859) src2(VGPR865) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR866) src0(VGPR860) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR866) src0(VGPR857) src1(VGPR866) // VOP2 V_MAD_F32 vDst(VGPR866) src0(VGPR863) src1(VGPR860) src2(VGPR866) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR867) src0(VGPR861) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR867) src0(VGPR858) src1(VGPR867) // VOP2 V_MAD_F32 vDst(VGPR867) src0(VGPR864) src1(VGPR861) src2(VGPR867) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 802: OpFSub: Float: tmp802 << const303, const714 V_MOV_B32 vDst(VGPR868) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR869) src0(0_5_F) src1(VGPR868) // VOP2 # 803: OpAccessChain: Float*: c1[1] # 804: OpCompositeExtract: Float: tmp804 << tmp723, 1 V_MOV_B32 vDst(VGPR870) src0(VGPR719) # 805: OpExtInst(FAbs): Float: tmp805 << tmp804 V_ADD_F32 vDst(VGPR871) src0(VGPR870) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 806: OpExtInst(SmoothStep): Float: tmp806 << tmp802, const303, tmp805 V_MOV_B32 vDst(VGPR872) src0(0_5_F) V_CMP_GE_F32 src0(VGPR869) src1(VGPR871) # CF Block: Merge: .lbl63 S_MOV_B64 sDst(SGPR252) src0(EXEC) # CF Block: Cond Branch: true: .lbl64, false: .lbl60 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl60 Label: .lbl64 V_MOV_B32 vDst(VGPR873) src0(0) Label: .lbl60 S_ANDN2_B64 sDst(EXEC) src0(SGPR252) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl63 V_CMP_LE_F32 src0(VGPR872) src1(VGPR871) # CF Block: Merge: .lbl62 S_MOV_B64 sDst(SGPR254) src0(EXEC) # CF Block: Cond Branch: true: .lbl65, false: .lbl61 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl61 Label: .lbl65 V_MOV_B32 vDst(VGPR873) src0(1_0_F) Label: .lbl61 S_ANDN2_B64 sDst(EXEC) src0(SGPR254) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl62 V_SUBREV_F32 vDst(VGPR874) src0(VGPR869) src1(VGPR872) // VOP2 V_RCP_F32 vDst(VGPR874) src0(VGPR874) V_SUBREV_F32 vDst(VGPR873) src0(VGPR869) src1(VGPR871) // VOP2 V_MUL_F32 vDst(VGPR874) src0(VGPR873) src1(VGPR874) // VOP2 V_MAX_F32 vDst(VGPR874) src0(0) src1(VGPR874) // VOP2 V_MIN_F32 vDst(VGPR874) src0(1_0_F) src1(VGPR874) // VOP2 V_MOV_B32 vDst(VGPR873) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR873) src0(2_0_F) src1(VGPR874) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR874) src0(VGPR874) src1(VGPR874) // VOP2 V_MUL_F32 vDst(VGPR873) src0(VGPR874) src1(VGPR873) // VOP2 Label: .lbl62 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR254) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) Label: .lbl63 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR252) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) # 808: OpFSub: Float: tmp808 << const303, const714 V_MOV_B32 vDst(VGPR875) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR876) src0(0_5_F) src1(VGPR875) // VOP2 # 809: OpAccessChain: Float*: c1[0] # 810: OpCompositeExtract: Float: tmp810 << tmp723, 0 V_MOV_B32 vDst(VGPR877) src0(VGPR718) # 811: OpExtInst(FAbs): Float: tmp811 << tmp810 V_ADD_F32 vDst(VGPR878) src0(VGPR877) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 812: OpExtInst(SmoothStep): Float: tmp812 << tmp808, const303, tmp811 V_MOV_B32 vDst(VGPR879) src0(0_5_F) V_CMP_GE_F32 src0(VGPR876) src1(VGPR878) # CF Block: Merge: .lbl69 S_MOV_B64 sDst(SGPR256) src0(EXEC) # CF Block: Cond Branch: true: .lbl70, false: .lbl66 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl66 Label: .lbl70 V_MOV_B32 vDst(VGPR880) src0(0) Label: .lbl66 S_ANDN2_B64 sDst(EXEC) src0(SGPR256) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl69 V_CMP_LE_F32 src0(VGPR879) src1(VGPR878) # CF Block: Merge: .lbl68 S_MOV_B64 sDst(SGPR258) src0(EXEC) # CF Block: Cond Branch: true: .lbl71, false: .lbl67 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl67 Label: .lbl71 V_MOV_B32 vDst(VGPR880) src0(1_0_F) Label: .lbl67 S_ANDN2_B64 sDst(EXEC) src0(SGPR258) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl68 V_SUBREV_F32 vDst(VGPR881) src0(VGPR876) src1(VGPR879) // VOP2 V_RCP_F32 vDst(VGPR881) src0(VGPR881) V_SUBREV_F32 vDst(VGPR880) src0(VGPR876) src1(VGPR878) // VOP2 V_MUL_F32 vDst(VGPR881) src0(VGPR880) src1(VGPR881) // VOP2 V_MAX_F32 vDst(VGPR881) src0(0) src1(VGPR881) // VOP2 V_MIN_F32 vDst(VGPR881) src0(1_0_F) src1(VGPR881) // VOP2 V_MOV_B32 vDst(VGPR880) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR880) src0(2_0_F) src1(VGPR881) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR881) src0(VGPR881) src1(VGPR881) // VOP2 V_MUL_F32 vDst(VGPR880) src0(VGPR881) src1(VGPR880) // VOP2 Label: .lbl68 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR258) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) Label: .lbl69 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR256) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) # 813: OpExtInst(FMax): Float: tmp813 << tmp806, tmp812 V_MAX_F32 vDst(VGPR882) src0(VGPR873) src1(VGPR880) // VOP2 # 816: OpFSub: Float: tmp816 << const303, const714 V_MOV_B32 vDst(VGPR883) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR884) src0(0_5_F) src1(VGPR883) // VOP2 # 817: OpAccessChain: Float*: rc1[1] # 818: OpCompositeExtract: Float: tmp818 << tmp733, 1 V_MOV_B32 vDst(VGPR885) src0(VGPR733) # 819: OpExtInst(FAbs): Float: tmp819 << tmp818 V_ADD_F32 vDst(VGPR886) src0(VGPR885) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 820: OpExtInst(SmoothStep): Float: tmp820 << tmp816, const303, tmp819 V_MOV_B32 vDst(VGPR887) src0(0_5_F) V_CMP_GE_F32 src0(VGPR884) src1(VGPR886) # CF Block: Merge: .lbl75 S_MOV_B64 sDst(SGPR260) src0(EXEC) # CF Block: Cond Branch: true: .lbl76, false: .lbl72 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl72 Label: .lbl76 V_MOV_B32 vDst(VGPR888) src0(0) Label: .lbl72 S_ANDN2_B64 sDst(EXEC) src0(SGPR260) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl75 V_CMP_LE_F32 src0(VGPR887) src1(VGPR886) # CF Block: Merge: .lbl74 S_MOV_B64 sDst(SGPR262) src0(EXEC) # CF Block: Cond Branch: true: .lbl77, false: .lbl73 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl73 Label: .lbl77 V_MOV_B32 vDst(VGPR888) src0(1_0_F) Label: .lbl73 S_ANDN2_B64 sDst(EXEC) src0(SGPR262) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl74 V_SUBREV_F32 vDst(VGPR889) src0(VGPR884) src1(VGPR887) // VOP2 V_RCP_F32 vDst(VGPR889) src0(VGPR889) V_SUBREV_F32 vDst(VGPR888) src0(VGPR884) src1(VGPR886) // VOP2 V_MUL_F32 vDst(VGPR889) src0(VGPR888) src1(VGPR889) // VOP2 V_MAX_F32 vDst(VGPR889) src0(0) src1(VGPR889) // VOP2 V_MIN_F32 vDst(VGPR889) src0(1_0_F) src1(VGPR889) // VOP2 V_MOV_B32 vDst(VGPR888) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR888) src0(2_0_F) src1(VGPR889) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR889) src0(VGPR889) src1(VGPR889) // VOP2 V_MUL_F32 vDst(VGPR888) src0(VGPR889) src1(VGPR888) // VOP2 Label: .lbl74 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR262) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) Label: .lbl75 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR260) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) # 822: OpFSub: Float: tmp822 << const303, const714 V_MOV_B32 vDst(VGPR890) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR891) src0(0_5_F) src1(VGPR890) // VOP2 # 823: OpAccessChain: Float*: rc1[0] # 824: OpCompositeExtract: Float: tmp824 << tmp733, 0 V_MOV_B32 vDst(VGPR892) src0(VGPR732) # 825: OpExtInst(FAbs): Float: tmp825 << tmp824 V_ADD_F32 vDst(VGPR893) src0(VGPR892) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 826: OpExtInst(SmoothStep): Float: tmp826 << tmp822, const303, tmp825 V_MOV_B32 vDst(VGPR894) src0(0_5_F) V_CMP_GE_F32 src0(VGPR891) src1(VGPR893) # CF Block: Merge: .lbl81 S_MOV_B64 sDst(SGPR264) src0(EXEC) # CF Block: Cond Branch: true: .lbl82, false: .lbl78 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl78 Label: .lbl82 V_MOV_B32 vDst(VGPR895) src0(0) Label: .lbl78 S_ANDN2_B64 sDst(EXEC) src0(SGPR264) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl81 V_CMP_LE_F32 src0(VGPR894) src1(VGPR893) # CF Block: Merge: .lbl80 S_MOV_B64 sDst(SGPR266) src0(EXEC) # CF Block: Cond Branch: true: .lbl83, false: .lbl79 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl79 Label: .lbl83 V_MOV_B32 vDst(VGPR895) src0(1_0_F) Label: .lbl79 S_ANDN2_B64 sDst(EXEC) src0(SGPR266) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR234) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl80 V_SUBREV_F32 vDst(VGPR896) src0(VGPR891) src1(VGPR894) // VOP2 V_RCP_F32 vDst(VGPR896) src0(VGPR896) V_SUBREV_F32 vDst(VGPR895) src0(VGPR891) src1(VGPR893) // VOP2 V_MUL_F32 vDst(VGPR896) src0(VGPR895) src1(VGPR896) // VOP2 V_MAX_F32 vDst(VGPR896) src0(0) src1(VGPR896) // VOP2 V_MIN_F32 vDst(VGPR896) src0(1_0_F) src1(VGPR896) // VOP2 V_MOV_B32 vDst(VGPR895) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR895) src0(2_0_F) src1(VGPR896) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR896) src0(VGPR896) src1(VGPR896) // VOP2 V_MUL_F32 vDst(VGPR895) src0(VGPR896) src1(VGPR895) // VOP2 Label: .lbl80 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR266) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) Label: .lbl81 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR264) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR234) # 827: OpExtInst(FMax): Float: tmp827 << tmp820, tmp826 V_MAX_F32 vDst(VGPR897) src0(VGPR888) src1(VGPR895) // VOP2 # 832: OpCompositeConstruct: FloatVector3: tmp832 << tmp827, tmp827, tmp827 V_MOV_B32 vDst(VGPR898) src0(VGPR897) V_MOV_B32 vDst(VGPR899) src0(VGPR897) V_MOV_B32 vDst(VGPR900) src0(VGPR897) # 833: OpExtInst(FMix): FloatVector3: tmp833 << tmp799, tmp746, tmp832 V_SUBREV_F32 vDst(VGPR901) src0(VGPR898) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR901) src0(VGPR865) src1(VGPR901) // VOP2 V_MAD_F32 vDst(VGPR901) src0(VGPR760) src1(VGPR898) src2(VGPR901) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR902) src0(VGPR899) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR902) src0(VGPR866) src1(VGPR902) // VOP2 V_MAD_F32 vDst(VGPR902) src0(VGPR761) src1(VGPR899) src2(VGPR902) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR903) src0(VGPR900) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR903) src0(VGPR867) src1(VGPR903) // VOP2 V_MAD_F32 vDst(VGPR903) src0(VGPR762) src1(VGPR900) src2(VGPR903) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 836: OpExtInst(FMax): Float: tmp836 << tmp827, tmp813 V_MAX_F32 vDst(VGPR904) src0(VGPR897) src1(VGPR882) // VOP2 # 837: OpCompositeConstruct: FloatVector3: tmp837 << tmp836, tmp836, tmp836 V_MOV_B32 vDst(VGPR905) src0(VGPR904) V_MOV_B32 vDst(VGPR906) src0(VGPR904) V_MOV_B32 vDst(VGPR907) src0(VGPR904) # 838: OpExtInst(FMix): FloatVector3: tmp838 << tmp795, tmp833, tmp837 V_SUBREV_F32 vDst(VGPR908) src0(VGPR905) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR908) src0(VGPR856) src1(VGPR908) // VOP2 V_MAD_F32 vDst(VGPR908) src0(VGPR901) src1(VGPR905) src2(VGPR908) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR909) src0(VGPR906) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR909) src0(VGPR857) src1(VGPR909) // VOP2 V_MAD_F32 vDst(VGPR909) src0(VGPR902) src1(VGPR906) src2(VGPR909) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR910) src0(VGPR907) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR910) src0(VGPR858) src1(VGPR910) // VOP2 V_MAD_F32 vDst(VGPR910) src0(VGPR903) src1(VGPR907) src2(VGPR910) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 839: OpVectorTimesScalar: FloatVector3: tmp839 << tmp838, const151 V_MOV_B32 vDst(VGPR914) src0(LITERAL_CONST) const: 0x3f4ccccd V_MUL_F32 vDst(VGPR911) src0(VGPR914) src1(VGPR908) // VOP2 V_MUL_F32 vDst(VGPR912) src0(VGPR914) src1(VGPR909) // VOP2 V_MUL_F32 vDst(VGPR913) src0(VGPR914) src1(VGPR910) // VOP2 # OpReturnValue: : << tmp839 S_MOV_B32 sDst(M0) src0(SGPR232) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR911) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR912) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR913) S_SETPC_B64 sDst(SGPR230) src0(SGPR230) # FloatVector3 cameraPos(f1;(Float* t) Function: FloatVector3 cameraPos(f1;() S_MOV_B64 sDst(SGPR272) src0(EXEC) # lb77 Label: lb77 # 842: OpLoad: Float: tmp842 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR271) const: 0x0 V_MOVRELS_B32 vDst(VGPR915) src0(VGPR0) # 843: OpFMul: Float: tmp843 << tmp842, const704 V_MOV_B32 vDst(VGPR916) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR917) src0(VGPR915) src1(VGPR916) // VOP2 # 845: OpLoad: Float: tmp845 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR271) const: 0x0 V_MOVRELS_B32 vDst(VGPR918) src0(VGPR0) # 846: OpFMul: Float: tmp846 << tmp845, const377 V_MOV_B32 vDst(VGPR919) src0(4_0_F) V_MUL_F32 vDst(VGPR920) src0(VGPR918) src1(VGPR919) // VOP2 # 847: OpExtInst(Cos): Float: tmp847 << tmp846 V_MUL_F32 vDst(VGPR921) src0(LITERAL_CONST) src1(VGPR920) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR921) src0(VGPR921) V_COS_F32 vDst(VGPR921) src0(VGPR921) # 849: OpFMul: Float: tmp849 << tmp847, const848 V_MOV_B32 vDst(VGPR922) src0(LITERAL_CONST) const: 0x3cf5c28f V_MUL_F32 vDst(VGPR923) src0(VGPR921) src1(VGPR922) // VOP2 # 850: OpFAdd: Float: tmp850 << const844, tmp849 V_MOV_B32 vDst(VGPR924) src0(LITERAL_CONST) const: 0x40c00000 V_ADD_F32 vDst(VGPR925) src0(VGPR924) src1(VGPR923) // VOP2 # 851: OpCompositeConstruct: FloatVector3: tmp851 << tmp843, tmp850, const100 V_MOV_B32 vDst(VGPR926) src0(VGPR917) V_MOV_B32 vDst(VGPR927) src0(VGPR925) V_MOV_B32 vDst(VGPR929) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR928) src0(VGPR929) # OpReturnValue: : << tmp851 S_MOV_B32 sDst(M0) src0(SGPR270) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR926) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR927) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR928) S_SETPC_B64 sDst(SGPR268) src0(SGPR268) # FloatVector3 targetPos(f1;(Float* ti) Function: FloatVector3 targetPos(f1;() S_MOV_B64 sDst(SGPR278) src0(EXEC) # lb80 Label: lb80 # 855: OpLoad: Float: tmp855 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR277) const: 0x0 V_MOVRELS_B32 vDst(VGPR934) src0(VGPR0) # 856: OpLoad: Float: tmp856 << t_per_target # 857: OpFMul: Float: tmp857 << tmp855, tmp856 V_MUL_F32 vDst(VGPR935) src0(VGPR934) src1(VGPR35) // VOP2 # OpStore: : tmp857 >> param858 V_MOV_B32 vDst(VGPR933) src0(VGPR935) # 859: OpFunctionCall: FloatVector3: cameraPos(f1;(param858) S_ADD_U32 sDst(SGPR271) src0(LITERAL_CONST) src1(0) const: 0x3a5 # VGPR933 S_MOV_B64 sDst(SGPR280) src0(EXEC) S_MOV_B32 sDst(SGPR270) src0(LITERAL_CONST) const: 0x3a8 # VGPR[936:938] # Indirect branch to cameraPos(f1;: ??? S_GETPC_B64 sDst(SGPR268) src0(SGPR268) S_ADD_U32 sDst(SGPR268) src0(SGPR268) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR269) src0(SGPR269) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR268) src0(SGPR268) S_MOV_B64 sDst(EXEC) src0(SGPR280) # .lbl84 # 861: OpFMul: FloatVector3: tmp861 << cameraPos(f1;, const860 V_MOV_B32 vDst(VGPR939) src0(1_0_F) V_MOV_B32 vDst(VGPR940) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR941) src0(LITERAL_CONST) const: 0x00000000 V_MUL_F32 vDst(VGPR942) src0(VGPR936) src1(VGPR939) // VOP2 V_MUL_F32 vDst(VGPR943) src0(VGPR937) src1(VGPR940) // VOP2 V_MUL_F32 vDst(VGPR944) src0(VGPR938) src1(VGPR941) // VOP2 # 862: OpLoad: Float: tmp862 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR277) const: 0x0 V_MOVRELS_B32 vDst(VGPR945) src0(VGPR0) # 864: OpFMul: Float: tmp864 << tmp862, const863 V_MOV_B32 vDst(VGPR946) src0(LITERAL_CONST) const: 0x41a00000 V_MUL_F32 vDst(VGPR947) src0(VGPR945) src1(VGPR946) // VOP2 # 865: OpExtInst(Cos): Float: tmp865 << tmp864 V_MUL_F32 vDst(VGPR948) src0(LITERAL_CONST) src1(VGPR947) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR948) src0(VGPR948) V_COS_F32 vDst(VGPR948) src0(VGPR948) # 866: OpFMul: Float: tmp866 << tmp865, const377 V_MOV_B32 vDst(VGPR949) src0(4_0_F) V_MUL_F32 vDst(VGPR950) src0(VGPR948) src1(VGPR949) // VOP2 # 868: OpLoad: Float: tmp868 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR277) const: 0x0 V_MOVRELS_B32 vDst(VGPR951) src0(VGPR0) # 870: OpFMul: Float: tmp870 << tmp868, const869 V_MOV_B32 vDst(VGPR952) src0(LITERAL_CONST) const: 0x41600000 V_MUL_F32 vDst(VGPR953) src0(VGPR951) src1(VGPR952) // VOP2 # 871: OpExtInst(Cos): Float: tmp871 << tmp870 V_MUL_F32 vDst(VGPR954) src0(LITERAL_CONST) src1(VGPR953) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR954) src0(VGPR954) V_COS_F32 vDst(VGPR954) src0(VGPR954) # 872: OpFMul: Float: tmp872 << tmp871, const109 V_MOV_B32 vDst(VGPR955) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR956) src0(VGPR954) src1(VGPR955) // VOP2 # 873: OpFAdd: Float: tmp873 << const867, tmp872 V_MOV_B32 vDst(VGPR957) src0(LITERAL_CONST) const: 0xc0e00000 V_ADD_F32 vDst(VGPR958) src0(VGPR957) src1(VGPR956) // VOP2 # 874: OpCompositeConstruct: FloatVector3: tmp874 << tmp866, const100, tmp873 V_MOV_B32 vDst(VGPR959) src0(VGPR950) V_MOV_B32 vDst(VGPR962) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR960) src0(VGPR962) V_MOV_B32 vDst(VGPR961) src0(VGPR958) # 875: OpFAdd: FloatVector3: tmp875 << tmp861, tmp874 V_ADD_F32 vDst(VGPR963) src0(VGPR942) src1(VGPR959) // VOP2 V_ADD_F32 vDst(VGPR964) src0(VGPR943) src1(VGPR960) // VOP2 V_ADD_F32 vDst(VGPR965) src0(VGPR944) src1(VGPR961) // VOP2 # OpStore: : tmp875 >> target V_MOV_B32 vDst(VGPR930) src0(VGPR963) V_MOV_B32 vDst(VGPR931) src0(VGPR964) V_MOV_B32 vDst(VGPR932) src0(VGPR965) # 876: OpLoad: FloatVector3: tmp876 << target # 877: OpVectorShuffle: FloatVector2: tmp877 << tmp876, tmp876, 0, 2 V_MOV_B32 vDst(VGPR966) src0(VGPR930) V_MOV_B32 vDst(VGPR967) src0(VGPR932) # 878: OpCompositeConstruct: FloatVector2: tmp878 << const109, const109 V_MOV_B32 vDst(VGPR970) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR968) src0(VGPR970) V_MOV_B32 vDst(VGPR971) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR969) src0(VGPR971) # 879: OpFDiv: FloatVector2: tmp879 << tmp877, tmp878 V_RCP_F32 vDst(VGPR972) src0(VGPR968) V_RCP_F32 vDst(VGPR973) src0(VGPR969) V_MUL_F32 vDst(VGPR972) src0(VGPR966) src1(VGPR972) // VOP2 V_MUL_F32 vDst(VGPR973) src0(VGPR967) src1(VGPR973) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR972) src0(VGPR972) src1(VGPR968) src2(VGPR966) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR973) src0(VGPR973) src1(VGPR969) src2(VGPR967) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 880: OpExtInst(Floor): FloatVector2: tmp880 << tmp879 V_FLOOR_F32 vDst(VGPR974) src0(VGPR972) V_FLOOR_F32 vDst(VGPR975) src0(VGPR973) # 881: OpVectorTimesScalar: FloatVector2: tmp881 << tmp880, const109 V_MOV_B32 vDst(VGPR978) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR976) src0(VGPR978) src1(VGPR974) // VOP2 V_MUL_F32 vDst(VGPR977) src0(VGPR978) src1(VGPR975) // VOP2 # 882: OpFAdd: FloatVector2: tmp882 << tmp881, const667 V_MOV_B32 vDst(VGPR979) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR980) src0(LITERAL_CONST) const: 0x3fc00000 V_ADD_F32 vDst(VGPR981) src0(VGPR976) src1(VGPR979) // VOP2 V_ADD_F32 vDst(VGPR982) src0(VGPR977) src1(VGPR980) // VOP2 # 883: OpLoad: FloatVector3: tmp883 << target # 884: OpVectorShuffle: FloatVector3: tmp884 << tmp883, tmp882, 3, 1, 4 V_MOV_B32 vDst(VGPR983) src0(VGPR981) V_MOV_B32 vDst(VGPR984) src0(VGPR931) V_MOV_B32 vDst(VGPR985) src0(VGPR982) # OpStore: : tmp884 >> target V_MOV_B32 vDst(VGPR930) src0(VGPR983) V_MOV_B32 vDst(VGPR931) src0(VGPR984) V_MOV_B32 vDst(VGPR932) src0(VGPR985) # 885: OpLoad: FloatVector3: tmp885 << target # OpReturnValue: : << tmp885 S_MOV_B32 sDst(M0) src0(SGPR276) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR930) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR931) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR932) S_SETPC_B64 sDst(SGPR274) src0(SGPR274) # Float cameraZoom(f1;(Float* ti) Function: Float cameraZoom(f1;() S_MOV_B64 sDst(SGPR286) src0(EXEC) # lb83 Label: lb83 # 889: OpLoad: Float: tmp889 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR285) const: 0x0 V_MOVRELS_B32 vDst(VGPR986) src0(VGPR0) # 890: OpFMul: Float: tmp890 << tmp889, const633 V_MOV_B32 vDst(VGPR987) src0(LITERAL_CONST) const: 0x41f00000 V_MUL_F32 vDst(VGPR988) src0(VGPR986) src1(VGPR987) // VOP2 # 891: OpExtInst(Cos): Float: tmp891 << tmp890 V_MUL_F32 vDst(VGPR989) src0(LITERAL_CONST) src1(VGPR988) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR989) src0(VGPR989) V_COS_F32 vDst(VGPR989) src0(VGPR989) # 892: OpFMul: Float: tmp892 << const303, tmp891 V_MUL_F32 vDst(VGPR990) src0(0_5_F) src1(VGPR989) // VOP2 # 893: OpFAdd: Float: tmp893 << const303, tmp892 V_ADD_F32 vDst(VGPR991) src0(0_5_F) src1(VGPR990) // VOP2 # 894: OpExtInst(FMix): Float: tmp894 << const109, const888, tmp893 V_MOV_B32 vDst(VGPR992) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR993) src0(LITERAL_CONST) const: 0x40600000 V_SUBREV_F32 vDst(VGPR994) src0(VGPR991) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR994) src0(VGPR992) src1(VGPR994) // VOP2 V_MAD_F32 vDst(VGPR994) src0(VGPR993) src1(VGPR991) src2(VGPR994) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 896: OpFMul: Float: tmp896 << tmp894, const895 V_MOV_B32 vDst(VGPR995) src0(LITERAL_CONST) const: 0x3fb33333 V_MUL_F32 vDst(VGPR996) src0(VGPR994) src1(VGPR995) // VOP2 # OpReturnValue: : << tmp896 S_MOV_B32 sDst(M0) src0(SGPR284) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR996) S_SETPC_B64 sDst(SGPR282) src0(SGPR282) # FloatVector3 trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* t, Float* max_t) Function: FloatVector3 trace(vf3;vf3;f1;f1;(, FloatVector3 cameraZoom(f1;.rd, Float cameraZoom(f1;.t, Float cameraZoom(f1;.max_t) S_MOV_B64 sDst(SGPR296) src0(EXEC) # lb90 Label: lb90 # OpStore: : const471 >> i V_MOV_B32 vDst(VGPR997) src0(0) # OpBranch: to lb900 # lb900 Label: lb900 # OpLoopMerge: (merge: lb902, continue: lb903) # CF Block: Merge: lb902, Continue: lb903 S_MOV_B64 sDst(SGPR298) src0(EXEC) S_MOV_B64 sDst(SGPR300) src0(EXEC) S_MOV_B64 sDst(SGPR302) src0(EXEC) Label: lb900Loop # OpBranch: to lb904 # lb904 Label: lb904 # 905: OpLoad: Int: tmp905 << i Decorators: RelaxedPrecision # 907: OpSLessThan: Bool: tmp907 << tmp905, const906 V_MOV_B32 vDst(VGPR1031) src0(LITERAL_CONST) const: 0x00000064 V_CMP_LT_I32 dst(SGPR304) src0(VGPR997) src1(VGPR1031) // VOP3a # OpBranchConditional: if(tmp907) then branch to lb901, else branch to lb902 # CF Block: Cond Branch: true: lb901, false: lb902 S_AND_B64 sDst(EXEC) src0(SGPR304) src1(EXEC) S_CBRANCH_EXECZ ??? lb902 # lb901 Label: lb901 S_MOV_B64 sDst(SGPR300) src0(EXEC) S_MOV_B64 sDst(SGPR302) src0(EXEC) # 909: OpLoad: FloatVector3: tmp909 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR291) const: 0x0 V_MOVRELS_B32 vDst(VGPR1032) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1033) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1034) src0(VGPR2) # 910: OpLoad: FloatVector3: tmp910 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1035) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1036) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1037) src0(VGPR2) # 911: OpLoad: Float: tmp911 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELS_B32 vDst(VGPR1038) src0(VGPR0) # 912: OpVectorTimesScalar: FloatVector3: tmp912 << tmp910, tmp911 V_MUL_F32 vDst(VGPR1039) src0(VGPR1038) src1(VGPR1035) // VOP2 V_MUL_F32 vDst(VGPR1040) src0(VGPR1038) src1(VGPR1036) // VOP2 V_MUL_F32 vDst(VGPR1041) src0(VGPR1038) src1(VGPR1037) // VOP2 # 913: OpFAdd: FloatVector3: tmp913 << tmp909, tmp912 V_ADD_F32 vDst(VGPR1042) src0(VGPR1032) src1(VGPR1039) // VOP2 V_ADD_F32 vDst(VGPR1043) src0(VGPR1033) src1(VGPR1040) // VOP2 V_ADD_F32 vDst(VGPR1044) src0(VGPR1034) src1(VGPR1041) // VOP2 # OpStore: : tmp913 >> param914 V_MOV_B32 vDst(VGPR998) src0(VGPR1042) V_MOV_B32 vDst(VGPR999) src0(VGPR1043) V_MOV_B32 vDst(VGPR1000) src0(VGPR1044) # 915: OpFunctionCall: Float: de(vf3;(param914) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3e6 # VGPR[998:1000] S_MOV_B64 sDst(SGPR306) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x415 # VGPR1045 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR306) # .lbl85 # 916: OpLoad: Float: tmp916 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELS_B32 vDst(VGPR1046) src0(VGPR0) # 917: OpLoad: Float: tmp917 << max_t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR294) const: 0x0 V_MOVRELS_B32 vDst(VGPR1047) src0(VGPR0) # 918: OpFOrdGreaterThan: Bool: tmp918 << tmp916, tmp917 V_CMP_GT_F32 dst(SGPR308) src0(VGPR1046) src1(VGPR1047) // VOP3a # OpSelectionMerge: (merge: lb920) # CF Block: Merge: lb920 S_MOV_B64 sDst(SGPR310) src0(EXEC) # OpBranchConditional: if(tmp918) then branch to lb919, else branch to lb920 # CF Block: Cond Branch: true: lb919, false: lb920 S_AND_B64 sDst(EXEC) src0(SGPR308) src1(EXEC) S_CBRANCH_EXECZ ??? lb920 # lb919 Label: lb919 # OpReturnValue: : << const921 V_MOV_B32 vDst(VGPR1048) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1049) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1050) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR290) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1048) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1049) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1050) S_ANDN2_B64 sDst(SGPR296) src0(SGPR296) src1(EXEC) S_ANDN2_B64 sDst(SGPR300) src0(SGPR300) src1(EXEC) S_ANDN2_B64 sDst(SGPR302) src0(SGPR302) src1(EXEC) # lb920 Label: lb920 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR310) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR302) # 924: OpExtInst(FAbs): Float: tmp924 << de(vf3; V_ADD_F32 vDst(VGPR1051) src0(VGPR1045) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 926: OpFOrdLessThan: Bool: tmp926 << tmp924, const925 V_MOV_B32 vDst(VGPR1052) src0(LITERAL_CONST) const: 0x38d1b717 V_CMP_LT_F32 dst(SGPR312) src0(VGPR1051) src1(VGPR1052) // VOP3a # OpSelectionMerge: (merge: lb928) # CF Block: Merge: lb928 S_MOV_B64 sDst(SGPR314) src0(EXEC) # OpBranchConditional: if(tmp926) then branch to lb927, else branch to lb928 # CF Block: Cond Branch: true: lb927, false: lb928 S_AND_B64 sDst(EXEC) src0(SGPR312) src1(EXEC) S_CBRANCH_EXECZ ??? lb928 # lb927 Label: lb927 # OpBranch: to lb902 S_ANDN2_B64 sDst(SGPR300) src0(SGPR300) src1(EXEC) S_ANDN2_B64 sDst(SGPR302) src0(SGPR302) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR302) src1(EXEC) # lb928 Label: lb928 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR314) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR302) # 930: OpLoad: Float: tmp930 << max_t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR294) const: 0x0 V_MOVRELS_B32 vDst(VGPR1053) src0(VGPR0) # 931: OpFAdd: Float: tmp931 << tmp930, const637 V_MOV_B32 vDst(VGPR1054) src0(LITERAL_CONST) const: 0x3a83126f V_ADD_F32 vDst(VGPR1055) src0(VGPR1053) src1(VGPR1054) // VOP2 # 932: OpLoad: Float: tmp932 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELS_B32 vDst(VGPR1056) src0(VGPR0) # 934: OpFAdd: Float: tmp934 << tmp932, de(vf3; V_ADD_F32 vDst(VGPR1057) src0(VGPR1056) src1(VGPR1045) // VOP2 # 935: OpExtInst(FMin): Float: tmp935 << tmp931, tmp934 V_MIN_F32 vDst(VGPR1058) src0(VGPR1055) src1(VGPR1057) // VOP2 # OpStore: : tmp935 >> t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1058) # OpBranch: to lb903 # lb903 Label: lb903 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR300) # 936: OpLoad: Int: tmp936 << i Decorators: RelaxedPrecision # 937: OpIAdd: Int: tmp937 << tmp936, const285 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR1059) src0(1_INT) V_ADD_I32 vDst(VGPR1060) src0(VGPR997) src1(VGPR1059) // VOP2 # OpStore: : tmp937 >> i V_MOV_B32 vDst(VGPR997) src0(VGPR1060) # OpBranch: to lb900 S_BRANCH ??? lb900Loop # lb902 Label: lb902 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR298) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR296) # 939: OpLoad: FloatVector3: tmp939 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR291) const: 0x0 V_MOVRELS_B32 vDst(VGPR1061) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1062) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1063) src0(VGPR2) # 940: OpLoad: FloatVector3: tmp940 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1064) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1065) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1066) src0(VGPR2) # 941: OpLoad: Float: tmp941 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR293) const: 0x0 V_MOVRELS_B32 vDst(VGPR1067) src0(VGPR0) # 942: OpVectorTimesScalar: FloatVector3: tmp942 << tmp940, tmp941 V_MUL_F32 vDst(VGPR1068) src0(VGPR1067) src1(VGPR1064) // VOP2 V_MUL_F32 vDst(VGPR1069) src0(VGPR1067) src1(VGPR1065) // VOP2 V_MUL_F32 vDst(VGPR1070) src0(VGPR1067) src1(VGPR1066) // VOP2 # 943: OpFAdd: FloatVector3: tmp943 << tmp939, tmp942 V_ADD_F32 vDst(VGPR1071) src0(VGPR1061) src1(VGPR1068) // VOP2 V_ADD_F32 vDst(VGPR1072) src0(VGPR1062) src1(VGPR1069) // VOP2 V_ADD_F32 vDst(VGPR1073) src0(VGPR1063) src1(VGPR1070) // VOP2 # OpStore: : const946 >> col V_MOV_B32 vDst(VGPR1074) src0(LITERAL_CONST) const: 0x3ca3d70a V_MOV_B32 vDst(VGPR1075) src0(LITERAL_CONST) const: 0x3c23d70a V_MOV_B32 vDst(VGPR1076) src0(LITERAL_CONST) const: 0x3ba3d70a V_MOV_B32 vDst(VGPR1001) src0(VGPR1074) V_MOV_B32 vDst(VGPR1002) src0(VGPR1075) V_MOV_B32 vDst(VGPR1003) src0(VGPR1076) # OpStore: : tmp943 >> param949 V_MOV_B32 vDst(VGPR1004) src0(VGPR1071) V_MOV_B32 vDst(VGPR1005) src0(VGPR1072) V_MOV_B32 vDst(VGPR1006) src0(VGPR1073) # 951: OpFunctionCall: Float: de(vf3;(param949) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3ec # VGPR[1004:1006] S_MOV_B64 sDst(SGPR316) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x435 # VGPR1077 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR316) # .lbl86 # 955: OpCompositeConstruct: FloatVector3: tmp955 << const637, const100, const100 V_MOV_B32 vDst(VGPR1081) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR1078) src0(VGPR1081) V_MOV_B32 vDst(VGPR1082) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1079) src0(VGPR1082) V_MOV_B32 vDst(VGPR1083) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1080) src0(VGPR1083) # 956: OpFAdd: FloatVector3: tmp956 << tmp943, tmp955 V_ADD_F32 vDst(VGPR1084) src0(VGPR1071) src1(VGPR1078) // VOP2 V_ADD_F32 vDst(VGPR1085) src0(VGPR1072) src1(VGPR1079) // VOP2 V_ADD_F32 vDst(VGPR1086) src0(VGPR1073) src1(VGPR1080) // VOP2 # OpStore: : tmp956 >> param957 V_MOV_B32 vDst(VGPR1007) src0(VGPR1084) V_MOV_B32 vDst(VGPR1008) src0(VGPR1085) V_MOV_B32 vDst(VGPR1009) src0(VGPR1086) # 958: OpFunctionCall: Float: de(vf3;(param957) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3ef # VGPR[1007:1009] S_MOV_B64 sDst(SGPR318) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x43f # VGPR1087 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR318) # .lbl87 # 960: OpFSub: Float: tmp960 << de(vf3;, de(vf3; V_SUB_F32 vDst(VGPR1088) src0(VGPR1087) src1(VGPR1077) // VOP2 # 963: OpCompositeConstruct: FloatVector3: tmp963 << const100, const637, const100 V_MOV_B32 vDst(VGPR1092) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1089) src0(VGPR1092) V_MOV_B32 vDst(VGPR1093) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR1090) src0(VGPR1093) V_MOV_B32 vDst(VGPR1094) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1091) src0(VGPR1094) # 964: OpFAdd: FloatVector3: tmp964 << tmp943, tmp963 V_ADD_F32 vDst(VGPR1095) src0(VGPR1071) src1(VGPR1089) // VOP2 V_ADD_F32 vDst(VGPR1096) src0(VGPR1072) src1(VGPR1090) // VOP2 V_ADD_F32 vDst(VGPR1097) src0(VGPR1073) src1(VGPR1091) // VOP2 # OpStore: : tmp964 >> param965 V_MOV_B32 vDst(VGPR1010) src0(VGPR1095) V_MOV_B32 vDst(VGPR1011) src0(VGPR1096) V_MOV_B32 vDst(VGPR1012) src0(VGPR1097) # 966: OpFunctionCall: Float: de(vf3;(param965) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3f2 # VGPR[1010:1012] S_MOV_B64 sDst(SGPR320) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x44a # VGPR1098 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR320) # .lbl88 # 968: OpFSub: Float: tmp968 << de(vf3;, de(vf3; V_SUB_F32 vDst(VGPR1099) src0(VGPR1098) src1(VGPR1077) // VOP2 # 971: OpCompositeConstruct: FloatVector3: tmp971 << const100, const100, const637 V_MOV_B32 vDst(VGPR1103) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1100) src0(VGPR1103) V_MOV_B32 vDst(VGPR1104) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1101) src0(VGPR1104) V_MOV_B32 vDst(VGPR1105) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR1102) src0(VGPR1105) # 972: OpFAdd: FloatVector3: tmp972 << tmp943, tmp971 V_ADD_F32 vDst(VGPR1106) src0(VGPR1071) src1(VGPR1100) // VOP2 V_ADD_F32 vDst(VGPR1107) src0(VGPR1072) src1(VGPR1101) // VOP2 V_ADD_F32 vDst(VGPR1108) src0(VGPR1073) src1(VGPR1102) // VOP2 # OpStore: : tmp972 >> param973 V_MOV_B32 vDst(VGPR1013) src0(VGPR1106) V_MOV_B32 vDst(VGPR1014) src0(VGPR1107) V_MOV_B32 vDst(VGPR1015) src0(VGPR1108) # 974: OpFunctionCall: Float: de(vf3;(param973) S_ADD_U32 sDst(SGPR221) src0(LITERAL_CONST) src1(0) const: 0x3f5 # VGPR[1013:1015] S_MOV_B64 sDst(SGPR322) src0(EXEC) S_MOV_B32 sDst(SGPR220) src0(LITERAL_CONST) const: 0x455 # VGPR1109 # Indirect branch to de(vf3;: ??? S_GETPC_B64 sDst(SGPR218) src0(SGPR218) S_ADD_U32 sDst(SGPR218) src0(SGPR218) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR219) src0(SGPR219) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR218) src0(SGPR218) S_MOV_B64 sDst(EXEC) src0(SGPR322) # .lbl89 # 976: OpFSub: Float: tmp976 << de(vf3;, de(vf3; V_SUB_F32 vDst(VGPR1110) src0(VGPR1109) src1(VGPR1077) // VOP2 # 977: OpCompositeConstruct: FloatVector3: tmp977 << tmp960, tmp968, tmp976 V_MOV_B32 vDst(VGPR1111) src0(VGPR1088) V_MOV_B32 vDst(VGPR1112) src0(VGPR1099) V_MOV_B32 vDst(VGPR1113) src0(VGPR1110) # 978: OpExtInst(Normalize): FloatVector3: tmp978 << tmp977 V_MUL_F32 vDst(VGPR1114) src0(VGPR1111) src1(VGPR1111) // VOP2 V_MAC_F32 vDst(VGPR1114) src0(VGPR1112) src1(VGPR1112) // VOP2 V_MAC_F32 vDst(VGPR1114) src0(VGPR1113) src1(VGPR1113) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1114) src0(VGPR1114) V_MUL_F32 vDst(VGPR1115) src0(VGPR1111) src1(VGPR1114) // VOP2 V_MUL_F32 vDst(VGPR1116) src0(VGPR1112) src1(VGPR1114) // VOP2 V_MUL_F32 vDst(VGPR1117) src0(VGPR1113) src1(VGPR1114) // VOP2 # 980: OpLoad: FloatVector3: tmp980 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1118) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1119) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1120) src0(VGPR2) # 982: OpLoad: FloatVector3: tmp982 << l # 983: OpLoad: FloatVector3: tmp983 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1121) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1122) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1123) src0(VGPR2) # 984: OpFSub: FloatVector3: tmp984 << tmp982, tmp983 V_SUB_F32 vDst(VGPR1124) src0(VGPR37) src1(VGPR1121) // VOP2 V_SUB_F32 vDst(VGPR1125) src0(VGPR38) src1(VGPR1122) // VOP2 V_SUB_F32 vDst(VGPR1126) src0(VGPR39) src1(VGPR1123) // VOP2 # 985: OpExtInst(Normalize): FloatVector3: tmp985 << tmp984 V_MUL_F32 vDst(VGPR1127) src0(VGPR1124) src1(VGPR1124) // VOP2 V_MAC_F32 vDst(VGPR1127) src0(VGPR1125) src1(VGPR1125) // VOP2 V_MAC_F32 vDst(VGPR1127) src0(VGPR1126) src1(VGPR1126) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1127) src0(VGPR1127) V_MUL_F32 vDst(VGPR1128) src0(VGPR1124) src1(VGPR1127) // VOP2 V_MUL_F32 vDst(VGPR1129) src0(VGPR1125) src1(VGPR1127) // VOP2 V_MUL_F32 vDst(VGPR1130) src0(VGPR1126) src1(VGPR1127) // VOP2 # 986: OpLoad: Float: tmp986 << is_choc # 987: OpFOrdLessThan: Bool: tmp987 << tmp986, const303 V_MOV_B32 vDst(VGPR1131) src0(0_5_F) V_CMP_LT_F32 dst(SGPR324) src0(VGPR33) src1(VGPR1131) // VOP3a # OpSelectionMerge: (merge: lb989) # CF Block: Merge: lb989 S_MOV_B64 sDst(SGPR326) src0(EXEC) # OpBranchConditional: if(tmp987) then branch to lb988, else branch to lb1078 # CF Block: Cond Branch: true: lb988, false: lb1078 S_AND_B64 sDst(EXEC) src0(SGPR324) src1(EXEC) S_CBRANCH_EXECZ ??? lb1078 # lb988 Label: lb988 # 990: OpAccessChain: Float*: rp[0] # 991: OpCompositeExtract: Float: tmp991 << tmp943, 0 V_MOV_B32 vDst(VGPR1132) src0(VGPR1071) # 992: OpFDiv: Float: tmp992 << tmp991, const109 V_MOV_B32 vDst(VGPR1133) src0(LITERAL_CONST) const: 0x40400000 V_RCP_F32 vDst(VGPR1134) src0(VGPR1133) V_MUL_F32 vDst(VGPR1134) src0(VGPR1132) src1(VGPR1134) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1134) src0(VGPR1134) src1(VGPR1133) src2(VGPR1132) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 993: OpExtInst(Floor): Float: tmp993 << tmp992 V_FLOOR_F32 vDst(VGPR1135) src0(VGPR1134) # 994: OpFMod: Float: tmp994 << tmp993, const127 V_MOV_B32 vDst(VGPR1136) src0(2_0_F) V_RCP_F32 vDst(VGPR1137) src0(VGPR1136) V_MUL_F32 vDst(VGPR1137) src0(VGPR1135) src1(VGPR1137) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1137) src0(VGPR1137) src1(VGPR1136) src2(VGPR1135) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR1137) src0(VGPR1137) V_MAD_F32 vDst(VGPR1137) src0(VGPR1136) src1(VGPR1137) src2(VGPR1135) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 995: OpFOrdGreaterThan: Bool: tmp995 << tmp994, const303 V_MOV_B32 vDst(VGPR1138) src0(0_5_F) V_CMP_GT_F32 dst(SGPR328) src0(VGPR1137) src1(VGPR1138) // VOP3a # OpSelectionMerge: (merge: lb997) # CF Block: Merge: lb997 S_MOV_B64 sDst(SGPR330) src0(EXEC) # OpBranchConditional: if(tmp995) then branch to lb996, else branch to lb1034 # CF Block: Cond Branch: true: lb996, false: lb1034 S_AND_B64 sDst(EXEC) src0(SGPR328) src1(EXEC) S_CBRANCH_EXECZ ??? lb1034 # lb996 Label: lb996 # 1000: OpVectorShuffle: FloatVector2: tmp1000 << tmp943, tmp943, 0, 2 V_MOV_B32 vDst(VGPR1139) src0(VGPR1071) V_MOV_B32 vDst(VGPR1140) src0(VGPR1073) # 1002: OpVectorShuffle: FloatVector2: tmp1002 << tmp943, tmp943, 0, 2 V_MOV_B32 vDst(VGPR1141) src0(VGPR1071) V_MOV_B32 vDst(VGPR1142) src0(VGPR1073) # 1003: OpCompositeConstruct: FloatVector2: tmp1003 << const109, const109 V_MOV_B32 vDst(VGPR1145) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR1143) src0(VGPR1145) V_MOV_B32 vDst(VGPR1146) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR1144) src0(VGPR1146) # 1004: OpFDiv: FloatVector2: tmp1004 << tmp1002, tmp1003 V_RCP_F32 vDst(VGPR1147) src0(VGPR1143) V_RCP_F32 vDst(VGPR1148) src0(VGPR1144) V_MUL_F32 vDst(VGPR1147) src0(VGPR1141) src1(VGPR1147) // VOP2 V_MUL_F32 vDst(VGPR1148) src0(VGPR1142) src1(VGPR1148) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1147) src0(VGPR1147) src1(VGPR1143) src2(VGPR1141) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR1148) src0(VGPR1148) src1(VGPR1144) src2(VGPR1142) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1005: OpExtInst(Floor): FloatVector2: tmp1005 << tmp1004 V_FLOOR_F32 vDst(VGPR1149) src0(VGPR1147) V_FLOOR_F32 vDst(VGPR1150) src0(VGPR1148) # 1006: OpVectorTimesScalar: FloatVector2: tmp1006 << tmp1005, const109 V_MOV_B32 vDst(VGPR1153) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR1151) src0(VGPR1153) src1(VGPR1149) // VOP2 V_MUL_F32 vDst(VGPR1152) src0(VGPR1153) src1(VGPR1150) // VOP2 # 1007: OpFAdd: FloatVector2: tmp1007 << tmp1006, const667 V_MOV_B32 vDst(VGPR1154) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR1155) src0(LITERAL_CONST) const: 0x3fc00000 V_ADD_F32 vDst(VGPR1156) src0(VGPR1151) src1(VGPR1154) // VOP2 V_ADD_F32 vDst(VGPR1157) src0(VGPR1152) src1(VGPR1155) // VOP2 # 1008: OpExtInst(Distance): Float: tmp1008 << tmp1000, tmp1007 V_SUB_F32 vDst(VGPR1158) src0(VGPR1139) src1(VGPR1156) // VOP2 V_SUB_F32 vDst(VGPR1159) src0(VGPR1140) src1(VGPR1157) // VOP2 V_MUL_F32 vDst(VGPR1160) src0(VGPR1158) src1(VGPR1158) // VOP2 V_MAC_F32 vDst(VGPR1160) src0(VGPR1159) src1(VGPR1159) // VOP2 V_SQRT_F32 vDst(VGPR1160) src0(VGPR1160) # 1009: OpFMul: Float: tmp1009 << tmp1008, const704 V_MOV_B32 vDst(VGPR1161) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR1162) src0(VGPR1160) src1(VGPR1161) // VOP2 # 1010: OpExtInst(Pow): Float: tmp1010 << tmp1009, const127 V_MOV_B32 vDst(VGPR1163) src0(2_0_F) V_LOG_F32 vDst(VGPR1164) src0(VGPR1162) V_MUL_F32 vDst(VGPR1164) src0(VGPR1163) src1(VGPR1164) // VOP2 V_EXP_F32 vDst(VGPR1164) src0(VGPR1164) # 1019: OpFAdd: Float: tmp1019 << const303, tmp1010 V_ADD_F32 vDst(VGPR1165) src0(0_5_F) src1(VGPR1164) // VOP2 # 1021: OpFAdd: Float: tmp1021 << const704, tmp1010 V_MOV_B32 vDst(VGPR1166) src0(LITERAL_CONST) const: 0x3f19999a V_ADD_F32 vDst(VGPR1167) src0(VGPR1166) src1(VGPR1164) // VOP2 # 1023: OpVectorShuffle: FloatVector2: tmp1023 << tmp943, tmp943, 0, 2 V_MOV_B32 vDst(VGPR1168) src0(VGPR1071) V_MOV_B32 vDst(VGPR1169) src0(VGPR1073) # 1024: OpVectorTimesScalar: FloatVector2: tmp1024 << tmp1023, const621 V_MOV_B32 vDst(VGPR1172) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR1170) src0(VGPR1172) src1(VGPR1168) // VOP2 V_MUL_F32 vDst(VGPR1171) src0(VGPR1172) src1(VGPR1169) // VOP2 # 1025: OpCompositeExtract: Float: tmp1025 << tmp1024, 0 V_MOV_B32 vDst(VGPR1173) src0(VGPR1170) # 1026: OpCompositeExtract: Float: tmp1026 << tmp1024, 1 V_MOV_B32 vDst(VGPR1174) src0(VGPR1171) # 1027: OpCompositeConstruct: FloatVector3: tmp1027 << tmp1025, tmp1026, const100 V_MOV_B32 vDst(VGPR1175) src0(VGPR1173) V_MOV_B32 vDst(VGPR1176) src0(VGPR1174) V_MOV_B32 vDst(VGPR1178) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1177) src0(VGPR1178) # OpStore: : tmp1027 >> param1028 V_MOV_B32 vDst(VGPR1019) src0(VGPR1175) V_MOV_B32 vDst(VGPR1020) src0(VGPR1176) V_MOV_B32 vDst(VGPR1021) src0(VGPR1177) # 1029: OpFunctionCall: Float: fbm3(vf3;(param1028) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x3fb # VGPR[1019:1021] S_MOV_B64 sDst(SGPR332) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x49b # VGPR1179 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR332) # .lbl90 # 1030: OpFAdd: Float: tmp1030 << const748, fbm3(vf3; V_MOV_B32 vDst(VGPR1180) src0(LITERAL_CONST) const: 0x3ecccccd V_ADD_F32 vDst(VGPR1181) src0(VGPR1180) src1(VGPR1179) // VOP2 # 1031: OpExtInst(SmoothStep): Float: tmp1031 << tmp1019, tmp1021, tmp1030 V_CMP_GE_F32 src0(VGPR1165) src1(VGPR1181) # CF Block: Merge: .lbl94 S_MOV_B64 sDst(SGPR334) src0(EXEC) # CF Block: Cond Branch: true: .lbl95, false: .lbl91 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl91 Label: .lbl95 V_MOV_B32 vDst(VGPR1182) src0(0) Label: .lbl91 S_ANDN2_B64 sDst(EXEC) src0(SGPR334) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR296) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl94 V_CMP_LE_F32 src0(VGPR1167) src1(VGPR1181) # CF Block: Merge: .lbl93 S_MOV_B64 sDst(SGPR336) src0(EXEC) # CF Block: Cond Branch: true: .lbl96, false: .lbl92 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl92 Label: .lbl96 V_MOV_B32 vDst(VGPR1182) src0(1_0_F) Label: .lbl92 S_ANDN2_B64 sDst(EXEC) src0(SGPR336) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR296) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl93 V_SUBREV_F32 vDst(VGPR1183) src0(VGPR1165) src1(VGPR1167) // VOP2 V_RCP_F32 vDst(VGPR1183) src0(VGPR1183) V_SUBREV_F32 vDst(VGPR1182) src0(VGPR1165) src1(VGPR1181) // VOP2 V_MUL_F32 vDst(VGPR1183) src0(VGPR1182) src1(VGPR1183) // VOP2 V_MAX_F32 vDst(VGPR1183) src0(0) src1(VGPR1183) // VOP2 V_MIN_F32 vDst(VGPR1183) src0(1_0_F) src1(VGPR1183) // VOP2 V_MOV_B32 vDst(VGPR1182) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1182) src0(2_0_F) src1(VGPR1183) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1183) src0(VGPR1183) src1(VGPR1183) // VOP2 V_MUL_F32 vDst(VGPR1182) src0(VGPR1183) src1(VGPR1182) // VOP2 Label: .lbl93 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR336) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR296) Label: .lbl94 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR334) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR296) # 1032: OpCompositeConstruct: FloatVector3: tmp1032 << tmp1031, tmp1031, tmp1031 V_MOV_B32 vDst(VGPR1184) src0(VGPR1182) V_MOV_B32 vDst(VGPR1185) src0(VGPR1182) V_MOV_B32 vDst(VGPR1186) src0(VGPR1182) # 1033: OpExtInst(FMix): FloatVector3: tmp1033 << const1013, const1017, tmp1032 V_MOV_B32 vDst(VGPR1187) src0(4_0_F) V_MOV_B32 vDst(VGPR1188) src0(4_0_F) V_MOV_B32 vDst(VGPR1189) src0(LITERAL_CONST) const: 0x40266666 V_MOV_B32 vDst(VGPR1190) src0(LITERAL_CONST) const: 0x3f47ae14 V_MOV_B32 vDst(VGPR1191) src0(LITERAL_CONST) const: 0x3eb851ec V_MOV_B32 vDst(VGPR1192) src0(LITERAL_CONST) const: 0x3df5c28f V_SUBREV_F32 vDst(VGPR1193) src0(VGPR1184) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1193) src0(VGPR1187) src1(VGPR1193) // VOP2 V_MAD_F32 vDst(VGPR1193) src0(VGPR1190) src1(VGPR1184) src2(VGPR1193) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1194) src0(VGPR1185) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1194) src0(VGPR1188) src1(VGPR1194) // VOP2 V_MAD_F32 vDst(VGPR1194) src0(VGPR1191) src1(VGPR1185) src2(VGPR1194) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1195) src0(VGPR1186) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1195) src0(VGPR1189) src1(VGPR1195) // VOP2 V_MAD_F32 vDst(VGPR1195) src0(VGPR1192) src1(VGPR1186) src2(VGPR1195) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1033 >> chocolour V_MOV_B32 vDst(VGPR1016) src0(VGPR1193) V_MOV_B32 vDst(VGPR1017) src0(VGPR1194) V_MOV_B32 vDst(VGPR1018) src0(VGPR1195) # OpBranch: to lb997 # lb1034 Label: lb1034 S_ANDN2_B64 sDst(EXEC) src0(SGPR330) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR296) src1(EXEC) S_CBRANCH_EXECZ ??? lb997 # 1036: OpAccessChain: Float*: rp[0] # 1037: OpCompositeExtract: Float: tmp1037 << tmp943, 0 V_MOV_B32 vDst(VGPR1196) src0(VGPR1071) # 1038: OpFMul: Float: tmp1038 << tmp1037, const621 V_MOV_B32 vDst(VGPR1197) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR1198) src0(VGPR1196) src1(VGPR1197) // VOP2 # 1039: OpAccessChain: Float*: rp[2] # 1040: OpCompositeExtract: Float: tmp1040 << tmp943, 2 V_MOV_B32 vDst(VGPR1199) src0(VGPR1073) # 1041: OpFMul: Float: tmp1041 << tmp1040, const401 V_MOV_B32 vDst(VGPR1200) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR1201) src0(VGPR1199) src1(VGPR1200) // VOP2 # 1042: OpExtInst(Sin): Float: tmp1042 << tmp1041 V_MUL_F32 vDst(VGPR1202) src0(LITERAL_CONST) src1(VGPR1201) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR1202) src0(VGPR1202) V_SIN_F32 vDst(VGPR1202) src0(VGPR1202) # 1043: OpFAdd: Float: tmp1043 << tmp1038, tmp1042 V_ADD_F32 vDst(VGPR1203) src0(VGPR1198) src1(VGPR1202) // VOP2 # 1044: OpExtInst(Cos): Float: tmp1044 << tmp1043 V_MUL_F32 vDst(VGPR1204) src0(LITERAL_CONST) src1(VGPR1203) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR1204) src0(VGPR1204) V_COS_F32 vDst(VGPR1204) src0(VGPR1204) # 1045: OpFMul: Float: tmp1045 << const303, tmp1044 V_MUL_F32 vDst(VGPR1205) src0(0_5_F) src1(VGPR1204) // VOP2 # 1046: OpFAdd: Float: tmp1046 << const303, tmp1045 V_ADD_F32 vDst(VGPR1206) src0(0_5_F) src1(VGPR1205) // VOP2 # 1047: OpExtInst(SmoothStep): Float: tmp1047 << const671, const435, tmp1046 V_MOV_B32 vDst(VGPR1207) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR1208) src0(LITERAL_CONST) const: 0x3f666666 V_CMP_GE_F32 src0(VGPR1207) src1(VGPR1206) # CF Block: Merge: .lbl100 S_MOV_B64 sDst(SGPR338) src0(EXEC) # CF Block: Cond Branch: true: .lbl101, false: .lbl97 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl97 Label: .lbl101 V_MOV_B32 vDst(VGPR1209) src0(0) Label: .lbl97 S_ANDN2_B64 sDst(EXEC) src0(SGPR338) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR296) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl100 V_CMP_LE_F32 src0(VGPR1208) src1(VGPR1206) # CF Block: Merge: .lbl99 S_MOV_B64 sDst(SGPR340) src0(EXEC) # CF Block: Cond Branch: true: .lbl102, false: .lbl98 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl98 Label: .lbl102 V_MOV_B32 vDst(VGPR1209) src0(1_0_F) Label: .lbl98 S_ANDN2_B64 sDst(EXEC) src0(SGPR340) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR296) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl99 V_SUBREV_F32 vDst(VGPR1210) src0(VGPR1207) src1(VGPR1208) // VOP2 V_RCP_F32 vDst(VGPR1210) src0(VGPR1210) V_SUBREV_F32 vDst(VGPR1209) src0(VGPR1207) src1(VGPR1206) // VOP2 V_MUL_F32 vDst(VGPR1210) src0(VGPR1209) src1(VGPR1210) // VOP2 V_MAX_F32 vDst(VGPR1210) src0(0) src1(VGPR1210) // VOP2 V_MIN_F32 vDst(VGPR1210) src0(1_0_F) src1(VGPR1210) // VOP2 V_MOV_B32 vDst(VGPR1209) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1209) src0(2_0_F) src1(VGPR1210) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1210) src0(VGPR1210) src1(VGPR1210) // VOP2 V_MUL_F32 vDst(VGPR1209) src0(VGPR1210) src1(VGPR1209) // VOP2 Label: .lbl99 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR340) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR296) Label: .lbl100 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR338) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR296) # 1048: OpCompositeConstruct: FloatVector3: tmp1048 << tmp1047, tmp1047, tmp1047 V_MOV_B32 vDst(VGPR1211) src0(VGPR1209) V_MOV_B32 vDst(VGPR1212) src0(VGPR1209) V_MOV_B32 vDst(VGPR1213) src0(VGPR1209) # 1049: OpExtInst(FMix): FloatVector3: tmp1049 << const1035, const1013, tmp1048 V_MOV_B32 vDst(VGPR1214) src0(LITERAL_CONST) const: 0x3fa66666 V_MOV_B32 vDst(VGPR1215) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR1216) src0(LITERAL_CONST) const: 0x3e4ccccd V_MOV_B32 vDst(VGPR1217) src0(4_0_F) V_MOV_B32 vDst(VGPR1218) src0(4_0_F) V_MOV_B32 vDst(VGPR1219) src0(LITERAL_CONST) const: 0x40266666 V_SUBREV_F32 vDst(VGPR1220) src0(VGPR1211) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1220) src0(VGPR1214) src1(VGPR1220) // VOP2 V_MAD_F32 vDst(VGPR1220) src0(VGPR1217) src1(VGPR1211) src2(VGPR1220) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1221) src0(VGPR1212) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1221) src0(VGPR1215) src1(VGPR1221) // VOP2 V_MAD_F32 vDst(VGPR1221) src0(VGPR1218) src1(VGPR1212) src2(VGPR1221) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1222) src0(VGPR1213) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1222) src0(VGPR1216) src1(VGPR1222) // VOP2 V_MAD_F32 vDst(VGPR1222) src0(VGPR1219) src1(VGPR1213) src2(VGPR1222) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1049 >> chocolour V_MOV_B32 vDst(VGPR1016) src0(VGPR1220) V_MOV_B32 vDst(VGPR1017) src0(VGPR1221) V_MOV_B32 vDst(VGPR1018) src0(VGPR1222) # OpBranch: to lb997 # lb997 Label: lb997 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR330) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR296) # 1050: OpLoad: FloatVector3: tmp1050 << chocolour # 1051: OpVectorTimesScalar: FloatVector3: tmp1051 << tmp1050, const576 V_MOV_B32 vDst(VGPR1226) src0(LITERAL_CONST) const: 0x3dcccccd V_MUL_F32 vDst(VGPR1223) src0(VGPR1226) src1(VGPR1016) // VOP2 V_MUL_F32 vDst(VGPR1224) src0(VGPR1226) src1(VGPR1017) // VOP2 V_MUL_F32 vDst(VGPR1225) src0(VGPR1226) src1(VGPR1018) // VOP2 # 1053: OpLoad: FloatVector3: tmp1053 << l # 1054: OpDot: Float: tmp1054 << tmp978, tmp1053 V_MUL_F32 vDst(VGPR1227) src0(VGPR1115) src1(VGPR37) // VOP2 V_MAC_F32 vDst(VGPR1227) src0(VGPR1116) src1(VGPR38) // VOP2 V_MAC_F32 vDst(VGPR1227) src0(VGPR1117) src1(VGPR39) // VOP2 # 1055: OpFMul: Float: tmp1055 << const303, tmp1054 V_MUL_F32 vDst(VGPR1228) src0(0_5_F) src1(VGPR1227) // VOP2 # 1056: OpFAdd: Float: tmp1056 << const303, tmp1055 V_ADD_F32 vDst(VGPR1229) src0(0_5_F) src1(VGPR1228) // VOP2 # 1057: OpCompositeConstruct: FloatVector3: tmp1057 << tmp1056, tmp1056, tmp1056 V_MOV_B32 vDst(VGPR1230) src0(VGPR1229) V_MOV_B32 vDst(VGPR1231) src0(VGPR1229) V_MOV_B32 vDst(VGPR1232) src0(VGPR1229) # 1058: OpFMul: FloatVector3: tmp1058 << tmp1051, tmp1057 V_MUL_F32 vDst(VGPR1233) src0(VGPR1223) src1(VGPR1230) // VOP2 V_MUL_F32 vDst(VGPR1234) src0(VGPR1224) src1(VGPR1231) // VOP2 V_MUL_F32 vDst(VGPR1235) src0(VGPR1225) src1(VGPR1232) // VOP2 # 1062: OpDot: Float: tmp1062 << tmp985, tmp978 V_MUL_F32 vDst(VGPR1236) src0(VGPR1128) src1(VGPR1115) // VOP2 V_MAC_F32 vDst(VGPR1236) src0(VGPR1129) src1(VGPR1116) // VOP2 V_MAC_F32 vDst(VGPR1236) src0(VGPR1130) src1(VGPR1117) // VOP2 # 1063: OpFMul: Float: tmp1063 << const303, tmp1062 V_MUL_F32 vDst(VGPR1237) src0(0_5_F) src1(VGPR1236) // VOP2 # 1064: OpFAdd: Float: tmp1064 << const303, tmp1063 V_ADD_F32 vDst(VGPR1238) src0(0_5_F) src1(VGPR1237) // VOP2 # 1065: OpExtInst(FClamp): Float: tmp1065 << tmp1064, const100, const106 V_MOV_B32 vDst(VGPR1239) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1240) src0(1_0_F) V_MAX_F32 vDst(VGPR1241) src0(VGPR1238) src1(VGPR1239) // VOP2 V_MIN_F32 vDst(VGPR1241) src0(VGPR1241) src1(VGPR1240) // VOP2 # 1066: OpExtInst(Pow): Float: tmp1066 << tmp1065, const863 V_MOV_B32 vDst(VGPR1242) src0(LITERAL_CONST) const: 0x41a00000 V_LOG_F32 vDst(VGPR1243) src0(VGPR1241) V_MUL_F32 vDst(VGPR1243) src0(VGPR1242) src1(VGPR1243) // VOP2 V_EXP_F32 vDst(VGPR1243) src0(VGPR1243) # 1067: OpCompositeConstruct: FloatVector3: tmp1067 << tmp1066, tmp1066, tmp1066 V_MOV_B32 vDst(VGPR1244) src0(VGPR1243) V_MOV_B32 vDst(VGPR1245) src0(VGPR1243) V_MOV_B32 vDst(VGPR1246) src0(VGPR1243) # 1068: OpFMul: FloatVector3: tmp1068 << const1059, tmp1067 V_MOV_B32 vDst(VGPR1247) src0(LITERAL_CONST) const: 0x3d75c28f V_MOV_B32 vDst(VGPR1248) src0(LITERAL_CONST) const: 0x3d75c28f V_MOV_B32 vDst(VGPR1249) src0(LITERAL_CONST) const: 0x3cf5c28f V_MUL_F32 vDst(VGPR1250) src0(VGPR1247) src1(VGPR1244) // VOP2 V_MUL_F32 vDst(VGPR1251) src0(VGPR1248) src1(VGPR1245) // VOP2 V_MUL_F32 vDst(VGPR1252) src0(VGPR1249) src1(VGPR1246) // VOP2 # 1069: OpFAdd: FloatVector3: tmp1069 << tmp1058, tmp1068 V_ADD_F32 vDst(VGPR1253) src0(VGPR1233) src1(VGPR1250) // VOP2 V_ADD_F32 vDst(VGPR1254) src0(VGPR1234) src1(VGPR1251) // VOP2 V_ADD_F32 vDst(VGPR1255) src0(VGPR1235) src1(VGPR1252) // VOP2 # 1071: OpLoad: FloatVector3: tmp1071 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR292) const: 0x0 V_MOVRELS_B32 vDst(VGPR1256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1257) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1258) src0(VGPR2) # 1072: OpFNegate: FloatVector3: tmp1072 << tmp1071 V_MUL_F32 vDst(VGPR1259) src0(M1_0_F) src1(VGPR1256) // VOP2 V_MUL_F32 vDst(VGPR1260) src0(M1_0_F) src1(VGPR1257) // VOP2 V_MUL_F32 vDst(VGPR1261) src0(M1_0_F) src1(VGPR1258) // VOP2 # 1073: OpDot: Float: tmp1073 << tmp978, tmp1072 V_MUL_F32 vDst(VGPR1262) src0(VGPR1115) src1(VGPR1259) // VOP2 V_MAC_F32 vDst(VGPR1262) src0(VGPR1116) src1(VGPR1260) // VOP2 V_MAC_F32 vDst(VGPR1262) src0(VGPR1117) src1(VGPR1261) // VOP2 # 1074: OpExtInst(Pow): Float: tmp1074 << tmp1073, const127 V_MOV_B32 vDst(VGPR1263) src0(2_0_F) V_LOG_F32 vDst(VGPR1264) src0(VGPR1262) V_MUL_F32 vDst(VGPR1264) src0(VGPR1263) src1(VGPR1264) // VOP2 V_EXP_F32 vDst(VGPR1264) src0(VGPR1264) # 1075: OpFMul: Float: tmp1075 << const704, tmp1074 V_MOV_B32 vDst(VGPR1265) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR1266) src0(VGPR1265) src1(VGPR1264) // VOP2 # 1076: OpFAdd: Float: tmp1076 << const106, tmp1075 V_ADD_F32 vDst(VGPR1267) src0(1_0_F) src1(VGPR1266) // VOP2 # 1077: OpVectorTimesScalar: FloatVector3: tmp1077 << tmp1069, tmp1076 V_MUL_F32 vDst(VGPR1268) src0(VGPR1267) src1(VGPR1253) // VOP2 V_MUL_F32 vDst(VGPR1269) src0(VGPR1267) src1(VGPR1254) // VOP2 V_MUL_F32 vDst(VGPR1270) src0(VGPR1267) src1(VGPR1255) // VOP2 # OpStore: : tmp1077 >> col V_MOV_B32 vDst(VGPR1001) src0(VGPR1268) V_MOV_B32 vDst(VGPR1002) src0(VGPR1269) V_MOV_B32 vDst(VGPR1003) src0(VGPR1270) # OpBranch: to lb989 # lb1078 Label: lb1078 S_ANDN2_B64 sDst(EXEC) src0(SGPR326) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR296) src1(EXEC) S_CBRANCH_EXECZ ??? lb989 # OpStore: : tmp978 >> param1079 V_MOV_B32 vDst(VGPR1022) src0(VGPR1115) V_MOV_B32 vDst(VGPR1023) src0(VGPR1116) V_MOV_B32 vDst(VGPR1024) src0(VGPR1117) # OpStore: : tmp943 >> param1081 V_MOV_B32 vDst(VGPR1025) src0(VGPR1071) V_MOV_B32 vDst(VGPR1026) src0(VGPR1072) V_MOV_B32 vDst(VGPR1027) src0(VGPR1073) # OpStore: : tmp980 >> param1083 V_MOV_B32 vDst(VGPR1028) src0(VGPR1118) V_MOV_B32 vDst(VGPR1029) src0(VGPR1119) V_MOV_B32 vDst(VGPR1030) src0(VGPR1120) # 1085: OpFunctionCall: FloatVector3: gummy(vf3;vf3;vf3;(param1079, param1081, param1083) S_ADD_U32 sDst(SGPR193) src0(LITERAL_CONST) src1(0) const: 0x3fe # VGPR[1022:1024] S_ADD_U32 sDst(SGPR194) src0(LITERAL_CONST) src1(0) const: 0x401 # VGPR[1025:1027] S_ADD_U32 sDst(SGPR195) src0(LITERAL_CONST) src1(0) const: 0x404 # VGPR[1028:1030] S_MOV_B64 sDst(SGPR342) src0(EXEC) S_MOV_B32 sDst(SGPR192) src0(LITERAL_CONST) const: 0x4f7 # VGPR[1271:1273] # Indirect branch to gummy(vf3;vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR190) src0(SGPR190) S_ADD_U32 sDst(SGPR190) src0(SGPR190) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR191) src0(SGPR191) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR190) src0(SGPR190) S_MOV_B64 sDst(EXEC) src0(SGPR342) # .lbl103 # 1086: OpVectorTimesScalar: FloatVector3: tmp1086 << gummy(vf3;vf3;vf3;, const401 V_MOV_B32 vDst(VGPR1277) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR1274) src0(VGPR1277) src1(VGPR1271) // VOP2 V_MUL_F32 vDst(VGPR1275) src0(VGPR1277) src1(VGPR1272) // VOP2 V_MUL_F32 vDst(VGPR1276) src0(VGPR1277) src1(VGPR1273) // VOP2 # 1089: OpDot: Float: tmp1089 << tmp985, tmp978 V_MUL_F32 vDst(VGPR1278) src0(VGPR1128) src1(VGPR1115) // VOP2 V_MAC_F32 vDst(VGPR1278) src0(VGPR1129) src1(VGPR1116) // VOP2 V_MAC_F32 vDst(VGPR1278) src0(VGPR1130) src1(VGPR1117) // VOP2 # 1090: OpFMul: Float: tmp1090 << const303, tmp1089 V_MUL_F32 vDst(VGPR1279) src0(0_5_F) src1(VGPR1278) // VOP2 # 1091: OpFAdd: Float: tmp1091 << const303, tmp1090 V_ADD_F32 vDst(VGPR1280) src0(0_5_F) src1(VGPR1279) // VOP2 # 1092: OpExtInst(FClamp): Float: tmp1092 << tmp1091, const100, const106 V_MOV_B32 vDst(VGPR1281) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1282) src0(1_0_F) V_MAX_F32 vDst(VGPR1283) src0(VGPR1280) src1(VGPR1281) // VOP2 V_MIN_F32 vDst(VGPR1283) src0(VGPR1283) src1(VGPR1282) // VOP2 # 1094: OpExtInst(Pow): Float: tmp1094 << tmp1092, const1093 V_MOV_B32 vDst(VGPR1284) src0(LITERAL_CONST) const: 0x43800000 V_LOG_F32 vDst(VGPR1285) src0(VGPR1283) V_MUL_F32 vDst(VGPR1285) src0(VGPR1284) src1(VGPR1285) // VOP2 V_EXP_F32 vDst(VGPR1285) src0(VGPR1285) # 1095: OpExtInst(SmoothStep): Float: tmp1095 << const303, const704, tmp1094 V_MOV_B32 vDst(VGPR1286) src0(LITERAL_CONST) const: 0x3f19999a V_CMP_GE_F32 src0(0_5_F) src1(VGPR1285) # CF Block: Merge: .lbl107 S_MOV_B64 sDst(SGPR344) src0(EXEC) # CF Block: Cond Branch: true: .lbl108, false: .lbl104 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl104 Label: .lbl108 V_MOV_B32 vDst(VGPR1287) src0(0) Label: .lbl104 S_ANDN2_B64 sDst(EXEC) src0(SGPR344) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR296) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl107 V_CMP_LE_F32 src0(VGPR1286) src1(VGPR1285) # CF Block: Merge: .lbl106 S_MOV_B64 sDst(SGPR346) src0(EXEC) # CF Block: Cond Branch: true: .lbl109, false: .lbl105 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl105 Label: .lbl109 V_MOV_B32 vDst(VGPR1287) src0(1_0_F) Label: .lbl105 S_ANDN2_B64 sDst(EXEC) src0(SGPR346) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR296) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl106 V_SUBREV_F32 vDst(VGPR1288) src0(0_5_F) src1(VGPR1286) // VOP2 V_RCP_F32 vDst(VGPR1288) src0(VGPR1288) V_SUBREV_F32 vDst(VGPR1287) src0(0_5_F) src1(VGPR1285) // VOP2 V_MUL_F32 vDst(VGPR1288) src0(VGPR1287) src1(VGPR1288) // VOP2 V_MAX_F32 vDst(VGPR1288) src0(0) src1(VGPR1288) // VOP2 V_MIN_F32 vDst(VGPR1288) src0(1_0_F) src1(VGPR1288) // VOP2 V_MOV_B32 vDst(VGPR1287) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1287) src0(2_0_F) src1(VGPR1288) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1288) src0(VGPR1288) src1(VGPR1288) // VOP2 V_MUL_F32 vDst(VGPR1287) src0(VGPR1288) src1(VGPR1287) // VOP2 Label: .lbl106 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR346) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR296) Label: .lbl107 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR344) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR296) # 1096: OpCompositeConstruct: FloatVector3: tmp1096 << tmp1095, tmp1095, tmp1095 V_MOV_B32 vDst(VGPR1289) src0(VGPR1287) V_MOV_B32 vDst(VGPR1290) src0(VGPR1287) V_MOV_B32 vDst(VGPR1291) src0(VGPR1287) # 1097: OpVectorTimesScalar: FloatVector3: tmp1097 << tmp1096, const576 V_MOV_B32 vDst(VGPR1295) src0(LITERAL_CONST) const: 0x3dcccccd V_MUL_F32 vDst(VGPR1292) src0(VGPR1295) src1(VGPR1289) // VOP2 V_MUL_F32 vDst(VGPR1293) src0(VGPR1295) src1(VGPR1290) // VOP2 V_MUL_F32 vDst(VGPR1294) src0(VGPR1295) src1(VGPR1291) // VOP2 # 1098: OpFAdd: FloatVector3: tmp1098 << tmp1086, tmp1097 V_ADD_F32 vDst(VGPR1296) src0(VGPR1274) src1(VGPR1292) // VOP2 V_ADD_F32 vDst(VGPR1297) src0(VGPR1275) src1(VGPR1293) // VOP2 V_ADD_F32 vDst(VGPR1298) src0(VGPR1276) src1(VGPR1294) // VOP2 # OpStore: : tmp1098 >> col V_MOV_B32 vDst(VGPR1001) src0(VGPR1296) V_MOV_B32 vDst(VGPR1002) src0(VGPR1297) V_MOV_B32 vDst(VGPR1003) src0(VGPR1298) # OpBranch: to lb989 # lb989 Label: lb989 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR326) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR296) # 1099: OpAccessChain: Float*: rp[1] # 1100: OpCompositeExtract: Float: tmp1100 << tmp943, 1 V_MOV_B32 vDst(VGPR1299) src0(VGPR1072) # 1101: OpExtInst(FMax): Float: tmp1101 << const100, tmp1100 V_MOV_B32 vDst(VGPR1300) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR1301) src0(VGPR1300) src1(VGPR1299) // VOP2 # 1102: OpExtInst(Pow): Float: tmp1102 << tmp1101, const303 V_MOV_B32 vDst(VGPR1302) src0(0_5_F) V_LOG_F32 vDst(VGPR1303) src0(VGPR1301) V_MUL_F32 vDst(VGPR1303) src0(VGPR1302) src1(VGPR1303) // VOP2 V_EXP_F32 vDst(VGPR1303) src0(VGPR1303) # 1103: OpExtInst(FMix): Float: tmp1103 << const106, tmp1102, const704 V_MOV_B32 vDst(VGPR1304) src0(LITERAL_CONST) const: 0x3f19999a V_SUBREV_F32 vDst(VGPR1305) src0(VGPR1304) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1305) src0(1_0_F) src1(VGPR1305) // VOP2 V_MAD_F32 vDst(VGPR1305) src0(VGPR1303) src1(VGPR1304) src2(VGPR1305) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1104: OpLoad: FloatVector3: tmp1104 << col # 1105: OpVectorTimesScalar: FloatVector3: tmp1105 << tmp1104, tmp1103 V_MUL_F32 vDst(VGPR1306) src0(VGPR1305) src1(VGPR1001) // VOP2 V_MUL_F32 vDst(VGPR1307) src0(VGPR1305) src1(VGPR1002) // VOP2 V_MUL_F32 vDst(VGPR1308) src0(VGPR1305) src1(VGPR1003) // VOP2 # OpStore: : tmp1105 >> col V_MOV_B32 vDst(VGPR1001) src0(VGPR1306) V_MOV_B32 vDst(VGPR1002) src0(VGPR1307) V_MOV_B32 vDst(VGPR1003) src0(VGPR1308) # 1106: OpLoad: FloatVector3: tmp1106 << col # OpReturnValue: : << tmp1106 S_MOV_B32 sDst(M0) src0(SGPR290) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1001) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1002) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1003) S_SETPC_B64 sDst(SGPR288) src0(SGPR288) # Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) Function: Void mainImage(vf4;vf2;(, FloatVector2 main.fragCoord) S_MOV_B64 sDst(SGPR348) src0(EXEC) # lb97 Label: lb97 # 1111: OpLoad: Float: tmp1111 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR350) S_WAITCNT 0 # OpStore: : tmp1111 >> time V_MOV_B32 vDst(VGPR28) src0(SGPR350) # 1112: OpLoad: FloatVector2: tmp1112 << fragCoord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR13) const: 0x0 V_MOVRELS_B32 vDst(VGPR1350) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1351) src0(VGPR1) # 1115: OpLoad: FloatVector3: tmp1115 << iResolution S_LOAD_DWORDX2_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR[352:353]) S_WAITCNT 0 S_LOAD_DWORD_IMM offset(12) sBase(SGPR[0:1]) sDst(SGPR354) S_WAITCNT 0 # 1116: OpVectorShuffle: FloatVector2: tmp1116 << tmp1115, tmp1115, 0, 1 V_MOV_B32 vDst(VGPR1352) src0(SGPR352) V_MOV_B32 vDst(VGPR1353) src0(SGPR353) # 1117: OpFDiv: FloatVector2: tmp1117 << tmp1112, tmp1116 V_RCP_F32 vDst(VGPR1354) src0(VGPR1352) V_RCP_F32 vDst(VGPR1355) src0(VGPR1353) V_MUL_F32 vDst(VGPR1354) src0(VGPR1350) src1(VGPR1354) // VOP2 V_MUL_F32 vDst(VGPR1355) src0(VGPR1351) src1(VGPR1355) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1354) src0(VGPR1354) src1(VGPR1352) src2(VGPR1350) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR1355) src0(VGPR1355) src1(VGPR1353) src2(VGPR1351) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1118: OpVectorTimesScalar: FloatVector2: tmp1118 << tmp1117, const127 V_MOV_B32 vDst(VGPR1358) src0(2_0_F) V_MUL_F32 vDst(VGPR1356) src0(VGPR1358) src1(VGPR1354) // VOP2 V_MUL_F32 vDst(VGPR1357) src0(VGPR1358) src1(VGPR1355) // VOP2 # 1119: OpFSub: FloatVector2: tmp1119 << tmp1118, const342 V_MOV_B32 vDst(VGPR1359) src0(1_0_F) V_MOV_B32 vDst(VGPR1360) src0(1_0_F) V_SUB_F32 vDst(VGPR1361) src0(VGPR1356) src1(VGPR1359) // VOP2 V_SUB_F32 vDst(VGPR1362) src0(VGPR1357) src1(VGPR1360) // VOP2 # OpStore: : tmp1119 >> tc V_MOV_B32 vDst(VGPR24) src0(VGPR1361) V_MOV_B32 vDst(VGPR25) src0(VGPR1362) # 1121: OpLoad: Float: tmp1121 << time # 1122: OpLoad: Float: tmp1122 << t_per_target # 1123: OpFDiv: Float: tmp1123 << tmp1121, tmp1122 V_RCP_F32 vDst(VGPR1363) src0(VGPR35) V_MUL_F32 vDst(VGPR1363) src0(VGPR28) src1(VGPR1363) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1363) src0(VGPR1363) src1(VGPR35) src2(VGPR28) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1124: OpExtInst(Floor): Float: tmp1124 << tmp1123 V_FLOOR_F32 vDst(VGPR1364) src0(VGPR1363) # 1126: OpLoad: Float: tmp1126 << time # 1127: OpLoad: Float: tmp1127 << t_per_target # 1128: OpFDiv: Float: tmp1128 << tmp1126, tmp1127 V_RCP_F32 vDst(VGPR1365) src0(VGPR35) V_MUL_F32 vDst(VGPR1365) src0(VGPR28) src1(VGPR1365) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1365) src0(VGPR1365) src1(VGPR35) src2(VGPR28) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1129: OpExtInst(Fract): Float: tmp1129 << tmp1128 V_FRACT_F32 vDst(VGPR1366) src0(VGPR1365) # 1132: OpLoad: Float: tmp1132 << time # OpStore: : tmp1132 >> param1131 V_MOV_B32 vDst(VGPR1309) src0(VGPR28) # 1133: OpFunctionCall: FloatVector3: cameraPos(f1;(param1131) S_ADD_U32 sDst(SGPR271) src0(LITERAL_CONST) src1(0) const: 0x51d # VGPR1309 S_MOV_B64 sDst(SGPR356) src0(EXEC) S_MOV_B32 sDst(SGPR270) src0(LITERAL_CONST) const: 0x557 # VGPR[1367:1369] # Indirect branch to cameraPos(f1;: ??? S_GETPC_B64 sDst(SGPR268) src0(SGPR268) S_ADD_U32 sDst(SGPR268) src0(SGPR268) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR269) src0(SGPR269) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR268) src0(SGPR268) S_MOV_B64 sDst(EXEC) src0(SGPR356) # .lbl110 # 1136: OpFSub: Float: tmp1136 << tmp1124, const106 V_MOV_B32 vDst(VGPR1370) src0(1_0_F) V_SUB_F32 vDst(VGPR1371) src0(VGPR1364) src1(VGPR1370) // VOP2 # OpStore: : tmp1136 >> param1137 V_MOV_B32 vDst(VGPR1310) src0(VGPR1371) # 1138: OpFunctionCall: FloatVector3: targetPos(f1;(param1137) S_ADD_U32 sDst(SGPR277) src0(LITERAL_CONST) src1(0) const: 0x51e # VGPR1310 S_MOV_B64 sDst(SGPR358) src0(EXEC) S_MOV_B32 sDst(SGPR276) src0(LITERAL_CONST) const: 0x55c # VGPR[1372:1374] # Indirect branch to targetPos(f1;: ??? S_GETPC_B64 sDst(SGPR274) src0(SGPR274) S_ADD_U32 sDst(SGPR274) src0(SGPR274) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR275) src0(SGPR275) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR274) src0(SGPR274) S_MOV_B64 sDst(EXEC) src0(SGPR358) # .lbl111 # OpStore: : tmp1124 >> param1139 V_MOV_B32 vDst(VGPR1311) src0(VGPR1364) # 1141: OpFunctionCall: FloatVector3: targetPos(f1;(param1139) S_ADD_U32 sDst(SGPR277) src0(LITERAL_CONST) src1(0) const: 0x51f # VGPR1311 S_MOV_B64 sDst(SGPR360) src0(EXEC) S_MOV_B32 sDst(SGPR276) src0(LITERAL_CONST) const: 0x55f # VGPR[1375:1377] # Indirect branch to targetPos(f1;: ??? S_GETPC_B64 sDst(SGPR274) src0(SGPR274) S_ADD_U32 sDst(SGPR274) src0(SGPR274) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR275) src0(SGPR275) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR274) src0(SGPR274) S_MOV_B64 sDst(EXEC) src0(SGPR360) # .lbl112 # 1143: OpExtInst(SmoothStep): Float: tmp1143 << const523, const671, tmp1129 V_MOV_B32 vDst(VGPR1378) src0(LITERAL_CONST) const: 0x3e99999a V_MOV_B32 vDst(VGPR1379) src0(LITERAL_CONST) const: 0x3f333333 V_CMP_GE_F32 src0(VGPR1378) src1(VGPR1366) # CF Block: Merge: .lbl116 S_MOV_B64 sDst(SGPR362) src0(EXEC) # CF Block: Cond Branch: true: .lbl117, false: .lbl113 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl113 Label: .lbl117 V_MOV_B32 vDst(VGPR1380) src0(0) Label: .lbl113 S_ANDN2_B64 sDst(EXEC) src0(SGPR362) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl116 V_CMP_LE_F32 src0(VGPR1379) src1(VGPR1366) # CF Block: Merge: .lbl115 S_MOV_B64 sDst(SGPR364) src0(EXEC) # CF Block: Cond Branch: true: .lbl118, false: .lbl114 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl114 Label: .lbl118 V_MOV_B32 vDst(VGPR1380) src0(1_0_F) Label: .lbl114 S_ANDN2_B64 sDst(EXEC) src0(SGPR364) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl115 V_SUBREV_F32 vDst(VGPR1381) src0(VGPR1378) src1(VGPR1379) // VOP2 V_RCP_F32 vDst(VGPR1381) src0(VGPR1381) V_SUBREV_F32 vDst(VGPR1380) src0(VGPR1378) src1(VGPR1366) // VOP2 V_MUL_F32 vDst(VGPR1381) src0(VGPR1380) src1(VGPR1381) // VOP2 V_MAX_F32 vDst(VGPR1381) src0(0) src1(VGPR1381) // VOP2 V_MIN_F32 vDst(VGPR1381) src0(1_0_F) src1(VGPR1381) // VOP2 V_MOV_B32 vDst(VGPR1380) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1380) src0(2_0_F) src1(VGPR1381) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1381) src0(VGPR1381) src1(VGPR1381) // VOP2 V_MUL_F32 vDst(VGPR1380) src0(VGPR1381) src1(VGPR1380) // VOP2 Label: .lbl115 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR364) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) Label: .lbl116 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR362) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) # 1144: OpCompositeConstruct: FloatVector3: tmp1144 << tmp1143, tmp1143, tmp1143 V_MOV_B32 vDst(VGPR1382) src0(VGPR1380) V_MOV_B32 vDst(VGPR1383) src0(VGPR1380) V_MOV_B32 vDst(VGPR1384) src0(VGPR1380) # 1145: OpExtInst(FMix): FloatVector3: tmp1145 << targetPos(f1;, targetPos(f1;, tmp1144 V_SUBREV_F32 vDst(VGPR1385) src0(VGPR1382) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1385) src0(VGPR1372) src1(VGPR1385) // VOP2 V_MAD_F32 vDst(VGPR1385) src0(VGPR1375) src1(VGPR1382) src2(VGPR1385) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1386) src0(VGPR1383) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1386) src0(VGPR1373) src1(VGPR1386) // VOP2 V_MAD_F32 vDst(VGPR1386) src0(VGPR1376) src1(VGPR1383) src2(VGPR1386) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1387) src0(VGPR1384) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1387) src0(VGPR1374) src1(VGPR1387) // VOP2 V_MAD_F32 vDst(VGPR1387) src0(VGPR1377) src1(VGPR1384) src2(VGPR1387) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1149: OpFSub: FloatVector3: tmp1149 << tmp1145, cameraPos(f1; V_SUB_F32 vDst(VGPR1388) src0(VGPR1385) src1(VGPR1367) // VOP2 V_SUB_F32 vDst(VGPR1389) src0(VGPR1386) src1(VGPR1368) // VOP2 V_SUB_F32 vDst(VGPR1390) src0(VGPR1387) src1(VGPR1369) // VOP2 # 1150: OpExtInst(Normalize): FloatVector3: tmp1150 << tmp1149 V_MUL_F32 vDst(VGPR1391) src0(VGPR1388) src1(VGPR1388) // VOP2 V_MAC_F32 vDst(VGPR1391) src0(VGPR1389) src1(VGPR1389) // VOP2 V_MAC_F32 vDst(VGPR1391) src0(VGPR1390) src1(VGPR1390) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1391) src0(VGPR1391) V_MUL_F32 vDst(VGPR1392) src0(VGPR1388) src1(VGPR1391) // VOP2 V_MUL_F32 vDst(VGPR1393) src0(VGPR1389) src1(VGPR1391) // VOP2 V_MUL_F32 vDst(VGPR1394) src0(VGPR1390) src1(VGPR1391) // VOP2 # 1154: OpExtInst(Cross): FloatVector3: tmp1154 << tmp1150, const1153 V_MOV_B32 vDst(VGPR1395) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1396) src0(1_0_F) V_MOV_B32 vDst(VGPR1397) src0(LITERAL_CONST) const: 0x00000000 V_MUL_F32 vDst(VGPR1398) src0(VGPR1393) src1(VGPR1397) // VOP2 V_MUL_F32 vDst(VGPR1399) src0(VGPR1394) src1(VGPR1395) // VOP2 V_MUL_F32 vDst(VGPR1400) src0(VGPR1392) src1(VGPR1396) // VOP2 V_MAC_F32 vDst(VGPR1398) src0(VGPR1394) src1(VGPR1396) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1399) src0(VGPR1392) src1(VGPR1397) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1400) src0(VGPR1393) src1(VGPR1395) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 1155: OpExtInst(Normalize): FloatVector3: tmp1155 << tmp1154 V_MUL_F32 vDst(VGPR1401) src0(VGPR1398) src1(VGPR1398) // VOP2 V_MAC_F32 vDst(VGPR1401) src0(VGPR1399) src1(VGPR1399) // VOP2 V_MAC_F32 vDst(VGPR1401) src0(VGPR1400) src1(VGPR1400) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1401) src0(VGPR1401) V_MUL_F32 vDst(VGPR1402) src0(VGPR1398) src1(VGPR1401) // VOP2 V_MUL_F32 vDst(VGPR1403) src0(VGPR1399) src1(VGPR1401) // VOP2 V_MUL_F32 vDst(VGPR1404) src0(VGPR1400) src1(VGPR1401) // VOP2 # OpStore: : tmp1155 >> camu V_MOV_B32 vDst(VGPR1312) src0(VGPR1402) V_MOV_B32 vDst(VGPR1313) src0(VGPR1403) V_MOV_B32 vDst(VGPR1314) src0(VGPR1404) # 1157: OpLoad: FloatVector3: tmp1157 << camu # 1159: OpExtInst(Cross): FloatVector3: tmp1159 << tmp1157, tmp1150 V_MUL_F32 vDst(VGPR1405) src0(VGPR1313) src1(VGPR1394) // VOP2 V_MUL_F32 vDst(VGPR1406) src0(VGPR1314) src1(VGPR1392) // VOP2 V_MUL_F32 vDst(VGPR1407) src0(VGPR1312) src1(VGPR1393) // VOP2 V_MAC_F32 vDst(VGPR1405) src0(VGPR1314) src1(VGPR1393) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1406) src0(VGPR1312) src1(VGPR1394) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1407) src0(VGPR1313) src1(VGPR1392) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 1160: OpExtInst(Normalize): FloatVector3: tmp1160 << tmp1159 V_MUL_F32 vDst(VGPR1408) src0(VGPR1405) src1(VGPR1405) // VOP2 V_MAC_F32 vDst(VGPR1408) src0(VGPR1406) src1(VGPR1406) // VOP2 V_MAC_F32 vDst(VGPR1408) src0(VGPR1407) src1(VGPR1407) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1408) src0(VGPR1408) V_MUL_F32 vDst(VGPR1409) src0(VGPR1405) src1(VGPR1408) // VOP2 V_MUL_F32 vDst(VGPR1410) src0(VGPR1406) src1(VGPR1408) // VOP2 V_MUL_F32 vDst(VGPR1411) src0(VGPR1407) src1(VGPR1408) // VOP2 # 1163: OpExtInst(Cross): FloatVector3: tmp1163 << tmp1150, tmp1160 V_MUL_F32 vDst(VGPR1412) src0(VGPR1393) src1(VGPR1411) // VOP2 V_MUL_F32 vDst(VGPR1413) src0(VGPR1394) src1(VGPR1409) // VOP2 V_MUL_F32 vDst(VGPR1414) src0(VGPR1392) src1(VGPR1410) // VOP2 V_MAC_F32 vDst(VGPR1412) src0(VGPR1394) src1(VGPR1410) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1413) src0(VGPR1392) src1(VGPR1411) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR1414) src0(VGPR1393) src1(VGPR1409) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 1164: OpExtInst(Normalize): FloatVector3: tmp1164 << tmp1163 V_MUL_F32 vDst(VGPR1415) src0(VGPR1412) src1(VGPR1412) // VOP2 V_MAC_F32 vDst(VGPR1415) src0(VGPR1413) src1(VGPR1413) // VOP2 V_MAC_F32 vDst(VGPR1415) src0(VGPR1414) src1(VGPR1414) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1415) src0(VGPR1415) V_MUL_F32 vDst(VGPR1416) src0(VGPR1412) src1(VGPR1415) // VOP2 V_MUL_F32 vDst(VGPR1417) src0(VGPR1413) src1(VGPR1415) // VOP2 V_MUL_F32 vDst(VGPR1418) src0(VGPR1414) src1(VGPR1415) // VOP2 # OpStore: : tmp1164 >> camu V_MOV_B32 vDst(VGPR1312) src0(VGPR1416) V_MOV_B32 vDst(VGPR1313) src0(VGPR1417) V_MOV_B32 vDst(VGPR1314) src0(VGPR1418) # 1168: OpLoad: FloatVector3: tmp1168 << camu # 1171: OpCompositeExtract: Float: tmp1171 << tmp1168, 0 V_MOV_B32 vDst(VGPR1419) src0(VGPR1312) # 1172: OpCompositeExtract: Float: tmp1172 << tmp1168, 1 V_MOV_B32 vDst(VGPR1420) src0(VGPR1313) # 1173: OpCompositeExtract: Float: tmp1173 << tmp1168, 2 V_MOV_B32 vDst(VGPR1421) src0(VGPR1314) # 1174: OpCompositeExtract: Float: tmp1174 << tmp1160, 0 V_MOV_B32 vDst(VGPR1422) src0(VGPR1409) # 1175: OpCompositeExtract: Float: tmp1175 << tmp1160, 1 V_MOV_B32 vDst(VGPR1423) src0(VGPR1410) # 1176: OpCompositeExtract: Float: tmp1176 << tmp1160, 2 V_MOV_B32 vDst(VGPR1424) src0(VGPR1411) # 1177: OpCompositeExtract: Float: tmp1177 << tmp1150, 0 V_MOV_B32 vDst(VGPR1425) src0(VGPR1392) # 1178: OpCompositeExtract: Float: tmp1178 << tmp1150, 1 V_MOV_B32 vDst(VGPR1426) src0(VGPR1393) # 1179: OpCompositeExtract: Float: tmp1179 << tmp1150, 2 V_MOV_B32 vDst(VGPR1427) src0(VGPR1394) # 1180: OpCompositeConstruct: FloatVector3: tmp1180 << tmp1171, tmp1172, tmp1173 V_MOV_B32 vDst(VGPR1428) src0(VGPR1419) V_MOV_B32 vDst(VGPR1429) src0(VGPR1420) V_MOV_B32 vDst(VGPR1430) src0(VGPR1421) # 1181: OpCompositeConstruct: FloatVector3: tmp1181 << tmp1174, tmp1175, tmp1176 V_MOV_B32 vDst(VGPR1431) src0(VGPR1422) V_MOV_B32 vDst(VGPR1432) src0(VGPR1423) V_MOV_B32 vDst(VGPR1433) src0(VGPR1424) # 1182: OpCompositeConstruct: FloatVector3: tmp1182 << tmp1177, tmp1178, tmp1179 V_MOV_B32 vDst(VGPR1434) src0(VGPR1425) V_MOV_B32 vDst(VGPR1435) src0(VGPR1426) V_MOV_B32 vDst(VGPR1436) src0(VGPR1427) # 1183: OpCompositeConstruct: FloatMatrix3x3: tmp1183 << tmp1180, tmp1181, tmp1182 V_MOV_B32 vDst(VGPR1437) src0(VGPR1428) V_MOV_B32 vDst(VGPR1438) src0(VGPR1429) V_MOV_B32 vDst(VGPR1439) src0(VGPR1430) V_MOV_B32 vDst(VGPR1440) src0(VGPR1431) V_MOV_B32 vDst(VGPR1441) src0(VGPR1432) V_MOV_B32 vDst(VGPR1442) src0(VGPR1433) V_MOV_B32 vDst(VGPR1443) src0(VGPR1434) V_MOV_B32 vDst(VGPR1444) src0(VGPR1435) V_MOV_B32 vDst(VGPR1445) src0(VGPR1436) # 1185: OpLoad: FloatVector2: tmp1185 << tc # 1186: OpVectorTimesScalar: FloatVector2: tmp1186 << tmp1185, const303 V_MOV_B32 vDst(VGPR1448) src0(0_5_F) V_MUL_F32 vDst(VGPR1446) src0(VGPR1448) src1(VGPR24) // VOP2 V_MUL_F32 vDst(VGPR1447) src0(VGPR1448) src1(VGPR25) // VOP2 # 1187: OpFAdd: FloatVector2: tmp1187 << tmp1186, const391 V_MOV_B32 vDst(VGPR1449) src0(0_5_F) V_MOV_B32 vDst(VGPR1450) src0(0_5_F) V_ADD_F32 vDst(VGPR1451) src0(VGPR1446) src1(VGPR1449) // VOP2 V_ADD_F32 vDst(VGPR1452) src0(VGPR1447) src1(VGPR1450) // VOP2 # 1189: OpLoad: FloatVector2: tmp1189 << tc # OpStore: : tmp1189 >> p V_MOV_B32 vDst(VGPR1315) src0(VGPR24) V_MOV_B32 vDst(VGPR1316) src0(VGPR25) # 1192: OpAccessChain: Float*: iResolution[0] # 1193: OpLoad: Float: tmp1193 << iResolution[0] S_LOAD_DWORD_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR366) S_WAITCNT 0 # 1194: OpAccessChain: Float*: iResolution[1] # 1195: OpLoad: Float: tmp1195 << iResolution[1] S_LOAD_DWORD_IMM offset(8) sBase(SGPR[0:1]) sDst(SGPR367) S_WAITCNT 0 # 1196: OpFDiv: Float: tmp1196 << tmp1193, tmp1195 V_MOV_B32 vDst(VGPR1453) src0(SGPR367) V_RCP_F32 vDst(VGPR1454) src0(VGPR1453) V_MUL_F32 vDst(VGPR1454) src0(SGPR366) src1(VGPR1454) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1454) src0(VGPR1454) src1(VGPR1453) src2(SGPR366) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1197: OpAccessChain: Float*: p[0] # 1198: OpLoad: Float: tmp1198 << p[0] V_MOV_B32 vDst(VGPR1455) src0(VGPR1315) # 1199: OpFMul: Float: tmp1199 << tmp1198, tmp1196 V_MUL_F32 vDst(VGPR1456) src0(VGPR1455) src1(VGPR1454) // VOP2 # 1200: OpAccessChain: Float*: p[0] # OpStore: : tmp1199 >> p[0] V_MOV_B32 vDst(VGPR1315) src0(VGPR1456) # 1203: OpFSub: Float: tmp1203 << tmp1124, const106 V_MOV_B32 vDst(VGPR1457) src0(1_0_F) V_SUB_F32 vDst(VGPR1458) src0(VGPR1364) src1(VGPR1457) // VOP2 # OpStore: : tmp1203 >> param1204 V_MOV_B32 vDst(VGPR1317) src0(VGPR1458) # 1205: OpFunctionCall: Float: cameraZoom(f1;(param1204) S_ADD_U32 sDst(SGPR285) src0(LITERAL_CONST) src1(0) const: 0x525 # VGPR1317 S_MOV_B64 sDst(SGPR368) src0(EXEC) S_MOV_B32 sDst(SGPR284) src0(LITERAL_CONST) const: 0x5b3 # VGPR1459 # Indirect branch to cameraZoom(f1;: ??? S_GETPC_B64 sDst(SGPR282) src0(SGPR282) S_ADD_U32 sDst(SGPR282) src0(SGPR282) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR283) src0(SGPR283) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR282) src0(SGPR282) S_MOV_B64 sDst(EXEC) src0(SGPR368) # .lbl119 # OpStore: : tmp1124 >> param1206 V_MOV_B32 vDst(VGPR1318) src0(VGPR1364) # 1208: OpFunctionCall: Float: cameraZoom(f1;(param1206) S_ADD_U32 sDst(SGPR285) src0(LITERAL_CONST) src1(0) const: 0x526 # VGPR1318 S_MOV_B64 sDst(SGPR370) src0(EXEC) S_MOV_B32 sDst(SGPR284) src0(LITERAL_CONST) const: 0x5b4 # VGPR1460 # Indirect branch to cameraZoom(f1;: ??? S_GETPC_B64 sDst(SGPR282) src0(SGPR282) S_ADD_U32 sDst(SGPR282) src0(SGPR282) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR283) src0(SGPR283) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR282) src0(SGPR282) S_MOV_B64 sDst(EXEC) src0(SGPR370) # .lbl120 # 1210: OpExtInst(SmoothStep): Float: tmp1210 << const671, const435, tmp1129 V_MOV_B32 vDst(VGPR1461) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR1462) src0(LITERAL_CONST) const: 0x3f666666 V_CMP_GE_F32 src0(VGPR1461) src1(VGPR1366) # CF Block: Merge: .lbl124 S_MOV_B64 sDst(SGPR372) src0(EXEC) # CF Block: Cond Branch: true: .lbl125, false: .lbl121 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl121 Label: .lbl125 V_MOV_B32 vDst(VGPR1463) src0(0) Label: .lbl121 S_ANDN2_B64 sDst(EXEC) src0(SGPR372) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl124 V_CMP_LE_F32 src0(VGPR1462) src1(VGPR1366) # CF Block: Merge: .lbl123 S_MOV_B64 sDst(SGPR374) src0(EXEC) # CF Block: Cond Branch: true: .lbl126, false: .lbl122 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl122 Label: .lbl126 V_MOV_B32 vDst(VGPR1463) src0(1_0_F) Label: .lbl122 S_ANDN2_B64 sDst(EXEC) src0(SGPR374) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl123 V_SUBREV_F32 vDst(VGPR1464) src0(VGPR1461) src1(VGPR1462) // VOP2 V_RCP_F32 vDst(VGPR1464) src0(VGPR1464) V_SUBREV_F32 vDst(VGPR1463) src0(VGPR1461) src1(VGPR1366) // VOP2 V_MUL_F32 vDst(VGPR1464) src0(VGPR1463) src1(VGPR1464) // VOP2 V_MAX_F32 vDst(VGPR1464) src0(0) src1(VGPR1464) // VOP2 V_MIN_F32 vDst(VGPR1464) src0(1_0_F) src1(VGPR1464) // VOP2 V_MOV_B32 vDst(VGPR1463) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1463) src0(2_0_F) src1(VGPR1464) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1464) src0(VGPR1464) src1(VGPR1464) // VOP2 V_MUL_F32 vDst(VGPR1463) src0(VGPR1464) src1(VGPR1463) // VOP2 Label: .lbl123 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR374) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) Label: .lbl124 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR372) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) # 1211: OpExtInst(FMix): Float: tmp1211 << cameraZoom(f1;, cameraZoom(f1;, tmp1210 V_SUBREV_F32 vDst(VGPR1465) src0(VGPR1463) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1465) src0(VGPR1459) src1(VGPR1465) // VOP2 V_MAD_F32 vDst(VGPR1465) src0(VGPR1460) src1(VGPR1463) src2(VGPR1465) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1214: OpLoad: FloatVector2: tmp1214 << p # 1216: OpCompositeExtract: Float: tmp1216 << tmp1214, 0 V_MOV_B32 vDst(VGPR1466) src0(VGPR1315) # 1217: OpCompositeExtract: Float: tmp1217 << tmp1214, 1 V_MOV_B32 vDst(VGPR1467) src0(VGPR1316) # 1218: OpCompositeConstruct: FloatVector3: tmp1218 << tmp1216, tmp1217, tmp1211 V_MOV_B32 vDst(VGPR1468) src0(VGPR1466) V_MOV_B32 vDst(VGPR1469) src0(VGPR1467) V_MOV_B32 vDst(VGPR1470) src0(VGPR1465) # 1219: OpExtInst(Normalize): FloatVector3: tmp1219 << tmp1218 V_MUL_F32 vDst(VGPR1471) src0(VGPR1468) src1(VGPR1468) // VOP2 V_MAC_F32 vDst(VGPR1471) src0(VGPR1469) src1(VGPR1469) // VOP2 V_MAC_F32 vDst(VGPR1471) src0(VGPR1470) src1(VGPR1470) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1471) src0(VGPR1471) V_MUL_F32 vDst(VGPR1472) src0(VGPR1468) src1(VGPR1471) // VOP2 V_MUL_F32 vDst(VGPR1473) src0(VGPR1469) src1(VGPR1471) // VOP2 V_MUL_F32 vDst(VGPR1474) src0(VGPR1470) src1(VGPR1471) // VOP2 # 1220: OpMatrixTimesVector: FloatVector3: tmp1220 << tmp1183, tmp1219 V_MUL_F32 vDst(VGPR1475) src0(VGPR1437) src1(VGPR1472) // VOP2 V_MUL_F32 vDst(VGPR1476) src0(VGPR1438) src1(VGPR1472) // VOP2 V_MUL_F32 vDst(VGPR1477) src0(VGPR1439) src1(VGPR1472) // VOP2 V_MAC_F32 vDst(VGPR1475) src0(VGPR1440) src1(VGPR1473) // VOP2 V_MAC_F32 vDst(VGPR1476) src0(VGPR1441) src1(VGPR1473) // VOP2 V_MAC_F32 vDst(VGPR1477) src0(VGPR1442) src1(VGPR1473) // VOP2 V_MAC_F32 vDst(VGPR1475) src0(VGPR1443) src1(VGPR1474) // VOP2 V_MAC_F32 vDst(VGPR1476) src0(VGPR1444) src1(VGPR1474) // VOP2 V_MAC_F32 vDst(VGPR1477) src0(VGPR1445) src1(VGPR1474) // VOP2 # 1222: OpAccessChain: Float*: ro[1] # 1223: OpCompositeExtract: Float: tmp1223 << cameraPos(f1;, 1 V_MOV_B32 vDst(VGPR1478) src0(VGPR1368) # 1224: OpFSub: Float: tmp1224 << const106, tmp1223 V_SUB_F32 vDst(VGPR1479) src0(1_0_F) src1(VGPR1478) // VOP2 # 1225: OpAccessChain: Float*: rd[1] # 1226: OpCompositeExtract: Float: tmp1226 << tmp1220, 1 V_MOV_B32 vDst(VGPR1480) src0(VGPR1476) # 1227: OpFDiv: Float: tmp1227 << tmp1224, tmp1226 V_RCP_F32 vDst(VGPR1481) src0(VGPR1480) V_MUL_F32 vDst(VGPR1481) src0(VGPR1479) src1(VGPR1481) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1481) src0(VGPR1481) src1(VGPR1480) src2(VGPR1479) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1228: OpExtInst(FMax): Float: tmp1228 << const100, tmp1227 V_MOV_B32 vDst(VGPR1482) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR1483) src0(VGPR1482) src1(VGPR1481) // VOP2 # OpStore: : tmp1228 >> t V_MOV_B32 vDst(VGPR1319) src0(VGPR1483) # 1231: OpAccessChain: Float*: ro[1] # 1232: OpCompositeExtract: Float: tmp1232 << cameraPos(f1;, 1 V_MOV_B32 vDst(VGPR1484) src0(VGPR1368) # 1233: OpFSub: Float: tmp1233 << const1230, tmp1232 V_MOV_B32 vDst(VGPR1485) src0(LITERAL_CONST) const: 0xbc23d70a V_SUB_F32 vDst(VGPR1486) src0(VGPR1485) src1(VGPR1484) // VOP2 # 1234: OpAccessChain: Float*: rd[1] # 1235: OpCompositeExtract: Float: tmp1235 << tmp1220, 1 V_MOV_B32 vDst(VGPR1487) src0(VGPR1476) # 1236: OpFDiv: Float: tmp1236 << tmp1233, tmp1235 V_RCP_F32 vDst(VGPR1488) src0(VGPR1487) V_MUL_F32 vDst(VGPR1488) src0(VGPR1486) src1(VGPR1488) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1488) src0(VGPR1488) src1(VGPR1487) src2(VGPR1486) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1237: OpExtInst(FMax): Float: tmp1237 << const100, tmp1236 V_MOV_B32 vDst(VGPR1489) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR1490) src0(VGPR1489) src1(VGPR1488) // VOP2 # OpStore: : cameraPos(f1; >> param1239 V_MOV_B32 vDst(VGPR1323) src0(VGPR1367) V_MOV_B32 vDst(VGPR1324) src0(VGPR1368) V_MOV_B32 vDst(VGPR1325) src0(VGPR1369) # OpStore: : tmp1220 >> param1241 V_MOV_B32 vDst(VGPR1326) src0(VGPR1475) V_MOV_B32 vDst(VGPR1327) src0(VGPR1476) V_MOV_B32 vDst(VGPR1328) src0(VGPR1477) # 1244: OpLoad: Float: tmp1244 << t # OpStore: : tmp1244 >> param1243 V_MOV_B32 vDst(VGPR1329) src0(VGPR1319) # OpStore: : tmp1237 >> param1245 V_MOV_B32 vDst(VGPR1330) src0(VGPR1490) # 1247: OpFunctionCall: FloatVector3: trace(vf3;vf3;f1;f1;(param1239, param1241, param1243, param1245) S_ADD_U32 sDst(SGPR291) src0(LITERAL_CONST) src1(0) const: 0x52b # VGPR[1323:1325] S_ADD_U32 sDst(SGPR292) src0(LITERAL_CONST) src1(0) const: 0x52e # VGPR[1326:1328] S_ADD_U32 sDst(SGPR293) src0(LITERAL_CONST) src1(0) const: 0x531 # VGPR1329 S_ADD_U32 sDst(SGPR294) src0(LITERAL_CONST) src1(0) const: 0x532 # VGPR1330 S_MOV_B64 sDst(SGPR376) src0(EXEC) S_MOV_B32 sDst(SGPR290) src0(LITERAL_CONST) const: 0x5d3 # VGPR[1491:1493] # Indirect branch to trace(vf3;vf3;f1;f1;: ??? S_GETPC_B64 sDst(SGPR288) src0(SGPR288) S_ADD_U32 sDst(SGPR288) src0(SGPR288) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR289) src0(SGPR289) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR288) src0(SGPR288) S_MOV_B64 sDst(EXEC) src0(SGPR376) # .lbl127 # 1248: OpLoad: Float: tmp1248 << param1243 # OpStore: : tmp1248 >> t V_MOV_B32 vDst(VGPR1319) src0(VGPR1329) # OpStore: : trace(vf3;vf3;f1;f1; >> col V_MOV_B32 vDst(VGPR1320) src0(VGPR1491) V_MOV_B32 vDst(VGPR1321) src0(VGPR1492) V_MOV_B32 vDst(VGPR1322) src0(VGPR1493) # 1252: OpLoad: Float: tmp1252 << t # 1253: OpVectorTimesScalar: FloatVector3: tmp1253 << tmp1220, tmp1252 V_MUL_F32 vDst(VGPR1494) src0(VGPR1319) src1(VGPR1475) // VOP2 V_MUL_F32 vDst(VGPR1495) src0(VGPR1319) src1(VGPR1476) // VOP2 V_MUL_F32 vDst(VGPR1496) src0(VGPR1319) src1(VGPR1477) // VOP2 # 1254: OpFAdd: FloatVector3: tmp1254 << cameraPos(f1;, tmp1253 V_ADD_F32 vDst(VGPR1497) src0(VGPR1367) src1(VGPR1494) // VOP2 V_ADD_F32 vDst(VGPR1498) src0(VGPR1368) src1(VGPR1495) // VOP2 V_ADD_F32 vDst(VGPR1499) src0(VGPR1369) src1(VGPR1496) // VOP2 # 1255: OpAccessChain: Float*: rp[1] # 1256: OpCompositeExtract: Float: tmp1256 << tmp1254, 1 V_MOV_B32 vDst(VGPR1500) src0(VGPR1498) # 1257: OpFMul: Float: tmp1257 << tmp1256, const127 V_MOV_B32 vDst(VGPR1501) src0(2_0_F) V_MUL_F32 vDst(VGPR1502) src0(VGPR1500) src1(VGPR1501) // VOP2 # 1258: OpExtInst(FClamp): Float: tmp1258 << tmp1257, const100, const106 V_MOV_B32 vDst(VGPR1503) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1504) src0(1_0_F) V_MAX_F32 vDst(VGPR1505) src0(VGPR1502) src1(VGPR1503) // VOP2 V_MIN_F32 vDst(VGPR1505) src0(VGPR1505) src1(VGPR1504) // VOP2 # OpStore: : tmp1258 >> icing_factor V_MOV_B32 vDst(VGPR43) src0(VGPR1505) # 1259: OpLoad: Float: tmp1259 << t # 1260: OpFOrdGreaterThan: Bool: tmp1260 << tmp1259, const100 V_MOV_B32 vDst(VGPR1506) src0(LITERAL_CONST) const: 0x00000000 V_CMP_GT_F32 dst(SGPR378) src0(VGPR1319) src1(VGPR1506) // VOP3a # 1262: OpLoad: Float: tmp1262 << t # 1263: OpFOrdLessThan: Bool: tmp1263 << tmp1237, tmp1262 V_CMP_LT_F32 dst(SGPR380) src0(VGPR1490) src1(VGPR1319) // VOP3a # 1264: OpLogicalAnd: Bool: tmp1264 << tmp1260, tmp1263 S_AND_B64 sDst(SGPR382) src0(SGPR378) src1(SGPR380) # OpSelectionMerge: (merge: lb1266) # CF Block: Merge: lb1266 S_MOV_B64 sDst(SGPR384) src0(EXEC) # OpBranchConditional: if(tmp1264) then branch to lb1265, else branch to lb1266 # CF Block: Cond Branch: true: lb1265, false: lb1266 S_AND_B64 sDst(EXEC) src0(SGPR382) src1(EXEC) S_CBRANCH_EXECZ ??? lb1266 # lb1265 Label: lb1265 # 1269: OpVectorShuffle: FloatVector2: tmp1269 << cameraPos(f1;, cameraPos(f1;, 0, 2 V_MOV_B32 vDst(VGPR1507) src0(VGPR1367) V_MOV_B32 vDst(VGPR1508) src0(VGPR1369) # 1271: OpVectorShuffle: FloatVector2: tmp1271 << tmp1220, tmp1220, 0, 2 V_MOV_B32 vDst(VGPR1509) src0(VGPR1475) V_MOV_B32 vDst(VGPR1510) src0(VGPR1477) # 1273: OpVectorTimesScalar: FloatVector2: tmp1273 << tmp1271, tmp1237 V_MUL_F32 vDst(VGPR1511) src0(VGPR1490) src1(VGPR1509) // VOP2 V_MUL_F32 vDst(VGPR1512) src0(VGPR1490) src1(VGPR1510) // VOP2 # 1274: OpFAdd: FloatVector2: tmp1274 << tmp1269, tmp1273 V_ADD_F32 vDst(VGPR1513) src0(VGPR1507) src1(VGPR1511) // VOP2 V_ADD_F32 vDst(VGPR1514) src0(VGPR1508) src1(VGPR1512) // VOP2 # OpStore: : tmp1274 >> c V_MOV_B32 vDst(VGPR1331) src0(VGPR1513) V_MOV_B32 vDst(VGPR1332) src0(VGPR1514) # 1276: OpLoad: FloatVector2: tmp1276 << c # 1277: OpVectorTimesScalar: FloatVector2: tmp1277 << tmp1276, const151 V_MOV_B32 vDst(VGPR1517) src0(LITERAL_CONST) const: 0x3f4ccccd V_MUL_F32 vDst(VGPR1515) src0(VGPR1517) src1(VGPR1331) // VOP2 V_MUL_F32 vDst(VGPR1516) src0(VGPR1517) src1(VGPR1332) // VOP2 # 1279: OpAccessChain: Float*: xc[0] # 1280: OpCompositeExtract: Float: tmp1280 << tmp1277, 0 V_MOV_B32 vDst(VGPR1518) src0(VGPR1515) # 1281: OpAccessChain: Float*: xc[1] # 1282: OpCompositeExtract: Float: tmp1282 << tmp1277, 1 V_MOV_B32 vDst(VGPR1519) src0(VGPR1516) # 1283: OpExtInst(Fract): Float: tmp1283 << tmp1282 V_FRACT_F32 vDst(VGPR1520) src0(VGPR1519) # 1284: OpExtInst(Step): Float: tmp1284 << const303, tmp1283 V_CMP_GT_F32 src0(0_5_F) src1(VGPR1520) # CF Block: Merge: .lbl129 S_MOV_B64 sDst(SGPR386) src0(EXEC) # CF Block: Cond Branch: true: .lbl130, false: .lbl128 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl128 Label: .lbl130 V_MOV_B32 vDst(VGPR1521) src0(0) Label: .lbl128 S_ANDN2_B64 sDst(EXEC) src0(SGPR386) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl129 V_MOV_B32 vDst(VGPR1521) src0(1_0_F) Label: .lbl129 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR386) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) # 1285: OpFMul: Float: tmp1285 << const303, tmp1284 V_MUL_F32 vDst(VGPR1522) src0(0_5_F) src1(VGPR1521) // VOP2 # 1286: OpFAdd: Float: tmp1286 << tmp1280, tmp1285 V_ADD_F32 vDst(VGPR1523) src0(VGPR1518) src1(VGPR1522) // VOP2 # 1287: OpExtInst(Fract): Float: tmp1287 << tmp1286 V_FRACT_F32 vDst(VGPR1524) src0(VGPR1523) # 1288: OpExtInst(Step): Float: tmp1288 << const303, tmp1287 V_CMP_GT_F32 src0(0_5_F) src1(VGPR1524) # CF Block: Merge: .lbl132 S_MOV_B64 sDst(SGPR388) src0(EXEC) # CF Block: Cond Branch: true: .lbl133, false: .lbl131 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl131 Label: .lbl133 V_MOV_B32 vDst(VGPR1525) src0(0) Label: .lbl131 S_ANDN2_B64 sDst(EXEC) src0(SGPR388) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl132 V_MOV_B32 vDst(VGPR1525) src0(1_0_F) Label: .lbl132 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR388) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) # 1294: OpCompositeConstruct: FloatVector3: tmp1294 << tmp1288, tmp1288, tmp1288 V_MOV_B32 vDst(VGPR1526) src0(VGPR1525) V_MOV_B32 vDst(VGPR1527) src0(VGPR1525) V_MOV_B32 vDst(VGPR1528) src0(VGPR1525) # 1295: OpExtInst(FMix): FloatVector3: tmp1295 << const1290, const1292, tmp1294 V_MOV_B32 vDst(VGPR1529) src0(1_0_F) V_MOV_B32 vDst(VGPR1530) src0(1_0_F) V_MOV_B32 vDst(VGPR1531) src0(1_0_F) V_MOV_B32 vDst(VGPR1532) src0(0_5_F) V_MOV_B32 vDst(VGPR1533) src0(0_5_F) V_MOV_B32 vDst(VGPR1534) src0(LITERAL_CONST) const: 0x3e800000 V_SUBREV_F32 vDst(VGPR1535) src0(VGPR1526) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1535) src0(VGPR1529) src1(VGPR1535) // VOP2 V_MAD_F32 vDst(VGPR1535) src0(VGPR1532) src1(VGPR1526) src2(VGPR1535) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1536) src0(VGPR1527) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1536) src0(VGPR1530) src1(VGPR1536) // VOP2 V_MAD_F32 vDst(VGPR1536) src0(VGPR1533) src1(VGPR1527) src2(VGPR1536) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1537) src0(VGPR1528) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1537) src0(VGPR1531) src1(VGPR1537) // VOP2 V_MAD_F32 vDst(VGPR1537) src0(VGPR1534) src1(VGPR1528) src2(VGPR1537) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1295 >> cc V_MOV_B32 vDst(VGPR1333) src0(VGPR1535) V_MOV_B32 vDst(VGPR1334) src0(VGPR1536) V_MOV_B32 vDst(VGPR1335) src0(VGPR1537) # 1296: OpLoad: FloatVector3: tmp1296 << cc # 1299: OpVectorTimesScalar: FloatVector2: tmp1299 << tmp1277, const621 V_MOV_B32 vDst(VGPR1540) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR1538) src0(VGPR1540) src1(VGPR1515) // VOP2 V_MUL_F32 vDst(VGPR1539) src0(VGPR1540) src1(VGPR1516) // VOP2 # 1300: OpAccessChain: Float*: xc[1] # 1301: OpCompositeExtract: Float: tmp1301 << tmp1277, 1 V_MOV_B32 vDst(VGPR1541) src0(VGPR1516) # 1302: OpFMul: Float: tmp1302 << tmp1301, const127 V_MOV_B32 vDst(VGPR1542) src0(2_0_F) V_MUL_F32 vDst(VGPR1543) src0(VGPR1541) src1(VGPR1542) // VOP2 # 1303: OpExtInst(Cos): Float: tmp1303 << tmp1302 V_MUL_F32 vDst(VGPR1544) src0(LITERAL_CONST) src1(VGPR1543) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR1544) src0(VGPR1544) V_COS_F32 vDst(VGPR1544) src0(VGPR1544) # 1304: OpFMul: Float: tmp1304 << tmp1303, const109 V_MOV_B32 vDst(VGPR1545) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR1546) src0(VGPR1544) src1(VGPR1545) // VOP2 # 1305: OpAccessChain: Float*: xc[0] # 1306: OpCompositeExtract: Float: tmp1306 << tmp1277, 0 V_MOV_B32 vDst(VGPR1547) src0(VGPR1515) # 1307: OpFMul: Float: tmp1307 << tmp1306, const106 V_MOV_B32 vDst(VGPR1548) src0(1_0_F) V_MUL_F32 vDst(VGPR1549) src0(VGPR1547) src1(VGPR1548) // VOP2 # 1308: OpExtInst(Cos): Float: tmp1308 << tmp1307 V_MUL_F32 vDst(VGPR1550) src0(LITERAL_CONST) src1(VGPR1549) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR1550) src0(VGPR1550) V_COS_F32 vDst(VGPR1550) src0(VGPR1550) # 1309: OpFMul: Float: tmp1309 << tmp1308, const377 V_MOV_B32 vDst(VGPR1551) src0(4_0_F) V_MUL_F32 vDst(VGPR1552) src0(VGPR1550) src1(VGPR1551) // VOP2 # 1310: OpCompositeConstruct: FloatVector2: tmp1310 << tmp1304, tmp1309 V_MOV_B32 vDst(VGPR1553) src0(VGPR1546) V_MOV_B32 vDst(VGPR1554) src0(VGPR1552) # 1311: OpFAdd: FloatVector2: tmp1311 << tmp1299, tmp1310 V_ADD_F32 vDst(VGPR1555) src0(VGPR1538) src1(VGPR1553) // VOP2 V_ADD_F32 vDst(VGPR1556) src0(VGPR1539) src1(VGPR1554) // VOP2 # OpStore: : tmp1311 >> param1312 V_MOV_B32 vDst(VGPR1336) src0(VGPR1555) V_MOV_B32 vDst(VGPR1337) src0(VGPR1556) # 1313: OpFunctionCall: Float: smN2(vf2;(param1312) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x538 # VGPR[1336:1337] S_MOV_B64 sDst(SGPR390) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x615 # VGPR1557 # Indirect branch to smN2(vf2;: ??? S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_ADD_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR390) # .lbl134 # 1314: OpFMul: Float: tmp1314 << const303, smN2(vf2; V_MUL_F32 vDst(VGPR1558) src0(0_5_F) src1(VGPR1557) // VOP2 # 1315: OpFAdd: Float: tmp1315 << const523, tmp1314 V_MOV_B32 vDst(VGPR1559) src0(LITERAL_CONST) const: 0x3e99999a V_ADD_F32 vDst(VGPR1560) src0(VGPR1559) src1(VGPR1558) // VOP2 # 1316: OpExtInst(Pow): Float: tmp1316 << tmp1315, const377 V_MOV_B32 vDst(VGPR1561) src0(4_0_F) V_LOG_F32 vDst(VGPR1562) src0(VGPR1560) V_MUL_F32 vDst(VGPR1562) src0(VGPR1561) src1(VGPR1562) // VOP2 V_EXP_F32 vDst(VGPR1562) src0(VGPR1562) # 1317: OpCompositeConstruct: FloatVector3: tmp1317 << tmp1316, tmp1316, tmp1316 V_MOV_B32 vDst(VGPR1563) src0(VGPR1562) V_MOV_B32 vDst(VGPR1564) src0(VGPR1562) V_MOV_B32 vDst(VGPR1565) src0(VGPR1562) # 1318: OpExtInst(FMix): FloatVector3: tmp1318 << tmp1296, const1297, tmp1317 V_MOV_B32 vDst(VGPR1566) src0(LITERAL_CONST) const: 0x3f666666 V_MOV_B32 vDst(VGPR1567) src0(LITERAL_CONST) const: 0x3f666666 V_MOV_B32 vDst(VGPR1568) src0(0_5_F) V_SUBREV_F32 vDst(VGPR1569) src0(VGPR1563) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1569) src0(VGPR1333) src1(VGPR1569) // VOP2 V_MAD_F32 vDst(VGPR1569) src0(VGPR1566) src1(VGPR1563) src2(VGPR1569) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1570) src0(VGPR1564) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1570) src0(VGPR1334) src1(VGPR1570) // VOP2 V_MAD_F32 vDst(VGPR1570) src0(VGPR1567) src1(VGPR1564) src2(VGPR1570) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1571) src0(VGPR1565) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1571) src0(VGPR1335) src1(VGPR1571) // VOP2 V_MAD_F32 vDst(VGPR1571) src0(VGPR1568) src1(VGPR1565) src2(VGPR1571) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1318 >> cc V_MOV_B32 vDst(VGPR1333) src0(VGPR1569) V_MOV_B32 vDst(VGPR1334) src0(VGPR1570) V_MOV_B32 vDst(VGPR1335) src0(VGPR1571) # 1320: OpLoad: FloatVector3: tmp1320 << l # 1322: OpFSub: FloatVector3: tmp1322 << tmp1320, tmp1220 V_SUB_F32 vDst(VGPR1572) src0(VGPR37) src1(VGPR1475) // VOP2 V_SUB_F32 vDst(VGPR1573) src0(VGPR38) src1(VGPR1476) // VOP2 V_SUB_F32 vDst(VGPR1574) src0(VGPR39) src1(VGPR1477) // VOP2 # 1323: OpExtInst(Normalize): FloatVector3: tmp1323 << tmp1322 V_MUL_F32 vDst(VGPR1575) src0(VGPR1572) src1(VGPR1572) // VOP2 V_MAC_F32 vDst(VGPR1575) src0(VGPR1573) src1(VGPR1573) // VOP2 V_MAC_F32 vDst(VGPR1575) src0(VGPR1574) src1(VGPR1574) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR1575) src0(VGPR1575) V_MUL_F32 vDst(VGPR1576) src0(VGPR1572) src1(VGPR1575) // VOP2 V_MUL_F32 vDst(VGPR1577) src0(VGPR1573) src1(VGPR1575) // VOP2 V_MUL_F32 vDst(VGPR1578) src0(VGPR1574) src1(VGPR1575) // VOP2 # 1326: OpExtInst(Reflect): FloatVector3: tmp1326 << tmp1220, const1153 V_MOV_B32 vDst(VGPR1579) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1580) src0(1_0_F) V_MOV_B32 vDst(VGPR1581) src0(LITERAL_CONST) const: 0x00000000 V_MUL_F32 vDst(VGPR1585) src0(VGPR1475) src1(VGPR1579) // VOP2 V_MAC_F32 vDst(VGPR1585) src0(VGPR1476) src1(VGPR1580) // VOP2 V_MAC_F32 vDst(VGPR1585) src0(VGPR1477) src1(VGPR1581) // VOP2 V_MUL_F32 vDst(VGPR1585) src0(2_0_F) src1(VGPR1585) // VOP2 V_MUL_F32 vDst(VGPR1582) src0(VGPR1579) src1(VGPR1585) // VOP2 V_MUL_F32 vDst(VGPR1583) src0(VGPR1580) src1(VGPR1585) // VOP2 V_MUL_F32 vDst(VGPR1584) src0(VGPR1581) src1(VGPR1585) // VOP2 V_SUB_F32 vDst(VGPR1582) src0(VGPR1475) src1(VGPR1582) // VOP2 V_SUB_F32 vDst(VGPR1583) src0(VGPR1476) src1(VGPR1583) // VOP2 V_SUB_F32 vDst(VGPR1584) src0(VGPR1477) src1(VGPR1584) // VOP2 # 1329: OpVectorTimesScalar: FloatVector2: tmp1329 << tmp1277, const303 V_MOV_B32 vDst(VGPR1588) src0(0_5_F) V_MUL_F32 vDst(VGPR1586) src0(VGPR1588) src1(VGPR1515) // VOP2 V_MUL_F32 vDst(VGPR1587) src0(VGPR1588) src1(VGPR1516) // VOP2 # OpStore: : const127 >> param1330 V_MOV_B32 vDst(VGPR1338) src0(2_0_F) # OpStore: : tmp1329 >> param1331 V_MOV_B32 vDst(VGPR1339) src0(VGPR1586) V_MOV_B32 vDst(VGPR1340) src0(VGPR1587) # 1332: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param1330, param1331) S_ADD_U32 sDst(SGPR123) src0(LITERAL_CONST) src1(0) const: 0x53a # VGPR1338 S_ADD_U32 sDst(SGPR124) src0(LITERAL_CONST) src1(0) const: 0x53b # VGPR[1339:1340] S_MOV_B64 sDst(SGPR392) src0(EXEC) S_MOV_B32 sDst(SGPR122) src0(LITERAL_CONST) const: 0x635 # VGPR[1589:1590] # Indirect branch to rotate(f1;vf2;: ??? S_GETPC_B64 sDst(SGPR120) src0(SGPR120) S_ADD_U32 sDst(SGPR120) src0(SGPR120) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR121) src0(SGPR121) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR120) src0(SGPR120) S_MOV_B64 sDst(EXEC) src0(SGPR392) # .lbl135 # OpStore: : rotate(f1;vf2; >> param1333 V_MOV_B32 vDst(VGPR1341) src0(VGPR1589) V_MOV_B32 vDst(VGPR1342) src0(VGPR1590) # 1334: OpFunctionCall: FloatVector3: marble(vf2;(param1333) S_ADD_U32 sDst(SGPR233) src0(LITERAL_CONST) src1(0) const: 0x53d # VGPR[1341:1342] S_MOV_B64 sDst(SGPR394) src0(EXEC) S_MOV_B32 sDst(SGPR232) src0(LITERAL_CONST) const: 0x637 # VGPR[1591:1593] # Indirect branch to marble(vf2;: ??? S_GETPC_B64 sDst(SGPR230) src0(SGPR230) S_ADD_U32 sDst(SGPR230) src0(SGPR230) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR231) src0(SGPR231) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR230) src0(SGPR230) S_MOV_B64 sDst(EXEC) src0(SGPR394) # .lbl136 # OpStore: : marble(vf2; >> cc V_MOV_B32 vDst(VGPR1333) src0(VGPR1591) V_MOV_B32 vDst(VGPR1334) src0(VGPR1592) V_MOV_B32 vDst(VGPR1335) src0(VGPR1593) # 1335: OpLoad: FloatVector2: tmp1335 << c # 1336: OpCompositeConstruct: FloatVector2: tmp1336 << const109, const109 V_MOV_B32 vDst(VGPR1596) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR1594) src0(VGPR1596) V_MOV_B32 vDst(VGPR1597) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR1595) src0(VGPR1597) # 1337: OpFDiv: FloatVector2: tmp1337 << tmp1335, tmp1336 V_RCP_F32 vDst(VGPR1598) src0(VGPR1594) V_RCP_F32 vDst(VGPR1599) src0(VGPR1595) V_MUL_F32 vDst(VGPR1598) src0(VGPR1331) src1(VGPR1598) // VOP2 V_MUL_F32 vDst(VGPR1599) src0(VGPR1332) src1(VGPR1599) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1598) src0(VGPR1598) src1(VGPR1594) src2(VGPR1331) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR1599) src0(VGPR1599) src1(VGPR1595) src2(VGPR1332) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1338: OpExtInst(Fract): FloatVector2: tmp1338 << tmp1337 V_FRACT_F32 vDst(VGPR1600) src0(VGPR1598) V_FRACT_F32 vDst(VGPR1601) src0(VGPR1599) # OpStore: : tmp1338 >> c V_MOV_B32 vDst(VGPR1331) src0(VGPR1600) V_MOV_B32 vDst(VGPR1332) src0(VGPR1601) # 1339: OpLoad: FloatVector3: tmp1339 << cc # 1340: OpVectorTimesScalar: FloatVector3: tmp1340 << tmp1339, const151 V_MOV_B32 vDst(VGPR1605) src0(LITERAL_CONST) const: 0x3f4ccccd V_MUL_F32 vDst(VGPR1602) src0(VGPR1605) src1(VGPR1333) // VOP2 V_MUL_F32 vDst(VGPR1603) src0(VGPR1605) src1(VGPR1334) // VOP2 V_MUL_F32 vDst(VGPR1604) src0(VGPR1605) src1(VGPR1335) // VOP2 # 1342: OpLoad: Float: tmp1342 << colour # OpStore: : tmp1342 >> param1341 V_MOV_B32 vDst(VGPR1343) src0(VGPR30) # 1343: OpFunctionCall: FloatVector3: gumColour(f1;(param1341) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x53f # VGPR1343 S_MOV_B64 sDst(SGPR396) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x646 # VGPR[1606:1608] # Indirect branch to gumColour(f1;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR396) # .lbl137 # 1344: OpVectorTimesScalar: FloatVector3: tmp1344 << gumColour(f1;, const127 V_MOV_B32 vDst(VGPR1612) src0(2_0_F) V_MUL_F32 vDst(VGPR1609) src0(VGPR1612) src1(VGPR1606) // VOP2 V_MUL_F32 vDst(VGPR1610) src0(VGPR1612) src1(VGPR1607) // VOP2 V_MUL_F32 vDst(VGPR1611) src0(VGPR1612) src1(VGPR1608) // VOP2 # 1345: OpLoad: Float: tmp1345 << is_choc # 1346: OpVectorTimesScalar: FloatVector3: tmp1346 << tmp1344, tmp1345 V_MUL_F32 vDst(VGPR1613) src0(VGPR33) src1(VGPR1609) // VOP2 V_MUL_F32 vDst(VGPR1614) src0(VGPR33) src1(VGPR1610) // VOP2 V_MUL_F32 vDst(VGPR1615) src0(VGPR33) src1(VGPR1611) // VOP2 # 1349: OpLoad: FloatVector2: tmp1349 << c # 1350: OpExtInst(Distance): Float: tmp1350 << const391, tmp1349 V_MOV_B32 vDst(VGPR1616) src0(0_5_F) V_MOV_B32 vDst(VGPR1617) src0(0_5_F) V_SUB_F32 vDst(VGPR1618) src0(VGPR1616) src1(VGPR1331) // VOP2 V_SUB_F32 vDst(VGPR1619) src0(VGPR1617) src1(VGPR1332) // VOP2 V_MUL_F32 vDst(VGPR1620) src0(VGPR1618) src1(VGPR1618) // VOP2 V_MAC_F32 vDst(VGPR1620) src0(VGPR1619) src1(VGPR1619) // VOP2 V_SQRT_F32 vDst(VGPR1620) src0(VGPR1620) # 1351: OpLoad: Float: tmp1351 << ss # 1352: OpFDiv: Float: tmp1352 << tmp1350, tmp1351 V_RCP_F32 vDst(VGPR1621) src0(VGPR32) V_MUL_F32 vDst(VGPR1621) src0(VGPR1620) src1(VGPR1621) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1621) src0(VGPR1621) src1(VGPR32) src2(VGPR1620) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1353: OpExtInst(SmoothStep): Float: tmp1353 << const1347, const1348, tmp1352 V_MOV_B32 vDst(VGPR1622) src0(LITERAL_CONST) const: 0x3ea8f5c3 V_MOV_B32 vDst(VGPR1623) src0(LITERAL_CONST) const: 0x3f07ae14 V_CMP_GE_F32 src0(VGPR1622) src1(VGPR1621) # CF Block: Merge: .lbl141 S_MOV_B64 sDst(SGPR398) src0(EXEC) # CF Block: Cond Branch: true: .lbl142, false: .lbl138 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl138 Label: .lbl142 V_MOV_B32 vDst(VGPR1624) src0(0) Label: .lbl138 S_ANDN2_B64 sDst(EXEC) src0(SGPR398) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl141 V_CMP_LE_F32 src0(VGPR1623) src1(VGPR1621) # CF Block: Merge: .lbl140 S_MOV_B64 sDst(SGPR400) src0(EXEC) # CF Block: Cond Branch: true: .lbl143, false: .lbl139 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl139 Label: .lbl143 V_MOV_B32 vDst(VGPR1624) src0(1_0_F) Label: .lbl139 S_ANDN2_B64 sDst(EXEC) src0(SGPR400) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl140 V_SUBREV_F32 vDst(VGPR1625) src0(VGPR1622) src1(VGPR1623) // VOP2 V_RCP_F32 vDst(VGPR1625) src0(VGPR1625) V_SUBREV_F32 vDst(VGPR1624) src0(VGPR1622) src1(VGPR1621) // VOP2 V_MUL_F32 vDst(VGPR1625) src0(VGPR1624) src1(VGPR1625) // VOP2 V_MAX_F32 vDst(VGPR1625) src0(0) src1(VGPR1625) // VOP2 V_MIN_F32 vDst(VGPR1625) src0(1_0_F) src1(VGPR1625) // VOP2 V_MOV_B32 vDst(VGPR1624) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1624) src0(2_0_F) src1(VGPR1625) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1625) src0(VGPR1625) src1(VGPR1625) // VOP2 V_MUL_F32 vDst(VGPR1624) src0(VGPR1625) src1(VGPR1624) // VOP2 Label: .lbl140 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR400) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) Label: .lbl141 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR398) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) # 1354: OpCompositeConstruct: FloatVector3: tmp1354 << tmp1353, tmp1353, tmp1353 V_MOV_B32 vDst(VGPR1626) src0(VGPR1624) V_MOV_B32 vDst(VGPR1627) src0(VGPR1624) V_MOV_B32 vDst(VGPR1628) src0(VGPR1624) # 1355: OpExtInst(FMix): FloatVector3: tmp1355 << tmp1346, const1290, tmp1354 V_MOV_B32 vDst(VGPR1629) src0(1_0_F) V_MOV_B32 vDst(VGPR1630) src0(1_0_F) V_MOV_B32 vDst(VGPR1631) src0(1_0_F) V_SUBREV_F32 vDst(VGPR1632) src0(VGPR1626) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1632) src0(VGPR1613) src1(VGPR1632) // VOP2 V_MAD_F32 vDst(VGPR1632) src0(VGPR1629) src1(VGPR1626) src2(VGPR1632) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1633) src0(VGPR1627) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1633) src0(VGPR1614) src1(VGPR1633) // VOP2 V_MAD_F32 vDst(VGPR1633) src0(VGPR1630) src1(VGPR1627) src2(VGPR1633) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1634) src0(VGPR1628) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1634) src0(VGPR1615) src1(VGPR1634) // VOP2 V_MAD_F32 vDst(VGPR1634) src0(VGPR1631) src1(VGPR1628) src2(VGPR1634) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1356: OpFMul: FloatVector3: tmp1356 << tmp1340, tmp1355 V_MUL_F32 vDst(VGPR1635) src0(VGPR1602) src1(VGPR1632) // VOP2 V_MUL_F32 vDst(VGPR1636) src0(VGPR1603) src1(VGPR1633) // VOP2 V_MUL_F32 vDst(VGPR1637) src0(VGPR1604) src1(VGPR1634) // VOP2 # OpStore: : tmp1356 >> col V_MOV_B32 vDst(VGPR1320) src0(VGPR1635) V_MOV_B32 vDst(VGPR1321) src0(VGPR1636) V_MOV_B32 vDst(VGPR1322) src0(VGPR1637) # OpStore: : const106 >> icing_factor V_MOV_B32 vDst(VGPR43) src0(1_0_F) # OpBranch: to lb1266 # lb1266 Label: lb1266 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR384) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) # 1360: OpAccessChain: Float*: iMouse[0] # 1361: OpLoad: Float: tmp1361 << iMouse[0] S_LOAD_DWORD_IMM offset(16) sBase(SGPR[0:1]) sDst(SGPR402) S_WAITCNT 0 # 1362: OpAccessChain: Float*: iResolution[0] # 1363: OpLoad: Float: tmp1363 << iResolution[0] S_LOAD_DWORD_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR403) S_WAITCNT 0 # 1364: OpFDiv: Float: tmp1364 << tmp1361, tmp1363 V_MOV_B32 vDst(VGPR1638) src0(SGPR403) V_RCP_F32 vDst(VGPR1639) src0(VGPR1638) V_MUL_F32 vDst(VGPR1639) src0(SGPR402) src1(VGPR1639) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR1639) src0(VGPR1639) src1(VGPR1638) src2(SGPR402) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1365: OpLoad: Float: tmp1365 << icing_factor # 1366: OpFMul: Float: tmp1366 << tmp1364, tmp1365 V_MUL_F32 vDst(VGPR1640) src0(VGPR1639) src1(VGPR43) // VOP2 # 1367: OpFSub: Float: tmp1367 << const106, tmp1366 V_SUB_F32 vDst(VGPR1641) src0(1_0_F) src1(VGPR1640) // VOP2 # 1368: OpLoad: FloatVector3: tmp1368 << col # 1371: OpFMul: Float: tmp1371 << const1369, tmp1367 V_MOV_B32 vDst(VGPR1642) src0(LITERAL_CONST) const: 0xbe800000 V_MUL_F32 vDst(VGPR1643) src0(VGPR1642) src1(VGPR1641) // VOP2 # 1373: OpFAdd: Float: tmp1373 << tmp1371, const1372 V_MOV_B32 vDst(VGPR1644) src0(LITERAL_CONST) const: 0x3eb33333 V_ADD_F32 vDst(VGPR1645) src0(VGPR1643) src1(VGPR1644) // VOP2 # 1375: OpVectorShuffle: FloatVector2: tmp1375 << tmp1254, tmp1254, 0, 2 V_MOV_B32 vDst(VGPR1646) src0(VGPR1497) V_MOV_B32 vDst(VGPR1647) src0(VGPR1499) # 1377: OpVectorTimesScalar: FloatVector2: tmp1377 << tmp1375, const1376 V_MOV_B32 vDst(VGPR1650) src0(LITERAL_CONST) const: 0x40866666 V_MUL_F32 vDst(VGPR1648) src0(VGPR1650) src1(VGPR1646) // VOP2 V_MUL_F32 vDst(VGPR1649) src0(VGPR1650) src1(VGPR1647) // VOP2 # 1378: OpCompositeExtract: Float: tmp1378 << tmp1377, 0 V_MOV_B32 vDst(VGPR1651) src0(VGPR1648) # 1379: OpCompositeExtract: Float: tmp1379 << tmp1377, 1 V_MOV_B32 vDst(VGPR1652) src0(VGPR1649) # 1380: OpCompositeConstruct: FloatVector3: tmp1380 << tmp1378, tmp1379, const100 V_MOV_B32 vDst(VGPR1653) src0(VGPR1651) V_MOV_B32 vDst(VGPR1654) src0(VGPR1652) V_MOV_B32 vDst(VGPR1656) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1655) src0(VGPR1656) # OpStore: : tmp1380 >> param1381 V_MOV_B32 vDst(VGPR1344) src0(VGPR1653) V_MOV_B32 vDst(VGPR1345) src0(VGPR1654) V_MOV_B32 vDst(VGPR1346) src0(VGPR1655) # 1382: OpFunctionCall: Float: fbm3(vf3;(param1381) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x540 # VGPR[1344:1346] S_MOV_B64 sDst(SGPR404) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x679 # VGPR1657 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR404) # .lbl144 # 1383: OpFAdd: Float: tmp1383 << tmp1373, fbm3(vf3; V_ADD_F32 vDst(VGPR1658) src0(VGPR1645) src1(VGPR1657) // VOP2 # 1384: OpExtInst(SmoothStep): Float: tmp1384 << const303, const671, tmp1383 V_MOV_B32 vDst(VGPR1659) src0(LITERAL_CONST) const: 0x3f333333 V_CMP_GE_F32 src0(0_5_F) src1(VGPR1658) # CF Block: Merge: .lbl148 S_MOV_B64 sDst(SGPR406) src0(EXEC) # CF Block: Cond Branch: true: .lbl149, false: .lbl145 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl145 Label: .lbl149 V_MOV_B32 vDst(VGPR1660) src0(0) Label: .lbl145 S_ANDN2_B64 sDst(EXEC) src0(SGPR406) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl148 V_CMP_LE_F32 src0(VGPR1659) src1(VGPR1658) # CF Block: Merge: .lbl147 S_MOV_B64 sDst(SGPR408) src0(EXEC) # CF Block: Cond Branch: true: .lbl150, false: .lbl146 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl146 Label: .lbl150 V_MOV_B32 vDst(VGPR1660) src0(1_0_F) Label: .lbl146 S_ANDN2_B64 sDst(EXEC) src0(SGPR408) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl147 V_SUBREV_F32 vDst(VGPR1661) src0(0_5_F) src1(VGPR1659) // VOP2 V_RCP_F32 vDst(VGPR1661) src0(VGPR1661) V_SUBREV_F32 vDst(VGPR1660) src0(0_5_F) src1(VGPR1658) // VOP2 V_MUL_F32 vDst(VGPR1661) src0(VGPR1660) src1(VGPR1661) // VOP2 V_MAX_F32 vDst(VGPR1661) src0(0) src1(VGPR1661) // VOP2 V_MIN_F32 vDst(VGPR1661) src0(1_0_F) src1(VGPR1661) // VOP2 V_MOV_B32 vDst(VGPR1660) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1660) src0(2_0_F) src1(VGPR1661) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1661) src0(VGPR1661) src1(VGPR1661) // VOP2 V_MUL_F32 vDst(VGPR1660) src0(VGPR1661) src1(VGPR1660) // VOP2 Label: .lbl147 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR408) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) Label: .lbl148 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR406) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) # 1385: OpFMul: Float: tmp1385 << const435, tmp1384 V_MOV_B32 vDst(VGPR1662) src0(LITERAL_CONST) const: 0x3f666666 V_MUL_F32 vDst(VGPR1663) src0(VGPR1662) src1(VGPR1660) // VOP2 # 1387: OpFMul: Float: tmp1387 << const1369, tmp1367 V_MOV_B32 vDst(VGPR1664) src0(LITERAL_CONST) const: 0xbe800000 V_MUL_F32 vDst(VGPR1665) src0(VGPR1664) src1(VGPR1641) // VOP2 # 1388: OpFAdd: Float: tmp1388 << tmp1387, const523 V_MOV_B32 vDst(VGPR1666) src0(LITERAL_CONST) const: 0x3e99999a V_ADD_F32 vDst(VGPR1667) src0(VGPR1665) src1(VGPR1666) // VOP2 # 1390: OpVectorShuffle: FloatVector2: tmp1390 << tmp1254, tmp1254, 0, 2 V_MOV_B32 vDst(VGPR1668) src0(VGPR1497) V_MOV_B32 vDst(VGPR1669) src0(VGPR1499) # 1392: OpVectorTimesScalar: FloatVector2: tmp1392 << tmp1390, const1391 V_MOV_B32 vDst(VGPR1672) src0(LITERAL_CONST) const: 0x4121999a V_MUL_F32 vDst(VGPR1670) src0(VGPR1672) src1(VGPR1668) // VOP2 V_MUL_F32 vDst(VGPR1671) src0(VGPR1672) src1(VGPR1669) // VOP2 # 1393: OpCompositeExtract: Float: tmp1393 << tmp1392, 0 V_MOV_B32 vDst(VGPR1673) src0(VGPR1670) # 1394: OpCompositeExtract: Float: tmp1394 << tmp1392, 1 V_MOV_B32 vDst(VGPR1674) src0(VGPR1671) # 1395: OpCompositeConstruct: FloatVector3: tmp1395 << tmp1393, tmp1394, const100 V_MOV_B32 vDst(VGPR1675) src0(VGPR1673) V_MOV_B32 vDst(VGPR1676) src0(VGPR1674) V_MOV_B32 vDst(VGPR1678) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1677) src0(VGPR1678) # OpStore: : tmp1395 >> param1396 V_MOV_B32 vDst(VGPR1347) src0(VGPR1675) V_MOV_B32 vDst(VGPR1348) src0(VGPR1676) V_MOV_B32 vDst(VGPR1349) src0(VGPR1677) # 1397: OpFunctionCall: Float: fbm3(vf3;(param1396) S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x543 # VGPR[1347:1349] S_MOV_B64 sDst(SGPR410) src0(EXEC) S_MOV_B32 sDst(SGPR106) src0(LITERAL_CONST) const: 0x68f # VGPR1679 # Indirect branch to fbm3(vf3;: ??? S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_ADD_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR410) # .lbl151 # 1398: OpFAdd: Float: tmp1398 << tmp1388, fbm3(vf3; V_ADD_F32 vDst(VGPR1680) src0(VGPR1667) src1(VGPR1679) // VOP2 # 1399: OpExtInst(SmoothStep): Float: tmp1399 << const303, const671, tmp1398 V_MOV_B32 vDst(VGPR1681) src0(LITERAL_CONST) const: 0x3f333333 V_CMP_GE_F32 src0(0_5_F) src1(VGPR1680) # CF Block: Merge: .lbl155 S_MOV_B64 sDst(SGPR412) src0(EXEC) # CF Block: Cond Branch: true: .lbl156, false: .lbl152 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl152 Label: .lbl156 V_MOV_B32 vDst(VGPR1682) src0(0) Label: .lbl152 S_ANDN2_B64 sDst(EXEC) src0(SGPR412) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl155 V_CMP_LE_F32 src0(VGPR1681) src1(VGPR1680) # CF Block: Merge: .lbl154 S_MOV_B64 sDst(SGPR414) src0(EXEC) # CF Block: Cond Branch: true: .lbl157, false: .lbl153 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl153 Label: .lbl157 V_MOV_B32 vDst(VGPR1682) src0(1_0_F) Label: .lbl153 S_ANDN2_B64 sDst(EXEC) src0(SGPR414) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR348) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl154 V_SUBREV_F32 vDst(VGPR1683) src0(0_5_F) src1(VGPR1681) // VOP2 V_RCP_F32 vDst(VGPR1683) src0(VGPR1683) V_SUBREV_F32 vDst(VGPR1682) src0(0_5_F) src1(VGPR1680) // VOP2 V_MUL_F32 vDst(VGPR1683) src0(VGPR1682) src1(VGPR1683) // VOP2 V_MAX_F32 vDst(VGPR1683) src0(0) src1(VGPR1683) // VOP2 V_MIN_F32 vDst(VGPR1683) src0(1_0_F) src1(VGPR1683) // VOP2 V_MOV_B32 vDst(VGPR1682) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR1682) src0(2_0_F) src1(VGPR1683) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR1683) src0(VGPR1683) src1(VGPR1683) // VOP2 V_MUL_F32 vDst(VGPR1682) src0(VGPR1683) src1(VGPR1682) // VOP2 Label: .lbl154 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR414) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) Label: .lbl155 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR412) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR348) # 1400: OpFMul: Float: tmp1400 << const435, tmp1399 V_MOV_B32 vDst(VGPR1684) src0(LITERAL_CONST) const: 0x3f666666 V_MUL_F32 vDst(VGPR1685) src0(VGPR1684) src1(VGPR1682) // VOP2 # 1401: OpFAdd: Float: tmp1401 << tmp1385, tmp1400 V_ADD_F32 vDst(VGPR1686) src0(VGPR1663) src1(VGPR1685) // VOP2 # 1402: OpCompositeConstruct: FloatVector3: tmp1402 << tmp1401, tmp1401, tmp1401 V_MOV_B32 vDst(VGPR1687) src0(VGPR1686) V_MOV_B32 vDst(VGPR1688) src0(VGPR1686) V_MOV_B32 vDst(VGPR1689) src0(VGPR1686) # 1403: OpExtInst(FMix): FloatVector3: tmp1403 << tmp1368, const1290, tmp1402 V_MOV_B32 vDst(VGPR1690) src0(1_0_F) V_MOV_B32 vDst(VGPR1691) src0(1_0_F) V_MOV_B32 vDst(VGPR1692) src0(1_0_F) V_SUBREV_F32 vDst(VGPR1693) src0(VGPR1687) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1693) src0(VGPR1320) src1(VGPR1693) // VOP2 V_MAD_F32 vDst(VGPR1693) src0(VGPR1690) src1(VGPR1687) src2(VGPR1693) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1694) src0(VGPR1688) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1694) src0(VGPR1321) src1(VGPR1694) // VOP2 V_MAD_F32 vDst(VGPR1694) src0(VGPR1691) src1(VGPR1688) src2(VGPR1694) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1695) src0(VGPR1689) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1695) src0(VGPR1322) src1(VGPR1695) // VOP2 V_MAD_F32 vDst(VGPR1695) src0(VGPR1692) src1(VGPR1689) src2(VGPR1695) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1403 >> col V_MOV_B32 vDst(VGPR1320) src0(VGPR1693) V_MOV_B32 vDst(VGPR1321) src0(VGPR1694) V_MOV_B32 vDst(VGPR1322) src0(VGPR1695) # 1404: OpLoad: FloatVector3: tmp1404 << col # 1405: OpVectorTimesScalar: FloatVector3: tmp1405 << tmp1404, const895 V_MOV_B32 vDst(VGPR1699) src0(LITERAL_CONST) const: 0x3fb33333 V_MUL_F32 vDst(VGPR1696) src0(VGPR1699) src1(VGPR1320) // VOP2 V_MUL_F32 vDst(VGPR1697) src0(VGPR1699) src1(VGPR1321) // VOP2 V_MUL_F32 vDst(VGPR1698) src0(VGPR1699) src1(VGPR1322) // VOP2 # 1406: OpExtInst(Sqrt): FloatVector3: tmp1406 << tmp1405 V_SQRT_F32 vDst(VGPR1700) src0(VGPR1696) V_SQRT_F32 vDst(VGPR1701) src0(VGPR1697) V_SQRT_F32 vDst(VGPR1702) src0(VGPR1698) # 1407: OpLoad: FloatVector4: tmp1407 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1703) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1704) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1705) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1706) src0(VGPR3) # 1408: OpVectorShuffle: FloatVector4: tmp1408 << tmp1407, tmp1406, 4, 5, 6, 3 V_MOV_B32 vDst(VGPR1707) src0(VGPR1700) V_MOV_B32 vDst(VGPR1708) src0(VGPR1701) V_MOV_B32 vDst(VGPR1709) src0(VGPR1702) V_MOV_B32 vDst(VGPR1710) src0(VGPR1706) # OpStore: : tmp1408 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1707) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1708) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1709) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1710) # 1410: OpAccessChain: Float*: q[0] # 1411: OpCompositeExtract: Float: tmp1411 << tmp1187, 0 V_MOV_B32 vDst(VGPR1711) src0(VGPR1451) # 1412: OpFMul: Float: tmp1412 << const1409, tmp1411 V_MOV_B32 vDst(VGPR1712) src0(LITERAL_CONST) const: 0x41800000 V_MUL_F32 vDst(VGPR1713) src0(VGPR1712) src1(VGPR1711) // VOP2 # 1413: OpAccessChain: Float*: q[1] # 1414: OpCompositeExtract: Float: tmp1414 << tmp1187, 1 V_MOV_B32 vDst(VGPR1714) src0(VGPR1452) # 1415: OpFMul: Float: tmp1415 << tmp1412, tmp1414 V_MUL_F32 vDst(VGPR1715) src0(VGPR1713) src1(VGPR1714) // VOP2 # 1416: OpAccessChain: Float*: q[0] # 1417: OpCompositeExtract: Float: tmp1417 << tmp1187, 0 V_MOV_B32 vDst(VGPR1716) src0(VGPR1451) # 1418: OpFSub: Float: tmp1418 << const106, tmp1417 V_SUB_F32 vDst(VGPR1717) src0(1_0_F) src1(VGPR1716) // VOP2 # 1419: OpFMul: Float: tmp1419 << tmp1415, tmp1418 V_MUL_F32 vDst(VGPR1718) src0(VGPR1715) src1(VGPR1717) // VOP2 # 1420: OpAccessChain: Float*: q[1] # 1421: OpCompositeExtract: Float: tmp1421 << tmp1187, 1 V_MOV_B32 vDst(VGPR1719) src0(VGPR1452) # 1422: OpFSub: Float: tmp1422 << const106, tmp1421 V_SUB_F32 vDst(VGPR1720) src0(1_0_F) src1(VGPR1719) // VOP2 # 1423: OpFMul: Float: tmp1423 << tmp1419, tmp1422 V_MUL_F32 vDst(VGPR1721) src0(VGPR1718) src1(VGPR1720) // VOP2 # 1424: OpExtInst(Pow): Float: tmp1424 << tmp1423, const576 V_MOV_B32 vDst(VGPR1722) src0(LITERAL_CONST) const: 0x3dcccccd V_LOG_F32 vDst(VGPR1723) src0(VGPR1721) V_MUL_F32 vDst(VGPR1723) src0(VGPR1722) src1(VGPR1723) // VOP2 V_EXP_F32 vDst(VGPR1723) src0(VGPR1723) # 1425: OpLoad: FloatVector4: tmp1425 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1724) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1725) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1726) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1727) src0(VGPR3) # 1426: OpVectorShuffle: FloatVector3: tmp1426 << tmp1425, tmp1425, 0, 1, 2 V_MOV_B32 vDst(VGPR1728) src0(VGPR1724) V_MOV_B32 vDst(VGPR1729) src0(VGPR1725) V_MOV_B32 vDst(VGPR1730) src0(VGPR1726) # 1427: OpVectorTimesScalar: FloatVector3: tmp1427 << tmp1426, tmp1424 V_MUL_F32 vDst(VGPR1731) src0(VGPR1723) src1(VGPR1728) // VOP2 V_MUL_F32 vDst(VGPR1732) src0(VGPR1723) src1(VGPR1729) // VOP2 V_MUL_F32 vDst(VGPR1733) src0(VGPR1723) src1(VGPR1730) // VOP2 # 1428: OpLoad: FloatVector4: tmp1428 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1734) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1735) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1736) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1737) src0(VGPR3) # 1429: OpVectorShuffle: FloatVector4: tmp1429 << tmp1428, tmp1427, 4, 5, 6, 3 V_MOV_B32 vDst(VGPR1738) src0(VGPR1731) V_MOV_B32 vDst(VGPR1739) src0(VGPR1732) V_MOV_B32 vDst(VGPR1740) src0(VGPR1733) V_MOV_B32 vDst(VGPR1741) src0(VGPR1737) # OpStore: : tmp1429 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1738) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1739) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1740) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1741) # OpReturn: S_SETPC_B64 sDst(SGPR10) src0(SGPR10) Performing register allocation... Register VGPR[26:27] contains scalar/constant data. Will try converting to SGPR. Register VGPR28 contains scalar/constant data. Will try converting to SGPR. Register VGPR28 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1363) src0(VGPR28) src1(VGPR1363) // VOP2 Register VGPR29 contains scalar/constant data. Will try converting to SGPR. Register VGPR31 contains scalar/constant data. Will try converting to SGPR. Register VGPR34 contains scalar/constant data. Will try converting to SGPR. Register VGPR35 contains scalar/constant data. Will try converting to SGPR. Register VGPR35 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR935) src0(VGPR934) src1(VGPR35) // VOP2 Register VGPR36 contains scalar/constant data. Will try converting to SGPR. Register VGPR[37:39] contains scalar/constant data. Will try converting to SGPR. Register VGPR[37:39] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR1124) src0(VGPR37) src1(VGPR1121) // VOP2 Register VGPR[40:42] contains scalar/constant data. Will try converting to SGPR. Register VGPR44 contains scalar/constant data. Will try converting to SGPR. Register VGPR[45:48] contains scalar/constant data. Will try converting to SGPR. Register VGPR[49:50] contains scalar/constant data. Will try converting to SGPR. Register VGPR56 contains scalar/constant data. Will try converting to SGPR. Register VGPR[57:59] contains scalar/constant data. Will try converting to SGPR. Register VGPR61 contains scalar/constant data. Will try converting to SGPR. Register VGPR[62:64] contains scalar/constant data. Will try converting to SGPR. Register VGPR66 contains scalar/constant data. Will try converting to SGPR. Register VGPR[67:69] contains scalar/constant data. Will try converting to SGPR. Register VGPR[70:72] contains scalar/constant data. Will try converting to SGPR. Register VGPR74 contains scalar/constant data. Will try converting to SGPR. Register VGPR[75:77] contains scalar/constant data. Will try converting to SGPR. Register VGPR79 contains scalar/constant data. Will try converting to SGPR. Register VGPR[80:82] contains scalar/constant data. Will try converting to SGPR. Register VGPR84 contains scalar/constant data. Will try converting to SGPR. Register VGPR[85:87] contains scalar/constant data. Will try converting to SGPR. Register VGPR[88:90] contains scalar/constant data. Will try converting to SGPR. Register VGPR93 contains scalar/constant data. Will try converting to SGPR. Register VGPR93 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR94) src0(VGPR92) src1(VGPR93) // VOP2 Register VGPR125 contains scalar/constant data. Will try converting to SGPR. Register VGPR125 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR122) src0(VGPR125) src1(VGPR96) // VOP2 Register VGPR[126:128] contains scalar/constant data. Will try converting to SGPR. Register VGPR[126:128] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR132) src0(VGPR126) src1(VGPR122) // VOP2 Register VGPR129 contains scalar/constant data. Will try converting to SGPR. Register VGPR130 contains scalar/constant data. Will try converting to SGPR. Register VGPR131 contains scalar/constant data. Will try converting to SGPR. Register VGPR140 contains scalar/constant data. Will try converting to SGPR. Register VGPR140 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR141) src0(VGPR139) src1(VGPR140) // VOP2 Register VGPR144 contains scalar/constant data. Will try converting to SGPR. Register VGPR144 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR145) src0(VGPR144) src1(VGPR143) // VOP2 Register VGPR147 contains scalar/constant data. Will try converting to SGPR. Register VGPR147 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR148) src0(VGPR146) src1(VGPR147) // VOP2 Register VGPR150 contains scalar/constant data. Will try converting to SGPR. Register VGPR150 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR151) src0(VGPR146) src1(VGPR150) // VOP2 Register VGPR155 contains scalar/constant data. Will try converting to SGPR. Register VGPR155 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR156) src0(VGPR146) src1(VGPR155) // VOP2 Register VGPR158 contains scalar/constant data. Will try converting to SGPR. Register VGPR158 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR159) src0(VGPR146) src1(VGPR158) // VOP2 Register VGPR165 contains scalar/constant data. Will try converting to SGPR. Register VGPR165 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR166) src0(VGPR146) src1(VGPR165) // VOP2 Register VGPR168 contains scalar/constant data. Will try converting to SGPR. Register VGPR168 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR169) src0(VGPR146) src1(VGPR168) // VOP2 Register VGPR173 contains scalar/constant data. Will try converting to SGPR. Register VGPR173 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR174) src0(VGPR146) src1(VGPR173) // VOP2 Register VGPR176 contains scalar/constant data. Will try converting to SGPR. Register VGPR176 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR177) src0(VGPR146) src1(VGPR176) // VOP2 Register VGPR195 contains scalar/constant data. Will try converting to SGPR. Register VGPR205 contains scalar/constant data. Will try converting to SGPR. Register VGPR205 can't be converted to SGPR, because the following instruction can't be converted: V_CVT_F32_I32 vDst(VGPR211) src0(VGPR205) Register VGPR209 contains scalar/constant data. Will try converting to SGPR. Register VGPR210 contains scalar/constant data. Will try converting to SGPR. Register VGPR211 contains scalar/constant data. Will try converting to SGPR. Register VGPR211 can't be converted to SGPR, because the following instruction can't be converted: V_CVT_F32_I32 vDst(VGPR211) src0(VGPR205) Register VGPR212 contains scalar/constant data. Will try converting to SGPR. Register VGPR212 can't be converted to SGPR, because the following instruction can't be converted: V_EXP_F32 vDst(VGPR212) src0(VGPR211) Register VGPR220 contains scalar/constant data. Will try converting to SGPR. Register VGPR220 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR221) src0(VGPR219) src1(VGPR220) // VOP2 Register VGPR224 contains scalar/constant data. Will try converting to SGPR. Register VGPR225 contains scalar/constant data. Will try converting to SGPR. Register VGPR[248:249] contains scalar/constant data. Will try converting to SGPR. Register VGPR[248:249] can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR252) src0(VGPR246) src1(VGPR248) // VOP2 Register VGPR[250:251] contains scalar/constant data. Will try converting to SGPR. Register VGPR[250:251] can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR252) src0(VGPR252) src1(VGPR250) // VOP2 Register VGPR256 contains scalar/constant data. Will try converting to SGPR. Register VGPR256 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR257) src0(VGPR256) src1(VGPR257) // VOP2 Register VGPR260 contains scalar/constant data. Will try converting to SGPR. Register VGPR260 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR262) src0(VGPR259) src1(VGPR260) // VOP2 Register VGPR261 contains scalar/constant data. Will try converting to SGPR. Register VGPR264 contains scalar/constant data. Will try converting to SGPR. Register VGPR264 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR265) src0(VGPR264) src1(VGPR265) // VOP2 Register VGPR268 contains scalar/constant data. Will try converting to SGPR. Register VGPR268 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR269) src0(VGPR267) src1(VGPR268) // VOP2 Register VGPR270 contains scalar/constant data. Will try converting to SGPR. Register VGPR270 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR271) src0(VGPR270) src1(VGPR271) // VOP2 Register VGPR275 contains scalar/constant data. Will try converting to SGPR. Register VGPR275 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR276) src0(VGPR275) src1(VGPR276) // VOP2 Register VGPR280 contains scalar/constant data. Will try converting to SGPR. Register VGPR280 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR281) src0(VGPR280) src1(VGPR281) // VOP2 Register VGPR284 contains scalar/constant data. Will try converting to SGPR. Register VGPR284 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR285) src0(VGPR284) src1(VGPR285) // VOP2 Register VGPR287 contains scalar/constant data. Will try converting to SGPR. Register VGPR287 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR288) src0(VGPR286) src1(VGPR287) // VOP2 Register VGPR304 contains scalar/constant data. Will try converting to SGPR. Register VGPR304 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR302) src0(VGPR304) src1(VGPR300) // VOP2 Register VGPR[307:308] contains scalar/constant data. Will try converting to SGPR. Register VGPR[307:308] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR309) src0(VGPR305) src1(VGPR307) // VOP2 Register VGPR315 contains scalar/constant data. Will try converting to SGPR. Register VGPR315 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR316) src0(VGPR314) src1(VGPR315) // VOP2 Register VGPR319 contains scalar/constant data. Will try converting to SGPR. Register VGPR319 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR320) src0(VGPR318) src1(VGPR319) // VOP2 Register VGPR323 contains scalar/constant data. Will try converting to SGPR. Register VGPR323 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR324) src0(VGPR322) src1(VGPR323) // VOP2 Register VGPR330 contains scalar/constant data. Will try converting to SGPR. Register VGPR330 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR328) src0(VGPR330) src1(VGPR326) // VOP2 Register VGPR[332:333] contains scalar/constant data. Will try converting to SGPR. Register VGPR[332:333] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR334) src0(VGPR311) src1(VGPR332) // VOP2 Register VGPR[339:340] contains scalar/constant data. Will try converting to SGPR. Register VGPR[339:340] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR341) src0(VGPR339) src1(VGPR337) // VOP2 Register VGPR345 contains scalar/constant data. Will try converting to SGPR. Register VGPR345 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR346) src0(VGPR345) src1(VGPR346) // VOP2 Register VGPR347 contains scalar/constant data. Will try converting to SGPR. Register VGPR347 can't be converted to SGPR, because the following instruction can't be converted: V_SUBREV_F32 vDst(VGPR348) src0(VGPR347) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR349 contains scalar/constant data. Will try converting to SGPR. Register VGPR349 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR350) src0(VGPR348) src1(VGPR349) // VOP2 Register VGPR355 contains scalar/constant data. Will try converting to SGPR. Register VGPR355 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR353) src0(VGPR355) src1(VGPR351) // VOP2 Register VGPR363 contains scalar/constant data. Will try converting to SGPR. Register VGPR363 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR361) src0(VGPR363) src1(VGPR302) // VOP2 Register VGPR365 contains scalar/constant data. Will try converting to SGPR. Register VGPR365 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR366) src0(VGPR364) src1(VGPR365) // VOP2 Register VGPR367 contains scalar/constant data. Will try converting to SGPR. Register VGPR367 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR368) src0(VGPR367) src1(VGPR366) // VOP2 Register VGPR382 contains scalar/constant data. Will try converting to SGPR. Register VGPR382 can't be converted to SGPR, because the following instruction can't be converted: V_CVT_F32_I32 vDst(VGPR390) src0(VGPR382) Register VGPR386 contains scalar/constant data. Will try converting to SGPR. Register VGPR387 contains scalar/constant data. Will try converting to SGPR. Register VGPR390 contains scalar/constant data. Will try converting to SGPR. Register VGPR390 can't be converted to SGPR, because the following instruction can't be converted: V_CVT_F32_I32 vDst(VGPR390) src0(VGPR382) Register VGPR391 contains scalar/constant data. Will try converting to SGPR. Register VGPR391 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR392) src0(VGPR390) src1(VGPR391) // VOP2 Register VGPR392 contains scalar/constant data. Will try converting to SGPR. Register VGPR392 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR392) src0(VGPR390) src1(VGPR391) // VOP2 Register VGPR[393:394] contains scalar/constant data. Will try converting to SGPR. Register VGPR[393:394] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR395) src0(VGPR388) src1(VGPR393) // VOP2 Register VGPR397 contains scalar/constant data. Will try converting to SGPR. Register VGPR397 can't be converted to SGPR, because the following instruction can't be converted: V_CVT_F32_I32 vDst(VGPR397) src0(VGPR382) Register VGPR398 contains scalar/constant data. Will try converting to SGPR. Register VGPR398 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR399) src0(VGPR397) src1(VGPR398) // VOP2 Register VGPR399 contains scalar/constant data. Will try converting to SGPR. Register VGPR399 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR399) src0(VGPR397) src1(VGPR398) // VOP2 Register VGPR400 contains scalar/constant data. Will try converting to SGPR. Register VGPR400 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR400) src0(1_0_F) src1(VGPR399) // VOP2 Register VGPR405 contains scalar/constant data. Will try converting to SGPR. Register VGPR405 can't be converted to SGPR, because the following instruction can't be converted: V_CVT_F32_I32 vDst(VGPR405) src0(VGPR382) Register VGPR406 contains scalar/constant data. Will try converting to SGPR. Register VGPR406 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR407) src0(VGPR406) Register VGPR407 contains scalar/constant data. Will try converting to SGPR. Register VGPR407 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR407) src0(VGPR406) Register VGPR408 contains scalar/constant data. Will try converting to SGPR. Register VGPR408 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR408) src0(1_0_F) src1(VGPR407) // VOP2 Register VGPR409 contains scalar/constant data. Will try converting to SGPR. Register VGPR409 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR410) src0(VGPR409) src1(VGPR410) // VOP2 Register VGPR410 contains scalar/constant data. Will try converting to SGPR. Register VGPR410 can't be converted to SGPR, because the following instruction can't be converted: V_LOG_F32 vDst(VGPR410) src0(VGPR408) Register VGPR413 contains scalar/constant data. Will try converting to SGPR. Register VGPR414 contains scalar/constant data. Will try converting to SGPR. Register VGPR425 contains scalar/constant data. Will try converting to SGPR. Register VGPR425 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR423) src0(VGPR425) src1(VGPR421) // VOP2 Register VGPR432 contains scalar/constant data. Will try converting to SGPR. Register VGPR432 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR430) src0(VGPR432) src1(VGPR428) // VOP2 Register VGPR435 contains scalar/constant data. Will try converting to SGPR. Register VGPR435 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR436) src0(VGPR434) src1(VGPR435) // VOP2 Register VGPR463 contains scalar/constant data. Will try converting to SGPR. Register VGPR463 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR475) src0(VGPR463) src1(VGPR474) src2(VGPR464) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR464 contains scalar/constant data. Will try converting to SGPR. Register VGPR464 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR475) src0(VGPR463) src1(VGPR474) src2(VGPR464) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR465 contains scalar/constant data. Will try converting to SGPR. Register VGPR465 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR465) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR466 contains scalar/constant data. Will try converting to SGPR. Register VGPR466 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR466) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR467 contains scalar/constant data. Will try converting to SGPR. Register VGPR467 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR467) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR468 contains scalar/constant data. Will try converting to SGPR. Register VGPR468 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR475) src0(VGPR475) src1(VGPR474) src2(VGPR468) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR469 contains scalar/constant data. Will try converting to SGPR. Register VGPR469 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR475) src0(VGPR469) src1(VGPR475) // VOP2 Register VGPR470 contains scalar/constant data. Will try converting to SGPR. Register VGPR470 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR475) src0(VGPR470) src1(VGPR475) // VOP2 Register VGPR477 contains scalar/constant data. Will try converting to SGPR. Register VGPR477 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR483) src0(VGPR477) src1(VGPR482) src2(VGPR478) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR478 contains scalar/constant data. Will try converting to SGPR. Register VGPR478 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR483) src0(VGPR477) src1(VGPR482) src2(VGPR478) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR479 contains scalar/constant data. Will try converting to SGPR. Register VGPR479 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR483) src0(VGPR482) src1(VGPR483) src2(VGPR479) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR480 contains scalar/constant data. Will try converting to SGPR. Register VGPR480 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR483) src0(VGPR482) src1(VGPR483) src2(VGPR480) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR481 contains scalar/constant data. Will try converting to SGPR. Register VGPR481 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR483) src0(VGPR482) src1(VGPR483) src2(VGPR481) abs(0) clamp(0) omod(0) neg(1) // VOP3a Register VGPR488 contains scalar/constant data. Will try converting to SGPR. Register VGPR488 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR486) src0(VGPR488) src1(VGPR484) // VOP2 Register VGPR497 contains scalar/constant data. Will try converting to SGPR. Register VGPR497 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_GE_F32 src0(VGPR497) src1(VGPR496) Register VGPR498 contains scalar/constant data. Will try converting to SGPR. Register VGPR498 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR498) src1(VGPR496) Register VGPR503 contains scalar/constant data. Will try converting to SGPR. Register VGPR503 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR504) src0(VGPR502) src1(VGPR503) // VOP2 Register VGPR505 contains scalar/constant data. Will try converting to SGPR. Register VGPR505 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR506) src0(VGPR504) src1(VGPR505) // VOP2 Register VGPR507 contains scalar/constant data. Will try converting to SGPR. Register VGPR507 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR509) src0(VGPR506) src1(VGPR507) // VOP2 Register VGPR508 contains scalar/constant data. Will try converting to SGPR. Register VGPR508 can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR509) src0(VGPR509) src1(VGPR508) // VOP2 Register VGPR[513:515] contains scalar/constant data. Will try converting to SGPR. Register VGPR[513:515] can't be converted to SGPR, because the following instruction can't be converted: V_SUBREV_F32 vDst(VGPR522) src0(VGPR513) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR516 contains scalar/constant data. Will try converting to SGPR. Register VGPR517 contains scalar/constant data. Will try converting to SGPR. Register VGPR518 contains scalar/constant data. Will try converting to SGPR. Register VGPR[519:521] contains scalar/constant data. Will try converting to SGPR. Register VGPR[519:521] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR522) src0(VGPR519) src1(VGPR522) // VOP2 Register VGPR528 contains scalar/constant data. Will try converting to SGPR. Register VGPR528 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR529) src0(VGPR527) src1(VGPR528) // VOP2 Register VGPR530 contains scalar/constant data. Will try converting to SGPR. Register VGPR530 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR531) src0(VGPR530) src1(VGPR531) // VOP2 Register VGPR532 contains scalar/constant data. Will try converting to SGPR. Register VGPR532 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR533) src0(VGPR532) src1(VGPR531) // VOP2 Register VGPR[541:543] contains scalar/constant data. Will try converting to SGPR. Register VGPR[541:543] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR544) src0(VGPR541) src1(VGPR538) src2(VGPR544) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR550 contains scalar/constant data. Will try converting to SGPR. Register VGPR550 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR551) src0(VGPR550) src1(VGPR460) // VOP2 Register VGPR556 contains scalar/constant data. Will try converting to SGPR. Register VGPR556 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR557) src0(VGPR556) src1(VGPR557) // VOP2 Register VGPR564 contains scalar/constant data. Will try converting to SGPR. Register VGPR564 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR561) src0(VGPR564) src1(VGPR558) // VOP2 Register VGPR575 contains scalar/constant data. Will try converting to SGPR. Register VGPR575 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR576) src0(VGPR574) src1(VGPR575) // VOP2 Register VGPR[580:582] contains scalar/constant data. Will try converting to SGPR. Register VGPR[580:582] can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR586) src0(VGPR580) Register VGPR583 contains scalar/constant data. Will try converting to SGPR. Register VGPR584 contains scalar/constant data. Will try converting to SGPR. Register VGPR585 contains scalar/constant data. Will try converting to SGPR. Register VGPR593 contains scalar/constant data. Will try converting to SGPR. Register VGPR593 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR594) src0(VGPR592) src1(VGPR593) // VOP2 Register VGPR596 contains scalar/constant data. Will try converting to SGPR. Register VGPR596 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR597) src0(VGPR595) src1(VGPR596) // VOP2 Register VGPR600 contains scalar/constant data. Will try converting to SGPR. Register VGPR600 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR601) src0(VGPR599) src1(VGPR600) // VOP2 Register VGPR602 contains scalar/constant data. Will try converting to SGPR. Register VGPR602 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_GT_F32 src0(VGPR602) src1(VGPR601) Register VGPR610 contains scalar/constant data. Will try converting to SGPR. Register VGPR610 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR607) src0(VGPR610) src1(VGPR604) // VOP2 Register VGPR612 contains scalar/constant data. Will try converting to SGPR. Register VGPR612 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR613) src0(VGPR611) src1(VGPR612) // VOP2 Register VGPR621 contains scalar/constant data. Will try converting to SGPR. Register VGPR621 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR618) src0(VGPR621) src1(VGPR615) // VOP2 Register VGPR623 contains scalar/constant data. Will try converting to SGPR. Register VGPR623 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR624) src0(VGPR623) src1(VGPR622) // VOP2 Register VGPR625 contains scalar/constant data. Will try converting to SGPR. Register VGPR625 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR626) src0(VGPR625) src1(VGPR626) // VOP2 Register VGPR628 contains scalar/constant data. Will try converting to SGPR. Register VGPR628 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR629) src0(VGPR628) src1(VGPR627) // VOP2 Register VGPR630 contains scalar/constant data. Will try converting to SGPR. Register VGPR630 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR631) src0(VGPR630) src1(VGPR629) // VOP2 Register VGPR637 contains scalar/constant data. Will try converting to SGPR. Register VGPR637 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR638) src0(VGPR636) src1(VGPR637) // VOP2 Register VGPR640 contains scalar/constant data. Will try converting to SGPR. Register VGPR640 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR641) src0(VGPR640) Register VGPR[647:648] contains scalar/constant data. Will try converting to SGPR. Register VGPR[647:648] can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR649) src0(VGPR647) Register VGPR[651:652] contains scalar/constant data. Will try converting to SGPR. Register VGPR[651:652] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR653) src0(VGPR649) src1(VGPR651) // VOP2 Register VGPR662 contains scalar/constant data. Will try converting to SGPR. Register VGPR662 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR663) src0(VGPR661) src1(VGPR662) // VOP2 Register VGPR665 contains scalar/constant data. Will try converting to SGPR. Register VGPR665 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR666) src0(VGPR664) src1(VGPR665) // VOP2 Register VGPR671 contains scalar/constant data. Will try converting to SGPR. Register VGPR671 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR673) src0(VGPR671) src1(VGPR673) // VOP2 Register VGPR672 contains scalar/constant data. Will try converting to SGPR. Register VGPR672 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR673) src0(VGPR672) src1(VGPR670) src2(VGPR673) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR681 contains scalar/constant data. Will try converting to SGPR. Register VGPR681 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR682) src0(VGPR681) src1(VGPR678) // VOP2 Register VGPR683 contains scalar/constant data. Will try converting to SGPR. Register VGPR683 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR684) src0(VGPR683) src1(VGPR680) // VOP2 Register VGPR688 contains scalar/constant data. Will try converting to SGPR. Register VGPR688 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR689) src0(VGPR687) src1(VGPR688) // VOP2 Register VGPR691 contains scalar/constant data. Will try converting to SGPR. Register VGPR691 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR692) src0(VGPR690) src1(VGPR691) // VOP2 Register VGPR706 contains scalar/constant data. Will try converting to SGPR. Register VGPR706 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR707) src0(VGPR705) src1(VGPR706) // VOP2 Register VGPR[716:717] contains scalar/constant data. Will try converting to SGPR. Register VGPR[716:717] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR718) src0(VGPR714) src1(VGPR716) // VOP2 Register VGPR[723:724] contains scalar/constant data. Will try converting to SGPR. Register VGPR[723:724] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR721) src0(VGPR720) src1(VGPR723) // VOP2 Register VGPR[728:729] contains scalar/constant data. Will try converting to SGPR. Register VGPR[728:729] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR726) src0(VGPR725) src1(VGPR728) // VOP2 Register VGPR734 contains scalar/constant data. Will try converting to SGPR. Register VGPR734 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR732) src0(VGPR734) src1(VGPR730) // VOP2 Register VGPR742 contains scalar/constant data. Will try converting to SGPR. Register VGPR744 contains scalar/constant data. Will try converting to SGPR. Register VGPR744 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR745) src0(VGPR743) src1(VGPR744) // VOP2 Register VGPR746 contains scalar/constant data. Will try converting to SGPR. Register VGPR746 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR747) src0(VGPR746) src1(VGPR745) // VOP2 Register VGPR[751:753] contains scalar/constant data. Will try converting to SGPR. Register VGPR[751:753] can't be converted to SGPR, because the following instruction can't be converted: V_SUBREV_F32 vDst(VGPR760) src0(VGPR751) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR754 contains scalar/constant data. Will try converting to SGPR. Register VGPR755 contains scalar/constant data. Will try converting to SGPR. Register VGPR756 contains scalar/constant data. Will try converting to SGPR. Register VGPR[757:759] contains scalar/constant data. Will try converting to SGPR. Register VGPR[757:759] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR760) src0(VGPR757) src1(VGPR760) // VOP2 Register VGPR765 contains scalar/constant data. Will try converting to SGPR. Register VGPR765 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR763) src0(VGPR765) src1(VGPR710) // VOP2 Register VGPR770 contains scalar/constant data. Will try converting to SGPR. Register VGPR770 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR768) src0(VGPR770) src1(VGPR766) // VOP2 Register VGPR779 contains scalar/constant data. Will try converting to SGPR. Register VGPR779 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR777) src0(VGPR779) src1(VGPR775) // VOP2 Register VGPR784 contains scalar/constant data. Will try converting to SGPR. Register VGPR784 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR782) src0(VGPR784) src1(VGPR780) // VOP2 Register VGPR792 contains scalar/constant data. Will try converting to SGPR. Register VGPR795 contains scalar/constant data. Will try converting to SGPR. Register VGPR795 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_GE_F32 src0(VGPR795) src1(VGPR794) Register VGPR796 contains scalar/constant data. Will try converting to SGPR. Register VGPR796 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR796) src1(VGPR794) Register VGPR[803:805] contains scalar/constant data. Will try converting to SGPR. Register VGPR[803:805] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR809) src0(VGPR803) src1(VGPR809) // VOP2 Register VGPR[806:808] contains scalar/constant data. Will try converting to SGPR. Register VGPR[806:808] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR809) src0(VGPR806) src1(VGPR800) src2(VGPR809) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR816 contains scalar/constant data. Will try converting to SGPR. Register VGPR816 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR814) src0(VGPR816) src1(VGPR812) // VOP2 Register VGPR822 contains scalar/constant data. Will try converting to SGPR. Register VGPR824 contains scalar/constant data. Will try converting to SGPR. Register VGPR824 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR825) src0(VGPR823) src1(VGPR824) // VOP2 Register VGPR826 contains scalar/constant data. Will try converting to SGPR. Register VGPR826 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR827) src0(VGPR826) src1(VGPR825) // VOP2 Register VGPR843 contains scalar/constant data. Will try converting to SGPR. Register VGPR845 contains scalar/constant data. Will try converting to SGPR. Register VGPR845 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_GE_F32 src0(VGPR845) src1(VGPR844) Register VGPR846 contains scalar/constant data. Will try converting to SGPR. Register VGPR846 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR846) src1(VGPR844) Register VGPR855 contains scalar/constant data. Will try converting to SGPR. Register VGPR855 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR852) src0(VGPR855) src1(VGPR849) // VOP2 Register VGPR[859:861] contains scalar/constant data. Will try converting to SGPR. Register VGPR[859:861] can't be converted to SGPR, because the following instruction can't be converted: V_SUBREV_F32 vDst(VGPR865) src0(VGPR859) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR[862:864] contains scalar/constant data. Will try converting to SGPR. Register VGPR[862:864] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR865) src0(VGPR862) src1(VGPR859) src2(VGPR865) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR868 contains scalar/constant data. Will try converting to SGPR. Register VGPR868 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR869) src0(0_5_F) src1(VGPR868) // VOP2 Register VGPR869 contains scalar/constant data. Will try converting to SGPR. Register VGPR869 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR869) src0(0_5_F) src1(VGPR868) // VOP2 Register VGPR872 contains scalar/constant data. Will try converting to SGPR. Register VGPR872 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR872) src1(VGPR871) Register VGPR875 contains scalar/constant data. Will try converting to SGPR. Register VGPR875 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR876) src0(0_5_F) src1(VGPR875) // VOP2 Register VGPR876 contains scalar/constant data. Will try converting to SGPR. Register VGPR876 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR876) src0(0_5_F) src1(VGPR875) // VOP2 Register VGPR879 contains scalar/constant data. Will try converting to SGPR. Register VGPR879 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR879) src1(VGPR878) Register VGPR883 contains scalar/constant data. Will try converting to SGPR. Register VGPR883 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR884) src0(0_5_F) src1(VGPR883) // VOP2 Register VGPR884 contains scalar/constant data. Will try converting to SGPR. Register VGPR884 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR884) src0(0_5_F) src1(VGPR883) // VOP2 Register VGPR887 contains scalar/constant data. Will try converting to SGPR. Register VGPR887 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR887) src1(VGPR886) Register VGPR890 contains scalar/constant data. Will try converting to SGPR. Register VGPR890 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR891) src0(0_5_F) src1(VGPR890) // VOP2 Register VGPR891 contains scalar/constant data. Will try converting to SGPR. Register VGPR891 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR891) src0(0_5_F) src1(VGPR890) // VOP2 Register VGPR894 contains scalar/constant data. Will try converting to SGPR. Register VGPR894 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR894) src1(VGPR893) Register VGPR914 contains scalar/constant data. Will try converting to SGPR. Register VGPR914 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR911) src0(VGPR914) src1(VGPR908) // VOP2 Register VGPR916 contains scalar/constant data. Will try converting to SGPR. Register VGPR916 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR917) src0(VGPR915) src1(VGPR916) // VOP2 Register VGPR919 contains scalar/constant data. Will try converting to SGPR. Register VGPR919 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR920) src0(VGPR918) src1(VGPR919) // VOP2 Register VGPR922 contains scalar/constant data. Will try converting to SGPR. Register VGPR922 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR923) src0(VGPR921) src1(VGPR922) // VOP2 Register VGPR924 contains scalar/constant data. Will try converting to SGPR. Register VGPR924 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR925) src0(VGPR924) src1(VGPR923) // VOP2 Register VGPR929 contains scalar/constant data. Will try converting to SGPR. Register VGPR[939:941] contains scalar/constant data. Will try converting to SGPR. Register VGPR[939:941] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR942) src0(VGPR936) src1(VGPR939) // VOP2 Register VGPR946 contains scalar/constant data. Will try converting to SGPR. Register VGPR946 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR947) src0(VGPR945) src1(VGPR946) // VOP2 Register VGPR949 contains scalar/constant data. Will try converting to SGPR. Register VGPR949 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR950) src0(VGPR948) src1(VGPR949) // VOP2 Register VGPR952 contains scalar/constant data. Will try converting to SGPR. Register VGPR952 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR953) src0(VGPR951) src1(VGPR952) // VOP2 Register VGPR955 contains scalar/constant data. Will try converting to SGPR. Register VGPR955 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR956) src0(VGPR954) src1(VGPR955) // VOP2 Register VGPR957 contains scalar/constant data. Will try converting to SGPR. Register VGPR957 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR958) src0(VGPR957) src1(VGPR956) // VOP2 Register VGPR962 contains scalar/constant data. Will try converting to SGPR. Register VGPR[968:969] contains scalar/constant data. Will try converting to SGPR. Register VGPR[968:969] can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR972) src0(VGPR968) Register VGPR970 contains scalar/constant data. Will try converting to SGPR. Register VGPR971 contains scalar/constant data. Will try converting to SGPR. Register VGPR978 contains scalar/constant data. Will try converting to SGPR. Register VGPR978 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR976) src0(VGPR978) src1(VGPR974) // VOP2 Register VGPR[979:980] contains scalar/constant data. Will try converting to SGPR. Register VGPR[979:980] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR981) src0(VGPR976) src1(VGPR979) // VOP2 Register VGPR987 contains scalar/constant data. Will try converting to SGPR. Register VGPR987 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR988) src0(VGPR986) src1(VGPR987) // VOP2 Register VGPR992 contains scalar/constant data. Will try converting to SGPR. Register VGPR992 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR994) src0(VGPR992) src1(VGPR994) // VOP2 Register VGPR993 contains scalar/constant data. Will try converting to SGPR. Register VGPR993 can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR994) src0(VGPR993) src1(VGPR991) src2(VGPR994) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR995 contains scalar/constant data. Will try converting to SGPR. Register VGPR995 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR996) src0(VGPR994) src1(VGPR995) // VOP2 Register VGPR997 contains scalar/constant data. Will try converting to SGPR. Register VGPR1031 contains scalar/constant data. Will try converting to SGPR. Register VGPR[1048:1050] contains scalar/constant data. Will try converting to SGPR. Register VGPR1052 contains scalar/constant data. Will try converting to SGPR. Register VGPR1054 contains scalar/constant data. Will try converting to SGPR. Register VGPR1054 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1055) src0(VGPR1053) src1(VGPR1054) // VOP2 Register VGPR1059 contains scalar/constant data. Will try converting to SGPR. Register VGPR1060 contains scalar/constant data. Will try converting to SGPR. Register VGPR[1074:1076] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1078:1080] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1078:1080] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1084) src0(VGPR1071) src1(VGPR1078) // VOP2 Register VGPR1081 contains scalar/constant data. Will try converting to SGPR. Register VGPR1082 contains scalar/constant data. Will try converting to SGPR. Register VGPR1083 contains scalar/constant data. Will try converting to SGPR. Register VGPR[1089:1091] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1089:1091] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1095) src0(VGPR1071) src1(VGPR1089) // VOP2 Register VGPR1092 contains scalar/constant data. Will try converting to SGPR. Register VGPR1093 contains scalar/constant data. Will try converting to SGPR. Register VGPR1094 contains scalar/constant data. Will try converting to SGPR. Register VGPR[1100:1102] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1100:1102] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1106) src0(VGPR1071) src1(VGPR1100) // VOP2 Register VGPR1103 contains scalar/constant data. Will try converting to SGPR. Register VGPR1104 contains scalar/constant data. Will try converting to SGPR. Register VGPR1105 contains scalar/constant data. Will try converting to SGPR. Register VGPR1131 contains scalar/constant data. Will try converting to SGPR. Register VGPR1133 contains scalar/constant data. Will try converting to SGPR. Register VGPR1133 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1134) src0(VGPR1133) Register VGPR1136 contains scalar/constant data. Will try converting to SGPR. Register VGPR1136 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1137) src0(VGPR1136) Register VGPR1138 contains scalar/constant data. Will try converting to SGPR. Register VGPR[1143:1144] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1143:1144] can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1147) src0(VGPR1143) Register VGPR1145 contains scalar/constant data. Will try converting to SGPR. Register VGPR1146 contains scalar/constant data. Will try converting to SGPR. Register VGPR1153 contains scalar/constant data. Will try converting to SGPR. Register VGPR1153 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1151) src0(VGPR1153) src1(VGPR1149) // VOP2 Register VGPR[1154:1155] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1154:1155] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1156) src0(VGPR1151) src1(VGPR1154) // VOP2 Register VGPR1161 contains scalar/constant data. Will try converting to SGPR. Register VGPR1161 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1162) src0(VGPR1160) src1(VGPR1161) // VOP2 Register VGPR1163 contains scalar/constant data. Will try converting to SGPR. Register VGPR1163 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1164) src0(VGPR1163) src1(VGPR1164) // VOP2 Register VGPR1166 contains scalar/constant data. Will try converting to SGPR. Register VGPR1166 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1167) src0(VGPR1166) src1(VGPR1164) // VOP2 Register VGPR1172 contains scalar/constant data. Will try converting to SGPR. Register VGPR1172 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1170) src0(VGPR1172) src1(VGPR1168) // VOP2 Register VGPR1178 contains scalar/constant data. Will try converting to SGPR. Register VGPR1180 contains scalar/constant data. Will try converting to SGPR. Register VGPR1180 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1181) src0(VGPR1180) src1(VGPR1179) // VOP2 Register VGPR[1187:1189] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1187:1189] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1193) src0(VGPR1187) src1(VGPR1193) // VOP2 Register VGPR[1190:1192] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1190:1192] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR1193) src0(VGPR1190) src1(VGPR1184) src2(VGPR1193) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR1197 contains scalar/constant data. Will try converting to SGPR. Register VGPR1197 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1198) src0(VGPR1196) src1(VGPR1197) // VOP2 Register VGPR1200 contains scalar/constant data. Will try converting to SGPR. Register VGPR1200 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1201) src0(VGPR1199) src1(VGPR1200) // VOP2 Register VGPR1207 contains scalar/constant data. Will try converting to SGPR. Register VGPR1207 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_GE_F32 src0(VGPR1207) src1(VGPR1206) Register VGPR1208 contains scalar/constant data. Will try converting to SGPR. Register VGPR1208 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR1208) src1(VGPR1206) Register VGPR[1214:1216] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1214:1216] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1220) src0(VGPR1214) src1(VGPR1220) // VOP2 Register VGPR[1217:1219] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1217:1219] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR1220) src0(VGPR1217) src1(VGPR1211) src2(VGPR1220) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR1226 contains scalar/constant data. Will try converting to SGPR. Register VGPR1226 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1223) src0(VGPR1226) src1(VGPR1016) // VOP2 Register VGPR1239 contains scalar/constant data. Will try converting to SGPR. Register VGPR1239 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR1241) src0(VGPR1238) src1(VGPR1239) // VOP2 Register VGPR1240 contains scalar/constant data. Will try converting to SGPR. Register VGPR1240 can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR1241) src0(VGPR1241) src1(VGPR1240) // VOP2 Register VGPR1242 contains scalar/constant data. Will try converting to SGPR. Register VGPR1242 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1243) src0(VGPR1242) src1(VGPR1243) // VOP2 Register VGPR[1247:1249] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1247:1249] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1250) src0(VGPR1247) src1(VGPR1244) // VOP2 Register VGPR1263 contains scalar/constant data. Will try converting to SGPR. Register VGPR1263 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1264) src0(VGPR1263) src1(VGPR1264) // VOP2 Register VGPR1265 contains scalar/constant data. Will try converting to SGPR. Register VGPR1265 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1266) src0(VGPR1265) src1(VGPR1264) // VOP2 Register VGPR1277 contains scalar/constant data. Will try converting to SGPR. Register VGPR1277 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1274) src0(VGPR1277) src1(VGPR1271) // VOP2 Register VGPR1281 contains scalar/constant data. Will try converting to SGPR. Register VGPR1281 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR1283) src0(VGPR1280) src1(VGPR1281) // VOP2 Register VGPR1282 contains scalar/constant data. Will try converting to SGPR. Register VGPR1282 can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR1283) src0(VGPR1283) src1(VGPR1282) // VOP2 Register VGPR1284 contains scalar/constant data. Will try converting to SGPR. Register VGPR1284 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1285) src0(VGPR1284) src1(VGPR1285) // VOP2 Register VGPR1286 contains scalar/constant data. Will try converting to SGPR. Register VGPR1286 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR1286) src1(VGPR1285) Register VGPR1295 contains scalar/constant data. Will try converting to SGPR. Register VGPR1295 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1292) src0(VGPR1295) src1(VGPR1289) // VOP2 Register VGPR1300 contains scalar/constant data. Will try converting to SGPR. Register VGPR1300 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR1301) src0(VGPR1300) src1(VGPR1299) // VOP2 Register VGPR1302 contains scalar/constant data. Will try converting to SGPR. Register VGPR1302 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1303) src0(VGPR1302) src1(VGPR1303) // VOP2 Register VGPR1304 contains scalar/constant data. Will try converting to SGPR. Register VGPR1304 can't be converted to SGPR, because the following instruction can't be converted: V_SUBREV_F32 vDst(VGPR1305) src0(VGPR1304) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR[1352:1353] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1352:1353] can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1354) src0(VGPR1352) Register VGPR1358 contains scalar/constant data. Will try converting to SGPR. Register VGPR1358 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1356) src0(VGPR1358) src1(VGPR1354) // VOP2 Register VGPR[1359:1360] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1359:1360] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR1361) src0(VGPR1356) src1(VGPR1359) // VOP2 Register VGPR1363 contains scalar/constant data. Will try converting to SGPR. Register VGPR1363 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1363) src0(VGPR35) Register VGPR1364 contains scalar/constant data. Will try converting to SGPR. Register VGPR1364 can't be converted to SGPR, because the following instruction can't be converted: V_FLOOR_F32 vDst(VGPR1364) src0(VGPR1363) Register VGPR1365 contains scalar/constant data. Will try converting to SGPR. Register VGPR1365 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1365) src0(VGPR35) Register VGPR1366 contains scalar/constant data. Will try converting to SGPR. Register VGPR1366 can't be converted to SGPR, because the following instruction can't be converted: V_FRACT_F32 vDst(VGPR1366) src0(VGPR1365) Register VGPR1370 contains scalar/constant data. Will try converting to SGPR. Register VGPR1370 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR1371) src0(VGPR1364) src1(VGPR1370) // VOP2 Register VGPR1371 contains scalar/constant data. Will try converting to SGPR. Register VGPR1371 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR1371) src0(VGPR1364) src1(VGPR1370) // VOP2 Register VGPR1378 contains scalar/constant data. Will try converting to SGPR. Register VGPR1378 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_GE_F32 src0(VGPR1378) src1(VGPR1366) Register VGPR1379 contains scalar/constant data. Will try converting to SGPR. Register VGPR1379 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR1379) src1(VGPR1366) Register VGPR[1395:1397] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1395:1397] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1398) src0(VGPR1393) src1(VGPR1397) // VOP2 Register VGPR1448 contains scalar/constant data. Will try converting to SGPR. Register VGPR1448 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1446) src0(VGPR1448) src1(VGPR24) // VOP2 Register VGPR[1449:1450] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1449:1450] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1451) src0(VGPR1446) src1(VGPR1449) // VOP2 Register VGPR1453 contains scalar/constant data. Will try converting to SGPR. Register VGPR1453 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1454) src0(VGPR1453) Register VGPR1454 contains scalar/constant data. Will try converting to SGPR. Register VGPR1454 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1454) src0(VGPR1453) Register VGPR1457 contains scalar/constant data. Will try converting to SGPR. Register VGPR1457 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR1458) src0(VGPR1364) src1(VGPR1457) // VOP2 Register VGPR1458 contains scalar/constant data. Will try converting to SGPR. Register VGPR1458 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR1458) src0(VGPR1364) src1(VGPR1457) // VOP2 Register VGPR1461 contains scalar/constant data. Will try converting to SGPR. Register VGPR1461 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_GE_F32 src0(VGPR1461) src1(VGPR1366) Register VGPR1462 contains scalar/constant data. Will try converting to SGPR. Register VGPR1462 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR1462) src1(VGPR1366) Register VGPR1482 contains scalar/constant data. Will try converting to SGPR. Register VGPR1482 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR1483) src0(VGPR1482) src1(VGPR1481) // VOP2 Register VGPR1485 contains scalar/constant data. Will try converting to SGPR. Register VGPR1485 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR1486) src0(VGPR1485) src1(VGPR1484) // VOP2 Register VGPR1489 contains scalar/constant data. Will try converting to SGPR. Register VGPR1489 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR1490) src0(VGPR1489) src1(VGPR1488) // VOP2 Register VGPR1501 contains scalar/constant data. Will try converting to SGPR. Register VGPR1501 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1502) src0(VGPR1500) src1(VGPR1501) // VOP2 Register VGPR1503 contains scalar/constant data. Will try converting to SGPR. Register VGPR1503 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR1505) src0(VGPR1502) src1(VGPR1503) // VOP2 Register VGPR1504 contains scalar/constant data. Will try converting to SGPR. Register VGPR1504 can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR1505) src0(VGPR1505) src1(VGPR1504) // VOP2 Register VGPR1506 contains scalar/constant data. Will try converting to SGPR. Register VGPR1517 contains scalar/constant data. Will try converting to SGPR. Register VGPR1517 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1515) src0(VGPR1517) src1(VGPR1331) // VOP2 Register VGPR[1529:1531] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1529:1531] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1535) src0(VGPR1529) src1(VGPR1535) // VOP2 Register VGPR[1532:1534] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1532:1534] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR1535) src0(VGPR1532) src1(VGPR1526) src2(VGPR1535) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR1540 contains scalar/constant data. Will try converting to SGPR. Register VGPR1540 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1538) src0(VGPR1540) src1(VGPR1515) // VOP2 Register VGPR1542 contains scalar/constant data. Will try converting to SGPR. Register VGPR1542 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1543) src0(VGPR1541) src1(VGPR1542) // VOP2 Register VGPR1545 contains scalar/constant data. Will try converting to SGPR. Register VGPR1545 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1546) src0(VGPR1544) src1(VGPR1545) // VOP2 Register VGPR1548 contains scalar/constant data. Will try converting to SGPR. Register VGPR1548 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1549) src0(VGPR1547) src1(VGPR1548) // VOP2 Register VGPR1551 contains scalar/constant data. Will try converting to SGPR. Register VGPR1551 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1552) src0(VGPR1550) src1(VGPR1551) // VOP2 Register VGPR1559 contains scalar/constant data. Will try converting to SGPR. Register VGPR1559 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1560) src0(VGPR1559) src1(VGPR1558) // VOP2 Register VGPR1561 contains scalar/constant data. Will try converting to SGPR. Register VGPR1561 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1562) src0(VGPR1561) src1(VGPR1562) // VOP2 Register VGPR[1566:1568] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1566:1568] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR1569) src0(VGPR1566) src1(VGPR1563) src2(VGPR1569) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR[1579:1581] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1579:1581] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1585) src0(VGPR1475) src1(VGPR1579) // VOP2 Register VGPR1588 contains scalar/constant data. Will try converting to SGPR. Register VGPR1588 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1586) src0(VGPR1588) src1(VGPR1515) // VOP2 Register VGPR[1594:1595] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1594:1595] can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1598) src0(VGPR1594) Register VGPR1596 contains scalar/constant data. Will try converting to SGPR. Register VGPR1597 contains scalar/constant data. Will try converting to SGPR. Register VGPR1605 contains scalar/constant data. Will try converting to SGPR. Register VGPR1605 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1602) src0(VGPR1605) src1(VGPR1333) // VOP2 Register VGPR1612 contains scalar/constant data. Will try converting to SGPR. Register VGPR1612 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1609) src0(VGPR1612) src1(VGPR1606) // VOP2 Register VGPR[1616:1617] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1616:1617] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR1618) src0(VGPR1616) src1(VGPR1331) // VOP2 Register VGPR1622 contains scalar/constant data. Will try converting to SGPR. Register VGPR1622 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_GE_F32 src0(VGPR1622) src1(VGPR1621) Register VGPR1623 contains scalar/constant data. Will try converting to SGPR. Register VGPR1623 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR1623) src1(VGPR1621) Register VGPR[1629:1631] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1629:1631] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR1632) src0(VGPR1629) src1(VGPR1626) src2(VGPR1632) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR1638 contains scalar/constant data. Will try converting to SGPR. Register VGPR1638 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1639) src0(VGPR1638) Register VGPR1639 contains scalar/constant data. Will try converting to SGPR. Register VGPR1639 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR1639) src0(VGPR1638) Register VGPR1642 contains scalar/constant data. Will try converting to SGPR. Register VGPR1642 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1643) src0(VGPR1642) src1(VGPR1641) // VOP2 Register VGPR1644 contains scalar/constant data. Will try converting to SGPR. Register VGPR1644 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1645) src0(VGPR1643) src1(VGPR1644) // VOP2 Register VGPR1650 contains scalar/constant data. Will try converting to SGPR. Register VGPR1650 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1648) src0(VGPR1650) src1(VGPR1646) // VOP2 Register VGPR1656 contains scalar/constant data. Will try converting to SGPR. Register VGPR1659 contains scalar/constant data. Will try converting to SGPR. Register VGPR1659 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR1659) src1(VGPR1658) Register VGPR1662 contains scalar/constant data. Will try converting to SGPR. Register VGPR1662 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1663) src0(VGPR1662) src1(VGPR1660) // VOP2 Register VGPR1664 contains scalar/constant data. Will try converting to SGPR. Register VGPR1664 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1665) src0(VGPR1664) src1(VGPR1641) // VOP2 Register VGPR1666 contains scalar/constant data. Will try converting to SGPR. Register VGPR1666 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR1667) src0(VGPR1665) src1(VGPR1666) // VOP2 Register VGPR1672 contains scalar/constant data. Will try converting to SGPR. Register VGPR1672 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1670) src0(VGPR1672) src1(VGPR1668) // VOP2 Register VGPR1678 contains scalar/constant data. Will try converting to SGPR. Register VGPR1681 contains scalar/constant data. Will try converting to SGPR. Register VGPR1681 can't be converted to SGPR, because the following instruction can't be converted: V_CMP_LE_F32 src0(VGPR1681) src1(VGPR1680) Register VGPR1684 contains scalar/constant data. Will try converting to SGPR. Register VGPR1684 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1685) src0(VGPR1684) src1(VGPR1682) // VOP2 Register VGPR[1690:1692] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1690:1692] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR1693) src0(VGPR1690) src1(VGPR1687) src2(VGPR1693) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR1699 contains scalar/constant data. Will try converting to SGPR. Register VGPR1699 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1696) src0(VGPR1699) src1(VGPR1320) // VOP2 Register VGPR1712 contains scalar/constant data. Will try converting to SGPR. Register VGPR1712 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1713) src0(VGPR1712) src1(VGPR1711) // VOP2 Register VGPR1722 contains scalar/constant data. Will try converting to SGPR. Register VGPR1722 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1723) src0(VGPR1722) src1(VGPR1723) // VOP2 Register VGPR[26:27] contains scalar/constant data. Will try converting to SGPR. Register VGPR29 contains scalar/constant data. Will try converting to SGPR. Register VGPR31 contains scalar/constant data. Will try converting to SGPR. Register VGPR34 contains scalar/constant data. Will try converting to SGPR. Register VGPR36 contains scalar/constant data. Will try converting to SGPR. Register VGPR[40:42] contains scalar/constant data. Will try converting to SGPR. Register VGPR44 contains scalar/constant data. Will try converting to SGPR. Register VGPR56 contains scalar/constant data. Will try converting to SGPR. Register VGPR[57:59] contains scalar/constant data. Will try converting to SGPR. Register VGPR61 contains scalar/constant data. Will try converting to SGPR. Register VGPR[62:64] contains scalar/constant data. Will try converting to SGPR. Register VGPR66 contains scalar/constant data. Will try converting to SGPR. Register VGPR[67:69] contains scalar/constant data. Will try converting to SGPR. Register VGPR[70:72] contains scalar/constant data. Will try converting to SGPR. Register VGPR74 contains scalar/constant data. Will try converting to SGPR. Register VGPR[75:77] contains scalar/constant data. Will try converting to SGPR. Register VGPR79 contains scalar/constant data. Will try converting to SGPR. Register VGPR[80:82] contains scalar/constant data. Will try converting to SGPR. Register VGPR84 contains scalar/constant data. Will try converting to SGPR. Register VGPR[85:87] contains scalar/constant data. Will try converting to SGPR. Register VGPR[88:90] contains scalar/constant data. Will try converting to SGPR. Register VGPR129 contains scalar/constant data. Will try converting to SGPR. Register VGPR130 contains scalar/constant data. Will try converting to SGPR. Register VGPR131 contains scalar/constant data. Will try converting to SGPR. Register VGPR195 contains scalar/constant data. Will try converting to SGPR. Register VGPR209 contains scalar/constant data. Will try converting to SGPR. Register VGPR210 contains scalar/constant data. Will try converting to SGPR. Register VGPR224 contains scalar/constant data. Will try converting to SGPR. Register VGPR261 contains scalar/constant data. Will try converting to SGPR. Register VGPR386 contains scalar/constant data. Will try converting to SGPR. Register VGPR387 contains scalar/constant data. Will try converting to SGPR. Register VGPR413 contains scalar/constant data. Will try converting to SGPR. Register VGPR516 contains scalar/constant data. Will try converting to SGPR. Register VGPR517 contains scalar/constant data. Will try converting to SGPR. Register VGPR518 contains scalar/constant data. Will try converting to SGPR. Register VGPR583 contains scalar/constant data. Will try converting to SGPR. Register VGPR584 contains scalar/constant data. Will try converting to SGPR. Register VGPR585 contains scalar/constant data. Will try converting to SGPR. Register VGPR742 contains scalar/constant data. Will try converting to SGPR. Register VGPR754 contains scalar/constant data. Will try converting to SGPR. Register VGPR755 contains scalar/constant data. Will try converting to SGPR. Register VGPR756 contains scalar/constant data. Will try converting to SGPR. Register VGPR792 contains scalar/constant data. Will try converting to SGPR. Register VGPR822 contains scalar/constant data. Will try converting to SGPR. Register VGPR843 contains scalar/constant data. Will try converting to SGPR. Register VGPR929 contains scalar/constant data. Will try converting to SGPR. Register VGPR962 contains scalar/constant data. Will try converting to SGPR. Register VGPR970 contains scalar/constant data. Will try converting to SGPR. Register VGPR971 contains scalar/constant data. Will try converting to SGPR. Register VGPR997 contains scalar/constant data. Will try converting to SGPR. Register VGPR1031 contains scalar/constant data. Will try converting to SGPR. Register VGPR[1048:1050] contains scalar/constant data. Will try converting to SGPR. Register VGPR1052 contains scalar/constant data. Will try converting to SGPR. Register VGPR1059 contains scalar/constant data. Will try converting to SGPR. Register VGPR1060 contains scalar/constant data. Will try converting to SGPR. Register VGPR[1074:1076] contains scalar/constant data. Will try converting to SGPR. Register VGPR1081 contains scalar/constant data. Will try converting to SGPR. Register VGPR1082 contains scalar/constant data. Will try converting to SGPR. Register VGPR1083 contains scalar/constant data. Will try converting to SGPR. Register VGPR1092 contains scalar/constant data. Will try converting to SGPR. Register VGPR1093 contains scalar/constant data. Will try converting to SGPR. Register VGPR1094 contains scalar/constant data. Will try converting to SGPR. Register VGPR1103 contains scalar/constant data. Will try converting to SGPR. Register VGPR1104 contains scalar/constant data. Will try converting to SGPR. Register VGPR1105 contains scalar/constant data. Will try converting to SGPR. Register VGPR1131 contains scalar/constant data. Will try converting to SGPR. Register VGPR1138 contains scalar/constant data. Will try converting to SGPR. Register VGPR1145 contains scalar/constant data. Will try converting to SGPR. Register VGPR1146 contains scalar/constant data. Will try converting to SGPR. Register VGPR1178 contains scalar/constant data. Will try converting to SGPR. Register VGPR1506 contains scalar/constant data. Will try converting to SGPR. Register VGPR1596 contains scalar/constant data. Will try converting to SGPR. Register VGPR1597 contains scalar/constant data. Will try converting to SGPR. Register VGPR1656 contains scalar/constant data. Will try converting to SGPR. Register VGPR1678 contains scalar/constant data. Will try converting to SGPR. No need to convert VGPR56 because it's only used for VGPR comparisons. No need to convert VGPR61 because it's only used for VGPR comparisons. No need to convert VGPR66 because it's only used for VGPR comparisons. No need to convert VGPR74 because it's only used for VGPR comparisons. No need to convert VGPR79 because it's only used for VGPR comparisons. No need to convert VGPR84 because it's only used for VGPR comparisons. No need to convert VGPR210 because it's only used for VGPR comparisons. No need to convert VGPR387 because it's only used for VGPR comparisons. No need to convert VGPR1031 because it's only used for VGPR comparisons. No need to convert VGPR1052 because it's only used for VGPR comparisons. No need to convert VGPR1131 because it's only used for VGPR comparisons. No need to convert VGPR1138 because it's only used for VGPR comparisons. No need to convert VGPR1506 because it's only used for VGPR comparisons. Converting VGPR[26:27] to SGPR, and adjusting instructions. Converting VGPR29 to SGPR, and adjusting instructions. Converting VGPR31 to SGPR, and adjusting instructions. Converting VGPR34 to SGPR, and adjusting instructions. Converting VGPR36 to SGPR, and adjusting instructions. Converting VGPR[40:42] to SGPR, and adjusting instructions. Converting VGPR44 to SGPR, and adjusting instructions. Converting VGPR[57:59] to SGPR, and adjusting instructions. Converting VGPR[62:64] to SGPR, and adjusting instructions. Converting VGPR[67:69] to SGPR, and adjusting instructions. Converting VGPR[70:72] to SGPR, and adjusting instructions. Converting VGPR[75:77] to SGPR, and adjusting instructions. Converting VGPR[80:82] to SGPR, and adjusting instructions. Converting VGPR[85:87] to SGPR, and adjusting instructions. Converting VGPR[88:90] to SGPR, and adjusting instructions. Converting VGPR129 to SGPR, and adjusting instructions. Converting VGPR130 to SGPR, and adjusting instructions. Converting VGPR131 to SGPR, and adjusting instructions. Converting VGPR195 to SGPR, and adjusting instructions. Converting VGPR209 to SGPR, and adjusting instructions. Converting VGPR224 to SGPR, and adjusting instructions. Converting VGPR261 to SGPR, and adjusting instructions. Converting VGPR386 to SGPR, and adjusting instructions. Converting VGPR413 to SGPR, and adjusting instructions. Converting VGPR516 to SGPR, and adjusting instructions. Converting VGPR517 to SGPR, and adjusting instructions. Converting VGPR518 to SGPR, and adjusting instructions. Converting VGPR583 to SGPR, and adjusting instructions. Converting VGPR584 to SGPR, and adjusting instructions. Converting VGPR585 to SGPR, and adjusting instructions. Converting VGPR742 to SGPR, and adjusting instructions. Converting VGPR754 to SGPR, and adjusting instructions. Converting VGPR755 to SGPR, and adjusting instructions. Converting VGPR756 to SGPR, and adjusting instructions. Converting VGPR792 to SGPR, and adjusting instructions. Converting VGPR822 to SGPR, and adjusting instructions. Converting VGPR843 to SGPR, and adjusting instructions. Converting VGPR929 to SGPR, and adjusting instructions. Converting VGPR962 to SGPR, and adjusting instructions. Converting VGPR970 to SGPR, and adjusting instructions. Converting VGPR971 to SGPR, and adjusting instructions. Converting VGPR997 to SGPR, and adjusting instructions. Converting VGPR[1048:1050] to SGPR, and adjusting instructions. Converting VGPR1059 to SGPR, and adjusting instructions. Converting VGPR1060 to SGPR, and adjusting instructions. Converting VGPR[1074:1076] to SGPR, and adjusting instructions. Converting VGPR1081 to SGPR, and adjusting instructions. Converting VGPR1082 to SGPR, and adjusting instructions. Converting VGPR1083 to SGPR, and adjusting instructions. Converting VGPR1092 to SGPR, and adjusting instructions. Converting VGPR1093 to SGPR, and adjusting instructions. Converting VGPR1094 to SGPR, and adjusting instructions. Converting VGPR1103 to SGPR, and adjusting instructions. Converting VGPR1104 to SGPR, and adjusting instructions. Converting VGPR1105 to SGPR, and adjusting instructions. Converting VGPR1145 to SGPR, and adjusting instructions. Converting VGPR1146 to SGPR, and adjusting instructions. Converting VGPR1178 to SGPR, and adjusting instructions. Converting VGPR1596 to SGPR, and adjusting instructions. Converting VGPR1597 to SGPR, and adjusting instructions. Converting VGPR1656 to SGPR, and adjusting instructions. Converting VGPR1678 to SGPR, and adjusting instructions. VGPR=>SGPR conversions done. Register lifetime ranges REG NAME START END SGPR[0:1] 0 4795 fixed SGPR2 0 4795 fixed SGPR3 0 4795 fixed SGPR[4:5] 0 4795 fixed SGPR[6:7] 0 4795 fixed SGPR8 0 4795 fixed SGPR[10:11] 0 4795 keep-active SGPR12 0 4795 keep-active SGPR13 0 4795 keep-active SGPR[14:15] 0 4795 keep-active SGPR[16:17] 0 4795 keep-active SGPR18 0 4795 keep-active SGPR19 0 4795 keep-active SGPR[20:21] 68 180 SGPR[22:23] 76 81 SGPR[24:25] 78 179 SGPR[26:27] 104 109 SGPR[28:29] 106 173 SGPR[30:31] 132 137 SGPR[32:33] 134 167 SGPR[34:36] 184 186 SGPR[38:39] 0 4795 keep-active SGPR40 0 4795 keep-active SGPR41 0 4795 keep-active SGPR[42:43] 190 302 SGPR[44:45] 198 203 SGPR[46:47] 200 301 SGPR[48:49] 226 231 SGPR[50:51] 228 295 SGPR[52:53] 254 259 SGPR[54:55] 256 289 SGPR[56:58] 306 308 SGPR[60:61] 0 4795 keep-active SGPR62 0 4795 keep-active SGPR63 0 4795 keep-active SGPR[64:65] 312 312 SGPR[66:67] 0 4795 keep-active SGPR68 0 4795 keep-active SGPR69 0 4795 keep-active SGPR[70:71] 333 333 SGPR[72:73] 0 4795 keep-active SGPR[74:75] 0 4795 keep-active SGPR[76:77] 0 4795 keep-active SGPR[78:79] 0 4795 keep-active SGPR[80:81] 0 4795 keep-active SGPR[82:83] 0 4795 keep-active SGPR[84:85] 0 4795 keep-active SGPR[86:87] 0 4795 keep-active SGPR[88:89] 0 4795 keep-active SGPR90 0 4795 keep-active SGPR91 0 4795 keep-active SGPR[92:93] 575 575 SGPR[94:95] 0 4795 keep-active SGPR[96:97] 0 4795 keep-active SGPR98 0 4795 keep-active SGPR99 0 4795 keep-active SGPR[100:101] 610 610 SGPR[102:103] 0 4795 keep-active SGPR[104:105] 0 4795 keep-active SGPR106 0 4795 keep-active SGPR107 0 4795 keep-active SGPR[108:109] 0 4795 keep-active SGPR[110:111] 0 4795 keep-active SGPR[112:113] 0 4795 keep-active SGPR[114:115] 0 4795 keep-active SGPR[116:117] 657 660 SGPR[118:119] 0 4795 keep-active SGPR[120:121] 0 4795 keep-active SGPR122 0 4795 keep-active SGPR123 0 4795 keep-active SGPR124 0 4795 keep-active SGPR[126:127] 730 730 SGPR[128:129] 0 4795 keep-active SGPR130 0 4795 keep-active SGPR131 0 4795 keep-active SGPR[132:133] 799 799 SGPR[134:135] 0 4795 keep-active SGPR136 0 4795 keep-active SGPR137 0 4795 keep-active SGPR138 0 4795 keep-active SGPR[140:141] 907 907 SGPR[142:143] 0 4795 keep-active SGPR[144:145] 0 4795 keep-active SGPR[146:147] 0 4795 keep-active SGPR[148:149] 0 4795 keep-active SGPR[150:151] 0 4795 keep-active SGPR[152:153] 0 4795 keep-active SGPR154 0 4795 keep-active SGPR155 0 4795 keep-active SGPR[156:157] 1093 1093 SGPR[158:159] 0 4795 keep-active SGPR[160:161] 0 4795 keep-active SGPR162 0 4795 keep-active SGPR163 0 4795 keep-active SGPR164 0 4795 keep-active SGPR[166:167] 0 4795 keep-active SGPR[168:169] 0 4795 keep-active SGPR[170:171] 0 4795 keep-active SGPR[172:173] 0 4795 keep-active SGPR[174:175] 1151 1154 SGPR[176:177] 0 4795 keep-active SGPR[178:179] 0 4795 keep-active SGPR180 0 4795 keep-active SGPR181 0 4795 keep-active SGPR182 0 4795 keep-active SGPR[184:185] 1253 1253 SGPR[186:187] 0 4795 keep-active SGPR[188:189] 0 4795 keep-active SGPR[190:191] 0 4795 keep-active SGPR192 0 4795 keep-active SGPR193 0 4795 keep-active SGPR194 0 4795 keep-active SGPR195 0 4795 keep-active SGPR[196:197] 0 4795 keep-active SGPR[198:199] 1373 1381 SGPR[200:201] 1384 1392 SGPR[202:203] 1395 1403 SGPR[204:205] 1423 1431 SGPR[206:207] 0 4795 keep-active SGPR[208:209] 0 4795 keep-active SGPR[210:211] 1488 1525 SGPR[212:213] 1499 1521 SGPR[214:215] 0 4795 keep-active SGPR[216:217] 0 4795 keep-active SGPR[218:219] 0 4795 keep-active SGPR220 0 4795 keep-active SGPR221 0 4795 keep-active SGPR[222:223] 1682 1760 SGPR[224:225] 1746 1759 SGPR[226:227] 0 4795 keep-active SGPR[228:229] 0 4795 keep-active SGPR[230:231] 0 4795 keep-active SGPR232 0 4795 keep-active SGPR233 0 4795 keep-active SGPR[234:235] 0 4795 keep-active SGPR[236:237] 0 4795 keep-active SGPR[238:239] 0 4795 keep-active SGPR[240:241] 2156 2193 SGPR[242:243] 2167 2189 SGPR[244:245] 0 4795 keep-active SGPR[246:247] 0 4795 keep-active SGPR[248:249] 2294 2331 SGPR[250:251] 2305 2327 SGPR[252:253] 2374 2411 SGPR[254:255] 2385 2407 SGPR[256:257] 2424 2461 SGPR[258:259] 2435 2457 SGPR[260:261] 2476 2513 SGPR[262:263] 2487 2509 SGPR[264:265] 2526 2563 SGPR[266:267] 2537 2559 SGPR[268:269] 0 4795 keep-active SGPR270 0 4795 keep-active SGPR271 0 4795 keep-active SGPR[272:273] 2610 2610 SGPR[274:275] 0 4795 keep-active SGPR276 0 4795 keep-active SGPR277 0 4795 keep-active SGPR[278:279] 2648 2648 SGPR[280:281] 0 4795 keep-active SGPR[282:283] 0 4795 keep-active SGPR284 0 4795 keep-active SGPR285 0 4795 keep-active SGPR[286:287] 2763 2763 SGPR[288:289] 0 4795 keep-active SGPR290 0 4795 keep-active SGPR291 0 4795 keep-active SGPR292 0 4795 keep-active SGPR293 0 4795 keep-active SGPR294 0 4795 keep-active SGPR[296:297] 0 4795 keep-active SGPR[298:299] 0 4795 keep-active SGPR[300:301] 0 4795 keep-active SGPR[302:303] 0 4795 keep-active SGPR[304:305] 2812 2815 SGPR[306:307] 0 4795 keep-active SGPR[308:309] 2862 2867 SGPR[310:311] 2864 2885 SGPR[312:313] 2891 2896 SGPR[314:315] 2893 2907 SGPR[316:317] 0 4795 keep-active SGPR[318:319] 0 4795 keep-active SGPR[320:321] 0 4795 keep-active SGPR[322:323] 0 4795 keep-active SGPR[324:325] 3100 3105 SGPR[326:327] 0 4795 keep-active SGPR[328:329] 3128 3133 SGPR[330:331] 0 4795 keep-active SGPR[332:333] 0 4795 keep-active SGPR[334:335] 3220 3257 SGPR[336:337] 3231 3253 SGPR[338:339] 3319 3356 SGPR[340:341] 3330 3352 SGPR[342:343] 0 4795 keep-active SGPR[344:345] 3532 3569 SGPR[346:347] 3543 3565 SGPR[348:349] 0 4795 keep-active SGPR350 3632 3635 SGPR[352:354] 3641 3647 SGPR[356:357] 0 4795 keep-active SGPR[358:359] 0 4795 keep-active SGPR[360:361] 0 4795 keep-active SGPR[362:363] 3724 3761 SGPR[364:365] 3735 3757 SGPR366 3903 3913 SGPR367 3907 3910 SGPR[368:369] 0 4795 keep-active SGPR[370:371] 0 4795 keep-active SGPR[372:373] 3951 3988 SGPR[374:375] 3962 3984 SGPR[376:377] 0 4795 keep-active SGPR[378:379] 4114 4119 SGPR[380:381] 4117 4119 SGPR[382:383] 4119 4124 SGPR[384:385] 0 4795 keep-active SGPR[386:387] 4158 4171 SGPR[388:389] 4181 4194 SGPR[390:391] 0 4795 keep-active SGPR[392:393] 0 4795 keep-active SGPR[394:395] 0 4795 keep-active SGPR[396:397] 0 4795 keep-active SGPR[398:399] 4428 4465 SGPR[400:401] 4439 4461 SGPR402 4502 4512 SGPR403 4506 4509 SGPR[404:405] 0 4795 keep-active SGPR[406:407] 4559 4596 SGPR[408:409] 4570 4592 SGPR[410:411] 0 4795 keep-active SGPR[412:413] 4641 4678 SGPR[414:415] 4652 4674 SGPR[416:417] 6 9 SGPR418 11 12 SGPR419 14 15 SGPR420 19 20 SGPR421 22 23 SGPR[422:424] 25 30 SGPR425 32 33 SGPR[426:428] 86 92 SGPR[429:431] 114 120 SGPR[432:434] 142 148 SGPR[435:437] 156 162 SGPR[438:440] 208 214 SGPR[441:443] 236 242 SGPR[444:446] 264 270 SGPR[447:449] 278 284 SGPR450 371 372 SGPR451 373 374 SGPR452 375 376 SGPR453 589 590 SGPR454 641 642 SGPR455 712 713 SGPR456 838 839 SGPR457 1135 1136 SGPR458 1235 1236 SGPR459 1559 1560 SGPR460 1561 1562 SGPR461 1563 1564 SGPR462 1702 1703 SGPR463 1704 1705 SGPR464 1706 1707 SGPR465 2043 2044 SGPR466 2069 2070 SGPR467 2071 2072 SGPR468 2073 2074 SGPR469 2135 2136 SGPR470 2232 2233 SGPR471 2275 2276 SGPR472 2638 2639 SGPR473 2706 2707 SGPR474 2722 2723 SGPR475 2724 2725 SGPR476 0 4795 keep-active SGPR[477:479] 2872 2878 SGPR480 2932 2933 SGPR481 2933 2935 SGPR[482:484] 2965 2970 SGPR485 2985 2986 SGPR486 2987 2988 SGPR487 2989 2990 SGPR488 3011 3012 SGPR489 3013 3014 SGPR490 3015 3016 SGPR491 3037 3038 SGPR492 3039 3040 SGPR493 3041 3042 SGPR494 3144 3145 SGPR495 3146 3147 SGPR496 3200 3201 SGPR497 4365 4366 SGPR498 4367 4368 SGPR499 4539 4540 SGPR500 4621 4622 VGPR[0:1] 0 4795 fixed VGPR[0:1] 0 4795 fixed VGPR[4:5] 0 4795 fixed VGPR[6:7] 0 4795 fixed VGPR[8:9] 0 4795 fixed VGPR[10:11] 0 4795 fixed VGPR12 0 4795 fixed VGPR[2:5] 0 4795 fixed VGPR17 0 4795 fixed VGPR[18:21] 0 4795 keep-active VGPR[22:23] 0 4795 keep-active VGPR[24:25] 0 4795 keep-active VGPR28 0 4795 keep-active VGPR30 0 4795 keep-active VGPR32 0 4795 keep-active VGPR33 0 4795 keep-active VGPR35 0 4795 keep-active VGPR[37:39] 0 4795 keep-active VGPR43 0 4795 keep-active VGPR[45:48] 35 41 VGPR[49:50] 40 44 VGPR[51:54] 56 63 VGPR55 73 76 VGPR56 75 76 VGPR60 101 104 VGPR61 103 104 VGPR65 129 132 VGPR66 131 132 VGPR73 195 198 VGPR74 197 198 VGPR78 223 226 VGPR79 225 226 VGPR83 251 254 VGPR84 253 254 VGPR91 317 319 VGPR92 319 324 VGPR93 323 324 VGPR94 324 326 VGPR95 326 329 VGPR[96:98] 0 4795 keep-active VGPR99 0 4795 keep-active VGPR100 0 4795 keep-active VGPR101 0 4795 keep-active VGPR102 0 4795 keep-active VGPR103 0 4795 keep-active VGPR104 0 4795 keep-active VGPR105 0 4795 keep-active VGPR106 0 4795 keep-active VGPR[107:109] 338 344 VGPR[110:112] 342 402 VGPR[113:115] 347 353 VGPR[116:118] 351 357 VGPR[119:121] 361 384 VGPR[122:124] 367 380 VGPR125 366 369 VGPR[126:128] 372 380 VGPR[132:134] 378 384 VGPR[135:137] 382 388 VGPR138 391 399 VGPR139 394 397 VGPR140 396 397 VGPR141 397 399 VGPR142 399 407 VGPR143 402 405 VGPR144 404 405 VGPR145 405 407 VGPR146 0 4795 keep-active VGPR147 409 410 VGPR148 410 412 VGPR149 0 4795 keep-active VGPR150 423 424 VGPR151 424 426 VGPR152 0 4795 keep-active VGPR153 438 442 VGPR154 0 4795 keep-active VGPR155 444 445 VGPR156 445 447 VGPR157 0 4795 keep-active VGPR158 458 459 VGPR159 459 461 VGPR160 0 4795 keep-active VGPR161 473 477 VGPR162 475 484 VGPR163 480 484 VGPR164 0 4795 keep-active VGPR165 486 487 VGPR166 487 489 VGPR167 0 4795 keep-active VGPR168 500 501 VGPR169 501 503 VGPR170 0 4795 keep-active VGPR171 515 519 VGPR172 0 4795 keep-active VGPR173 521 522 VGPR174 522 524 VGPR175 0 4795 keep-active VGPR176 535 536 VGPR177 536 538 VGPR178 0 4795 keep-active VGPR179 550 554 VGPR180 552 561 VGPR181 557 561 VGPR182 559 568 VGPR183 564 568 VGPR184 566 571 VGPR[185:187] 0 4795 keep-active VGPR[188:189] 580 585 VGPR190 583 587 VGPR191 585 588 VGPR[192:194] 587 594 VGPR196 0 4795 keep-active VGPR[197:199] 0 4795 keep-active VGPR[200:202] 615 621 VGPR203 0 4795 keep-active VGPR204 0 4795 keep-active VGPR205 0 4795 keep-active VGPR[206:208] 0 4795 keep-active VGPR210 656 657 VGPR211 668 670 VGPR212 0 4795 keep-active VGPR[213:215] 673 679 VGPR[216:218] 677 683 VGPR219 0 4795 keep-active VGPR220 694 695 VGPR221 695 699 VGPR222 697 702 VGPR223 702 704 VGPR225 713 715 VGPR226 735 737 VGPR227 737 745 VGPR228 743 745 VGPR229 745 760 VGPR230 748 750 VGPR231 750 758 VGPR232 756 758 VGPR233 758 760 VGPR234 760 790 VGPR235 763 765 VGPR236 765 773 VGPR237 771 773 VGPR238 773 788 VGPR239 776 778 VGPR240 778 786 VGPR241 784 786 VGPR242 786 788 VGPR243 788 791 VGPR[244:245] 790 795 VGPR[246:247] 804 812 VGPR[248:249] 807 812 VGPR[250:251] 809 814 VGPR[252:253] 811 818 VGPR254 822 824 VGPR255 824 827 VGPR256 826 828 VGPR257 827 831 VGPR258 831 852 VGPR259 835 841 VGPR260 839 841 VGPR262 841 843 VGPR263 843 846 VGPR264 845 847 VGPR265 846 850 VGPR266 850 852 VGPR267 852 855 VGPR268 854 855 VGPR269 855 858 VGPR270 857 859 VGPR271 858 862 VGPR272 862 897 VGPR273 866 868 VGPR274 868 871 VGPR275 870 872 VGPR276 871 875 VGPR277 875 890 VGPR278 879 881 VGPR279 881 884 VGPR280 883 885 VGPR281 884 888 VGPR282 888 890 VGPR283 890 893 VGPR284 892 894 VGPR285 893 897 VGPR286 897 900 VGPR287 899 900 VGPR288 900 903 VGPR[289:290] 0 4795 keep-active VGPR[291:292] 0 4795 keep-active VGPR293 0 4795 keep-active VGPR[294:295] 0 4795 keep-active VGPR[296:297] 0 4795 keep-active VGPR[298:299] 0 4795 keep-active VGPR[300:301] 912 917 VGPR[302:303] 0 4795 keep-active VGPR304 915 917 VGPR[305:306] 919 925 VGPR[307:308] 922 925 VGPR[309:310] 0 4795 keep-active VGPR[311:312] 0 4795 keep-active VGPR313 931 939 VGPR314 934 937 VGPR315 936 937 VGPR316 937 939 VGPR317 0 4795 keep-active VGPR318 942 945 VGPR319 944 945 VGPR320 945 947 VGPR321 947 961 VGPR322 952 955 VGPR323 954 955 VGPR324 955 957 VGPR325 957 962 VGPR[326:327] 961 966 VGPR[328:329] 0 4795 keep-active VGPR330 964 966 VGPR331 0 4795 keep-active VGPR[332:333] 980 983 VGPR[334:335] 982 986 VGPR336 0 4795 keep-active VGPR[337:338] 997 1004 VGPR[339:340] 1000 1004 VGPR[341:342] 1003 1025 VGPR343 1007 1009 VGPR344 1009 1012 VGPR345 1011 1013 VGPR346 1012 1019 VGPR347 1016 1019 VGPR348 1017 1022 VGPR349 1021 1022 VGPR350 0 4795 keep-active VGPR[351:352] 1024 1029 VGPR[353:354] 1028 1032 VGPR355 1027 1029 VGPR[356:357] 1031 1037 VGPR[358:359] 0 4795 keep-active VGPR360 0 4795 keep-active VGPR[361:362] 1063 1067 VGPR363 1062 1064 VGPR364 0 4795 keep-active VGPR365 1078 1079 VGPR366 1079 1082 VGPR367 1081 1082 VGPR368 1082 1084 VGPR369 1084 1086 VGPR370 1086 1089 VGPR371 0 4795 keep-active VGPR[372:374] 0 4795 keep-active VGPR[375:377] 0 4795 keep-active VGPR[378:380] 1114 1127 VGPR381 0 4795 keep-active VGPR382 0 4795 keep-active VGPR[383:384] 0 4795 keep-active VGPR385 0 4795 keep-active VGPR387 1150 1151 VGPR[388:389] 1162 1175 VGPR390 1166 1169 VGPR391 1168 1169 VGPR392 1169 1172 VGPR[393:394] 1171 1175 VGPR[395:396] 1174 1186 VGPR397 1178 1181 VGPR398 1180 1181 VGPR399 1181 1183 VGPR400 1183 1186 VGPR[401:402] 1185 1189 VGPR403 1192 1194 VGPR404 0 4795 keep-active VGPR405 1208 1213 VGPR406 1210 1213 VGPR407 1211 1215 VGPR408 1215 1218 VGPR409 1217 1219 VGPR410 1218 1222 VGPR411 1222 1225 VGPR412 1225 1227 VGPR414 1236 1238 VGPR[415:416] 0 4795 keep-active VGPR417 0 4795 keep-active VGPR[418:419] 0 4795 keep-active VGPR420 0 4795 keep-active VGPR[421:422] 1258 1263 VGPR[423:424] 1262 1266 VGPR425 1261 1263 VGPR426 1269 1271 VGPR427 0 4795 keep-active VGPR[428:429] 1285 1290 VGPR[430:431] 1289 1293 VGPR432 1288 1290 VGPR433 1296 1298 VGPR434 0 4795 keep-active VGPR435 1311 1312 VGPR436 1312 1314 VGPR437 1314 1317 VGPR[438:439] 0 4795 keep-active VGPR440 0 4795 keep-active VGPR[441:442] 0 4795 keep-active VGPR443 0 4795 keep-active VGPR[444:446] 1633 1678 VGPR447 0 4795 keep-active VGPR[448:450] 0 4795 keep-active VGPR[451:453] 1326 1341 VGPR[454:456] 1331 1337 VGPR[457:459] 1335 1341 VGPR460 0 4795 keep-active VGPR461 1345 1394 VGPR462 1349 1383 VGPR463 1351 1366 VGPR464 1352 1366 VGPR465 1353 1367 VGPR466 1354 1368 VGPR467 1355 1369 VGPR468 1356 1370 VGPR469 1357 1378 VGPR470 1358 1389 VGPR[471:474] 1359 1372 VGPR475 1366 1434 VGPR476 1408 1422 VGPR477 1410 1416 VGPR478 1411 1416 VGPR479 1412 1417 VGPR480 1413 1418 VGPR481 1414 1421 VGPR482 1415 1421 VGPR483 1416 1435 VGPR[484:485] 1434 1439 VGPR[486:487] 1438 1442 VGPR488 1437 1439 VGPR489 0 4795 keep-active VGPR[490:492] 1458 1463 VGPR[493:494] 1462 1466 VGPR495 0 4795 keep-active VGPR496 1483 1511 VGPR497 1485 1511 VGPR498 1486 1509 VGPR499 1493 1530 VGPR500 1509 1518 VGPR501 0 4795 keep-active VGPR502 1534 1537 VGPR503 1536 1537 VGPR504 1537 1540 VGPR505 1539 1540 VGPR506 1540 1544 VGPR507 1542 1544 VGPR508 1543 1545 VGPR509 0 4795 keep-active VGPR[510:512] 0 4795 keep-active VGPR[513:515] 1560 1577 VGPR[519:521] 1566 1576 VGPR[522:524] 1569 1599 VGPR525 1580 1582 VGPR526 1582 1584 VGPR527 1584 1587 VGPR528 1586 1587 VGPR529 1587 1590 VGPR530 1589 1591 VGPR531 1590 1595 VGPR532 1594 1595 VGPR533 1595 1599 VGPR[534:536] 1597 1617 VGPR537 1601 1605 VGPR[538:540] 1603 1618 VGPR[541:543] 1607 1618 VGPR[544:546] 1610 1622 VGPR[547:549] 0 4795 keep-active VGPR550 1637 1638 VGPR551 1638 1643 VGPR[552:554] 1641 1647 VGPR555 1649 1652 VGPR556 1651 1653 VGPR557 1652 1658 VGPR[558:560] 1656 1663 VGPR[561:563] 1661 1668 VGPR564 1660 1663 VGPR[565:567] 1666 1672 VGPR[568:570] 0 4795 keep-active VGPR[571:573] 0 4795 keep-active VGPR574 1688 1691 VGPR575 1690 1691 VGPR576 1691 1695 VGPR[577:579] 1698 1717 VGPR[580:582] 1703 1717 VGPR[586:588] 1709 1721 VGPR[589:591] 0 4795 keep-active VGPR592 1724 1727 VGPR593 1726 1727 VGPR594 1727 1735 VGPR595 1730 1733 VGPR596 1732 1733 VGPR597 1733 1735 VGPR598 1735 1737 VGPR599 1737 1742 VGPR600 1741 1742 VGPR601 1742 1745 VGPR602 1744 1745 VGPR603 1751 1762 VGPR[604:606] 1765 1772 VGPR[607:609] 1770 1776 VGPR610 1769 1772 VGPR611 0 4795 keep-active VGPR612 1787 1788 VGPR613 1788 1791 VGPR614 0 4795 keep-active VGPR[615:617] 1794 1801 VGPR[618:620] 1799 1805 VGPR621 1798 1801 VGPR622 0 4795 keep-active VGPR623 1816 1817 VGPR624 1817 1820 VGPR625 1819 1821 VGPR626 1820 1833 VGPR627 1825 1828 VGPR628 1827 1828 VGPR629 1828 1831 VGPR630 1830 1831 VGPR631 1831 1833 VGPR632 1833 1835 VGPR633 1835 1966 VGPR634 1838 1850 VGPR635 1841 1843 VGPR636 1843 1848 VGPR637 1847 1848 VGPR638 1848 1850 VGPR639 1850 1857 VGPR640 1852 1857 VGPR641 1853 1859 VGPR[642:644] 1862 1867 VGPR[645:646] 1866 1880 VGPR[647:648] 1869 1880 VGPR[649:650] 1871 1885 VGPR[651:652] 1882 1885 VGPR[653:654] 1884 1894 VGPR[655:657] 1888 1893 VGPR[658:660] 1892 1899 VGPR661 1902 1905 VGPR662 1904 1905 VGPR663 1905 1913 VGPR664 1908 1911 VGPR665 1910 1911 VGPR666 1911 1913 VGPR667 1913 1915 VGPR668 1915 1919 VGPR669 1919 1921 VGPR670 1921 1927 VGPR671 1923 1926 VGPR672 1924 1927 VGPR673 1925 1929 VGPR[674:676] 1932 1938 VGPR677 1936 1942 VGPR678 1942 1951 VGPR679 1946 1948 VGPR680 1948 1954 VGPR681 1950 1951 VGPR682 1951 1956 VGPR683 1953 1954 VGPR684 1954 1957 VGPR[685:686] 1956 1960 VGPR687 1959 1964 VGPR688 1963 1964 VGPR689 1964 1966 VGPR690 1966 1969 VGPR691 1968 1969 VGPR692 1969 1972 VGPR[693:695] 0 4795 keep-active VGPR[696:698] 0 4795 keep-active VGPR[699:701] 0 4795 keep-active VGPR[702:704] 0 4795 keep-active VGPR705 1982 1985 VGPR706 1984 1985 VGPR707 1985 1989 VGPR[708:709] 1992 1996 VGPR[710:711] 0 4795 keep-active VGPR[712:713] 1999 2003 VGPR[714:715] 2002 2008 VGPR[716:717] 2005 2008 VGPR[718:719] 0 4795 keep-active VGPR720 2011 2016 VGPR[721:722] 2015 2027 VGPR[723:724] 2013 2016 VGPR725 2019 2024 VGPR[726:727] 2023 2027 VGPR[728:729] 2021 2024 VGPR[730:731] 2026 2031 VGPR[732:733] 0 4795 keep-active VGPR734 2029 2031 VGPR[735:736] 2034 2039 VGPR737 2037 2041 VGPR738 2039 2042 VGPR[739:741] 2041 2048 VGPR743 0 4795 keep-active VGPR744 2059 2060 VGPR745 2060 2063 VGPR746 2062 2063 VGPR747 2063 2067 VGPR[748:750] 2065 2087 VGPR[751:753] 2070 2087 VGPR[757:759] 2076 2086 VGPR[760:762] 0 4795 keep-active VGPR[763:764] 2090 2102 VGPR765 2089 2091 VGPR[766:767] 2094 2099 VGPR[768:769] 2098 2102 VGPR770 2097 2099 VGPR[771:772] 2101 2127 VGPR[773:774] 2105 2109 VGPR[775:776] 2108 2113 VGPR[777:778] 2112 2117 VGPR779 2111 2113 VGPR[780:781] 2115 2124 VGPR[782:783] 2123 2127 VGPR784 2122 2124 VGPR[785:786] 2126 2131 VGPR787 2129 2133 VGPR788 2131 2134 VGPR[789:791] 2133 2140 VGPR793 0 4795 keep-active VGPR794 2151 2179 VGPR795 2153 2179 VGPR796 2154 2177 VGPR797 2161 2196 VGPR798 2177 2186 VGPR799 2196 2200 VGPR[800:802] 2198 2216 VGPR[803:805] 2202 2215 VGPR[806:808] 2205 2216 VGPR[809:811] 0 4795 keep-active VGPR[812:813] 2219 2224 VGPR[814:815] 2223 2228 VGPR816 2222 2224 VGPR817 2226 2230 VGPR818 2228 2231 VGPR[819:821] 2230 2237 VGPR823 0 4795 keep-active VGPR824 2248 2249 VGPR825 2249 2252 VGPR826 2251 2252 VGPR827 2252 2256 VGPR[828:830] 2254 2260 VGPR[831:833] 0 4795 keep-active VGPR[834:835] 2263 2267 VGPR[836:837] 2266 2271 VGPR838 2269 2273 VGPR839 2271 2274 VGPR[840:842] 2273 2280 VGPR844 0 4795 keep-active VGPR845 2291 2317 VGPR846 2292 2315 VGPR847 2299 2336 VGPR848 2315 2324 VGPR[849:851] 2334 2341 VGPR[852:854] 2339 2345 VGPR855 2338 2341 VGPR[856:858] 2343 2595 VGPR[859:861] 2347 2362 VGPR[862:864] 2351 2362 VGPR[865:867] 2354 2579 VGPR868 2364 2365 VGPR869 2365 2397 VGPR870 2368 2370 VGPR871 2370 2397 VGPR872 2372 2395 VGPR873 2379 2464 VGPR874 2395 2404 VGPR875 2414 2415 VGPR876 2415 2447 VGPR877 2418 2420 VGPR878 2420 2447 VGPR879 2422 2445 VGPR880 2429 2464 VGPR881 2445 2454 VGPR882 2464 2582 VGPR883 2466 2467 VGPR884 2467 2499 VGPR885 2470 2472 VGPR886 2472 2499 VGPR887 2474 2497 VGPR888 2481 2566 VGPR889 2497 2506 VGPR890 2516 2517 VGPR891 2517 2549 VGPR892 2520 2522 VGPR893 2522 2549 VGPR894 2524 2547 VGPR895 2531 2566 VGPR896 2547 2556 VGPR897 2566 2582 VGPR[898:900] 2568 2580 VGPR[901:903] 2572 2596 VGPR904 2582 2586 VGPR[905:907] 2584 2596 VGPR[908:910] 2588 2601 VGPR[911:913] 2599 2606 VGPR914 2598 2601 VGPR915 2615 2618 VGPR916 2617 2618 VGPR917 2618 2636 VGPR918 2621 2624 VGPR919 2623 2624 VGPR920 2624 2626 VGPR921 2626 2631 VGPR922 2630 2631 VGPR923 2631 2634 VGPR924 2633 2634 VGPR925 2634 2637 VGPR[926:928] 2636 2644 VGPR[930:932] 2714 2759 VGPR933 0 4795 keep-active VGPR934 2653 2656 VGPR935 2656 2658 VGPR[936:938] 0 4795 keep-active VGPR[939:941] 2669 2674 VGPR[942:944] 2672 2712 VGPR945 2677 2680 VGPR946 2679 2680 VGPR947 2680 2682 VGPR948 2682 2687 VGPR949 2686 2687 VGPR950 2687 2705 VGPR951 2690 2693 VGPR952 2692 2693 VGPR953 2693 2695 VGPR954 2695 2700 VGPR955 2699 2700 VGPR956 2700 2703 VGPR957 2702 2703 VGPR958 2703 2708 VGPR[959:961] 2705 2712 VGPR[963:965] 2710 2716 VGPR[966:967] 2719 2732 VGPR[968:969] 2723 2732 VGPR[972:973] 2727 2735 VGPR[974:975] 2734 2739 VGPR[976:977] 2738 2744 VGPR978 2737 2739 VGPR[979:980] 2741 2744 VGPR[981:982] 2743 2749 VGPR[983:985] 2747 2753 VGPR986 2768 2771 VGPR987 2770 2771 VGPR988 2771 2773 VGPR989 2773 2777 VGPR990 2777 2779 VGPR991 2779 2785 VGPR992 2781 2784 VGPR993 2782 2785 VGPR994 2783 2788 VGPR995 2787 2788 VGPR996 2788 2791 VGPR[998:1000] 0 4795 keep-active VGPR[1001:1003] 0 4795 keep-active VGPR[1004:1006] 0 4795 keep-active VGPR[1007:1009] 0 4795 keep-active VGPR[1010:1012] 0 4795 keep-active VGPR[1013:1015] 0 4795 keep-active VGPR[1016:1018] 3280 3393 VGPR[1019:1021] 0 4795 keep-active VGPR[1022:1024] 0 4795 keep-active VGPR[1025:1027] 0 4795 keep-active VGPR[1028:1030] 0 4795 keep-active VGPR1031 2811 2812 VGPR[1032:1034] 2823 2841 VGPR[1035:1037] 2828 2837 VGPR1038 2833 2837 VGPR[1039:1041] 2835 2841 VGPR[1042:1044] 2839 2845 VGPR1045 0 4795 keep-active VGPR1046 2857 2862 VGPR1047 2860 2862 VGPR1051 2888 2891 VGPR1052 2890 2891 VGPR1053 2911 2914 VGPR1054 2913 2914 VGPR1055 2914 2921 VGPR1056 2917 2919 VGPR1057 2919 2921 VGPR1058 2921 2924 VGPR[1061:1063] 2945 2963 VGPR[1064:1066] 2950 2959 VGPR1067 2955 2959 VGPR[1068:1070] 2957 2963 VGPR[1071:1073] 0 4795 keep-active VGPR1077 0 4795 keep-active VGPR[1078:1080] 2986 2994 VGPR[1084:1086] 2992 2998 VGPR1087 0 4795 keep-active VGPR1088 0 4795 keep-active VGPR[1089:1091] 3012 3020 VGPR[1095:1097] 3018 3024 VGPR1098 0 4795 keep-active VGPR1099 0 4795 keep-active VGPR[1100:1102] 3038 3046 VGPR[1106:1108] 3044 3050 VGPR1109 0 4795 keep-active VGPR1110 3061 3065 VGPR[1111:1113] 3063 3073 VGPR1114 3067 3073 VGPR[1115:1117] 0 4795 keep-active VGPR[1118:1120] 0 4795 keep-active VGPR[1121:1123] 3082 3088 VGPR[1124:1126] 3086 3096 VGPR1127 3090 3096 VGPR[1128:1130] 0 4795 keep-active VGPR1131 3099 3100 VGPR1132 3111 3116 VGPR1133 3113 3116 VGPR1134 3114 3118 VGPR1135 3118 3125 VGPR1136 3120 3125 VGPR1137 3121 3128 VGPR1138 3127 3128 VGPR[1139:1140] 3138 3169 VGPR[1141:1142] 3141 3154 VGPR[1143:1144] 3145 3154 VGPR[1147:1148] 3149 3157 VGPR[1149:1150] 3156 3161 VGPR[1151:1152] 3160 3166 VGPR1153 3159 3161 VGPR[1154:1155] 3163 3166 VGPR[1156:1157] 3165 3169 VGPR[1158:1159] 3168 3171 VGPR1160 3170 3175 VGPR1161 3174 3175 VGPR1162 3175 3178 VGPR1163 3177 3179 VGPR1164 3178 3185 VGPR1165 0 4795 keep-active VGPR1166 3184 3185 VGPR1167 0 4795 keep-active VGPR[1168:1169] 3187 3192 VGPR[1170:1171] 3191 3196 VGPR1172 3190 3192 VGPR1173 3194 3198 VGPR1174 3196 3199 VGPR[1175:1177] 3198 3205 VGPR1179 0 4795 keep-active VGPR1180 3216 3217 VGPR1181 3217 3243 VGPR1182 3225 3262 VGPR1183 3241 3250 VGPR[1184:1186] 3260 3278 VGPR[1187:1189] 3264 3277 VGPR[1190:1192] 3267 3278 VGPR[1193:1195] 3270 3282 VGPR1196 3291 3294 VGPR1197 3293 3294 VGPR1198 3294 3306 VGPR1199 3297 3300 VGPR1200 3299 3300 VGPR1201 3300 3302 VGPR1202 3302 3306 VGPR1203 3306 3308 VGPR1204 3308 3312 VGPR1205 3312 3314 VGPR1206 3314 3342 VGPR1207 3316 3342 VGPR1208 3317 3340 VGPR1209 3324 3361 VGPR1210 3340 3349 VGPR[1211:1213] 3359 3377 VGPR[1214:1216] 3363 3376 VGPR[1217:1219] 3366 3377 VGPR[1220:1222] 3369 3381 VGPR[1223:1225] 3391 3410 VGPR1226 3390 3393 VGPR1227 3396 3400 VGPR1228 3400 3402 VGPR1229 3402 3406 VGPR[1230:1232] 3404 3410 VGPR[1233:1235] 3408 3443 VGPR1236 3412 3416 VGPR1237 3416 3418 VGPR1238 3418 3422 VGPR1239 3420 3422 VGPR1240 3421 3423 VGPR1241 3422 3426 VGPR1242 3425 3427 VGPR1243 3426 3432 VGPR[1244:1246] 3430 3439 VGPR[1247:1249] 3434 3439 VGPR[1250:1252] 3437 3443 VGPR[1253:1255] 3441 3470 VGPR[1256:1258] 3446 3452 VGPR[1259:1261] 3450 3456 VGPR1262 3454 3459 VGPR1263 3458 3460 VGPR1264 3459 3464 VGPR1265 3463 3464 VGPR1266 3464 3466 VGPR1267 3466 3470 VGPR[1268:1270] 3468 3474 VGPR[1271:1273] 0 4795 keep-active VGPR[1274:1276] 3508 3583 VGPR1277 3507 3510 VGPR1278 3512 3516 VGPR1279 3516 3518 VGPR1280 3518 3522 VGPR1281 3520 3522 VGPR1282 3521 3523 VGPR1283 3522 3526 VGPR1284 3525 3527 VGPR1285 3526 3555 VGPR1286 3530 3553 VGPR1287 3537 3574 VGPR1288 3553 3562 VGPR[1289:1291] 3572 3579 VGPR[1292:1294] 3577 3583 VGPR1295 3576 3579 VGPR[1296:1298] 3581 3587 VGPR1299 3596 3599 VGPR1300 3598 3599 VGPR1301 3599 3602 VGPR1302 3601 3603 VGPR1303 3602 3609 VGPR1304 3606 3609 VGPR1305 3607 3614 VGPR[1306:1308] 3612 3618 VGPR1309 0 4795 keep-active VGPR1310 0 4795 keep-active VGPR1311 0 4795 keep-active VGPR[1312:1314] 3808 3852 VGPR[1315:1316] 0 4795 keep-active VGPR1317 0 4795 keep-active VGPR1318 0 4795 keep-active VGPR1319 0 4795 keep-active VGPR[1320:1322] 0 4795 keep-active VGPR[1323:1325] 0 4795 keep-active VGPR[1326:1328] 0 4795 keep-active VGPR1329 0 4795 keep-active VGPR1330 0 4795 keep-active VGPR[1331:1332] 0 4795 keep-active VGPR[1333:1335] 0 4795 keep-active VGPR[1336:1337] 0 4795 keep-active VGPR1338 0 4795 keep-active VGPR[1339:1340] 0 4795 keep-active VGPR[1341:1342] 0 4795 keep-active VGPR1343 0 4795 keep-active VGPR[1344:1346] 0 4795 keep-active VGPR[1347:1349] 0 4795 keep-active VGPR[1350:1351] 3638 3654 VGPR[1352:1353] 3646 3654 VGPR[1354:1355] 3649 3658 VGPR[1356:1357] 3657 3663 VGPR1358 3656 3658 VGPR[1359:1360] 3660 3663 VGPR[1361:1362] 3662 3666 VGPR1363 3670 3674 VGPR1364 0 4795 keep-active VGPR1365 3678 3682 VGPR1366 0 4795 keep-active VGPR[1367:1369] 0 4795 keep-active VGPR1370 3696 3697 VGPR1371 3697 3699 VGPR[1372:1374] 0 4795 keep-active VGPR[1375:1377] 0 4795 keep-active VGPR1378 3721 3747 VGPR1379 3722 3745 VGPR1380 3729 3766 VGPR1381 3745 3754 VGPR[1382:1384] 3764 3776 VGPR[1385:1387] 3768 3780 VGPR[1388:1390] 3778 3788 VGPR1391 3782 3788 VGPR[1392:1394] 3786 3864 VGPR[1395:1397] 3790 3798 VGPR[1398:1400] 3793 3806 VGPR1401 3800 3806 VGPR[1402:1404] 3804 3810 VGPR[1405:1407] 3813 3826 VGPR1408 3820 3826 VGPR[1409:1411] 3824 3858 VGPR[1412:1414] 3828 3841 VGPR1415 3835 3841 VGPR[1416:1418] 3839 3845 VGPR1419 3848 3866 VGPR1420 3850 3867 VGPR1421 3852 3868 VGPR1422 3854 3870 VGPR1423 3856 3871 VGPR1424 3858 3872 VGPR1425 3860 3874 VGPR1426 3862 3875 VGPR1427 3864 3876 VGPR[1428:1430] 3866 3880 VGPR[1431:1433] 3870 3883 VGPR[1434:1436] 3874 3886 VGPR[1437:1445] 0 4795 keep-active VGPR[1446:1447] 3890 3896 VGPR1448 3889 3891 VGPR[1449:1450] 3893 3896 VGPR[1451:1452] 0 4795 keep-active VGPR1453 3910 3913 VGPR1454 3911 3918 VGPR1455 3916 3918 VGPR1456 3918 3921 VGPR1457 3923 3924 VGPR1458 3924 3926 VGPR1459 0 4795 keep-active VGPR1460 0 4795 keep-active VGPR1461 3948 3974 VGPR1462 3949 3972 VGPR1463 3956 3993 VGPR1464 3972 3981 VGPR1465 3991 4002 VGPR1466 3996 4000 VGPR1467 3998 4001 VGPR[1468:1470] 4000 4010 VGPR1471 4004 4010 VGPR[1472:1474] 4008 4020 VGPR[1475:1477] 0 4795 keep-active VGPR1478 4023 4025 VGPR1479 4025 4032 VGPR1480 4028 4032 VGPR1481 4030 4035 VGPR1482 4034 4035 VGPR1483 4035 4037 VGPR1484 4040 4043 VGPR1485 4042 4043 VGPR1486 4043 4050 VGPR1487 4046 4050 VGPR1488 4048 4053 VGPR1489 4052 4053 VGPR1490 0 4795 keep-active VGPR[1491:1493] 0 4795 keep-active VGPR[1494:1496] 4091 4097 VGPR[1497:1499] 0 4795 keep-active VGPR1500 4100 4103 VGPR1501 4102 4103 VGPR1502 4103 4107 VGPR1503 4105 4107 VGPR1504 4106 4108 VGPR1505 4107 4110 VGPR1506 4113 4114 VGPR[1507:1508] 4129 4139 VGPR[1509:1510] 4132 4136 VGPR[1511:1512] 4135 4139 VGPR[1513:1514] 4138 4142 VGPR[1515:1516] 0 4795 keep-active VGPR1517 4145 4147 VGPR1518 4150 4176 VGPR1519 4153 4155 VGPR1520 4155 4157 VGPR1521 4163 4174 VGPR1522 4174 4176 VGPR1523 4176 4178 VGPR1524 4178 4180 VGPR1525 4186 4199 VGPR[1526:1528] 4197 4215 VGPR[1529:1531] 4201 4214 VGPR[1532:1534] 4204 4215 VGPR[1535:1537] 4207 4219 VGPR[1538:1539] 4223 4256 VGPR1540 4222 4224 VGPR1541 4227 4230 VGPR1542 4229 4230 VGPR1543 4230 4232 VGPR1544 4232 4237 VGPR1545 4236 4237 VGPR1546 4237 4252 VGPR1547 4240 4243 VGPR1548 4242 4243 VGPR1549 4243 4245 VGPR1550 4245 4250 VGPR1551 4249 4250 VGPR1552 4250 4253 VGPR[1553:1554] 4252 4256 VGPR[1555:1556] 4255 4259 VGPR1557 0 4795 keep-active VGPR1558 4270 4273 VGPR1559 4272 4273 VGPR1560 4273 4276 VGPR1561 4275 4277 VGPR1562 4276 4282 VGPR[1563:1565] 4280 4295 VGPR[1566:1568] 4284 4295 VGPR[1569:1571] 4287 4299 VGPR[1572:1574] 4302 4312 VGPR1575 4306 4312 VGPR[1576:1578] 4310 4312 VGPR[1579:1581] 4314 4323 VGPR[1582:1584] 4321 4326 VGPR1585 4317 4323 VGPR[1586:1587] 4329 4335 VGPR1588 4328 4330 VGPR[1589:1590] 0 4795 keep-active VGPR[1591:1593] 0 4795 keep-active VGPR[1594:1595] 4366 4375 VGPR[1598:1599] 4370 4378 VGPR[1600:1601] 4377 4381 VGPR[1602:1604] 0 4795 keep-active VGPR1605 4384 4387 VGPR[1606:1608] 0 4795 keep-active VGPR[1609:1611] 4402 4409 VGPR1612 4401 4404 VGPR[1613:1615] 4407 4482 VGPR[1616:1617] 4412 4415 VGPR[1618:1619] 4414 4417 VGPR1620 4416 4423 VGPR1621 4421 4451 VGPR1622 4425 4451 VGPR1623 4426 4449 VGPR1624 4433 4470 VGPR1625 4449 4458 VGPR[1626:1628] 4468 4483 VGPR[1629:1631] 4472 4483 VGPR[1632:1634] 4475 4487 VGPR[1635:1637] 4485 4491 VGPR1638 4509 4512 VGPR1639 4510 4515 VGPR1640 4515 4517 VGPR1641 0 4795 keep-active VGPR1642 4520 4521 VGPR1643 4521 4524 VGPR1644 4523 4524 VGPR1645 0 4795 keep-active VGPR[1646:1647] 4526 4531 VGPR[1648:1649] 4530 4535 VGPR1650 4529 4531 VGPR1651 4533 4537 VGPR1652 4535 4538 VGPR[1653:1655] 4537 4544 VGPR1657 0 4795 keep-active VGPR1658 4555 4582 VGPR1659 4557 4580 VGPR1660 4564 4600 VGPR1661 4580 4589 VGPR1662 4599 4600 VGPR1663 0 4795 keep-active VGPR1664 4602 4603 VGPR1665 4603 4606 VGPR1666 4605 4606 VGPR1667 0 4795 keep-active VGPR[1668:1669] 4608 4613 VGPR[1670:1671] 4612 4617 VGPR1672 4611 4613 VGPR1673 4615 4619 VGPR1674 4617 4620 VGPR[1675:1677] 4619 4626 VGPR1679 0 4795 keep-active VGPR1680 4637 4664 VGPR1681 4639 4662 VGPR1682 4646 4682 VGPR1683 4662 4671 VGPR1684 4681 4682 VGPR1685 4682 4684 VGPR1686 4684 4688 VGPR[1687:1689] 4686 4701 VGPR[1690:1692] 4690 4701 VGPR[1693:1695] 4693 4705 VGPR[1696:1698] 4709 4715 VGPR1699 4708 4711 VGPR[1700:1702] 4713 4725 VGPR[1703:1706] 4718 4726 VGPR[1707:1710] 4723 4732 VGPR1711 4735 4738 VGPR1712 4737 4738 VGPR1713 4738 4743 VGPR1714 4741 4743 VGPR1715 4743 4750 VGPR1716 4746 4748 VGPR1717 4748 4750 VGPR1718 4750 4757 VGPR1719 4753 4755 VGPR1720 4755 4757 VGPR1721 4757 4760 VGPR1722 4759 4761 VGPR1723 4760 4776 VGPR[1724:1727] 4765 4772 VGPR[1728:1730] 4770 4776 VGPR[1731:1733] 4774 4786 VGPR[1734:1737] 4779 4787 VGPR[1738:1741] 4784 4793 Register final registers REG NAME START END SGPR[0:1] 0 4795 fixed SGPR2 0 4795 fixed SGPR3 0 4795 fixed SGPR[4:5] 0 4795 fixed SGPR[6:7] 0 4795 fixed SGPR8 0 4795 fixed SGPR9 0 4795 keep-active SGPR[10:11] 0 4795 keep-active SGPR12 0 4795 keep-active SGPR13 0 4795 keep-active SGPR[14:15] 0 4795 keep-active SGPR[16:17] 0 4795 keep-active SGPR18 0 4795 keep-active SGPR19 0 4795 keep-active SGPR[20:21] 0 4795 keep-active SGPR22 0 4795 keep-active SGPR23 0 4795 keep-active SGPR[24:25] 0 4795 keep-active SGPR26 0 4795 keep-active SGPR27 0 4795 keep-active SGPR[28:29] 0 4795 keep-active SGPR30 0 4795 keep-active SGPR31 0 4795 keep-active SGPR[32:33] 0 4795 keep-active SGPR[34:35] 0 4795 keep-active SGPR[36:37] 0 4795 keep-active SGPR[38:39] 0 4795 keep-active SGPR[40:41] 0 4795 keep-active SGPR[42:43] 0 4795 keep-active SGPR[44:45] 0 4795 keep-active SGPR[46:47] 0 4795 keep-active SGPR[48:49] 0 4795 keep-active SGPR50 0 4795 keep-active SGPR51 0 4795 keep-active SGPR[52:53] 0 4795 keep-active SGPR[54:55] 0 4795 keep-active SGPR56 0 4795 keep-active SGPR57 0 4795 keep-active SGPR[58:59] 0 4795 keep-active SGPR[60:61] 0 4795 keep-active SGPR62 0 4795 keep-active SGPR63 0 4795 keep-active SGPR[64:65] 0 4795 keep-active SGPR[66:67] 0 4795 keep-active SGPR[68:69] 0 4795 keep-active SGPR[70:71] 0 4795 keep-active SGPR[72:73] 0 4795 keep-active SGPR[74:75] 0 4795 keep-active SGPR76 0 4795 keep-active SGPR77 0 4795 keep-active SGPR[78:79] 0 4795 keep-active SGPR80 0 4795 keep-active SGPR81 0 4795 keep-active SGPR[82:83] 0 4795 keep-active SGPR84 0 4795 keep-active SGPR85 0 4795 keep-active SGPR86 0 4795 keep-active SGPR87 0 4795 keep-active SGPR[88:89] 0 4795 keep-active SGPR[90:91] 0 4795 keep-active SGPR[92:93] 0 4795 keep-active SGPR[94:95] 0 4795 keep-active SGPR[96:97] 0 4795 keep-active SGPR[98:99] 0 4795 keep-active SGPR100 0 4795 keep-active SGPR101 0 4795 keep-active SGPR[102:103] 0 4795 keep-active SGPR[104:105] 0 4795 keep-active SGPR106 0 4795 keep-active SGPR107 0 4795 keep-active SGPR[108:109] 0 4795 keep-active SGPR[110:111] 0 4795 keep-active SGPR[112:113] 0 4795 keep-active SGPR[114:115] 0 4795 keep-active SGPR[116:117] 0 4795 keep-active SGPR[118:119] 0 4795 keep-active SGPR120 0 4795 keep-active SGPR121 0 4795 keep-active SGPR122 0 4795 keep-active SGPR123 0 4795 keep-active SGPR[124:125] 0 4795 keep-active SGPR[126:127] 0 4795 keep-active SGPR[128:129] 0 4795 keep-active SGPR130 0 4795 keep-active SGPR131 0 4795 keep-active SGPR132 0 4795 keep-active SGPR133 0 4795 keep-active SGPR[134:135] 0 4795 keep-active SGPR[136:137] 0 4795 keep-active SGPR[138:139] 0 4795 keep-active SGPR[140:141] 0 4795 keep-active SGPR[142:143] 0 4795 keep-active SGPR[144:145] 0 4795 keep-active SGPR146 0 4795 keep-active SGPR147 0 4795 keep-active SGPR[148:149] 0 4795 keep-active SGPR[150:151] 0 4795 keep-active SGPR[152:153] 0 4795 keep-active SGPR154 0 4795 keep-active SGPR155 0 4795 keep-active SGPR[156:157] 0 4795 keep-active SGPR[158:159] 0 4795 keep-active SGPR[160:161] 0 4795 keep-active SGPR[162:163] 0 4795 keep-active SGPR[164:165] 0 4795 keep-active SGPR[166:167] 0 4795 keep-active SGPR168 0 4795 keep-active SGPR169 0 4795 keep-active SGPR[170:171] 0 4795 keep-active SGPR172 0 4795 keep-active SGPR173 0 4795 keep-active SGPR[174:175] 0 4795 keep-active SGPR[176:177] 0 4795 keep-active SGPR178 0 4795 keep-active SGPR179 0 4795 keep-active SGPR[180:181] 0 4795 keep-active SGPR182 0 4795 keep-active SGPR183 0 4795 keep-active SGPR184 0 4795 keep-active SGPR185 0 4795 keep-active SGPR[186:187] 0 4795 keep-active SGPR[188:189] 0 4795 keep-active SGPR[190:191] 0 4795 keep-active SGPR[192:193] 0 4795 keep-active SGPR[194:195] 0 4795 keep-active SGPR[196:197] 0 4795 keep-active SGPR[198:199] 0 4795 keep-active SGPR[200:201] 0 4795 keep-active SGPR[202:203] 0 4795 keep-active SGPR[204:205] 0 4795 keep-active SGPR[206:207] 0 4795 keep-active SGPR[208:209] 0 4795 keep-active SGPR[210:211] 0 4795 keep-active SGPR[212:213] 0 4795 keep-active SGPR[214:215] 0 4795 keep-active SGPR[216:217] 0 4795 keep-active SGPR[218:219] 0 4795 keep-active SGPR[220:221] 0 4795 keep-active SGPR[222:223] 0 4795 keep-active SGPR[224:225] 0 4795 keep-active SGPR[226:227] 0 4795 keep-active SGPR[228:229] 0 4795 keep-active SGPR[230:231] 0 4795 keep-active SGPR[232:233] 0 4795 keep-active SGPR[234:235] 0 4795 keep-active SGPR[236:237] 0 4795 keep-active SGPR[238:239] 0 4795 keep-active SGPR240 0 4795 keep-active SGPR[241:242] 6 9 SGPR241 11 12 SGPR241 14 15 SGPR241 19 20 SGPR241 22 23 SGPR[241:243] 25 30 SGPR241 32 33 SGPR[241:243] 184 186 SGPR[241:243] 306 308 SGPR241 371 372 SGPR241 373 374 SGPR241 375 376 SGPR241 589 590 SGPR241 641 642 SGPR241 712 713 SGPR241 838 839 SGPR241 1135 1136 SGPR241 1235 1236 SGPR241 1559 1560 SGPR241 1561 1562 SGPR241 1563 1564 SGPR241 1702 1703 SGPR241 1704 1705 SGPR241 1706 1707 SGPR241 2043 2044 SGPR241 2069 2070 SGPR241 2071 2072 SGPR241 2073 2074 SGPR241 2135 2136 SGPR241 2232 2233 SGPR241 2275 2276 SGPR241 2638 2639 SGPR241 2706 2707 SGPR241 2722 2723 SGPR241 2724 2725 SGPR[241:243] 2872 2878 SGPR241 2932 2933 SGPR241 2985 2986 SGPR241 2987 2988 SGPR241 2989 2990 SGPR241 3011 3012 SGPR241 3013 3014 SGPR241 3015 3016 SGPR241 3037 3038 SGPR241 3039 3040 SGPR241 3041 3042 SGPR241 3144 3145 SGPR241 3146 3147 SGPR241 3200 3201 SGPR241 3632 3635 SGPR241 3903 3913 SGPR241 4365 4366 SGPR241 4367 4368 SGPR241 4502 4512 SGPR241 4539 4540 SGPR241 4621 4622 SGPR[242:243] 68 180 SGPR[242:243] 190 302 SGPR[242:243] 312 312 SGPR[242:243] 333 333 SGPR[242:243] 575 575 SGPR[242:243] 610 610 SGPR[242:243] 657 660 SGPR[242:243] 730 730 SGPR[242:243] 799 799 SGPR[242:243] 907 907 SGPR[242:243] 1093 1093 SGPR[242:243] 1151 1154 SGPR[242:243] 1253 1253 SGPR[242:243] 1373 1381 SGPR[242:243] 1384 1392 SGPR[242:243] 1395 1403 SGPR[242:243] 1423 1431 SGPR[242:243] 1488 1525 SGPR[242:243] 1682 1760 SGPR[242:243] 2156 2193 SGPR[242:243] 2294 2331 SGPR[242:243] 2374 2411 SGPR[242:243] 2424 2461 SGPR[242:243] 2476 2513 SGPR[242:243] 2526 2563 SGPR[242:243] 2610 2610 SGPR[242:243] 2648 2648 SGPR[242:243] 2763 2763 SGPR[242:243] 2812 2815 SGPR[242:243] 2862 2867 SGPR[242:243] 2891 2896 SGPR242 2933 2935 SGPR[242:243] 3128 3133 SGPR[242:243] 3220 3257 SGPR[242:243] 3319 3356 SGPR[242:243] 3532 3569 SGPR[242:243] 3724 3761 SGPR242 3907 3910 SGPR[242:243] 3962 3984 SGPR[242:243] 4114 4119 SGPR[242:243] 4158 4171 SGPR[242:243] 4181 4194 SGPR[242:243] 4428 4465 SGPR242 4506 4509 SGPR[242:243] 4570 4592 SGPR[242:243] 4641 4678 SGPR[243:245] 2965 2970 SGPR[244:245] 76 81 SGPR[244:245] 104 109 SGPR[244:245] 132 137 SGPR[244:245] 198 203 SGPR[244:245] 226 231 SGPR[244:245] 254 259 SGPR[244:245] 1499 1521 SGPR[244:245] 1746 1759 SGPR[244:245] 2167 2189 SGPR[244:245] 2305 2327 SGPR[244:245] 2385 2407 SGPR[244:245] 2435 2457 SGPR[244:245] 2487 2509 SGPR[244:245] 2537 2559 SGPR[244:245] 2864 2885 SGPR[244:245] 2893 2907 SGPR[244:245] 3231 3253 SGPR[244:245] 3330 3352 SGPR[244:245] 3543 3565 SGPR[244:245] 3735 3757 SGPR[244:245] 3951 3988 SGPR[244:245] 4117 4119 SGPR[244:245] 4439 4461 SGPR[244:245] 4559 4596 SGPR[244:245] 4652 4674 SGPR[246:247] 78 179 SGPR[246:247] 200 301 SGPR[246:247] 3100 3105 SGPR[246:248] 3641 3647 SGPR[246:247] 4119 4124 SGPR[248:250] 86 92 SGPR[248:249] 106 173 SGPR[248:250] 208 214 SGPR[248:249] 228 295 SGPR[250:252] 114 120 SGPR[250:251] 134 167 SGPR[250:252] 236 242 SGPR[250:251] 256 289 SGPR[252:254] 142 148 SGPR[252:254] 156 162 SGPR[252:254] 264 270 SGPR[252:254] 278 284 VGPR[0:1] 0 4795 fixed VGPR[0:1] 0 4795 fixed VGPR[2:5] 0 4795 fixed VGPR[4:5] 0 4795 fixed VGPR[6:7] 0 4795 fixed VGPR[8:9] 0 4795 fixed VGPR[10:11] 0 4795 fixed VGPR12 0 4795 fixed VGPR[13:16] 0 4795 keep-active VGPR17 0 4795 fixed VGPR[18:19] 0 4795 keep-active VGPR[20:21] 0 4795 keep-active VGPR22 0 4795 keep-active VGPR23 0 4795 keep-active VGPR24 0 4795 keep-active VGPR25 0 4795 keep-active VGPR26 0 4795 keep-active VGPR[27:29] 0 4795 keep-active VGPR30 0 4795 keep-active VGPR[31:33] 0 4795 keep-active VGPR34 0 4795 keep-active VGPR35 0 4795 keep-active VGPR36 0 4795 keep-active VGPR37 0 4795 keep-active VGPR38 0 4795 keep-active VGPR39 0 4795 keep-active VGPR40 0 4795 keep-active VGPR41 0 4795 keep-active VGPR42 0 4795 keep-active VGPR43 0 4795 keep-active VGPR44 0 4795 keep-active VGPR45 0 4795 keep-active VGPR46 0 4795 keep-active VGPR47 0 4795 keep-active VGPR48 0 4795 keep-active VGPR49 0 4795 keep-active VGPR50 0 4795 keep-active VGPR51 0 4795 keep-active VGPR52 0 4795 keep-active VGPR53 0 4795 keep-active VGPR[54:56] 0 4795 keep-active VGPR57 0 4795 keep-active VGPR[58:60] 0 4795 keep-active VGPR61 0 4795 keep-active VGPR62 0 4795 keep-active VGPR63 0 4795 keep-active VGPR[64:66] 0 4795 keep-active VGPR67 0 4795 keep-active VGPR68 0 4795 keep-active VGPR[69:70] 0 4795 keep-active VGPR[71:72] 0 4795 keep-active VGPR73 0 4795 keep-active VGPR[74:75] 0 4795 keep-active VGPR[76:77] 0 4795 keep-active VGPR[78:79] 0 4795 keep-active VGPR[80:81] 0 4795 keep-active VGPR[82:83] 0 4795 keep-active VGPR[84:85] 0 4795 keep-active VGPR86 0 4795 keep-active VGPR[87:88] 0 4795 keep-active VGPR89 0 4795 keep-active VGPR90 0 4795 keep-active VGPR91 0 4795 keep-active VGPR[92:93] 0 4795 keep-active VGPR94 0 4795 keep-active VGPR95 0 4795 keep-active VGPR96 0 4795 keep-active VGPR[97:99] 0 4795 keep-active VGPR[100:102] 0 4795 keep-active VGPR103 0 4795 keep-active VGPR104 0 4795 keep-active VGPR[105:106] 0 4795 keep-active VGPR107 0 4795 keep-active VGPR108 0 4795 keep-active VGPR[109:110] 0 4795 keep-active VGPR111 0 4795 keep-active VGPR[112:113] 0 4795 keep-active VGPR114 0 4795 keep-active VGPR115 0 4795 keep-active VGPR116 0 4795 keep-active VGPR[117:118] 0 4795 keep-active VGPR119 0 4795 keep-active VGPR[120:121] 0 4795 keep-active VGPR122 0 4795 keep-active VGPR123 0 4795 keep-active VGPR[124:126] 0 4795 keep-active VGPR127 0 4795 keep-active VGPR128 0 4795 keep-active VGPR129 0 4795 keep-active VGPR130 0 4795 keep-active VGPR131 0 4795 keep-active VGPR[132:134] 0 4795 keep-active VGPR[135:137] 0 4795 keep-active VGPR[138:140] 0 4795 keep-active VGPR[141:143] 0 4795 keep-active VGPR[144:146] 0 4795 keep-active VGPR147 0 4795 keep-active VGPR148 0 4795 keep-active VGPR149 0 4795 keep-active VGPR[150:152] 0 4795 keep-active VGPR[153:155] 0 4795 keep-active VGPR[156:158] 0 4795 keep-active VGPR[159:161] 0 4795 keep-active VGPR[162:163] 0 4795 keep-active VGPR[164:165] 0 4795 keep-active VGPR[166:167] 0 4795 keep-active VGPR168 0 4795 keep-active VGPR[169:171] 0 4795 keep-active VGPR172 0 4795 keep-active VGPR[173:175] 0 4795 keep-active VGPR176 0 4795 keep-active VGPR[177:179] 0 4795 keep-active VGPR180 0 4795 keep-active VGPR181 0 4795 keep-active VGPR[182:184] 0 4795 keep-active VGPR[185:187] 0 4795 keep-active VGPR[188:190] 0 4795 keep-active VGPR[191:193] 0 4795 keep-active VGPR[194:196] 0 4795 keep-active VGPR[197:199] 0 4795 keep-active VGPR[200:202] 0 4795 keep-active VGPR[203:205] 0 4795 keep-active VGPR[206:208] 0 4795 keep-active VGPR[209:211] 0 4795 keep-active VGPR[212:214] 0 4795 keep-active VGPR215 0 4795 keep-active VGPR[216:218] 0 4795 keep-active VGPR219 0 4795 keep-active VGPR220 0 4795 keep-active VGPR221 0 4795 keep-active VGPR222 0 4795 keep-active VGPR223 0 4795 keep-active VGPR224 0 4795 keep-active VGPR[225:227] 0 4795 keep-active VGPR[228:230] 0 4795 keep-active VGPR[231:233] 0 4795 keep-active VGPR234 0 4795 keep-active VGPR235 0 4795 keep-active VGPR236 0 4795 keep-active VGPR[237:239] 0 4795 keep-active VGPR240 0 4795 keep-active VGPR241 0 4795 keep-active VGPR242 0 4795 keep-active VGPR[243:244] 0 4795 keep-active VGPR245 0 4795 keep-active VGPR246 0 4795 keep-active VGPR247 0 4795 keep-active VGPR[248:250] 0 4795 keep-active VGPR[251:253] 0 4795 keep-active VGPR[254:256] 0 4795 keep-active VGPR257 0 4795 keep-active VGPR258 0 4795 keep-active VGPR[259:260] 0 4795 keep-active VGPR[261:263] 0 4795 keep-active VGPR[264:265] 0 4795 keep-active VGPR266 0 4795 keep-active VGPR[267:268] 0 4795 keep-active VGPR[269:270] 0 4795 keep-active VGPR271 0 4795 keep-active VGPR[272:274] 0 4795 keep-active VGPR[275:277] 0 4795 keep-active VGPR278 0 4795 keep-active VGPR279 0 4795 keep-active VGPR[280:282] 0 4795 keep-active VGPR[283:285] 0 4795 keep-active VGPR[286:288] 0 4795 keep-active VGPR[289:297] 0 4795 keep-active VGPR[298:299] 0 4795 keep-active VGPR300 0 4795 keep-active VGPR301 0 4795 keep-active VGPR[302:304] 0 4795 keep-active VGPR305 0 4795 keep-active VGPR[306:308] 0 4795 keep-active VGPR[309:311] 0 4795 keep-active VGPR[312:313] 0 4795 keep-active VGPR314 0 4795 keep-active VGPR[315:316] 0 4795 keep-active VGPR[317:319] 0 4795 keep-active VGPR[320:322] 0 4795 keep-active VGPR[323:325] 0 4795 keep-active VGPR326 0 4795 keep-active VGPR327 0 4795 keep-active VGPR328 0 4795 keep-active VGPR329 0 4795 keep-active VGPR330 0 4795 keep-active VGPR331 0 4795 keep-active VGPR[332:335] 35 41 VGPR[332:335] 56 63 VGPR332 73 76 VGPR332 101 104 VGPR332 129 132 VGPR332 195 198 VGPR332 223 226 VGPR332 251 254 VGPR332 317 319 VGPR332 323 324 VGPR332 326 329 VGPR[332:334] 338 344 VGPR[332:334] 347 353 VGPR[332:334] 361 384 VGPR332 391 399 VGPR332 402 405 VGPR332 409 410 VGPR332 423 424 VGPR332 438 442 VGPR332 444 445 VGPR332 458 459 VGPR332 473 477 VGPR332 480 484 VGPR332 486 487 VGPR332 500 501 VGPR332 515 519 VGPR332 521 522 VGPR332 535 536 VGPR332 550 554 VGPR332 557 561 VGPR332 564 568 VGPR[332:333] 580 585 VGPR[332:334] 615 621 VGPR332 656 657 VGPR332 668 670 VGPR[332:334] 673 679 VGPR332 694 695 VGPR332 697 702 VGPR332 713 715 VGPR332 735 737 VGPR332 743 745 VGPR332 748 750 VGPR332 756 758 VGPR332 760 790 VGPR[332:333] 804 812 VGPR332 822 824 VGPR332 826 828 VGPR332 831 852 VGPR332 854 855 VGPR332 857 859 VGPR332 862 897 VGPR332 899 900 VGPR[332:333] 912 917 VGPR[332:333] 919 925 VGPR332 931 939 VGPR332 942 945 VGPR332 947 961 VGPR332 964 966 VGPR[332:333] 980 983 VGPR[332:333] 997 1004 VGPR332 1007 1009 VGPR332 1011 1013 VGPR332 1016 1019 VGPR332 1021 1022 VGPR332 1027 1029 VGPR[332:333] 1031 1037 VGPR332 1062 1064 VGPR332 1078 1079 VGPR332 1081 1082 VGPR332 1084 1086 VGPR[332:334] 1114 1127 VGPR332 1150 1151 VGPR[332:333] 1162 1175 VGPR332 1178 1181 VGPR332 1183 1186 VGPR332 1192 1194 VGPR332 1208 1213 VGPR332 1215 1218 VGPR332 1222 1225 VGPR332 1236 1238 VGPR[332:333] 1258 1263 VGPR332 1269 1271 VGPR[332:333] 1285 1290 VGPR332 1296 1298 VGPR332 1311 1312 VGPR332 1314 1317 VGPR332 1345 1394 VGPR332 1408 1422 VGPR332 1437 1439 VGPR[332:334] 1458 1463 VGPR332 1483 1511 VGPR332 1534 1537 VGPR332 1539 1540 VGPR332 1542 1544 VGPR[332:334] 1560 1577 VGPR332 1580 1582 VGPR332 1584 1587 VGPR332 1589 1591 VGPR332 1594 1595 VGPR332 1601 1605 VGPR[332:334] 1607 1618 VGPR[332:334] 1633 1678 VGPR332 1688 1691 VGPR[332:334] 1698 1717 VGPR332 1724 1727 VGPR332 1730 1733 VGPR332 1735 1737 VGPR332 1741 1742 VGPR332 1744 1745 VGPR332 1751 1762 VGPR[332:334] 1765 1772 VGPR332 1787 1788 VGPR332 1798 1801 VGPR332 1816 1817 VGPR332 1819 1821 VGPR332 1825 1828 VGPR332 1830 1831 VGPR332 1833 1835 VGPR332 1838 1850 VGPR332 1852 1857 VGPR332 1902 1905 VGPR332 1908 1911 VGPR332 1913 1915 VGPR332 1919 1921 VGPR332 1923 1926 VGPR332 1936 1942 VGPR332 1946 1948 VGPR332 1950 1951 VGPR332 1953 1954 VGPR332 1959 1964 VGPR332 1966 1969 VGPR332 1982 1985 VGPR[332:333] 1992 1996 VGPR[332:333] 1999 2003 VGPR[332:333] 2005 2008 VGPR332 2011 2016 VGPR332 2019 2024 VGPR332 2029 2031 VGPR[332:333] 2034 2039 VGPR332 2059 2060 VGPR332 2062 2063 VGPR[332:334] 2076 2086 VGPR332 2089 2091 VGPR332 2097 2099 VGPR[332:333] 2105 2109 VGPR332 2111 2113 VGPR332 2122 2124 VGPR332 2129 2133 VGPR332 2151 2179 VGPR332 2196 2200 VGPR[332:333] 2219 2224 VGPR332 2226 2230 VGPR332 2248 2249 VGPR332 2251 2252 VGPR[332:333] 2263 2267 VGPR332 2269 2273 VGPR332 2291 2317 VGPR332 2338 2341 VGPR[332:334] 2343 2595 VGPR332 2598 2601 VGPR332 2615 2618 VGPR332 2621 2624 VGPR332 2626 2631 VGPR332 2633 2634 VGPR332 2653 2656 VGPR332 2677 2680 VGPR332 2682 2687 VGPR332 2690 2693 VGPR332 2695 2700 VGPR332 2702 2703 VGPR[332:334] 2714 2759 VGPR332 2768 2771 VGPR332 2773 2777 VGPR332 2779 2785 VGPR332 2787 2788 VGPR332 2811 2812 VGPR[332:334] 2823 2841 VGPR332 2857 2862 VGPR332 2888 2891 VGPR332 2911 2914 VGPR332 2917 2919 VGPR332 2921 2924 VGPR[332:334] 2945 2963 VGPR[332:334] 2986 2994 VGPR[332:334] 3012 3020 VGPR[332:334] 3038 3046 VGPR332 3061 3065 VGPR332 3067 3073 VGPR[332:334] 3086 3096 VGPR332 3099 3100 VGPR332 3111 3116 VGPR332 3118 3125 VGPR332 3127 3128 VGPR[332:333] 3138 3169 VGPR332 3170 3175 VGPR332 3177 3179 VGPR332 3184 3185 VGPR332 3190 3192 VGPR332 3194 3198 VGPR332 3216 3217 VGPR332 3225 3262 VGPR[332:334] 3267 3278 VGPR[332:334] 3280 3393 VGPR332 3396 3400 VGPR332 3402 3406 VGPR332 3412 3416 VGPR332 3418 3422 VGPR332 3425 3427 VGPR[332:334] 3441 3470 VGPR332 3507 3510 VGPR332 3512 3516 VGPR332 3518 3522 VGPR332 3525 3527 VGPR332 3530 3553 VGPR332 3576 3579 VGPR332 3596 3599 VGPR332 3601 3603 VGPR332 3606 3609 VGPR[332:333] 3638 3654 VGPR332 3656 3658 VGPR332 3670 3674 VGPR332 3678 3682 VGPR332 3696 3697 VGPR332 3721 3747 VGPR[332:334] 3768 3780 VGPR332 3782 3788 VGPR[332:334] 3790 3798 VGPR332 3800 3806 VGPR[332:334] 3808 3852 VGPR332 3854 3870 VGPR332 3889 3891 VGPR332 3910 3913 VGPR332 3916 3918 VGPR332 3923 3924 VGPR332 3948 3974 VGPR332 3991 4002 VGPR332 4004 4010 VGPR332 4023 4025 VGPR332 4028 4032 VGPR332 4034 4035 VGPR332 4040 4043 VGPR332 4046 4050 VGPR332 4052 4053 VGPR332 4100 4103 VGPR332 4105 4107 VGPR332 4113 4114 VGPR[332:333] 4129 4139 VGPR332 4145 4147 VGPR332 4150 4176 VGPR332 4178 4180 VGPR332 4186 4199 VGPR332 4222 4224 VGPR332 4227 4230 VGPR332 4232 4237 VGPR332 4240 4243 VGPR332 4245 4250 VGPR332 4270 4273 VGPR332 4275 4277 VGPR[332:334] 4302 4312 VGPR[332:334] 4314 4323 VGPR332 4328 4330 VGPR[332:333] 4370 4378 VGPR332 4384 4387 VGPR332 4401 4404 VGPR[332:333] 4412 4415 VGPR332 4416 4423 VGPR332 4425 4451 VGPR[332:334] 4468 4483 VGPR[332:334] 4485 4491 VGPR332 4509 4512 VGPR332 4515 4517 VGPR332 4520 4521 VGPR332 4523 4524 VGPR332 4529 4531 VGPR332 4533 4537 VGPR332 4555 4582 VGPR332 4599 4600 VGPR332 4602 4603 VGPR332 4605 4606 VGPR332 4611 4613 VGPR332 4615 4619 VGPR332 4637 4664 VGPR332 4681 4682 VGPR332 4684 4688 VGPR332 4708 4711 VGPR[332:335] 4718 4726 VGPR332 4735 4738 VGPR332 4741 4743 VGPR332 4746 4748 VGPR332 4750 4757 VGPR332 4759 4761 VGPR333 75 76 VGPR333 103 104 VGPR333 131 132 VGPR333 197 198 VGPR333 225 226 VGPR333 253 254 VGPR333 319 324 VGPR333 394 397 VGPR333 399 407 VGPR333 410 412 VGPR333 424 426 VGPR333 445 447 VGPR333 459 461 VGPR333 475 484 VGPR333 487 489 VGPR333 501 503 VGPR333 522 524 VGPR333 536 538 VGPR333 552 561 VGPR333 566 571 VGPR333 695 699 VGPR333 702 704 VGPR333 737 745 VGPR333 750 758 VGPR333 763 765 VGPR333 771 773 VGPR333 776 778 VGPR333 784 786 VGPR333 788 791 VGPR333 824 827 VGPR333 835 841 VGPR333 843 846 VGPR333 850 852 VGPR333 855 858 VGPR333 866 868 VGPR333 870 872 VGPR333 875 890 VGPR333 892 894 VGPR333 897 900 VGPR333 934 937 VGPR333 944 945 VGPR333 952 955 VGPR333 957 962 VGPR333 1009 1012 VGPR333 1017 1022 VGPR[333:334] 1063 1067 VGPR333 1079 1082 VGPR333 1086 1089 VGPR333 1180 1181 VGPR333 1210 1213 VGPR333 1217 1219 VGPR333 1225 1227 VGPR333 1312 1314 VGPR333 1349 1383 VGPR333 1410 1416 VGPR[333:334] 1438 1442 VGPR333 1485 1511 VGPR333 1536 1537 VGPR333 1540 1544 VGPR333 1582 1584 VGPR333 1586 1587 VGPR333 1590 1595 VGPR333 1690 1691 VGPR333 1726 1727 VGPR333 1732 1733 VGPR333 1737 1742 VGPR333 1788 1791 VGPR333 1817 1820 VGPR333 1827 1828 VGPR333 1831 1833 VGPR333 1835 1966 VGPR333 1968 1969 VGPR333 1984 1985 VGPR[333:334] 2013 2016 VGPR[333:334] 2021 2024 VGPR333 2060 2063 VGPR[333:334] 2090 2102 VGPR[333:334] 2112 2117 VGPR[333:334] 2123 2127 VGPR333 2131 2134 VGPR333 2153 2179 VGPR[333:335] 2198 2216 VGPR333 2228 2231 VGPR333 2249 2252 VGPR333 2271 2274 VGPR333 2292 2315 VGPR[333:335] 2599 2606 VGPR333 2617 2618 VGPR333 2623 2624 VGPR333 2630 2631 VGPR333 2634 2637 VGPR333 2656 2658 VGPR333 2679 2680 VGPR333 2686 2687 VGPR333 2692 2693 VGPR333 2699 2700 VGPR333 2703 2708 VGPR333 2770 2771 VGPR333 2777 2779 VGPR333 2781 2784 VGPR333 2788 2791 VGPR333 2860 2862 VGPR333 2890 2891 VGPR333 2913 2914 VGPR333 2919 2921 VGPR[333:335] 3063 3073 VGPR333 3113 3116 VGPR333 3120 3125 VGPR333 3174 3175 VGPR333 3178 3185 VGPR333 3196 3199 VGPR333 3217 3243 VGPR333 3400 3402 VGPR[333:335] 3404 3410 VGPR333 3416 3418 VGPR333 3420 3422 VGPR333 3426 3432 VGPR[333:335] 3508 3583 VGPR333 3598 3599 VGPR333 3602 3609 VGPR[333:334] 3657 3663 VGPR333 3697 3699 VGPR333 3722 3745 VGPR333 3856 3871 VGPR[333:334] 3890 3896 VGPR333 3911 3918 VGPR333 3924 3926 VGPR333 3949 3972 VGPR333 3996 4000 VGPR333 4025 4032 VGPR333 4035 4037 VGPR333 4042 4043 VGPR333 4048 4053 VGPR333 4102 4103 VGPR333 4106 4108 VGPR333 4153 4155 VGPR333 4163 4174 VGPR333 4176 4178 VGPR[333:335] 4197 4215 VGPR[333:334] 4223 4256 VGPR333 4272 4273 VGPR333 4276 4282 VGPR[333:334] 4329 4335 VGPR[333:335] 4402 4409 VGPR333 4421 4451 VGPR333 4510 4515 VGPR333 4521 4524 VGPR333 4535 4538 VGPR333 4557 4580 VGPR333 4603 4606 VGPR333 4617 4620 VGPR333 4639 4662 VGPR333 4682 4684 VGPR[333:335] 4686 4701 VGPR[333:335] 4709 4715 VGPR333 4737 4738 VGPR333 4743 4750 VGPR333 4753 4755 VGPR333 4757 4760 VGPR334 324 326 VGPR334 396 397 VGPR334 404 405 VGPR334 559 568 VGPR334 583 587 VGPR334 745 760 VGPR334 765 773 VGPR334 778 786 VGPR[334:335] 790 795 VGPR[334:335] 807 812 VGPR334 827 831 VGPR334 839 841 VGPR334 845 847 VGPR334 852 855 VGPR334 858 862 VGPR334 868 871 VGPR334 879 881 VGPR334 883 885 VGPR334 888 890 VGPR334 893 897 VGPR334 900 903 VGPR334 915 917 VGPR[334:335] 922 925 VGPR334 936 937 VGPR334 945 947 VGPR334 954 955 VGPR[334:335] 982 986 VGPR[334:335] 1000 1004 VGPR334 1012 1019 VGPR[334:335] 1024 1029 VGPR334 1082 1084 VGPR334 1166 1169 VGPR[334:335] 1174 1186 VGPR334 1211 1215 VGPR334 1218 1222 VGPR334 1261 1263 VGPR334 1288 1290 VGPR[334:336] 1326 1341 VGPR334 1351 1366 VGPR334 1411 1416 VGPR334 1486 1509 VGPR334 1537 1540 VGPR334 1543 1545 VGPR334 1587 1590 VGPR334 1595 1599 VGPR334 1691 1695 VGPR334 1727 1735 VGPR334 1742 1745 VGPR[334:336] 1794 1801 VGPR334 1820 1833 VGPR334 1841 1843 VGPR334 1847 1848 VGPR334 1850 1857 VGPR[334:335] 1866 1880 VGPR[334:335] 1882 1885 VGPR334 1904 1905 VGPR334 1910 1911 VGPR334 1915 1919 VGPR334 1921 1927 VGPR[334:336] 1932 1938 VGPR334 1942 1951 VGPR334 1954 1957 VGPR334 1963 1964 VGPR334 1969 1972 VGPR334 1985 1989 VGPR[334:335] 2002 2008 VGPR334 2037 2041 VGPR334 2063 2067 VGPR[334:336] 2133 2140 VGPR334 2154 2177 VGPR334 2222 2224 VGPR[334:336] 2230 2237 VGPR334 2252 2256 VGPR[334:335] 2266 2271 VGPR[334:336] 2273 2280 VGPR334 2299 2336 VGPR334 2618 2636 VGPR[334:336] 2669 2674 VGPR334 2680 2682 VGPR334 2687 2705 VGPR334 2771 2773 VGPR334 2782 2785 VGPR334 2914 2921 VGPR334 3114 3118 VGPR334 3121 3128 VGPR[334:335] 3141 3154 VGPR[334:335] 3156 3161 VGPR[334:335] 3163 3166 VGPR[334:335] 3168 3171 VGPR334 3175 3178 VGPR[334:335] 3187 3192 VGPR[334:336] 3198 3205 VGPR334 3241 3250 VGPR334 3421 3423 VGPR[334:336] 3430 3439 VGPR334 3599 3602 VGPR334 3607 3614 VGPR[334:335] 3646 3654 VGPR334 3729 3766 VGPR334 3858 3872 VGPR334 3918 3921 VGPR334 3956 3993 VGPR334 3998 4001 VGPR334 4030 4035 VGPR334 4043 4050 VGPR[334:336] 4091 4097 VGPR334 4103 4107 VGPR[334:335] 4132 4136 VGPR[334:335] 4138 4142 VGPR334 4155 4157 VGPR334 4174 4176 VGPR334 4273 4276 VGPR[334:336] 4280 4295 VGPR[334:335] 4377 4381 VGPR[334:335] 4414 4417 VGPR334 4426 4449 VGPR[334:335] 4526 4531 VGPR[334:336] 4537 4544 VGPR334 4564 4600 VGPR[334:335] 4608 4613 VGPR[334:336] 4619 4626 VGPR334 4646 4682 VGPR334 4738 4743 VGPR334 4748 4750 VGPR334 4755 4757 VGPR334 4760 4776 VGPR[335:337] 342 402 VGPR335 405 407 VGPR335 585 588 VGPR[335:337] 677 683 VGPR335 758 760 VGPR335 773 788 VGPR335 841 843 VGPR335 846 850 VGPR335 871 875 VGPR335 881 884 VGPR335 890 893 VGPR335 937 939 VGPR335 955 957 VGPR335 1168 1169 VGPR[335:336] 1262 1266 VGPR[335:336] 1289 1293 VGPR335 1352 1366 VGPR335 1412 1417 VGPR[335:336] 1462 1466 VGPR335 1493 1530 VGPR[335:337] 1566 1576 VGPR[335:337] 1597 1617 VGPR335 1637 1638 VGPR335 1649 1652 VGPR335 1660 1663 VGPR[335:337] 1666 1672 VGPR[335:337] 1703 1717 VGPR335 1733 1735 VGPR335 1769 1772 VGPR335 1828 1831 VGPR335 1843 1848 VGPR335 1853 1859 VGPR335 1905 1913 VGPR335 1924 1927 VGPR335 1948 1954 VGPR335 1964 1966 VGPR[335:336] 2015 2027 VGPR335 2039 2042 VGPR[335:337] 2065 2087 VGPR[335:336] 2094 2099 VGPR[335:336] 2101 2127 VGPR335 2161 2196 VGPR[335:336] 2223 2228 VGPR[335:337] 2254 2260 VGPR335 2315 2324 VGPR[335:337] 2334 2341 VGPR[335:337] 2347 2362 VGPR335 2364 2365 VGPR335 2368 2370 VGPR335 2372 2395 VGPR335 2414 2415 VGPR335 2418 2420 VGPR335 2422 2445 VGPR335 2464 2582 VGPR335 2624 2626 VGPR335 2631 2634 VGPR[335:337] 2636 2644 VGPR335 2693 2695 VGPR335 2700 2703 VGPR[335:336] 2719 2732 VGPR[335:336] 2734 2739 VGPR[335:336] 2741 2744 VGPR[335:337] 2747 2753 VGPR335 2783 2788 VGPR[335:337] 2828 2837 VGPR[335:337] 2839 2845 VGPR[335:337] 2950 2959 VGPR[335:337] 2992 2998 VGPR[335:337] 3018 3024 VGPR[335:337] 3044 3050 VGPR335 3090 3096 VGPR[335:337] 3260 3278 VGPR335 3291 3294 VGPR335 3297 3300 VGPR335 3302 3306 VGPR335 3308 3312 VGPR335 3314 3342 VGPR[335:337] 3359 3377 VGPR335 3390 3393 VGPR335 3422 3426 VGPR[335:337] 3446 3452 VGPR335 3454 3459 VGPR335 3463 3464 VGPR335 3466 3470 VGPR[335:337] 3612 3618 VGPR[335:336] 3660 3663 VGPR335 3745 3754 VGPR[335:337] 3764 3776 VGPR[335:337] 3778 3788 VGPR[335:337] 3793 3806 VGPR[335:337] 3813 3826 VGPR[335:337] 3828 3841 VGPR335 3848 3866 VGPR[335:336] 3893 3896 VGPR335 3972 3981 VGPR[335:337] 4000 4010 VGPR335 4107 4110 VGPR335 4229 4230 VGPR335 4236 4237 VGPR335 4242 4243 VGPR335 4249 4250 VGPR[335:336] 4255 4259 VGPR335 4306 4312 VGPR335 4317 4323 VGPR[335:336] 4366 4375 VGPR335 4433 4470 VGPR335 4580 4589 VGPR335 4662 4671 VGPR[335:338] 4765 4772 VGPR[335:337] 4774 4786 VGPR[336:337] 40 44 VGPR[336:338] 587 594 VGPR336 786 788 VGPR[336:337] 809 814 VGPR336 884 888 VGPR[336:337] 961 966 VGPR[336:337] 1003 1025 VGPR[336:337] 1028 1032 VGPR336 1169 1172 VGPR336 1181 1183 VGPR[336:337] 1185 1189 VGPR336 1353 1367 VGPR336 1413 1418 VGPR336 1509 1518 VGPR336 1638 1643 VGPR336 1651 1653 VGPR[336:338] 1770 1776 VGPR336 1848 1850 VGPR[336:338] 1862 1867 VGPR[336:337] 1869 1880 VGPR[336:337] 1884 1894 VGPR336 1911 1913 VGPR336 1925 1929 VGPR336 1951 1956 VGPR[336:338] 2041 2048 VGPR336 2177 2186 VGPR[336:338] 2202 2215 VGPR336 2365 2397 VGPR336 2415 2447 VGPR336 2466 2467 VGPR336 2470 2472 VGPR336 2474 2497 VGPR336 2516 2517 VGPR336 2520 2522 VGPR336 2524 2547 VGPR336 2566 2582 VGPR[336:338] 3082 3088 VGPR[336:337] 3145 3154 VGPR336 3159 3161 VGPR[336:337] 3191 3196 VGPR336 3293 3294 VGPR336 3299 3300 VGPR336 3306 3308 VGPR336 3312 3314 VGPR336 3316 3342 VGPR[336:338] 3391 3410 VGPR336 3458 3460 VGPR336 3464 3466 VGPR[336:338] 3468 3474 VGPR336 3516 3518 VGPR336 3520 3522 VGPR336 3526 3555 VGPR[336:338] 3581 3587 VGPR[336:337] 3649 3658 VGPR336 3850 3867 VGPR[336:337] 4135 4139 VGPR[336:338] 4201 4214 VGPR336 4230 4232 VGPR336 4237 4252 VGPR[336:338] 4310 4312 VGPR[336:338] 4321 4326 VGPR[336:338] 4407 4482 VGPR[336:337] 4530 4535 VGPR[336:337] 4612 4617 VGPR[336:338] 4690 4701 VGPR[336:338] 4713 4725 VGPR[337:338] 1171 1175 VGPR[337:339] 1331 1337 VGPR337 1354 1368 VGPR337 1414 1421 VGPR[337:339] 1641 1647 VGPR337 1652 1658 VGPR[337:339] 1799 1805 VGPR[337:338] 1956 1960 VGPR[337:338] 2023 2027 VGPR[337:338] 2098 2102 VGPR[337:338] 2108 2113 VGPR[337:338] 2115 2124 VGPR[337:338] 2126 2131 VGPR337 2370 2397 VGPR337 2420 2447 VGPR337 2467 2499 VGPR337 2517 2549 VGPR[337:339] 2568 2580 VGPR337 2582 2586 VGPR[337:339] 2672 2712 VGPR[337:338] 2723 2732 VGPR337 2737 2739 VGPR[337:338] 3160 3166 VGPR337 3294 3306 VGPR337 3317 3340 VGPR337 3459 3464 VGPR337 3521 3523 VGPR337 3537 3574 VGPR[337:338] 3662 3666 VGPR337 3852 3868 VGPR337 4243 4245 VGPR337 4250 4253 VGPR[337:339] 4284 4295 VGPR[338:340] 351 357 VGPR338 366 369 VGPR[338:340] 382 388 VGPR338 397 399 VGPR[338:339] 811 818 VGPR338 1355 1369 VGPR338 1415 1421 VGPR[338:340] 1569 1599 VGPR[338:340] 1603 1618 VGPR[338:340] 1656 1663 VGPR[338:340] 1709 1721 VGPR[338:339] 1871 1885 VGPR[338:340] 1888 1893 VGPR[338:340] 2070 2087 VGPR[338:340] 2339 2345 VGPR[338:340] 2351 2362 VGPR338 2379 2464 VGPR338 2472 2499 VGPR338 2522 2549 VGPR[338:340] 2584 2596 VGPR[338:339] 2738 2744 VGPR338 2833 2837 VGPR338 2955 2959 VGPR[338:339] 3149 3157 VGPR[338:340] 3264 3277 VGPR338 3300 3302 VGPR338 3324 3361 VGPR[338:340] 3363 3376 VGPR[338:340] 3450 3456 VGPR338 3522 3526 VGPR338 3553 3562 VGPR[338:340] 3572 3579 VGPR[338:340] 3786 3864 VGPR[338:340] 3866 3880 VGPR[338:340] 4008 4020 VGPR[338:339] 4252 4256 VGPR[338:341] 4779 4787 VGPR[339:341] 367 380 VGPR339 1356 1370 VGPR339 1416 1435 VGPR[339:340] 2026 2031 VGPR[339:341] 2205 2216 VGPR339 2395 2404 VGPR339 2429 2464 VGPR339 2481 2566 VGPR[339:340] 2727 2735 VGPR[339:341] 2835 2841 VGPR[339:341] 2957 2963 VGPR[339:340] 3165 3169 VGPR339 3340 3349 VGPR[339:341] 3408 3443 VGPR[339:341] 4204 4215 VGPR339 4449 4458 VGPR[339:341] 4472 4483 VGPR[339:341] 4693 4705 VGPR[339:342] 4723 4732 VGPR[339:341] 4770 4776 VGPR[340:342] 1335 1341 VGPR340 1357 1378 VGPR[340:341] 1434 1439 VGPR340 2445 2454 VGPR340 2497 2506 VGPR340 2531 2566 VGPR[340:342] 2705 2712 VGPR[340:341] 2743 2749 VGPR[340:342] 4287 4299 VGPR341 1358 1389 VGPR[341:343] 1610 1622 VGPR[341:343] 1661 1668 VGPR[341:343] 1892 1899 VGPR[341:343] 2354 2579 VGPR[341:343] 2588 2601 VGPR[341:343] 3270 3282 VGPR[341:343] 3366 3377 VGPR[341:343] 3577 3583 VGPR[341:343] 3804 3810 VGPR341 3820 3826 VGPR341 3835 3841 VGPR341 3860 3874 VGPR[342:344] 372 380 VGPR[342:345] 1359 1372 VGPR[342:344] 3434 3439 VGPR[342:344] 3824 3858 VGPR342 3862 3875 VGPR[342:344] 4207 4219 VGPR[342:344] 4475 4487 VGPR[342:345] 4784 4793 VGPR[343:345] 2710 2716 VGPR343 3864 3876 VGPR344 2547 2556 VGPR[344:346] 2572 2596 VGPR[344:346] 3369 3381 VGPR[344:346] 3870 3883 VGPR[345:347] 378 384 VGPR[345:347] 3437 3443 VGPR[345:347] 3839 3845 VGPR346 1366 1434 VGPR[347:349] 3874 3886 Linking branch instructions to their targets... Final disassembly: Program Type: Fragment Special Input Variables: offset: unset, size: 16, FloatVector4 gl_FragCoord BuiltIn(FragCoord) Textures: offset: 0, size: 4, Float iChannel0 offset: 1, size: 4, Float iChannel1 offset: 2, size: 4, Float iChannel2 offset: 3, size: 4, Float iChannel3 Output Variables: offset: 0, size: 16, FloatVector4 finalColor Uniform Constants: offset: 0, size: 4, Float iTime offset: 4, size: 12, FloatVector3 iResolution offset: 16, size: 16, FloatVector4 iMouse offset: 32, size: 16, FloatVector4 iDate offset: 48, size: 4, Float iFrame offset: 52, size: 48, FloatVector3 iChannelResolution[4] Private Global Variables: offset: unset, size: 8, FloatVector2 tc offset: unset, size: 4, Float time offset: unset, size: 4, Float colour offset: unset, size: 4, Float ss offset: unset, size: 4, Float is_choc offset: unset, size: 4, Float t_per_target offset: unset, size: 12, FloatVector3 l offset: unset, size: 4, Float icing_factor offset: unset, size: 48, FloatVector3 gum_colours[4] offset: unset, size: 48, FloatVector3 gum_ramps[4] Constants: Float const100: 0 FloatVector2 const101: {0, 0} Float const106: 1 Float const109: 3 Float const112: 0.316228 Float const113: 0.948683 FloatVector3 const114: {0.316228, 0.948683, 0} Float const121: 0.11 Float const122: 0.002 FloatVector3 const123: {0.11, 0, 0.002} Float const127: 2 Float const131: 0.06 FloatVector3 const132: {0.002, 0.06, 0} Float const139: 0.02 FloatVector3 const140: {0, 0.02, 0.11} Float const143: 0.012 FloatVector3 const144: {0.11, 0.012, 0} Float const151: 0.8 FloatVector3 const152: {0.8, 1, 1} FloatVector3 const159: {0.8, 0.8, 1} FloatVector3 const166: {1, 0.8, 1} Float const173: 43758.5 UInt32 const194: 0 UInt32 const197: 1 Float const200: 157 Float const203: 113 UInt32 const204: 2 Float const225: 158 Float const240: 114 Float const248: 270 Float const253: 271 Int32 const285: 1 Int32 const292: 9 Float const303: 0.5 Float const340: -1 FloatVector2 const341: {-1, -1} FloatVector2 const342: {1, 1} Float const349: 8 Float const361: 0.95 Float const377: 4 FloatVector2 const391: {0.5, 0.5} Float const401: 5 Float const407: 53 Float const412: 125 Float const416: 2.5 Float const423: 100 FloatVector2 const424: {100, 100} Float const435: 0.9 Float const437: 25 Int32 const471: 0 Int32 const478: 4 Float const483: 10.45 Float const489: 0.2 Float const511: 0.75 Float const523: 0.3 FloatVector3 const569: {0.5, 0.5, 0.5} Float const573: 0.98 Float const576: 0.1 FloatVector3 const585: {2, 2, 2} Float const593: 1.05 Float const602: 0.01 Float const609: 1.3 Float const621: 10 Float const625: 103 Float const633: 30 Float const637: 0.001 Float const647: 0.05 FloatVector2 const664: {3, 3} Float const666: 1.5 FloatVector2 const667: {1.5, 1.5} Float const671: 0.7 Float const674: 7 Float const678: 9 Float const704: 0.6 Float const714: 0.015 FloatVector2 const730: {1, -1} FloatVector3 const735: {0.1, 0.1, 0.05} Float const748: 0.4 Float const749: 0.24 FloatVector3 const750: {0.4, 0.4, 0.24} Float const751: 0.56 FloatVector3 const752: {0.7, 0.7, 0.56} Float const844: 6 Float const848: 0.03 FloatVector3 const860: {1, 0, 0} Float const863: 20 Float const867: -7 Float const869: 14 Float const888: 3.5 Float const895: 1.4 Int32 const906: 100 FloatVector3 const921: {0, 0, 0} Float const925: 0.0001 Float const945: 0.005 FloatVector3 const946: {0.02, 0.01, 0.005} Float const1012: 2.6 FloatVector3 const1013: {4, 4, 2.6} Float const1014: 0.78 Float const1015: 0.36 Float const1016: 0.12 FloatVector3 const1017: {0.78, 0.36, 0.12} FloatVector3 const1035: {1.3, 0.6, 0.2} FloatVector3 const1059: {0.06, 0.06, 0.03} Float const1093: 256 FloatVector3 const1153: {0, 1, 0} Float const1230: -0.01 FloatVector3 const1290: {1, 1, 1} Float const1291: 0.25 FloatVector3 const1292: {0.5, 0.5, 0.25} FloatVector3 const1297: {0.9, 0.9, 0.5} Float const1347: 0.33 Float const1348: 0.53 Float const1369: -0.25 Float const1372: 0.35 Float const1376: 4.2 Float const1391: 10.1 Float const1409: 16 UInt32 const1444: 4 Function Local Variables: offset: unset, size: 16, FloatVector4 main.param1433 offset: unset, size: 8, FloatVector2 main.param1434 offset: unset, size: 16, FloatVector4 main.fragColor offset: unset, size: 8, FloatVector2 main.fragCoord offset: unset, size: 4, Float main.i offset: unset, size: 4, Float gumColour(f1;.i offset: unset, size: 4, Float gumRamp(f1;.n offset: unset, size: 12, FloatVector3 hash(f1;.x offset: unset, size: 12, FloatVector3 noise(vf3;.f offset: unset, size: 4, Float noise(vf3;.param211 offset: unset, size: 4, Float noise(vf3;.param215 offset: unset, size: 4, Float noise(vf3;.param222 offset: unset, size: 4, Float noise(vf3;.param227 offset: unset, size: 4, Float noise(vf3;.param237 offset: unset, size: 4, Float noise(vf3;.param242 offset: unset, size: 4, Float noise(vf3;.param250 offset: unset, size: 4, Float noise(vf3;.param255 offset: unset, size: 8, FloatVector2 noise(vf3;.p offset: unset, size: 12, FloatVector3 smN2(vf2;.param272 offset: unset, size: 12, FloatVector3 smN2(vf2;.p offset: unset, size: 12, FloatVector3 smN3(vf3;.param276 offset: unset, size: 12, FloatVector3 smN3(vf3;.p offset: unset, size: 4, Float fbm3(vf3;.f offset: unset, size: 4, Int32 fbm3(vf3;.i offset: unset, size: 12, FloatVector3 fbm3(vf3;.param301 offset: unset, size: 4, Float fbm3(vf3;.a offset: unset, size: 8, FloatVector2 fbm3(vf3;.v offset: unset, size: 8, FloatVector2 rotate(f1;vf2;.p offset: unset, size: 8, FloatVector2 sugarybit(vf2;.t offset: unset, size: 4, Float sugarybit(vf2;.ndotv offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param419 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param426 offset: unset, size: 4, Float sugarlayer(vf2;f1;.param445 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param447 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param449 offset: unset, size: 8, FloatVector2 sugarlayer(vf2;f1;.param453 offset: unset, size: 12, FloatVector3 sugarlayer(vf2;f1;.c offset: unset, size: 4, Float saturatecol(vf3;.param463 offset: unset, size: 8, FloatVector2 saturatecol(vf3;.coord offset: unset, size: 4, Float saturatecol(vf3;.ndotv offset: unset, size: 4, Float sprinkles2(vf2;f1;.sprinkle offset: unset, size: 4, Int32 sprinkles2(vf2;f1;.i offset: unset, size: 8, FloatVector2 sprinkles2(vf2;f1;.param493 offset: unset, size: 4, Float sprinkles2(vf2;f1;.param494 offset: unset, size: 8, FloatVector2 sprinkles2(vf2;f1;.coord offset: unset, size: 4, Float sprinkles2(vf2;f1;.ndotv offset: unset, size: 8, FloatVector2 sprinkles(vf2;f1;.param513 offset: unset, size: 4, Float sprinkles(vf2;f1;.param514 offset: unset, size: 8, FloatVector2 sprinkles(vf2;f1;.param519 offset: unset, size: 4, Float sprinkles(vf2;f1;.param520 offset: unset, size: 12, FloatVector3 sprinkles(vf2;f1;.no offset: unset, size: 12, FloatVector3 sprinkles(vf2;f1;.vo offset: unset, size: 12, FloatVector3 sprinkles(vf2;f1;.v offset: unset, size: 8, FloatVector2 gummy(vf3;vf3;vf3;.param544 offset: unset, size: 4, Float gummy(vf3;vf3;vf3;.param545 offset: unset, size: 8, FloatVector2 gummy(vf3;vf3;vf3;.param549 offset: unset, size: 4, Float gummy(vf3;vf3;vf3;.param552 offset: unset, size: 12, FloatVector3 gummy(vf3;vf3;vf3;.tex offset: unset, size: 4, Float gummy(vf3;vf3;vf3;.param570 offset: unset, size: 12, FloatVector3 gummy(vf3;vf3;vf3;.param591 offset: unset, size: 12, FloatVector3 gummy(vf3;vf3;vf3;.p offset: unset, size: 12, FloatVector3 de(vf3;.param635 offset: unset, size: 12, FloatVector3 de(vf3;.param643 offset: unset, size: 8, FloatVector2 de(vf3;.p offset: unset, size: 12, FloatVector3 marble(vf2;.param740 offset: unset, size: 12, FloatVector3 marble(vf2;.param767 offset: unset, size: 12, FloatVector3 marble(vf2;.param779 offset: unset, size: 12, FloatVector3 marble(vf2;.param790 offset: unset, size: 4, Float marble(vf2;.t offset: unset, size: 4, Float cameraPos(f1;.ti offset: unset, size: 12, FloatVector3 targetPos(f1;.target offset: unset, size: 4, Float targetPos(f1;.param858 offset: unset, size: 4, Float targetPos(f1;.ti offset: unset, size: 12, FloatVector3 cameraZoom(f1;.ro offset: unset, size: 12, FloatVector3 cameraZoom(f1;.rd offset: unset, size: 4, Float cameraZoom(f1;.t offset: unset, size: 4, Float cameraZoom(f1;.max_t offset: unset, size: 4, Int32 trace(vf3;vf3;f1;f1;.i offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param914 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.col offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param949 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param957 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param965 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param973 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.chocolour offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1028 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1079 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1081 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param1083 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1131 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1137 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1139 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.camu offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.p offset: unset, size: 4, Float mainImage(vf4;vf2;.param1204 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1206 offset: unset, size: 4, Float mainImage(vf4;vf2;.t offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.col offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1239 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1241 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1243 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1245 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.c offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.cc offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param1312 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1330 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param1331 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param1333 offset: unset, size: 4, Float mainImage(vf4;vf2;.param1341 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1381 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param1396 Instructions: V_SUB_F32 vDst(VGPR3) src0(SGPR2) src1(VGPR3) // VOP2 # Void main() Function: Void main() # lb5 Label: lb5 # OpStore: : const101 >> tc S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR242) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR20) src0(SGPR241) V_MOV_B32 vDst(VGPR21) src0(SGPR242) # OpStore: : const100 >> time S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR22) src0(SGPR241) # OpStore: : const100 >> colour S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR23) src0(SGPR241) # OpStore: : const106 >> ss V_MOV_B32 vDst(VGPR24) src0(1_0_F) # OpStore: : const100 >> is_choc S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR25) src0(SGPR241) # OpStore: : const109 >> t_per_target S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR26) src0(SGPR241) # OpStore: : const114 >> l S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3ea1e89b S_MOV_B32 sDst(SGPR242) src0(LITERAL_CONST) const: 0x3f72dce9 S_MOV_B32 sDst(SGPR243) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR27) src0(SGPR241) V_MOV_B32 vDst(VGPR28) src0(SGPR242) V_MOV_B32 vDst(VGPR29) src0(SGPR243) # OpStore: : const100 >> icing_factor S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR30) src0(SGPR241) # 1435: OpLoad: FloatVector4: tmp1435 << gl_FragCoord V_MOV_B32 vDst(VGPR332) src0(VGPR2) V_MOV_B32 vDst(VGPR333) src0(VGPR3) V_MOV_B32 vDst(VGPR334) src0(VGPR4) V_MOV_B32 vDst(VGPR335) src0(VGPR5) # 1436: OpVectorShuffle: FloatVector2: tmp1436 << tmp1435, tmp1435, 0, 1 V_MOV_B32 vDst(VGPR336) src0(VGPR332) V_MOV_B32 vDst(VGPR337) src0(VGPR333) # OpStore: : tmp1436 >> param1434 V_MOV_B32 vDst(VGPR18) src0(VGPR336) V_MOV_B32 vDst(VGPR19) src0(VGPR337) # 1437: OpFunctionCall: Void: mainImage(vf4;vf2;(param1433, param1434) S_ADD_U32 sDst(SGPR9) src0(LITERAL_CONST) src1(0) const: 0xd # VGPR[18:21] S_ADD_U32 sDst(SGPR12) src0(LITERAL_CONST) src1(0) const: 0x12 # VGPR[22:23] S_MOV_B64 sDst(SGPR14) src0(EXEC) # Indirect branch to mainImage(vf4;vf2;: 12416 S_GETPC_B64 sDst(SGPR10) src0(SGPR10) S_ADD_U32 sDst(SGPR10) src0(SGPR10) src1(LITERAL_CONST) const: 0x3080 S_ADDC_U32 sDst(SGPR11) src0(SGPR11) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR10) src0(SGPR10) S_MOV_B64 sDst(EXEC) src0(SGPR14) # .lbl0 # 1438: OpLoad: FloatVector4: tmp1438 << param1433 # OpStore: : tmp1438 >> finalColor V_MOV_B32 vDst(VGPR332) src0(VGPR13) V_MOV_B32 vDst(VGPR333) src0(VGPR14) V_MOV_B32 vDst(VGPR334) src0(VGPR15) V_MOV_B32 vDst(VGPR335) src0(VGPR16) # OpReturn: V_CVT_PKRTZ_F16_F32 vDst(VGPR332) src0(VGPR332) src1(VGPR333) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_CVT_PKRTZ_F16_F32 vDst(VGPR333) src0(VGPR334) src1(VGPR335) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a EXP en(0xf) tgt(0) compr(1) done(1) vm(1) vsrc0(VGPR332) vsrc1(VGPR333) vsrc2(VGPR334) vsrc3(VGPR335) S_WAITCNT 0 S_ENDPGM 0 # FloatVector3 gumColour(f1;(Float* i) Function: FloatVector3 gumColour(f1;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb12 Label: lb12 # 116: OpLoad: Float: tmp116 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR18) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 118: OpFOrdLessThan: Bool: tmp118 << tmp116, const106 V_MOV_B32 vDst(VGPR333) src0(1_0_F) V_CMP_LT_F32 dst(SGPR244) src0(VGPR332) src1(VGPR333) // VOP3a # OpSelectionMerge: (merge: lb120) # CF Block: Merge: lb120 S_MOV_B64 sDst(SGPR246) src0(EXEC) # OpBranchConditional: if(tmp118) then branch to lb119, else branch to lb125 # CF Block: Cond Branch: true: lb119, false: lb125 S_AND_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_CBRANCH_EXECZ 11 lb125 # lb119 Label: lb119 # OpReturnValue: : << const123 S_MOV_B32 sDst(SGPR248) src0(LITERAL_CONST) const: 0x3de147ae S_MOV_B32 sDst(SGPR249) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR250) src0(LITERAL_CONST) const: 0x3b03126f S_MOV_B32 sDst(M0) src0(SGPR13) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR248) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR249) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR250) S_ANDN2_B64 sDst(SGPR242) src0(SGPR242) src1(EXEC) # lb125 Label: lb125 S_ANDN2_B64 sDst(EXEC) src0(SGPR246) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 62 lb120 # 126: OpLoad: Float: tmp126 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR18) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 128: OpFOrdLessThan: Bool: tmp128 << tmp126, const127 V_MOV_B32 vDst(VGPR333) src0(2_0_F) V_CMP_LT_F32 dst(SGPR244) src0(VGPR332) src1(VGPR333) // VOP3a # OpSelectionMerge: (merge: lb130) # CF Block: Merge: lb130 S_MOV_B64 sDst(SGPR248) src0(EXEC) # OpBranchConditional: if(tmp128) then branch to lb129, else branch to lb134 # CF Block: Cond Branch: true: lb129, false: lb134 S_AND_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_CBRANCH_EXECZ 11 lb134 # lb129 Label: lb129 # OpReturnValue: : << const132 S_MOV_B32 sDst(SGPR250) src0(LITERAL_CONST) const: 0x3b03126f S_MOV_B32 sDst(SGPR251) src0(LITERAL_CONST) const: 0x3d75c28f S_MOV_B32 sDst(SGPR252) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(M0) src0(SGPR13) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR250) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR251) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR252) S_ANDN2_B64 sDst(SGPR242) src0(SGPR242) src1(EXEC) # lb134 Label: lb134 S_ANDN2_B64 sDst(EXEC) src0(SGPR248) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 37 lb130 # 135: OpLoad: Float: tmp135 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR18) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 136: OpFOrdLessThan: Bool: tmp136 << tmp135, const109 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x40400000 V_CMP_LT_F32 dst(SGPR244) src0(VGPR332) src1(VGPR333) // VOP3a # OpSelectionMerge: (merge: lb138) # CF Block: Merge: lb138 S_MOV_B64 sDst(SGPR250) src0(EXEC) # OpBranchConditional: if(tmp136) then branch to lb137, else branch to lb142 # CF Block: Cond Branch: true: lb137, false: lb142 S_AND_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_CBRANCH_EXECZ 11 lb142 # lb137 Label: lb137 # OpReturnValue: : << const140 S_MOV_B32 sDst(SGPR252) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR253) src0(LITERAL_CONST) const: 0x3ca3d70a S_MOV_B32 sDst(SGPR254) src0(LITERAL_CONST) const: 0x3de147ae S_MOV_B32 sDst(M0) src0(SGPR13) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR252) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR253) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR254) S_ANDN2_B64 sDst(SGPR242) src0(SGPR242) src1(EXEC) # lb142 Label: lb142 S_ANDN2_B64 sDst(EXEC) src0(SGPR250) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 11 lb138 # OpReturnValue: : << const144 S_MOV_B32 sDst(SGPR252) src0(LITERAL_CONST) const: 0x3de147ae S_MOV_B32 sDst(SGPR253) src0(LITERAL_CONST) const: 0x3c449ba6 S_MOV_B32 sDst(SGPR254) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(M0) src0(SGPR13) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR252) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR253) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR254) S_ANDN2_B64 sDst(SGPR242) src0(SGPR242) src1(EXEC) # lb138 Label: lb138 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR250) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR242) # OpBranch: to lb130 # lb130 Label: lb130 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR248) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR242) # OpBranch: to lb120 # lb120 Label: lb120 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR246) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR242) # 146: OpUndef: FloatVector3: tmp146 << # OpReturnValue: : << tmp146 S_MOV_B32 sDst(M0) src0(SGPR13) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR241) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR242) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR243) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # FloatVector3 gumRamp(f1;(Float* i) Function: FloatVector3 gumRamp(f1;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb15 Label: lb15 # 147: OpLoad: Float: tmp147 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR22) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 148: OpFOrdLessThan: Bool: tmp148 << tmp147, const106 V_MOV_B32 vDst(VGPR333) src0(1_0_F) V_CMP_LT_F32 dst(SGPR244) src0(VGPR332) src1(VGPR333) // VOP3a # OpSelectionMerge: (merge: lb150) # CF Block: Merge: lb150 S_MOV_B64 sDst(SGPR246) src0(EXEC) # OpBranchConditional: if(tmp148) then branch to lb149, else branch to lb154 # CF Block: Cond Branch: true: lb149, false: lb154 S_AND_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_CBRANCH_EXECZ 9 lb154 # lb149 Label: lb149 # OpReturnValue: : << const152 S_MOV_B32 sDst(SGPR248) src0(LITERAL_CONST) const: 0x3f4ccccd S_MOV_B32 sDst(SGPR249) src0(1_0_F) S_MOV_B32 sDst(SGPR250) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR19) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR248) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR249) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR250) S_ANDN2_B64 sDst(SGPR242) src0(SGPR242) src1(EXEC) # lb154 Label: lb154 S_ANDN2_B64 sDst(EXEC) src0(SGPR246) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 58 lb150 # 155: OpLoad: Float: tmp155 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR22) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 156: OpFOrdLessThan: Bool: tmp156 << tmp155, const127 V_MOV_B32 vDst(VGPR333) src0(2_0_F) V_CMP_LT_F32 dst(SGPR244) src0(VGPR332) src1(VGPR333) // VOP3a # OpSelectionMerge: (merge: lb158) # CF Block: Merge: lb158 S_MOV_B64 sDst(SGPR248) src0(EXEC) # OpBranchConditional: if(tmp156) then branch to lb157, else branch to lb161 # CF Block: Cond Branch: true: lb157, false: lb161 S_AND_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_CBRANCH_EXECZ 10 lb161 # lb157 Label: lb157 # OpReturnValue: : << const159 S_MOV_B32 sDst(SGPR250) src0(LITERAL_CONST) const: 0x3f4ccccd S_MOV_B32 sDst(SGPR251) src0(LITERAL_CONST) const: 0x3f4ccccd S_MOV_B32 sDst(SGPR252) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR19) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR250) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR251) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR252) S_ANDN2_B64 sDst(SGPR242) src0(SGPR242) src1(EXEC) # lb161 Label: lb161 S_ANDN2_B64 sDst(EXEC) src0(SGPR248) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 34 lb158 # 162: OpLoad: Float: tmp162 << i S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR22) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 163: OpFOrdLessThan: Bool: tmp163 << tmp162, const109 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x40400000 V_CMP_LT_F32 dst(SGPR244) src0(VGPR332) src1(VGPR333) // VOP3a # OpSelectionMerge: (merge: lb165) # CF Block: Merge: lb165 S_MOV_B64 sDst(SGPR250) src0(EXEC) # OpBranchConditional: if(tmp163) then branch to lb164, else branch to lb168 # CF Block: Cond Branch: true: lb164, false: lb168 S_AND_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_CBRANCH_EXECZ 9 lb168 # lb164 Label: lb164 # OpReturnValue: : << const166 S_MOV_B32 sDst(SGPR252) src0(1_0_F) S_MOV_B32 sDst(SGPR253) src0(LITERAL_CONST) const: 0x3f4ccccd S_MOV_B32 sDst(SGPR254) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR19) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR252) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR253) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR254) S_ANDN2_B64 sDst(SGPR242) src0(SGPR242) src1(EXEC) # lb168 Label: lb168 S_ANDN2_B64 sDst(EXEC) src0(SGPR250) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 10 lb165 # OpReturnValue: : << const159 S_MOV_B32 sDst(SGPR252) src0(LITERAL_CONST) const: 0x3f4ccccd S_MOV_B32 sDst(SGPR253) src0(LITERAL_CONST) const: 0x3f4ccccd S_MOV_B32 sDst(SGPR254) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR19) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR252) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR253) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR254) S_ANDN2_B64 sDst(SGPR242) src0(SGPR242) src1(EXEC) # lb165 Label: lb165 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR250) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR242) # OpBranch: to lb158 # lb158 Label: lb158 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR248) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR242) # OpBranch: to lb150 # lb150 Label: lb150 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR246) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR242) # 170: OpUndef: FloatVector3: tmp170 << # OpReturnValue: : << tmp170 S_MOV_B32 sDst(M0) src0(SGPR19) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR241) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR242) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR243) S_SETPC_B64 sDst(SGPR20) src0(SGPR20) # Float hash(f1;(Float* n) Function: Float hash(f1;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb19 Label: lb19 # 171: OpLoad: Float: tmp171 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR26) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 172: OpExtInst(Sin): Float: tmp172 << tmp171 V_MUL_F32 vDst(VGPR333) src0(LITERAL_CONST) src1(VGPR332) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR333) src0(VGPR333) V_SIN_F32 vDst(VGPR333) src0(VGPR333) # 174: OpFMul: Float: tmp174 << tmp172, const173 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x472aee8c V_MUL_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) // VOP2 # 175: OpExtInst(Fract): Float: tmp175 << tmp174 V_FRACT_F32 vDst(VGPR332) src0(VGPR334) # OpReturnValue: : << tmp175 S_MOV_B32 sDst(M0) src0(SGPR23) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR332) S_SETPC_B64 sDst(SGPR24) src0(SGPR24) # Float noise(vf3;(FloatVector3* x) Function: Float noise(vf3;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb24 Label: lb24 # 179: OpLoad: FloatVector3: tmp179 << x S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR30) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) # 180: OpExtInst(Floor): FloatVector3: tmp180 << tmp179 V_FLOOR_F32 vDst(VGPR335) src0(VGPR332) V_FLOOR_F32 vDst(VGPR336) src0(VGPR333) V_FLOOR_F32 vDst(VGPR337) src0(VGPR334) # 182: OpLoad: FloatVector3: tmp182 << x S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR30) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) # 183: OpExtInst(Fract): FloatVector3: tmp183 << tmp182 V_FRACT_F32 vDst(VGPR338) src0(VGPR332) V_FRACT_F32 vDst(VGPR339) src0(VGPR333) V_FRACT_F32 vDst(VGPR340) src0(VGPR334) # OpStore: : tmp183 >> f V_MOV_B32 vDst(VGPR31) src0(VGPR338) V_MOV_B32 vDst(VGPR32) src0(VGPR339) V_MOV_B32 vDst(VGPR33) src0(VGPR340) # 184: OpLoad: FloatVector3: tmp184 << f # 185: OpLoad: FloatVector3: tmp185 << f # 186: OpFMul: FloatVector3: tmp186 << tmp184, tmp185 V_MUL_F32 vDst(VGPR332) src0(VGPR31) src1(VGPR31) // VOP2 V_MUL_F32 vDst(VGPR333) src0(VGPR32) src1(VGPR32) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR33) src1(VGPR33) // VOP2 # 187: OpLoad: FloatVector3: tmp187 << f # 188: OpVectorTimesScalar: FloatVector3: tmp188 << tmp187, const127 V_MOV_B32 vDst(VGPR338) src0(2_0_F) V_MUL_F32 vDst(VGPR339) src0(VGPR338) src1(VGPR31) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR338) src1(VGPR32) // VOP2 V_MUL_F32 vDst(VGPR341) src0(VGPR338) src1(VGPR33) // VOP2 # 189: OpCompositeConstruct: FloatVector3: tmp189 << const109, const109, const109 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR342) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR343) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR344) src0(SGPR241) # 190: OpFSub: FloatVector3: tmp190 << tmp189, tmp188 V_SUB_F32 vDst(VGPR345) src0(VGPR342) src1(VGPR339) // VOP2 V_SUB_F32 vDst(VGPR346) src0(VGPR343) src1(VGPR340) // VOP2 V_SUB_F32 vDst(VGPR347) src0(VGPR344) src1(VGPR341) // VOP2 # 191: OpFMul: FloatVector3: tmp191 << tmp186, tmp190 V_MUL_F32 vDst(VGPR338) src0(VGPR332) src1(VGPR345) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR333) src1(VGPR346) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR334) src1(VGPR347) // VOP2 # OpStore: : tmp191 >> f V_MOV_B32 vDst(VGPR31) src0(VGPR338) V_MOV_B32 vDst(VGPR32) src0(VGPR339) V_MOV_B32 vDst(VGPR33) src0(VGPR340) # 195: OpAccessChain: Float*: p[0] # 196: OpCompositeExtract: Float: tmp196 << tmp180, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR335) # 198: OpAccessChain: Float*: p[1] # 199: OpCompositeExtract: Float: tmp199 << tmp180, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR336) # 201: OpFMul: Float: tmp201 << tmp199, const200 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x431d0000 V_MUL_F32 vDst(VGPR338) src0(VGPR333) src1(VGPR334) // VOP2 # 202: OpFAdd: Float: tmp202 << tmp196, tmp201 V_ADD_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR338) // VOP2 # 205: OpAccessChain: Float*: p[2] # 206: OpCompositeExtract: Float: tmp206 << tmp180, 2 V_MOV_B32 vDst(VGPR332) src0(VGPR337) # 207: OpFMul: Float: tmp207 << const203, tmp206 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x42e20000 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR332) // VOP2 # 208: OpFAdd: Float: tmp208 << tmp202, tmp207 V_ADD_F32 vDst(VGPR42) src0(VGPR333) src1(VGPR335) // VOP2 # 210: OpFAdd: Float: tmp210 << tmp208, const100 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR333) src0(VGPR42) src1(VGPR332) // VOP2 # OpStore: : tmp210 >> param211 V_MOV_B32 vDst(VGPR34) src0(VGPR333) # 212: OpFunctionCall: Float: hash(f1;(param211) S_ADD_U32 sDst(SGPR26) src0(LITERAL_CONST) src1(0) const: 0x22 # VGPR99 S_MOV_B64 sDst(SGPR32) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0x2b # VGPR149 # Indirect branch to hash(f1;: -324 S_GETPC_B64 sDst(SGPR24) src0(SGPR24) S_SUB_U32 sDst(SGPR24) src0(SGPR24) src1(LITERAL_CONST) const: 0x144 S_SUBB_U32 sDst(SGPR25) src0(SGPR25) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR24) src0(SGPR24) S_MOV_B64 sDst(EXEC) src0(SGPR32) # .lbl1 # 214: OpFAdd: Float: tmp214 << tmp208, const106 V_MOV_B32 vDst(VGPR332) src0(1_0_F) V_ADD_F32 vDst(VGPR333) src0(VGPR42) src1(VGPR332) // VOP2 # OpStore: : tmp214 >> param215 V_MOV_B32 vDst(VGPR35) src0(VGPR333) # 216: OpFunctionCall: Float: hash(f1;(param215) S_ADD_U32 sDst(SGPR26) src0(LITERAL_CONST) src1(0) const: 0x23 # VGPR100 S_MOV_B64 sDst(SGPR34) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0x2c # VGPR152 # Indirect branch to hash(f1;: -384 S_GETPC_B64 sDst(SGPR24) src0(SGPR24) S_SUB_U32 sDst(SGPR24) src0(SGPR24) src1(LITERAL_CONST) const: 0x180 S_SUBB_U32 sDst(SGPR25) src0(SGPR25) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR24) src0(SGPR24) S_MOV_B64 sDst(EXEC) src0(SGPR34) # .lbl2 # 217: OpAccessChain: Float*: f[0] # 218: OpLoad: Float: tmp218 << f[0] V_MOV_B32 vDst(VGPR332) src0(VGPR31) # 219: OpExtInst(FMix): Float: tmp219 << hash(f1;, hash(f1;, tmp218 V_SUBREV_F32 vDst(VGPR45) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR45) src0(VGPR43) src1(VGPR45) // VOP2 V_MAD_F32 vDst(VGPR45) src0(VGPR44) src1(VGPR332) src2(VGPR45) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 221: OpFAdd: Float: tmp221 << tmp208, const200 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x431d0000 V_ADD_F32 vDst(VGPR333) src0(VGPR42) src1(VGPR332) // VOP2 # OpStore: : tmp221 >> param222 V_MOV_B32 vDst(VGPR36) src0(VGPR333) # 223: OpFunctionCall: Float: hash(f1;(param222) S_ADD_U32 sDst(SGPR26) src0(LITERAL_CONST) src1(0) const: 0x24 # VGPR101 S_MOV_B64 sDst(SGPR36) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0x2e # VGPR157 # Indirect branch to hash(f1;: -472 S_GETPC_B64 sDst(SGPR24) src0(SGPR24) S_SUB_U32 sDst(SGPR24) src0(SGPR24) src1(LITERAL_CONST) const: 0x1d8 S_SUBB_U32 sDst(SGPR25) src0(SGPR25) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR24) src0(SGPR24) S_MOV_B64 sDst(EXEC) src0(SGPR36) # .lbl3 # 226: OpFAdd: Float: tmp226 << tmp208, const225 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x431e0000 V_ADD_F32 vDst(VGPR333) src0(VGPR42) src1(VGPR332) // VOP2 # OpStore: : tmp226 >> param227 V_MOV_B32 vDst(VGPR37) src0(VGPR333) # 228: OpFunctionCall: Float: hash(f1;(param227) S_ADD_U32 sDst(SGPR26) src0(LITERAL_CONST) src1(0) const: 0x25 # VGPR102 S_MOV_B64 sDst(SGPR38) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0x2f # VGPR160 # Indirect branch to hash(f1;: -536 S_GETPC_B64 sDst(SGPR24) src0(SGPR24) S_SUB_U32 sDst(SGPR24) src0(SGPR24) src1(LITERAL_CONST) const: 0x218 S_SUBB_U32 sDst(SGPR25) src0(SGPR25) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR24) src0(SGPR24) S_MOV_B64 sDst(EXEC) src0(SGPR38) # .lbl4 # 229: OpAccessChain: Float*: f[0] # 230: OpLoad: Float: tmp230 << f[0] V_MOV_B32 vDst(VGPR332) src0(VGPR31) # 231: OpExtInst(FMix): Float: tmp231 << hash(f1;, hash(f1;, tmp230 V_SUBREV_F32 vDst(VGPR333) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR333) src0(VGPR46) src1(VGPR333) // VOP2 V_MAD_F32 vDst(VGPR333) src0(VGPR47) src1(VGPR332) src2(VGPR333) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 232: OpAccessChain: Float*: f[1] # 233: OpLoad: Float: tmp233 << f[1] V_MOV_B32 vDst(VGPR332) src0(VGPR32) # 234: OpExtInst(FMix): Float: tmp234 << tmp219, tmp231, tmp233 V_SUBREV_F32 vDst(VGPR48) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR48) src0(VGPR45) src1(VGPR48) // VOP2 V_MAD_F32 vDst(VGPR48) src0(VGPR333) src1(VGPR332) src2(VGPR48) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 236: OpFAdd: Float: tmp236 << tmp208, const203 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x42e20000 V_ADD_F32 vDst(VGPR333) src0(VGPR42) src1(VGPR332) // VOP2 # OpStore: : tmp236 >> param237 V_MOV_B32 vDst(VGPR38) src0(VGPR333) # 238: OpFunctionCall: Float: hash(f1;(param237) S_ADD_U32 sDst(SGPR26) src0(LITERAL_CONST) src1(0) const: 0x26 # VGPR103 S_MOV_B64 sDst(SGPR40) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0x31 # VGPR167 # Indirect branch to hash(f1;: -648 S_GETPC_B64 sDst(SGPR24) src0(SGPR24) S_SUB_U32 sDst(SGPR24) src0(SGPR24) src1(LITERAL_CONST) const: 0x288 S_SUBB_U32 sDst(SGPR25) src0(SGPR25) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR24) src0(SGPR24) S_MOV_B64 sDst(EXEC) src0(SGPR40) # .lbl5 # 241: OpFAdd: Float: tmp241 << tmp208, const240 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x42e40000 V_ADD_F32 vDst(VGPR333) src0(VGPR42) src1(VGPR332) // VOP2 # OpStore: : tmp241 >> param242 V_MOV_B32 vDst(VGPR39) src0(VGPR333) # 243: OpFunctionCall: Float: hash(f1;(param242) S_ADD_U32 sDst(SGPR26) src0(LITERAL_CONST) src1(0) const: 0x27 # VGPR104 S_MOV_B64 sDst(SGPR42) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0x32 # VGPR170 # Indirect branch to hash(f1;: -712 S_GETPC_B64 sDst(SGPR24) src0(SGPR24) S_SUB_U32 sDst(SGPR24) src0(SGPR24) src1(LITERAL_CONST) const: 0x2c8 S_SUBB_U32 sDst(SGPR25) src0(SGPR25) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR24) src0(SGPR24) S_MOV_B64 sDst(EXEC) src0(SGPR42) # .lbl6 # 244: OpAccessChain: Float*: f[0] # 245: OpLoad: Float: tmp245 << f[0] V_MOV_B32 vDst(VGPR332) src0(VGPR31) # 246: OpExtInst(FMix): Float: tmp246 << hash(f1;, hash(f1;, tmp245 V_SUBREV_F32 vDst(VGPR51) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR51) src0(VGPR49) src1(VGPR51) // VOP2 V_MAD_F32 vDst(VGPR51) src0(VGPR50) src1(VGPR332) src2(VGPR51) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 249: OpFAdd: Float: tmp249 << tmp208, const248 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x43870000 V_ADD_F32 vDst(VGPR333) src0(VGPR42) src1(VGPR332) // VOP2 # OpStore: : tmp249 >> param250 V_MOV_B32 vDst(VGPR40) src0(VGPR333) # 251: OpFunctionCall: Float: hash(f1;(param250) S_ADD_U32 sDst(SGPR26) src0(LITERAL_CONST) src1(0) const: 0x28 # VGPR105 S_MOV_B64 sDst(SGPR44) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0x34 # VGPR175 # Indirect branch to hash(f1;: -800 S_GETPC_B64 sDst(SGPR24) src0(SGPR24) S_SUB_U32 sDst(SGPR24) src0(SGPR24) src1(LITERAL_CONST) const: 0x320 S_SUBB_U32 sDst(SGPR25) src0(SGPR25) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR24) src0(SGPR24) S_MOV_B64 sDst(EXEC) src0(SGPR44) # .lbl7 # 254: OpFAdd: Float: tmp254 << tmp208, const253 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x43878000 V_ADD_F32 vDst(VGPR333) src0(VGPR42) src1(VGPR332) // VOP2 # OpStore: : tmp254 >> param255 V_MOV_B32 vDst(VGPR41) src0(VGPR333) # 256: OpFunctionCall: Float: hash(f1;(param255) S_ADD_U32 sDst(SGPR26) src0(LITERAL_CONST) src1(0) const: 0x29 # VGPR106 S_MOV_B64 sDst(SGPR46) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0x35 # VGPR178 # Indirect branch to hash(f1;: -864 S_GETPC_B64 sDst(SGPR24) src0(SGPR24) S_SUB_U32 sDst(SGPR24) src0(SGPR24) src1(LITERAL_CONST) const: 0x360 S_SUBB_U32 sDst(SGPR25) src0(SGPR25) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR24) src0(SGPR24) S_MOV_B64 sDst(EXEC) src0(SGPR46) # .lbl8 # 257: OpAccessChain: Float*: f[0] # 258: OpLoad: Float: tmp258 << f[0] V_MOV_B32 vDst(VGPR332) src0(VGPR31) # 259: OpExtInst(FMix): Float: tmp259 << hash(f1;, hash(f1;, tmp258 V_SUBREV_F32 vDst(VGPR333) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR333) src0(VGPR52) src1(VGPR333) // VOP2 V_MAD_F32 vDst(VGPR333) src0(VGPR53) src1(VGPR332) src2(VGPR333) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 260: OpAccessChain: Float*: f[1] # 261: OpLoad: Float: tmp261 << f[1] V_MOV_B32 vDst(VGPR332) src0(VGPR32) # 262: OpExtInst(FMix): Float: tmp262 << tmp246, tmp259, tmp261 V_SUBREV_F32 vDst(VGPR334) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR334) src0(VGPR51) src1(VGPR334) // VOP2 V_MAD_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) src2(VGPR334) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 263: OpAccessChain: Float*: f[2] # 264: OpLoad: Float: tmp264 << f[2] V_MOV_B32 vDst(VGPR332) src0(VGPR33) # 265: OpExtInst(FMix): Float: tmp265 << tmp234, tmp262, tmp264 V_SUBREV_F32 vDst(VGPR333) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR333) src0(VGPR48) src1(VGPR333) // VOP2 V_MAD_F32 vDst(VGPR333) src0(VGPR334) src1(VGPR332) src2(VGPR333) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp265 S_MOV_B32 sDst(M0) src0(SGPR27) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR333) S_SETPC_B64 sDst(SGPR28) src0(SGPR28) # Float smN2(vf2;(FloatVector2* p) Function: Float smN2(vf2;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb30 Label: lb30 # 268: OpLoad: FloatVector2: tmp268 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR50) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 269: OpCompositeExtract: Float: tmp269 << tmp268, 0 V_MOV_B32 vDst(VGPR334) src0(VGPR332) # 270: OpCompositeExtract: Float: tmp270 << tmp268, 1 V_MOV_B32 vDst(VGPR335) src0(VGPR333) # 271: OpCompositeConstruct: FloatVector3: tmp271 << tmp269, tmp270, const100 V_MOV_B32 vDst(VGPR336) src0(VGPR334) V_MOV_B32 vDst(VGPR337) src0(VGPR335) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR338) src0(SGPR241) # OpStore: : tmp271 >> param272 V_MOV_B32 vDst(VGPR54) src0(VGPR336) V_MOV_B32 vDst(VGPR55) src0(VGPR337) V_MOV_B32 vDst(VGPR56) src0(VGPR338) # 273: OpFunctionCall: Float: noise(vf3;(param272) S_ADD_U32 sDst(SGPR30) src0(LITERAL_CONST) src1(0) const: 0x36 # VGPR[185:187] S_MOV_B64 sDst(SGPR52) src0(EXEC) S_MOV_B32 sDst(SGPR27) src0(LITERAL_CONST) const: 0x39 # VGPR196 # Indirect branch to noise(vf3;: -996 S_GETPC_B64 sDst(SGPR28) src0(SGPR28) S_SUB_U32 sDst(SGPR28) src0(SGPR28) src1(LITERAL_CONST) const: 0x3e4 S_SUBB_U32 sDst(SGPR29) src0(SGPR29) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR28) src0(SGPR28) S_MOV_B64 sDst(EXEC) src0(SGPR52) # .lbl9 # OpReturnValue: : << noise(vf3; S_MOV_B32 sDst(M0) src0(SGPR31) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR57) S_SETPC_B64 sDst(SGPR48) src0(SGPR48) # Float smN3(vf3;(FloatVector3* p) Function: Float smN3(vf3;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb33 Label: lb33 # 277: OpLoad: FloatVector3: tmp277 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR56) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) # OpStore: : tmp277 >> param276 V_MOV_B32 vDst(VGPR58) src0(VGPR332) V_MOV_B32 vDst(VGPR59) src0(VGPR333) V_MOV_B32 vDst(VGPR60) src0(VGPR334) # 278: OpFunctionCall: Float: noise(vf3;(param276) S_ADD_U32 sDst(SGPR30) src0(LITERAL_CONST) src1(0) const: 0x3a # VGPR[197:199] S_MOV_B64 sDst(SGPR58) src0(EXEC) S_MOV_B32 sDst(SGPR27) src0(LITERAL_CONST) const: 0x3d # VGPR203 # Indirect branch to noise(vf3;: -1092 S_GETPC_B64 sDst(SGPR28) src0(SGPR28) S_SUB_U32 sDst(SGPR28) src0(SGPR28) src1(LITERAL_CONST) const: 0x444 S_SUBB_U32 sDst(SGPR29) src0(SGPR29) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR28) src0(SGPR28) S_MOV_B64 sDst(EXEC) src0(SGPR58) # .lbl10 # OpReturnValue: : << noise(vf3; S_MOV_B32 sDst(M0) src0(SGPR51) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR61) S_SETPC_B64 sDst(SGPR54) src0(SGPR54) # Float fbm3(vf3;(FloatVector3* p) Function: Float fbm3(vf3;() S_MOV_B64 sDst(SGPR64) src0(EXEC) # lb36 Label: lb36 # OpStore: : const100 >> f S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR62) src0(SGPR241) # OpStore: : const285 >> i V_MOV_B32 vDst(VGPR63) src0(1_INT) # OpBranch: to lb286 # lb286 Label: lb286 # OpLoopMerge: (merge: lb288, continue: lb289) # CF Block: Merge: lb288, Continue: lb289 S_MOV_B64 sDst(SGPR66) src0(EXEC) S_MOV_B64 sDst(SGPR68) src0(EXEC) S_MOV_B64 sDst(SGPR70) src0(EXEC) Label: lb286Loop # OpBranch: to lb290 # lb290 Label: lb290 # 291: OpLoad: Int: tmp291 << i Decorators: RelaxedPrecision # 293: OpSLessThanEqual: Bool: tmp293 << tmp291, const292 V_MOV_B32 vDst(VGPR332) src0(9_INT) V_CMP_LE_I32 dst(SGPR242) src0(VGPR63) src1(VGPR332) // VOP3a # OpBranchConditional: if(tmp293) then branch to lb287, else branch to lb288 # CF Block: Cond Branch: true: lb287, false: lb288 S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 41 lb288 # lb287 Label: lb287 S_MOV_B64 sDst(SGPR68) src0(EXEC) S_MOV_B64 sDst(SGPR70) src0(EXEC) # 295: OpLoad: Int: tmp295 << i Decorators: RelaxedPrecision # 296: OpConvertSToF: Float: tmp296 << tmp295 V_CVT_F32_I32 vDst(VGPR332) src0(VGPR63) # 297: OpExtInst(Exp2): Float: tmp297 << tmp296 V_EXP_F32 vDst(VGPR67) src0(VGPR332) # 298: OpLoad: FloatVector3: tmp298 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR62) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) # 300: OpVectorTimesScalar: FloatVector3: tmp300 << tmp298, tmp297 V_MUL_F32 vDst(VGPR335) src0(VGPR67) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR67) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR67) src1(VGPR334) // VOP2 # OpStore: : tmp300 >> param301 V_MOV_B32 vDst(VGPR64) src0(VGPR335) V_MOV_B32 vDst(VGPR65) src0(VGPR336) V_MOV_B32 vDst(VGPR66) src0(VGPR337) # 302: OpFunctionCall: Float: noise(vf3;(param301) S_ADD_U32 sDst(SGPR30) src0(LITERAL_CONST) src1(0) const: 0x40 # VGPR[206:208] S_MOV_B64 sDst(SGPR72) src0(EXEC) S_MOV_B32 sDst(SGPR27) src0(LITERAL_CONST) const: 0x44 # VGPR219 # Indirect branch to noise(vf3;: -1264 S_GETPC_B64 sDst(SGPR28) src0(SGPR28) S_SUB_U32 sDst(SGPR28) src0(SGPR28) src1(LITERAL_CONST) const: 0x4f0 S_SUBB_U32 sDst(SGPR29) src0(SGPR29) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR28) src0(SGPR28) S_MOV_B64 sDst(EXEC) src0(SGPR72) # .lbl11 # 304: OpFSub: Float: tmp304 << noise(vf3;, const303 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_SUB_F32 vDst(VGPR333) src0(VGPR68) src1(VGPR332) // VOP2 # 306: OpFDiv: Float: tmp306 << tmp304, tmp297 V_RCP_F32 vDst(VGPR332) src0(VGPR67) V_MUL_F32 vDst(VGPR332) src0(VGPR333) src1(VGPR332) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR332) src0(VGPR332) src1(VGPR67) src2(VGPR333) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 307: OpLoad: Float: tmp307 << f # 308: OpFAdd: Float: tmp308 << tmp307, tmp306 V_ADD_F32 vDst(VGPR333) src0(VGPR62) src1(VGPR332) // VOP2 # OpStore: : tmp308 >> f V_MOV_B32 vDst(VGPR62) src0(VGPR333) # OpBranch: to lb289 # lb289 Label: lb289 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR68) # 309: OpLoad: Int: tmp309 << i Decorators: RelaxedPrecision # 310: OpIAdd: Int: tmp310 << tmp309, const285 Decorators: RelaxedPrecision S_MOV_B32 sDst(SGPR241) src0(1_INT) V_ADD_I32 vDst(VGPR332) src0(VGPR63) src1(SGPR241) src2(N/A) omod(0) neg(0) sDst(VCC) // VOP3b # OpStore: : tmp310 >> i V_MOV_B32 vDst(VGPR63) src0(VGPR332) # OpBranch: to lb286 S_BRANCH -46 lb286Loop # lb288 Label: lb288 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR66) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR64) # 311: OpLoad: Float: tmp311 << f # OpReturnValue: : << tmp311 S_MOV_B32 sDst(M0) src0(SGPR57) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR62) S_SETPC_B64 sDst(SGPR60) src0(SGPR60) # FloatVector2 rotate(f1;vf2;(Float* a, FloatVector2* v) Function: FloatVector2 rotate(f1;vf2;(, FloatVector2 fbm3(vf3;.v) S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb41 Label: lb41 # 314: OpLoad: Float: tmp314 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR76) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 315: OpExtInst(Cos): Float: tmp315 << tmp314 V_MUL_F32 vDst(VGPR333) src0(LITERAL_CONST) src1(VGPR332) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR333) src0(VGPR333) V_COS_F32 vDst(VGPR333) src0(VGPR333) # 316: OpAccessChain: Float*: v[0] # 317: OpLoad: Float: tmp317 << v[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 318: OpFMul: Float: tmp318 << tmp315, tmp317 V_MUL_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) // VOP2 # 319: OpLoad: Float: tmp319 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR76) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 320: OpExtInst(Sin): Float: tmp320 << tmp319 V_MUL_F32 vDst(VGPR333) src0(LITERAL_CONST) src1(VGPR332) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR333) src0(VGPR333) V_SIN_F32 vDst(VGPR333) src0(VGPR333) # 321: OpAccessChain: Float*: v[1] # 322: OpLoad: Float: tmp322 << v[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR1) # 323: OpFMul: Float: tmp323 << tmp320, tmp322 V_MUL_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR332) // VOP2 # 324: OpFAdd: Float: tmp324 << tmp318, tmp323 V_ADD_F32 vDst(VGPR332) src0(VGPR334) src1(VGPR335) // VOP2 # 325: OpLoad: Float: tmp325 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR76) const: 0x0 V_MOVRELS_B32 vDst(VGPR333) src0(VGPR0) # 326: OpExtInst(Cos): Float: tmp326 << tmp325 V_MUL_F32 vDst(VGPR334) src0(LITERAL_CONST) src1(VGPR333) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR334) src0(VGPR334) V_COS_F32 vDst(VGPR334) src0(VGPR334) # 327: OpAccessChain: Float*: v[1] # 328: OpLoad: Float: tmp328 << v[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 329: OpFMul: Float: tmp329 << tmp326, tmp328 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR333) // VOP2 # 330: OpLoad: Float: tmp330 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR76) const: 0x0 V_MOVRELS_B32 vDst(VGPR333) src0(VGPR0) # 331: OpExtInst(Sin): Float: tmp331 << tmp330 V_MUL_F32 vDst(VGPR334) src0(LITERAL_CONST) src1(VGPR333) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR334) src0(VGPR334) V_SIN_F32 vDst(VGPR334) src0(VGPR334) # 332: OpAccessChain: Float*: v[0] # 333: OpLoad: Float: tmp333 << v[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELS_B32 vDst(VGPR333) src0(VGPR0) # 334: OpFMul: Float: tmp334 << tmp331, tmp333 V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR333) // VOP2 # 335: OpFSub: Float: tmp335 << tmp329, tmp334 V_SUB_F32 vDst(VGPR333) src0(VGPR335) src1(VGPR336) // VOP2 # 336: OpCompositeConstruct: FloatVector2: tmp336 << tmp324, tmp335 V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR333) # OpReturnValue: : << tmp336 S_MOV_B32 sDst(M0) src0(SGPR63) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR334) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR335) S_SETPC_B64 sDst(SGPR74) src0(SGPR74) # Float sugarybit(vf2;(FloatVector2* p) Function: Float sugarybit(vf2;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb44 Label: lb44 # 339: OpLoad: FloatVector2: tmp339 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR81) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 343: OpExtInst(FClamp): FloatVector2: tmp343 << tmp339, const341, const342 V_MOV_B32 vDst(VGPR334) src0(M1_0_F) V_MOV_B32 vDst(VGPR335) src0(M1_0_F) V_MOV_B32 vDst(VGPR336) src0(1_0_F) V_MOV_B32 vDst(VGPR337) src0(1_0_F) V_MAX_F32 vDst(VGPR338) src0(VGPR332) src1(VGPR334) // VOP2 V_MAX_F32 vDst(VGPR339) src0(VGPR333) src1(VGPR335) // VOP2 V_MIN_F32 vDst(VGPR338) src0(VGPR338) src1(VGPR336) // VOP2 V_MIN_F32 vDst(VGPR339) src0(VGPR339) src1(VGPR337) // VOP2 # OpStore: : tmp343 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR81) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR338) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR339) # 346: OpAccessChain: Float*: p[0] # 347: OpLoad: Float: tmp347 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR81) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 348: OpExtInst(FAbs): Float: tmp348 << tmp347 V_ADD_F32 vDst(VGPR333) src0(VGPR332) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 350: OpExtInst(Pow): Float: tmp350 << tmp348, const349 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR334) src0(VGPR333) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR334) // VOP2 V_EXP_F32 vDst(VGPR334) src0(VGPR334) # 351: OpFSub: Float: tmp351 << const106, tmp350 V_SUB_F32 vDst(VGPR332) src0(1_0_F) src1(VGPR334) // VOP2 # 352: OpAccessChain: Float*: p[1] # 353: OpLoad: Float: tmp353 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR81) const: 0x0 V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 354: OpAccessChain: Float*: o[1] # 355: OpCompositeExtract: Float: tmp355 << const101, 1 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR334) src0(SGPR242) # 356: OpFAdd: Float: tmp356 << tmp353, tmp355 V_ADD_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR334) // VOP2 # 357: OpExtInst(FAbs): Float: tmp357 << tmp356 V_ADD_F32 vDst(VGPR333) src0(VGPR335) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 358: OpExtInst(Pow): Float: tmp358 << tmp357, const349 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR335) src0(VGPR333) V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR335) // VOP2 V_EXP_F32 vDst(VGPR335) src0(VGPR335) # 359: OpFSub: Float: tmp359 << const106, tmp358 V_SUB_F32 vDst(VGPR333) src0(1_0_F) src1(VGPR335) // VOP2 # 360: OpFMul: Float: tmp360 << tmp351, tmp359 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 362: OpFMul: Float: tmp362 << tmp360, const361 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f733333 V_MUL_F32 vDst(VGPR333) src0(VGPR334) src1(VGPR332) // VOP2 # 363: OpExtInst(Pow): Float: tmp363 << tmp362, const303 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_LOG_F32 vDst(VGPR334) src0(VGPR333) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR334) // VOP2 V_EXP_F32 vDst(VGPR334) src0(VGPR334) # 364: OpFSub: Float: tmp364 << const106, tmp363 V_SUB_F32 vDst(VGPR332) src0(1_0_F) src1(VGPR334) // VOP2 # 366: OpAccessChain: Float*: p[0] # 367: OpLoad: Float: tmp367 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR81) const: 0x0 V_MOVRELS_B32 vDst(VGPR333) src0(VGPR0) # 368: OpExtInst(FAbs): Float: tmp368 << tmp367 V_ADD_F32 vDst(VGPR334) src0(VGPR333) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 369: OpExtInst(Pow): Float: tmp369 << tmp368, const349 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR335) src0(VGPR334) V_MUL_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR335) // VOP2 V_EXP_F32 vDst(VGPR335) src0(VGPR335) # 370: OpFSub: Float: tmp370 << const106, tmp369 V_SUB_F32 vDst(VGPR333) src0(1_0_F) src1(VGPR335) // VOP2 # 371: OpAccessChain: Float*: p[1] # 372: OpLoad: Float: tmp372 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR81) const: 0x0 V_MOVRELS_B32 vDst(VGPR334) src0(VGPR1) # 373: OpExtInst(FAbs): Float: tmp373 << tmp372 V_ADD_F32 vDst(VGPR335) src0(VGPR334) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 374: OpExtInst(Pow): Float: tmp374 << tmp373, const349 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR336) src0(VGPR335) V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR336) // VOP2 V_EXP_F32 vDst(VGPR336) src0(VGPR336) # 375: OpFSub: Float: tmp375 << const106, tmp374 V_SUB_F32 vDst(VGPR334) src0(1_0_F) src1(VGPR336) // VOP2 # 376: OpFMul: Float: tmp376 << tmp370, tmp375 V_MUL_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR334) // VOP2 # 378: OpExtInst(Pow): Float: tmp378 << tmp376, const377 V_MOV_B32 vDst(VGPR333) src0(4_0_F) V_LOG_F32 vDst(VGPR334) src0(VGPR335) V_MUL_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR334) // VOP2 V_EXP_F32 vDst(VGPR334) src0(VGPR334) # 381: OpFMul: Float: tmp381 << tmp364, tmp378 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR334) // VOP2 # 382: OpFMul: Float: tmp382 << tmp381, const109 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) // VOP2 # OpReturnValue: : << tmp382 S_MOV_B32 sDst(M0) src0(SGPR80) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR334) S_SETPC_B64 sDst(SGPR78) src0(SGPR78) # Float sugarlayer(vf2;f1;(FloatVector2* t, Float* ndotv) Function: Float sugarlayer(vf2;f1;(, Float sugarybit(vf2;.ndotv) S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb49 Label: lb49 # 386: OpLoad: FloatVector2: tmp386 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 387: OpVectorTimesScalar: FloatVector2: tmp387 << tmp386, const349 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x41000000 V_MUL_F32 vDst(VGPR80) src0(VGPR334) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR81) src0(VGPR334) src1(VGPR333) // VOP2 # 390: OpExtInst(Fract): FloatVector2: tmp390 << tmp387 V_FRACT_F32 vDst(VGPR332) src0(VGPR80) V_FRACT_F32 vDst(VGPR333) src0(VGPR81) # 392: OpFSub: FloatVector2: tmp392 << tmp390, const391 V_MOV_B32 vDst(VGPR334) src0(0_5_F) V_MOV_B32 vDst(VGPR335) src0(0_5_F) V_SUB_F32 vDst(VGPR82) src0(VGPR332) src1(VGPR334) // VOP2 V_SUB_F32 vDst(VGPR83) src0(VGPR333) src1(VGPR335) // VOP2 # 395: OpExtInst(Floor): FloatVector2: tmp395 << tmp387 V_FLOOR_F32 vDst(VGPR84) src0(VGPR80) V_FLOOR_F32 vDst(VGPR85) src0(VGPR81) # 397: OpAccessChain: Float*: c[0] # 398: OpCompositeExtract: Float: tmp398 << tmp395, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR84) # 399: OpAccessChain: Float*: c[1] # 400: OpCompositeExtract: Float: tmp400 << tmp395, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR85) # 402: OpFMul: Float: tmp402 << tmp400, const401 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR334) // VOP2 # 403: OpFAdd: Float: tmp403 << tmp398, tmp402 V_ADD_F32 vDst(VGPR86) src0(VGPR332) src1(VGPR335) // VOP2 # 405: OpAccessChain: Float*: c[1] # 406: OpCompositeExtract: Float: tmp406 << tmp395, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR85) # 408: OpFMul: Float: tmp408 << tmp406, const407 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x42540000 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 409: OpExtInst(Cos): Float: tmp409 << tmp408 V_MUL_F32 vDst(VGPR332) src0(LITERAL_CONST) src1(VGPR334) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR332) src0(VGPR332) V_COS_F32 vDst(VGPR332) src0(VGPR332) # 410: OpAccessChain: Float*: c[0] # 411: OpCompositeExtract: Float: tmp411 << tmp395, 0 V_MOV_B32 vDst(VGPR333) src0(VGPR84) # 413: OpFMul: Float: tmp413 << tmp411, const412 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x42fa0000 V_MUL_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR334) // VOP2 # 414: OpExtInst(Sin): Float: tmp414 << tmp413 V_MUL_F32 vDst(VGPR333) src0(LITERAL_CONST) src1(VGPR335) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR333) src0(VGPR333) V_SIN_F32 vDst(VGPR333) src0(VGPR333) # 415: OpCompositeConstruct: FloatVector2: tmp415 << tmp409, tmp414 V_MOV_B32 vDst(VGPR336) src0(VGPR332) V_MOV_B32 vDst(VGPR337) src0(VGPR333) # 417: OpVectorTimesScalar: FloatVector2: tmp417 << tmp415, const416 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40200000 V_MUL_F32 vDst(VGPR87) src0(VGPR332) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR88) src0(VGPR332) src1(VGPR337) // VOP2 # OpStore: : tmp395 >> param419 V_MOV_B32 vDst(VGPR69) src0(VGPR84) V_MOV_B32 vDst(VGPR70) src0(VGPR85) # 421: OpFunctionCall: Float: smN2(vf2;(param419) S_ADD_U32 sDst(SGPR50) src0(LITERAL_CONST) src1(0) const: 0x45 # VGPR[289:290] S_MOV_B64 sDst(SGPR88) src0(EXEC) S_MOV_B32 sDst(SGPR31) src0(LITERAL_CONST) const: 0x59 # VGPR331 # Indirect branch to smN2(vf2;: -1220 S_GETPC_B64 sDst(SGPR48) src0(SGPR48) S_SUB_U32 sDst(SGPR48) src0(SGPR48) src1(LITERAL_CONST) const: 0x4c4 S_SUBB_U32 sDst(SGPR49) src0(SGPR49) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR48) src0(SGPR48) S_MOV_B64 sDst(EXEC) src0(SGPR88) # .lbl12 # 425: OpFAdd: FloatVector2: tmp425 << tmp395, const424 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x42c80000 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x42c80000 V_ADD_F32 vDst(VGPR334) src0(VGPR84) src1(VGPR332) // VOP2 V_ADD_F32 vDst(VGPR335) src0(VGPR85) src1(VGPR333) // VOP2 # OpStore: : tmp425 >> param426 V_MOV_B32 vDst(VGPR71) src0(VGPR334) V_MOV_B32 vDst(VGPR72) src0(VGPR335) # 427: OpFunctionCall: Float: smN2(vf2;(param426) S_ADD_U32 sDst(SGPR50) src0(LITERAL_CONST) src1(0) const: 0x47 # VGPR[291:292] S_MOV_B64 sDst(SGPR90) src0(EXEC) S_MOV_B32 sDst(SGPR31) src0(LITERAL_CONST) const: 0x5a # VGPR336 # Indirect branch to smN2(vf2;: -1300 S_GETPC_B64 sDst(SGPR48) src0(SGPR48) S_SUB_U32 sDst(SGPR48) src0(SGPR48) src1(LITERAL_CONST) const: 0x514 S_SUBB_U32 sDst(SGPR49) src0(SGPR49) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR48) src0(SGPR48) S_MOV_B64 sDst(EXEC) src0(SGPR90) # .lbl13 # 428: OpCompositeConstruct: FloatVector2: tmp428 << smN2(vf2;, smN2(vf2; V_MOV_B32 vDst(VGPR332) src0(VGPR89) V_MOV_B32 vDst(VGPR333) src0(VGPR90) # 429: OpCompositeConstruct: FloatVector2: tmp429 << const106, const106 V_MOV_B32 vDst(VGPR334) src0(1_0_F) V_MOV_B32 vDst(VGPR335) src0(1_0_F) # 430: OpFAdd: FloatVector2: tmp430 << tmp429, tmp428 V_ADD_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR332) // VOP2 V_ADD_F32 vDst(VGPR337) src0(VGPR335) src1(VGPR333) // VOP2 # 432: OpLoad: Float: tmp432 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR86) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 433: OpFSub: Float: tmp433 << const106, tmp432 V_SUB_F32 vDst(VGPR333) src0(1_0_F) src1(VGPR332) // VOP2 # 434: OpExtInst(Pow): Float: tmp434 << tmp433, const377 V_MOV_B32 vDst(VGPR332) src0(4_0_F) V_LOG_F32 vDst(VGPR334) src0(VGPR333) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR334) // VOP2 V_EXP_F32 vDst(VGPR334) src0(VGPR334) # 436: OpExtInst(FMix): Float: tmp436 << const106, tmp434, const435 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f666666 V_SUBREV_F32 vDst(VGPR333) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR333) src0(1_0_F) src1(VGPR333) // VOP2 V_MAD_F32 vDst(VGPR333) src0(VGPR334) src1(VGPR332) src2(VGPR333) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 438: OpFMul: Float: tmp438 << tmp436, const437 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x41c80000 V_MUL_F32 vDst(VGPR91) src0(VGPR333) src1(VGPR332) // VOP2 # 441: OpFMul: FloatVector2: tmp441 << tmp392, tmp430 V_MUL_F32 vDst(VGPR334) src0(VGPR82) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR83) src1(VGPR337) // VOP2 # 442: OpVectorTimesScalar: FloatVector2: tmp442 << tmp441, const377 V_MOV_B32 vDst(VGPR332) src0(4_0_F) V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR335) // VOP2 # 444: OpFAdd: FloatVector2: tmp444 << tmp442, tmp417 V_ADD_F32 vDst(VGPR332) src0(VGPR336) src1(VGPR87) // VOP2 V_ADD_F32 vDst(VGPR333) src0(VGPR337) src1(VGPR88) // VOP2 # OpStore: : tmp403 >> param445 V_MOV_B32 vDst(VGPR73) src0(VGPR86) # OpStore: : tmp444 >> param447 V_MOV_B32 vDst(VGPR74) src0(VGPR332) V_MOV_B32 vDst(VGPR75) src0(VGPR333) # 448: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param445, param447) S_ADD_U32 sDst(SGPR76) src0(LITERAL_CONST) src1(0) const: 0x49 # VGPR293 S_ADD_U32 sDst(SGPR77) src0(LITERAL_CONST) src1(0) const: 0x4a # VGPR[294:295] S_MOV_B64 sDst(SGPR92) src0(EXEC) S_MOV_B32 sDst(SGPR63) src0(LITERAL_CONST) const: 0x5c # VGPR[358:359] # Indirect branch to rotate(f1;vf2;: -1040 S_GETPC_B64 sDst(SGPR74) src0(SGPR74) S_SUB_U32 sDst(SGPR74) src0(SGPR74) src1(LITERAL_CONST) const: 0x410 S_SUBB_U32 sDst(SGPR75) src0(SGPR75) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR74) src0(SGPR74) S_MOV_B64 sDst(EXEC) src0(SGPR92) # .lbl14 # OpStore: : rotate(f1;vf2; >> param449 V_MOV_B32 vDst(VGPR76) src0(VGPR92) V_MOV_B32 vDst(VGPR77) src0(VGPR93) # 450: OpFunctionCall: Float: sugarybit(vf2;(param449) S_ADD_U32 sDst(SGPR81) src0(LITERAL_CONST) src1(0) const: 0x4c # VGPR[296:297] S_MOV_B64 sDst(SGPR94) src0(EXEC) S_MOV_B32 sDst(SGPR80) src0(LITERAL_CONST) const: 0x5e # VGPR360 # Indirect branch to sugarybit(vf2;: -884 S_GETPC_B64 sDst(SGPR78) src0(SGPR78) S_SUB_U32 sDst(SGPR78) src0(SGPR78) src1(LITERAL_CONST) const: 0x374 S_SUBB_U32 sDst(SGPR79) src0(SGPR79) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR78) src0(SGPR78) S_MOV_B64 sDst(EXEC) src0(SGPR94) # .lbl15 # 452: OpVectorTimesScalar: FloatVector2: tmp452 << tmp387, const401 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR80) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR81) // VOP2 # OpStore: : tmp452 >> param453 V_MOV_B32 vDst(VGPR78) src0(VGPR333) V_MOV_B32 vDst(VGPR79) src0(VGPR334) # 454: OpFunctionCall: Float: smN2(vf2;(param453) S_ADD_U32 sDst(SGPR50) src0(LITERAL_CONST) src1(0) const: 0x4e # VGPR[298:299] S_MOV_B64 sDst(SGPR96) src0(EXEC) S_MOV_B32 sDst(SGPR31) src0(LITERAL_CONST) const: 0x5f # VGPR364 # Indirect branch to smN2(vf2;: -1620 S_GETPC_B64 sDst(SGPR48) src0(SGPR48) S_SUB_U32 sDst(SGPR48) src0(SGPR48) src1(LITERAL_CONST) const: 0x654 S_SUBB_U32 sDst(SGPR49) src0(SGPR49) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR48) src0(SGPR48) S_MOV_B64 sDst(EXEC) src0(SGPR96) # .lbl16 # 455: OpFSub: Float: tmp455 << smN2(vf2;, const303 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_SUB_F32 vDst(VGPR333) src0(VGPR95) src1(VGPR332) // VOP2 # 456: OpExtInst(FMax): Float: tmp456 << const100, tmp455 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 457: OpFMul: Float: tmp457 << sugarybit(vf2;, tmp456 V_MUL_F32 vDst(VGPR332) src0(VGPR94) src1(VGPR334) // VOP2 # 459: OpFMul: Float: tmp459 << tmp457, tmp438 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR91) // VOP2 # OpReturnValue: : << tmp459 S_MOV_B32 sDst(M0) src0(SGPR84) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR333) S_SETPC_B64 sDst(SGPR82) src0(SGPR82) # FloatVector3 saturatecol(vf3;(FloatVector3* c) Function: FloatVector3 saturatecol(vf3;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb53 Label: lb53 # 462: OpLoad: FloatVector3: tmp462 << c S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR100) const: 0x0 V_MOVRELS_B32 vDst(VGPR97) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR98) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR99) src0(VGPR2) # 464: OpLoad: Float: tmp464 << colour # OpStore: : tmp464 >> param463 V_MOV_B32 vDst(VGPR96) src0(VGPR23) # 465: OpFunctionCall: FloatVector3: gumRamp(f1;(param463) S_ADD_U32 sDst(SGPR22) src0(LITERAL_CONST) src1(0) const: 0x60 # VGPR371 S_MOV_B64 sDst(SGPR102) src0(EXEC) S_MOV_B32 sDst(SGPR19) src0(LITERAL_CONST) const: 0x64 # VGPR[375:377] # Indirect branch to gumRamp(f1;: -3056 S_GETPC_B64 sDst(SGPR20) src0(SGPR20) S_SUB_U32 sDst(SGPR20) src0(SGPR20) src1(LITERAL_CONST) const: 0xbf0 S_SUBB_U32 sDst(SGPR21) src0(SGPR21) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR20) src0(SGPR20) S_MOV_B64 sDst(EXEC) src0(SGPR102) # .lbl17 # 466: OpExtInst(Pow): FloatVector3: tmp466 << tmp462, gumRamp(f1; V_LOG_F32 vDst(VGPR332) src0(VGPR97) V_LOG_F32 vDst(VGPR333) src0(VGPR98) V_LOG_F32 vDst(VGPR334) src0(VGPR99) V_MUL_F32 vDst(VGPR332) src0(VGPR100) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR333) src0(VGPR101) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR102) src1(VGPR334) // VOP2 V_EXP_F32 vDst(VGPR332) src0(VGPR332) V_EXP_F32 vDst(VGPR333) src0(VGPR333) V_EXP_F32 vDst(VGPR334) src0(VGPR334) # OpReturnValue: : << tmp466 S_MOV_B32 sDst(M0) src0(SGPR87) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR332) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR333) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR334) S_SETPC_B64 sDst(SGPR98) src0(SGPR98) # Float sprinkles2(vf2;f1;(FloatVector2* coord, Float* ndotv) Function: Float sprinkles2(vf2;f1;(, Float saturatecol(vf3;.ndotv) S_MOV_B64 sDst(SGPR108) src0(EXEC) # lb57 Label: lb57 # OpStore: : const100 >> sprinkle S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR103) src0(SGPR241) # OpStore: : const471 >> i V_MOV_B32 vDst(VGPR104) src0(0) # OpBranch: to lb472 # lb472 Label: lb472 # OpLoopMerge: (merge: lb474, continue: lb475) # CF Block: Merge: lb474, Continue: lb475 S_MOV_B64 sDst(SGPR110) src0(EXEC) S_MOV_B64 sDst(SGPR112) src0(EXEC) S_MOV_B64 sDst(SGPR114) src0(EXEC) Label: lb472Loop # OpBranch: to lb476 # lb476 Label: lb476 # 477: OpLoad: Int: tmp477 << i Decorators: RelaxedPrecision # 479: OpSLessThan: Bool: tmp479 << tmp477, const478 V_MOV_B32 vDst(VGPR332) src0(4_INT) V_CMP_LT_I32 dst(SGPR242) src0(VGPR104) src1(VGPR332) // VOP3a # OpBranchConditional: if(tmp479) then branch to lb473, else branch to lb474 # CF Block: Cond Branch: true: lb473, false: lb474 S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 61 lb474 # lb473 Label: lb473 S_MOV_B64 sDst(SGPR112) src0(EXEC) S_MOV_B64 sDst(SGPR114) src0(EXEC) # 480: OpLoad: FloatVector2: tmp480 << coord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR106) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 481: OpLoad: Int: tmp481 << i Decorators: RelaxedPrecision # 482: OpConvertSToF: Float: tmp482 << tmp481 V_CVT_F32_I32 vDst(VGPR334) src0(VGPR104) # 484: OpFMul: Float: tmp484 << tmp482, const483 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x41273333 V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR335) // VOP2 # 485: OpCompositeConstruct: FloatVector2: tmp485 << tmp484, tmp484 V_MOV_B32 vDst(VGPR337) src0(VGPR336) V_MOV_B32 vDst(VGPR338) src0(VGPR336) # 486: OpFAdd: FloatVector2: tmp486 << tmp480, tmp485 V_ADD_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR337) // VOP2 V_ADD_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR338) // VOP2 # 487: OpLoad: Int: tmp487 << i Decorators: RelaxedPrecision # 488: OpConvertSToF: Float: tmp488 << tmp487 V_CVT_F32_I32 vDst(VGPR332) src0(VGPR104) # 490: OpFMul: Float: tmp490 << tmp488, const489 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3e4ccccd V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR333) // VOP2 # 491: OpFAdd: Float: tmp491 << const106, tmp490 V_ADD_F32 vDst(VGPR332) src0(1_0_F) src1(VGPR336) // VOP2 # 492: OpVectorTimesScalar: FloatVector2: tmp492 << tmp486, tmp491 V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR335) // VOP2 # OpStore: : tmp492 >> param493 V_MOV_B32 vDst(VGPR105) src0(VGPR336) V_MOV_B32 vDst(VGPR106) src0(VGPR337) # 495: OpLoad: Float: tmp495 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR107) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # OpStore: : tmp495 >> param494 V_MOV_B32 vDst(VGPR107) src0(VGPR332) # 496: OpFunctionCall: Float: sugarlayer(vf2;f1;(param493, param494) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x69 # VGPR[383:384] S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x6b # VGPR385 S_MOV_B64 sDst(SGPR116) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x6c # VGPR404 # Indirect branch to sugarlayer(vf2;f1;: -1000 S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_SUB_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x3e8 S_SUBB_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR116) # .lbl18 # 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision # 498: OpConvertSToF: Float: tmp498 << tmp497 V_CVT_F32_I32 vDst(VGPR332) src0(VGPR104) # 499: OpFDiv: Float: tmp499 << tmp498, const377 V_MOV_B32 vDst(VGPR333) src0(4_0_F) V_RCP_F32 vDst(VGPR334) src0(VGPR333) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR334) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR334) src0(VGPR334) src1(VGPR333) src2(VGPR332) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 500: OpFSub: Float: tmp500 << const106, tmp499 V_SUB_F32 vDst(VGPR332) src0(1_0_F) src1(VGPR334) // VOP2 # 501: OpExtInst(Pow): Float: tmp501 << tmp500, const377 V_MOV_B32 vDst(VGPR333) src0(4_0_F) V_LOG_F32 vDst(VGPR334) src0(VGPR332) V_MUL_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR334) // VOP2 V_EXP_F32 vDst(VGPR334) src0(VGPR334) # 502: OpFMul: Float: tmp502 << sugarlayer(vf2;f1;, tmp501 V_MUL_F32 vDst(VGPR332) src0(VGPR108) src1(VGPR334) // VOP2 # 503: OpLoad: Float: tmp503 << sprinkle # 504: OpFAdd: Float: tmp504 << tmp503, tmp502 V_ADD_F32 vDst(VGPR333) src0(VGPR103) src1(VGPR332) // VOP2 # OpStore: : tmp504 >> sprinkle V_MOV_B32 vDst(VGPR103) src0(VGPR333) # OpBranch: to lb475 # lb475 Label: lb475 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR112) # 505: OpLoad: Int: tmp505 << i Decorators: RelaxedPrecision # 506: OpIAdd: Int: tmp506 << tmp505, const285 Decorators: RelaxedPrecision S_MOV_B32 sDst(SGPR241) src0(1_INT) V_ADD_I32 vDst(VGPR332) src0(VGPR104) src1(SGPR241) src2(N/A) omod(0) neg(0) sDst(VCC) // VOP3b # OpStore: : tmp506 >> i V_MOV_B32 vDst(VGPR104) src0(VGPR332) # OpBranch: to lb472 S_BRANCH -66 lb472Loop # lb474 Label: lb474 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR110) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR108) # 507: OpLoad: Float: tmp507 << sprinkle # OpReturnValue: : << tmp507 S_MOV_B32 sDst(M0) src0(SGPR101) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR103) S_SETPC_B64 sDst(SGPR104) src0(SGPR104) # Float sprinkles(vf2;f1;(FloatVector2* coord, Float* ndotv) Function: Float sprinkles(vf2;f1;(, Float sprinkles2(vf2;f1;.ndotv) S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb61 Label: lb61 # 510: OpLoad: FloatVector2: tmp510 << coord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR121) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 512: OpVectorTimesScalar: FloatVector2: tmp512 << tmp510, const511 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3f400000 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR333) // VOP2 # OpStore: : tmp512 >> param513 V_MOV_B32 vDst(VGPR109) src0(VGPR335) V_MOV_B32 vDst(VGPR110) src0(VGPR336) # 515: OpLoad: Float: tmp515 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR122) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # OpStore: : tmp515 >> param514 V_MOV_B32 vDst(VGPR111) src0(VGPR332) # 516: OpFunctionCall: Float: sprinkles2(vf2;f1;(param513, param514) S_ADD_U32 sDst(SGPR106) src0(LITERAL_CONST) src1(0) const: 0x6d # VGPR[415:416] S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x6f # VGPR417 S_MOV_B64 sDst(SGPR124) src0(EXEC) S_MOV_B32 sDst(SGPR101) src0(LITERAL_CONST) const: 0x73 # VGPR427 # Indirect branch to sprinkles2(vf2;f1;: -408 S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_SUB_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x198 S_SUBB_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR124) # .lbl19 # 517: OpLoad: FloatVector2: tmp517 << coord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR121) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 518: OpVectorTimesScalar: FloatVector2: tmp518 << tmp517, const127 V_MOV_B32 vDst(VGPR334) src0(2_0_F) V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR333) // VOP2 # OpStore: : tmp518 >> param519 V_MOV_B32 vDst(VGPR112) src0(VGPR335) V_MOV_B32 vDst(VGPR113) src0(VGPR336) # 521: OpLoad: Float: tmp521 << ndotv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR122) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # OpStore: : tmp521 >> param520 V_MOV_B32 vDst(VGPR114) src0(VGPR332) # 522: OpFunctionCall: Float: sprinkles2(vf2;f1;(param519, param520) S_ADD_U32 sDst(SGPR106) src0(LITERAL_CONST) src1(0) const: 0x70 # VGPR[418:419] S_ADD_U32 sDst(SGPR107) src0(LITERAL_CONST) src1(0) const: 0x72 # VGPR420 S_MOV_B64 sDst(SGPR126) src0(EXEC) S_MOV_B32 sDst(SGPR101) src0(LITERAL_CONST) const: 0x74 # VGPR434 # Indirect branch to sprinkles2(vf2;f1;: -516 S_GETPC_B64 sDst(SGPR104) src0(SGPR104) S_SUB_U32 sDst(SGPR104) src0(SGPR104) src1(LITERAL_CONST) const: 0x204 S_SUBB_U32 sDst(SGPR105) src0(SGPR105) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR104) src0(SGPR104) S_MOV_B64 sDst(EXEC) src0(SGPR126) # .lbl20 # 524: OpFMul: Float: tmp524 << sprinkles2(vf2;f1;, const523 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3e99999a V_MUL_F32 vDst(VGPR333) src0(VGPR116) src1(VGPR332) // VOP2 # 525: OpFAdd: Float: tmp525 << sprinkles2(vf2;f1;, tmp524 V_ADD_F32 vDst(VGPR332) src0(VGPR115) src1(VGPR333) // VOP2 # OpReturnValue: : << tmp525 S_MOV_B32 sDst(M0) src0(SGPR120) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR332) S_SETPC_B64 sDst(SGPR118) src0(SGPR118) # FloatVector3 gummy(vf3;vf3;vf3;(FloatVector3* no, FloatVector3* vo, FloatVector3* v) Function: FloatVector3 gummy(vf3;vf3;vf3;(, FloatVector3 sprinkles(vf2;f1;.vo, FloatVector3 sprinkles(vf2;f1;.v) S_MOV_B64 sDst(SGPR134) src0(EXEC) # lb67 Label: lb67 # 529: OpLoad: FloatVector3: tmp529 << no S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR130) const: 0x0 V_MOVRELS_B32 vDst(VGPR334) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR335) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR336) src0(VGPR2) # 530: OpLoad: FloatVector3: tmp530 << v S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR132) const: 0x0 V_MOVRELS_B32 vDst(VGPR337) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR338) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR339) src0(VGPR2) # 531: OpFNegate: FloatVector3: tmp531 << tmp530 V_MUL_F32 vDst(VGPR340) src0(M1_0_F) src1(VGPR337) // VOP2 V_MUL_F32 vDst(VGPR341) src0(M1_0_F) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR342) src0(M1_0_F) src1(VGPR339) // VOP2 # 532: OpDot: Float: tmp532 << tmp529, tmp531 V_MUL_F32 vDst(VGPR127) src0(VGPR334) src1(VGPR340) // VOP2 V_MAC_F32 vDst(VGPR127) src0(VGPR335) src1(VGPR341) // VOP2 V_MAC_F32 vDst(VGPR127) src0(VGPR336) src1(VGPR342) // VOP2 # 534: OpAccessChain: Float*: no[2] # 535: OpLoad: Float: tmp535 << no[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR130) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR2) # 536: OpAccessChain: Float*: no[0] # 537: OpLoad: Float: tmp537 << no[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR130) const: 0x0 V_MOVRELS_B32 vDst(VGPR333) src0(VGPR0) # 538: OpExtInst(Atan2): Float: tmp538 << tmp535, tmp537 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0xbc5cdd30 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3d6b6d55 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0xbdf84c31 V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x3e4854c9 V_MOV_B32 vDst(VGPR338) src0(LITERAL_CONST) const: 0xbeaa7e45 V_MOV_B32 vDst(VGPR339) src0(LITERAL_CONST) const: 0x3f7fffb7 V_MOV_B32 vDst(VGPR340) src0(LITERAL_CONST) const: 0x3fc90fdb V_MOV_B32 vDst(VGPR341) src0(LITERAL_CONST) const: 0x40490fdb V_ADD_F32 vDst(VGPR342) src0(VGPR333) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR343) src0(VGPR332) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_MAX_F32 vDst(VGPR344) src0(VGPR342) src1(VGPR343) // VOP2 V_MIN_F32 vDst(VGPR345) src0(VGPR342) src1(VGPR343) // VOP2 V_RCP_F32 vDst(VGPR344) src0(VGPR344) V_MUL_F32 vDst(VGPR344) src0(VGPR344) src1(VGPR345) // VOP2 V_MUL_F32 vDst(VGPR345) src0(VGPR344) src1(VGPR344) // VOP2 V_MAD_F32 vDst(VGPR346) src0(VGPR334) src1(VGPR345) src2(VGPR335) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR346) src0(VGPR346) src1(VGPR345) src2(VGPR336) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR346) src0(VGPR346) src1(VGPR345) src2(VGPR337) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR346) src0(VGPR346) src1(VGPR345) src2(VGPR338) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR346) src0(VGPR346) src1(VGPR345) src2(VGPR339) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR346) src0(VGPR346) src1(VGPR344) // VOP2 V_CMP_GT_F32 src0(VGPR343) src1(VGPR342) # CF Block: Merge: .lbl21 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl22, false: .lbl21 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl21 Label: .lbl22 V_SUB_F32 vDst(VGPR346) src0(VGPR340) src1(VGPR346) // VOP2 Label: .lbl21 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR134) V_CMP_GT_F32 src0(0) src1(VGPR333) # CF Block: Merge: .lbl23 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl24, false: .lbl23 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl23 Label: .lbl24 V_SUB_F32 vDst(VGPR346) src0(VGPR341) src1(VGPR346) // VOP2 Label: .lbl23 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR134) V_CMP_GT_F32 src0(0) src1(VGPR332) # CF Block: Merge: .lbl25 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl26, false: .lbl25 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl25 Label: .lbl26 V_SUB_F32 vDst(VGPR346) src0(0) src1(VGPR346) // VOP2 Label: .lbl25 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR134) # 539: OpAccessChain: Float*: no[1] # 540: OpLoad: Float: tmp540 << no[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR130) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR1) # 541: OpExtInst(Asin): Float: tmp541 << tmp540 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0xbc996e30 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3d981627 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0xbe593484 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x3fc90da4 V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x3fc90fdb V_ADD_F32 vDst(VGPR338) src0(VGPR332) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR339) src0(VGPR333) src1(VGPR338) src2(VGPR334) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR339) src0(VGPR338) src1(VGPR339) src2(VGPR335) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MAD_F32 vDst(VGPR339) src0(VGPR338) src1(VGPR339) src2(VGPR336) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUB_F32 vDst(VGPR338) src0(1_0_F) src1(VGPR338) // VOP2 V_SQRT_F32 vDst(VGPR338) src0(VGPR338) V_MAD_F32 vDst(VGPR339) src0(VGPR338) src1(VGPR339) src2(VGPR337) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_CMP_GT_F32 src0(0) src1(VGPR332) # CF Block: Merge: .lbl27 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl28, false: .lbl27 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl27 Label: .lbl28 V_MUL_F32 vDst(VGPR339) src0(M1_0_F) src1(VGPR339) // VOP2 Label: .lbl27 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR134) # 542: OpCompositeConstruct: FloatVector2: tmp542 << tmp538, tmp541 V_MOV_B32 vDst(VGPR340) src0(VGPR346) V_MOV_B32 vDst(VGPR341) src0(VGPR339) # 543: OpVectorTimesScalar: FloatVector2: tmp543 << tmp542, const511 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f400000 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR340) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR341) // VOP2 # OpStore: : tmp543 >> param544 V_MOV_B32 vDst(VGPR117) src0(VGPR333) V_MOV_B32 vDst(VGPR118) src0(VGPR334) # OpStore: : tmp532 >> param545 V_MOV_B32 vDst(VGPR119) src0(VGPR127) # 547: OpFunctionCall: Float: sprinkles(vf2;f1;(param544, param545) S_ADD_U32 sDst(SGPR121) src0(LITERAL_CONST) src1(0) const: 0x75 # VGPR[438:439] S_ADD_U32 sDst(SGPR122) src0(LITERAL_CONST) src1(0) const: 0x77 # VGPR440 S_MOV_B64 sDst(SGPR136) src0(EXEC) S_MOV_B32 sDst(SGPR120) src0(LITERAL_CONST) const: 0x80 # VGPR489 # Indirect branch to sprinkles(vf2;f1;: -768 S_GETPC_B64 sDst(SGPR118) src0(SGPR118) S_SUB_U32 sDst(SGPR118) src0(SGPR118) src1(LITERAL_CONST) const: 0x300 S_SUBB_U32 sDst(SGPR119) src0(SGPR119) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR118) src0(SGPR118) S_MOV_B64 sDst(EXEC) src0(SGPR136) # .lbl29 # 550: OpLoad: FloatVector3: tmp550 << vo S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR131) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) # 551: OpVectorShuffle: FloatVector2: tmp551 << tmp550, tmp550, 0, 2 V_MOV_B32 vDst(VGPR335) src0(VGPR332) V_MOV_B32 vDst(VGPR336) src0(VGPR334) # OpStore: : tmp551 >> param549 V_MOV_B32 vDst(VGPR120) src0(VGPR335) V_MOV_B32 vDst(VGPR121) src0(VGPR336) # OpStore: : tmp532 >> param552 V_MOV_B32 vDst(VGPR122) src0(VGPR127) # 554: OpFunctionCall: Float: sprinkles(vf2;f1;(param549, param552) S_ADD_U32 sDst(SGPR121) src0(LITERAL_CONST) src1(0) const: 0x78 # VGPR[441:442] S_ADD_U32 sDst(SGPR122) src0(LITERAL_CONST) src1(0) const: 0x7a # VGPR443 S_MOV_B64 sDst(SGPR138) src0(EXEC) S_MOV_B32 sDst(SGPR120) src0(LITERAL_CONST) const: 0x81 # VGPR495 # Indirect branch to sprinkles(vf2;f1;: -864 S_GETPC_B64 sDst(SGPR118) src0(SGPR118) S_SUB_U32 sDst(SGPR118) src0(SGPR118) src1(LITERAL_CONST) const: 0x360 S_SUBB_U32 sDst(SGPR119) src0(SGPR119) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR118) src0(SGPR118) S_MOV_B64 sDst(EXEC) src0(SGPR138) # .lbl30 # 558: OpAccessChain: Float*: no[1] # 559: OpLoad: Float: tmp559 << no[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR130) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR1) # 560: OpExtInst(SmoothStep): Float: tmp560 << const523, const303, tmp559 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3e99999a V_MOV_B32 vDst(VGPR334) src0(0_5_F) V_CMP_GE_F32 src0(VGPR333) src1(VGPR332) # CF Block: Merge: .lbl34 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl35, false: .lbl31 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl31 Label: .lbl35 V_MOV_B32 vDst(VGPR335) src0(0) Label: .lbl31 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR134) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl34 V_CMP_LE_F32 src0(VGPR334) src1(VGPR332) # CF Block: Merge: .lbl33 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl36, false: .lbl32 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl32 Label: .lbl36 V_MOV_B32 vDst(VGPR335) src0(1_0_F) Label: .lbl32 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR134) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl33 V_SUBREV_F32 vDst(VGPR336) src0(VGPR333) src1(VGPR334) // VOP2 V_RCP_F32 vDst(VGPR336) src0(VGPR336) V_SUBREV_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR335) src1(VGPR336) // VOP2 V_MAX_F32 vDst(VGPR336) src0(0) src1(VGPR336) // VOP2 V_MIN_F32 vDst(VGPR336) src0(1_0_F) src1(VGPR336) // VOP2 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR335) src0(2_0_F) src1(VGPR336) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR336) src0(VGPR336) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR336) src1(VGPR335) // VOP2 Label: .lbl33 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR134) Label: .lbl34 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR134) # 561: OpExtInst(FMix): Float: tmp561 << sprinkles(vf2;f1;, sprinkles(vf2;f1;, tmp560 V_SUBREV_F32 vDst(VGPR130) src0(VGPR335) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR130) src0(VGPR128) src1(VGPR130) // VOP2 V_MAD_F32 vDst(VGPR130) src0(VGPR129) src1(VGPR335) src2(VGPR130) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 563: OpAccessChain: Float*: no[1] # 564: OpLoad: Float: tmp564 << no[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR130) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR1) # 565: OpFSub: Float: tmp565 << tmp564, const523 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3e99999a V_SUB_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 566: OpFMul: Float: tmp566 << tmp565, const401 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR333) src0(VGPR334) src1(VGPR332) // VOP2 # 567: OpExtInst(FClamp): Float: tmp567 << tmp566, const100, const106 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR334) src0(1_0_F) V_MAX_F32 vDst(VGPR131) src0(VGPR333) src1(VGPR332) // VOP2 V_MIN_F32 vDst(VGPR131) src0(VGPR131) src1(VGPR334) // VOP2 # 571: OpLoad: Float: tmp571 << colour # OpStore: : tmp571 >> param570 V_MOV_B32 vDst(VGPR123) src0(VGPR23) # 572: OpFunctionCall: FloatVector3: gumColour(f1;(param570) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x7b # VGPR447 S_MOV_B64 sDst(SGPR140) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x84 # VGPR[510:512] # Indirect branch to gumColour(f1;: -4968 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x1368 S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR140) # .lbl37 # 574: OpCompositeConstruct: FloatVector3: tmp574 << const573, const573, const573 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3f7ae148 V_MOV_B32 vDst(VGPR332) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3f7ae148 V_MOV_B32 vDst(VGPR333) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3f7ae148 V_MOV_B32 vDst(VGPR334) src0(SGPR241) # 575: OpExtInst(FMix): FloatVector3: tmp575 << const569, gumColour(f1;, tmp574 V_MOV_B32 vDst(VGPR335) src0(0_5_F) V_MOV_B32 vDst(VGPR336) src0(0_5_F) V_MOV_B32 vDst(VGPR337) src0(0_5_F) V_SUBREV_F32 vDst(VGPR338) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR338) src0(VGPR335) src1(VGPR338) // VOP2 V_MAD_F32 vDst(VGPR338) src0(VGPR132) src1(VGPR332) src2(VGPR338) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR339) src0(VGPR333) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR339) src0(VGPR336) src1(VGPR339) // VOP2 V_MAD_F32 vDst(VGPR339) src0(VGPR133) src1(VGPR333) src2(VGPR339) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR340) src0(VGPR334) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR340) src0(VGPR337) src1(VGPR340) // VOP2 V_MAD_F32 vDst(VGPR340) src0(VGPR134) src1(VGPR334) src2(VGPR340) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 577: OpAccessChain: Float*: tc[0] # 578: OpLoad: Float: tmp578 << tc[0] V_MOV_B32 vDst(VGPR332) src0(VGPR20) # 579: OpExtInst(FAbs): Float: tmp579 << tmp578 V_ADD_F32 vDst(VGPR333) src0(VGPR332) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 580: OpFSub: Float: tmp580 << const106, tmp579 V_SUB_F32 vDst(VGPR332) src0(1_0_F) src1(VGPR333) // VOP2 # 581: OpFMul: Float: tmp581 << tmp580, const303 V_MOV_B32 vDst(VGPR333) src0(0_5_F) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 582: OpExtInst(Pow): Float: tmp582 << tmp581, const489 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3e4ccccd V_LOG_F32 vDst(VGPR333) src0(VGPR334) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR333) // VOP2 V_EXP_F32 vDst(VGPR333) src0(VGPR333) # 583: OpFAdd: Float: tmp583 << const576, tmp582 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3dcccccd V_ADD_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 584: OpVectorTimesScalar: FloatVector3: tmp584 << tmp575, tmp583 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR334) src1(VGPR340) // VOP2 # 588: OpFMul: Float: tmp588 << tmp561, tmp567 V_MUL_F32 vDst(VGPR332) src0(VGPR130) src1(VGPR131) // VOP2 # 589: OpCompositeConstruct: FloatVector3: tmp589 << tmp588, tmp588, tmp588 V_MOV_B32 vDst(VGPR338) src0(VGPR332) V_MOV_B32 vDst(VGPR339) src0(VGPR332) V_MOV_B32 vDst(VGPR340) src0(VGPR332) # 590: OpExtInst(FMix): FloatVector3: tmp590 << tmp584, const585, tmp589 V_MOV_B32 vDst(VGPR332) src0(2_0_F) V_MOV_B32 vDst(VGPR333) src0(2_0_F) V_MOV_B32 vDst(VGPR334) src0(2_0_F) V_SUBREV_F32 vDst(VGPR341) src0(VGPR338) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR341) src0(VGPR335) src1(VGPR341) // VOP2 V_MAD_F32 vDst(VGPR341) src0(VGPR332) src1(VGPR338) src2(VGPR341) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR342) src0(VGPR339) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR342) src0(VGPR336) src1(VGPR342) // VOP2 V_MAD_F32 vDst(VGPR342) src0(VGPR333) src1(VGPR339) src2(VGPR342) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR343) src0(VGPR340) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR343) src0(VGPR337) src1(VGPR343) // VOP2 V_MAD_F32 vDst(VGPR343) src0(VGPR334) src1(VGPR340) src2(VGPR343) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp590 >> param591 V_MOV_B32 vDst(VGPR124) src0(VGPR341) V_MOV_B32 vDst(VGPR125) src0(VGPR342) V_MOV_B32 vDst(VGPR126) src0(VGPR343) # 592: OpFunctionCall: FloatVector3: saturatecol(vf3;(param591) S_ADD_U32 sDst(SGPR100) src0(LITERAL_CONST) src1(0) const: 0x7c # VGPR[448:450] S_MOV_B64 sDst(SGPR142) src0(EXEC) S_MOV_B32 sDst(SGPR87) src0(LITERAL_CONST) const: 0x87 # VGPR[547:549] # Indirect branch to saturatecol(vf3;: -1916 S_GETPC_B64 sDst(SGPR98) src0(SGPR98) S_SUB_U32 sDst(SGPR98) src0(SGPR98) src1(LITERAL_CONST) const: 0x77c S_SUBB_U32 sDst(SGPR99) src0(SGPR99) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR98) src0(SGPR98) S_MOV_B64 sDst(EXEC) src0(SGPR142) # .lbl38 # OpStore: : saturatecol(vf3; >> tex V_MOV_B32 vDst(VGPR332) src0(VGPR135) V_MOV_B32 vDst(VGPR333) src0(VGPR136) V_MOV_B32 vDst(VGPR334) src0(VGPR137) # 595: OpFSub: Float: tmp595 << const593, tmp532 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3f866666 V_SUB_F32 vDst(VGPR336) src0(VGPR335) src1(VGPR127) // VOP2 # 596: OpLoad: FloatVector3: tmp596 << tex # 597: OpVectorTimesScalar: FloatVector3: tmp597 << tmp596, tmp595 V_MUL_F32 vDst(VGPR337) src0(VGPR336) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR336) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR336) src1(VGPR334) // VOP2 # OpStore: : tmp597 >> tex V_MOV_B32 vDst(VGPR332) src0(VGPR337) V_MOV_B32 vDst(VGPR333) src0(VGPR338) V_MOV_B32 vDst(VGPR334) src0(VGPR339) # 599: OpFSub: Float: tmp599 << const106, tmp532 V_SUB_F32 vDst(VGPR335) src0(1_0_F) src1(VGPR127) // VOP2 # 600: OpExtInst(Pow): Float: tmp600 << tmp599, const349 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR337) src0(VGPR335) V_MUL_F32 vDst(VGPR337) src0(VGPR336) src1(VGPR337) // VOP2 V_EXP_F32 vDst(VGPR337) src0(VGPR337) # 601: OpCompositeConstruct: FloatVector3: tmp601 << tmp600, tmp600, tmp600 V_MOV_B32 vDst(VGPR338) src0(VGPR337) V_MOV_B32 vDst(VGPR339) src0(VGPR337) V_MOV_B32 vDst(VGPR340) src0(VGPR337) # 603: OpVectorTimesScalar: FloatVector3: tmp603 << tmp601, const602 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3c23d70a V_MUL_F32 vDst(VGPR341) src0(VGPR335) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR342) src0(VGPR335) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR343) src0(VGPR335) src1(VGPR340) // VOP2 # 604: OpLoad: FloatVector3: tmp604 << tex # 605: OpFAdd: FloatVector3: tmp605 << tmp604, tmp603 V_ADD_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR341) // VOP2 V_ADD_F32 vDst(VGPR336) src0(VGPR333) src1(VGPR342) // VOP2 V_ADD_F32 vDst(VGPR337) src0(VGPR334) src1(VGPR343) // VOP2 # OpStore: : tmp605 >> tex V_MOV_B32 vDst(VGPR332) src0(VGPR335) V_MOV_B32 vDst(VGPR333) src0(VGPR336) V_MOV_B32 vDst(VGPR334) src0(VGPR337) # 606: OpLoad: FloatVector3: tmp606 << tex # OpReturnValue: : << tmp606 S_MOV_B32 sDst(M0) src0(SGPR123) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR332) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR333) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR334) S_SETPC_B64 sDst(SGPR128) src0(SGPR128) # Float de(vf3;(FloatVector3* p) Function: Float de(vf3;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb70 Label: lb70 # 610: OpAccessChain: Float*: p[1] # 611: OpLoad: Float: tmp611 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR1) # 612: OpFMul: Float: tmp612 << tmp611, const609 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3fa66666 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 613: OpAccessChain: Float*: p[1] # OpStore: : tmp612 >> p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELD_B32 vDst(VGPR1) src0(VGPR334) # 615: OpLoad: FloatVector3: tmp615 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) # 616: OpCompositeConstruct: FloatVector3: tmp616 << const109, const109, const109 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR335) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR336) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR337) src0(SGPR241) # 617: OpFDiv: FloatVector3: tmp617 << tmp615, tmp616 V_RCP_F32 vDst(VGPR338) src0(VGPR335) V_RCP_F32 vDst(VGPR339) src0(VGPR336) V_RCP_F32 vDst(VGPR340) src0(VGPR337) V_MUL_F32 vDst(VGPR338) src0(VGPR332) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR333) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR334) src1(VGPR340) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR338) src0(VGPR338) src1(VGPR335) src2(VGPR332) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR339) src0(VGPR339) src1(VGPR336) src2(VGPR333) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR340) src0(VGPR340) src1(VGPR337) src2(VGPR334) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 618: OpExtInst(Floor): FloatVector3: tmp618 << tmp617 V_FLOOR_F32 vDst(VGPR144) src0(VGPR338) V_FLOOR_F32 vDst(VGPR145) src0(VGPR339) V_FLOOR_F32 vDst(VGPR146) src0(VGPR340) # 619: OpAccessChain: Float*: fp[0] # 620: OpCompositeExtract: Float: tmp620 << tmp618, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR144) # 622: OpFMul: Float: tmp622 << tmp620, const621 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 623: OpAccessChain: Float*: fp[2] # 624: OpCompositeExtract: Float: tmp624 << tmp618, 2 V_MOV_B32 vDst(VGPR332) src0(VGPR146) # 626: OpFMul: Float: tmp626 << tmp624, const625 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x42ce0000 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 # 627: OpFSub: Float: tmp627 << tmp622, tmp626 V_SUB_F32 vDst(VGPR332) src0(VGPR334) src1(VGPR335) // VOP2 # 628: OpExtInst(Cos): Float: tmp628 << tmp627 V_MUL_F32 vDst(VGPR333) src0(LITERAL_CONST) src1(VGPR332) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR333) src0(VGPR333) V_COS_F32 vDst(VGPR333) src0(VGPR333) # 629: OpFAdd: Float: tmp629 << tmp628, const576 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3dcccccd V_ADD_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) // VOP2 # 630: OpExtInst(Step): Float: tmp630 << const100, tmp629 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_CMP_GT_F32 src0(VGPR332) src1(VGPR334) # CF Block: Merge: .lbl40 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl41, false: .lbl39 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl39 Label: .lbl41 V_MOV_B32 vDst(VGPR332) src0(0) Label: .lbl39 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl40 V_MOV_B32 vDst(VGPR332) src0(1_0_F) Label: .lbl40 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR242) # OpStore: : tmp630 >> is_choc V_MOV_B32 vDst(VGPR25) src0(VGPR332) # 632: OpLoad: FloatVector3: tmp632 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) # 634: OpVectorTimesScalar: FloatVector3: tmp634 << tmp632, const633 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x41f00000 V_MUL_F32 vDst(VGPR336) src0(VGPR335) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR335) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR335) src1(VGPR334) // VOP2 # OpStore: : tmp634 >> param635 V_MOV_B32 vDst(VGPR138) src0(VGPR336) V_MOV_B32 vDst(VGPR139) src0(VGPR337) V_MOV_B32 vDst(VGPR140) src0(VGPR338) # 636: OpFunctionCall: Float: smN3(vf3;(param635) S_ADD_U32 sDst(SGPR56) src0(LITERAL_CONST) src1(0) const: 0x8a # VGPR[568:570] S_MOV_B64 sDst(SGPR148) src0(EXEC) S_MOV_B32 sDst(SGPR51) src0(LITERAL_CONST) const: 0x93 # VGPR611 # Indirect branch to smN3(vf3;: -4004 S_GETPC_B64 sDst(SGPR54) src0(SGPR54) S_SUB_U32 sDst(SGPR54) src0(SGPR54) src1(LITERAL_CONST) const: 0xfa4 S_SUBB_U32 sDst(SGPR55) src0(SGPR55) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR54) src0(SGPR54) S_MOV_B64 sDst(EXEC) src0(SGPR148) # .lbl42 # 638: OpFMul: Float: tmp638 << smN3(vf3;, const637 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3a83126f V_MUL_F32 vDst(VGPR333) src0(VGPR147) src1(VGPR332) // VOP2 # 639: OpLoad: Float: tmp639 << is_choc # 640: OpFMul: Float: tmp640 << tmp638, tmp639 V_MUL_F32 vDst(VGPR148) src0(VGPR333) src1(VGPR25) // VOP2 # 641: OpLoad: FloatVector3: tmp641 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELS_B32 vDst(VGPR334) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR335) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR336) src0(VGPR2) # 642: OpVectorTimesScalar: FloatVector3: tmp642 << tmp641, const401 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR332) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR332) src1(VGPR336) // VOP2 # OpStore: : tmp642 >> param643 V_MOV_B32 vDst(VGPR141) src0(VGPR337) V_MOV_B32 vDst(VGPR142) src0(VGPR338) V_MOV_B32 vDst(VGPR143) src0(VGPR339) # 644: OpFunctionCall: Float: smN3(vf3;(param643) S_ADD_U32 sDst(SGPR56) src0(LITERAL_CONST) src1(0) const: 0x8d # VGPR[571:573] S_MOV_B64 sDst(SGPR150) src0(EXEC) S_MOV_B32 sDst(SGPR51) src0(LITERAL_CONST) const: 0x95 # VGPR622 # Indirect branch to smN3(vf3;: -4120 S_GETPC_B64 sDst(SGPR54) src0(SGPR54) S_SUB_U32 sDst(SGPR54) src0(SGPR54) src1(LITERAL_CONST) const: 0x1018 S_SUBB_U32 sDst(SGPR55) src0(SGPR55) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR54) src0(SGPR54) S_MOV_B64 sDst(EXEC) src0(SGPR150) # .lbl43 # 645: OpExtInst(FMax): Float: tmp645 << const100, smN3(vf3; V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR149) // VOP2 # 646: OpExtInst(Pow): Float: tmp646 << tmp645, const401 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40a00000 V_LOG_F32 vDst(VGPR334) src0(VGPR333) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR334) // VOP2 V_EXP_F32 vDst(VGPR334) src0(VGPR334) # 648: OpLoad: Float: tmp648 << is_choc # 649: OpFSub: Float: tmp649 << const106, tmp648 V_SUB_F32 vDst(VGPR332) src0(1_0_F) src1(VGPR25) // VOP2 # 650: OpFMul: Float: tmp650 << const647, tmp649 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3d4ccccd V_MUL_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR332) // VOP2 # 651: OpFAdd: Float: tmp651 << const602, tmp650 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3c23d70a V_ADD_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR335) // VOP2 # 652: OpFMul: Float: tmp652 << tmp646, tmp651 V_MUL_F32 vDst(VGPR332) src0(VGPR334) src1(VGPR333) // VOP2 # 653: OpFSub: Float: tmp653 << tmp640, tmp652 V_SUB_F32 vDst(VGPR333) src0(VGPR148) src1(VGPR332) // VOP2 # 654: OpAccessChain: Float*: fp[0] # 655: OpCompositeExtract: Float: tmp655 << tmp618, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR144) # 656: OpAccessChain: Float*: fp[2] # 657: OpCompositeExtract: Float: tmp657 << tmp618, 2 V_MOV_B32 vDst(VGPR334) src0(VGPR146) # 658: OpExtInst(Sin): Float: tmp658 << tmp657 V_MUL_F32 vDst(VGPR335) src0(LITERAL_CONST) src1(VGPR334) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR335) src0(VGPR335) V_SIN_F32 vDst(VGPR335) src0(VGPR335) # 659: OpFMul: Float: tmp659 << tmp658, const109 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR336) src0(VGPR335) src1(VGPR334) // VOP2 # 660: OpFAdd: Float: tmp660 << tmp655, tmp659 V_ADD_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR336) // VOP2 # 661: OpFMod: Float: tmp661 << tmp660, const377 V_MOV_B32 vDst(VGPR332) src0(4_0_F) V_RCP_F32 vDst(VGPR335) src0(VGPR332) V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR335) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR335) src0(VGPR335) src1(VGPR332) src2(VGPR334) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR335) src0(VGPR335) V_MAD_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR335) src2(VGPR334) abs(0) clamp(0) omod(0) neg(1) // VOP3a # OpStore: : tmp661 >> colour V_MOV_B32 vDst(VGPR23) src0(VGPR335) # 662: OpLoad: FloatVector3: tmp662 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELS_B32 vDst(VGPR336) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR337) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR338) src0(VGPR2) # 663: OpVectorShuffle: FloatVector2: tmp663 << tmp662, tmp662, 0, 2 V_MOV_B32 vDst(VGPR334) src0(VGPR336) V_MOV_B32 vDst(VGPR335) src0(VGPR338) # 665: OpFMod: FloatVector2: tmp665 << tmp663, const664 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x40400000 V_RCP_F32 vDst(VGPR338) src0(VGPR336) V_MUL_F32 vDst(VGPR338) src0(VGPR334) src1(VGPR338) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR338) src0(VGPR338) src1(VGPR336) src2(VGPR334) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR338) src0(VGPR338) V_RCP_F32 vDst(VGPR339) src0(VGPR337) V_MUL_F32 vDst(VGPR339) src0(VGPR335) src1(VGPR339) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR339) src0(VGPR339) src1(VGPR337) src2(VGPR335) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR339) src0(VGPR339) V_MAD_F32 vDst(VGPR338) src0(VGPR336) src1(VGPR338) src2(VGPR334) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR339) src0(VGPR337) src1(VGPR339) src2(VGPR335) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 668: OpFSub: FloatVector2: tmp668 << tmp665, const667 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3fc00000 V_SUB_F32 vDst(VGPR336) src0(VGPR338) src1(VGPR334) // VOP2 V_SUB_F32 vDst(VGPR337) src0(VGPR339) src1(VGPR335) // VOP2 # 669: OpLoad: FloatVector3: tmp669 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELS_B32 vDst(VGPR338) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR339) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR340) src0(VGPR2) # 670: OpVectorShuffle: FloatVector3: tmp670 << tmp669, tmp668, 3, 1, 4 V_MOV_B32 vDst(VGPR341) src0(VGPR336) V_MOV_B32 vDst(VGPR342) src0(VGPR339) V_MOV_B32 vDst(VGPR343) src0(VGPR337) # OpStore: : tmp670 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR341) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR342) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR343) # 672: OpAccessChain: Float*: fp[2] # 673: OpCompositeExtract: Float: tmp673 << tmp618, 2 V_MOV_B32 vDst(VGPR332) src0(VGPR146) # 675: OpFMul: Float: tmp675 << tmp673, const674 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x40e00000 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR334) // VOP2 # 676: OpAccessChain: Float*: fp[0] # 677: OpCompositeExtract: Float: tmp677 << tmp618, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR144) # 679: OpFMul: Float: tmp679 << tmp677, const678 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x41100000 V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR334) // VOP2 # 680: OpFAdd: Float: tmp680 << tmp675, tmp679 V_ADD_F32 vDst(VGPR332) src0(VGPR335) src1(VGPR336) // VOP2 # 681: OpExtInst(Cos): Float: tmp681 << tmp680 V_MUL_F32 vDst(VGPR334) src0(LITERAL_CONST) src1(VGPR332) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR334) src0(VGPR334) V_COS_F32 vDst(VGPR334) src0(VGPR334) # 682: OpFMul: Float: tmp682 << const303, tmp681 V_MUL_F32 vDst(VGPR332) src0(0_5_F) src1(VGPR334) // VOP2 # 683: OpFAdd: Float: tmp683 << const303, tmp682 V_ADD_F32 vDst(VGPR334) src0(0_5_F) src1(VGPR332) // VOP2 # 684: OpExtInst(FMix): Float: tmp684 << const671, const106, tmp683 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR335) src0(1_0_F) V_SUBREV_F32 vDst(VGPR336) src0(VGPR334) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR336) // VOP2 V_MAD_F32 vDst(VGPR336) src0(VGPR335) src1(VGPR334) src2(VGPR336) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp684 >> ss V_MOV_B32 vDst(VGPR24) src0(VGPR336) # 686: OpLoad: FloatVector3: tmp686 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELS_B32 vDst(VGPR334) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR335) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR336) src0(VGPR2) # 687: OpExtInst(Length): Float: tmp687 << tmp686 V_MUL_F32 vDst(VGPR332) src0(VGPR334) src1(VGPR334) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR335) src1(VGPR335) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR336) src1(VGPR336) // VOP2 V_SQRT_F32 vDst(VGPR332) src0(VGPR332) # 688: OpLoad: Float: tmp688 << ss # 689: OpFSub: Float: tmp689 << tmp687, tmp688 V_SUB_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR24) // VOP2 # 691: OpAccessChain: Float*: p[1] # 692: OpLoad: Float: tmp692 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR146) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR1) # 693: OpFNegate: Float: tmp693 << tmp692 V_MUL_F32 vDst(VGPR335) src0(M1_0_F) src1(VGPR332) // VOP2 # 696: OpExtInst(FMax): Float: tmp696 << const100, tmp689 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR334) // VOP2 # 698: OpExtInst(FMax): Float: tmp698 << const100, tmp693 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR335) // VOP2 # 699: OpCompositeConstruct: FloatVector2: tmp699 << tmp696, tmp698 V_MOV_B32 vDst(VGPR337) src0(VGPR336) V_MOV_B32 vDst(VGPR338) src0(VGPR334) # 700: OpExtInst(Length): Float: tmp700 << tmp699 V_MUL_F32 vDst(VGPR332) src0(VGPR337) src1(VGPR337) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR338) src1(VGPR338) // VOP2 V_SQRT_F32 vDst(VGPR332) src0(VGPR332) # 701: OpFSub: Float: tmp701 << tmp700, const576 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3dcccccd V_SUB_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR334) // VOP2 # 703: OpFAdd: Float: tmp703 << tmp701, tmp653 V_ADD_F32 vDst(VGPR332) src0(VGPR335) src1(VGPR333) // VOP2 # 705: OpFMul: Float: tmp705 << tmp703, const704 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # OpReturnValue: : << tmp705 S_MOV_B32 sDst(M0) src0(SGPR133) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR334) S_SETPC_B64 sDst(SGPR144) src0(SGPR144) # FloatVector3 marble(vf2;(FloatVector2* p) Function: FloatVector3 marble(vf2;() S_MOV_B64 sDst(SGPR156) src0(EXEC) # lb74 Label: lb74 # 709: OpAccessChain: Float*: p[0] # 710: OpLoad: Float: tmp710 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 711: OpFAdd: Float: tmp711 << tmp710, const127 V_MOV_B32 vDst(VGPR333) src0(2_0_F) V_ADD_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 712: OpAccessChain: Float*: p[0] # OpStore: : tmp711 >> p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR334) # 717: OpLoad: FloatVector2: tmp717 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 718: OpExtInst(Floor): FloatVector2: tmp718 << tmp717 V_FLOOR_F32 vDst(VGPR162) src0(VGPR332) V_FLOOR_F32 vDst(VGPR163) src0(VGPR333) # 720: OpLoad: FloatVector2: tmp720 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 722: OpFSub: FloatVector2: tmp722 << tmp720, tmp718 V_SUB_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR162) // VOP2 V_SUB_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR163) // VOP2 # 723: OpFSub: FloatVector2: tmp723 << tmp722, const391 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_MOV_B32 vDst(VGPR333) src0(0_5_F) V_SUB_F32 vDst(VGPR164) src0(VGPR334) src1(VGPR332) // VOP2 V_SUB_F32 vDst(VGPR165) src0(VGPR335) src1(VGPR333) // VOP2 # 725: OpAccessChain: Float*: c1[0] # 726: OpCompositeExtract: Float: tmp726 << tmp723, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR164) # 727: OpVectorTimesScalar: FloatVector2: tmp727 << const342, tmp726 V_MOV_B32 vDst(VGPR333) src0(1_0_F) V_MOV_B32 vDst(VGPR334) src0(1_0_F) V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR334) // VOP2 # 728: OpAccessChain: Float*: c1[1] # 729: OpCompositeExtract: Float: tmp729 << tmp723, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR165) # 731: OpVectorTimesScalar: FloatVector2: tmp731 << const730, tmp729 V_MOV_B32 vDst(VGPR333) src0(1_0_F) V_MOV_B32 vDst(VGPR334) src0(M1_0_F) V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR332) src1(VGPR334) // VOP2 # 732: OpFAdd: FloatVector2: tmp732 << tmp727, tmp731 V_ADD_F32 vDst(VGPR339) src0(VGPR335) src1(VGPR337) // VOP2 V_ADD_F32 vDst(VGPR340) src0(VGPR336) src1(VGPR338) // VOP2 # 733: OpVectorTimesScalar: FloatVector2: tmp733 << tmp732, const704 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR166) src0(VGPR332) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR167) src0(VGPR332) src1(VGPR340) // VOP2 # 736: OpLoad: FloatVector2: tmp736 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 737: OpCompositeExtract: Float: tmp737 << tmp736, 0 V_MOV_B32 vDst(VGPR334) src0(VGPR332) # 738: OpCompositeExtract: Float: tmp738 << tmp736, 1 V_MOV_B32 vDst(VGPR335) src0(VGPR333) # 739: OpCompositeConstruct: FloatVector3: tmp739 << tmp737, tmp738, const100 V_MOV_B32 vDst(VGPR336) src0(VGPR334) V_MOV_B32 vDst(VGPR337) src0(VGPR335) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR338) src0(SGPR241) # OpStore: : tmp739 >> param740 V_MOV_B32 vDst(VGPR150) src0(VGPR336) V_MOV_B32 vDst(VGPR151) src0(VGPR337) V_MOV_B32 vDst(VGPR152) src0(VGPR338) # 741: OpFunctionCall: Float: fbm3(vf3;(param740) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x96 # VGPR[693:695] S_MOV_B64 sDst(SGPR158) src0(EXEC) S_MOV_B32 sDst(SGPR57) src0(LITERAL_CONST) const: 0xa8 # VGPR743 # Indirect branch to fbm3(vf3;: -4848 S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_SUB_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x12f0 S_SUBB_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR158) # .lbl44 # 742: OpFMul: Float: tmp742 << fbm3(vf3;, const303 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_MUL_F32 vDst(VGPR333) src0(VGPR168) src1(VGPR332) // VOP2 # 743: OpExtInst(FMax): Float: tmp743 << const100, tmp742 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 744: OpCompositeConstruct: FloatVector3: tmp744 << tmp743, tmp743, tmp743 V_MOV_B32 vDst(VGPR335) src0(VGPR334) V_MOV_B32 vDst(VGPR336) src0(VGPR334) V_MOV_B32 vDst(VGPR337) src0(VGPR334) # 745: OpCompositeConstruct: FloatVector3: tmp745 << const511, const511, const511 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3f400000 V_MOV_B32 vDst(VGPR338) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3f400000 V_MOV_B32 vDst(VGPR339) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3f400000 V_MOV_B32 vDst(VGPR340) src0(SGPR241) # 746: OpExtInst(FMix): FloatVector3: tmp746 << const735, tmp744, tmp745 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3d4ccccd V_SUBREV_F32 vDst(VGPR169) src0(VGPR338) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR169) src0(VGPR332) src1(VGPR169) // VOP2 V_MAD_F32 vDst(VGPR169) src0(VGPR335) src1(VGPR338) src2(VGPR169) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR170) src0(VGPR339) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR170) src0(VGPR333) src1(VGPR170) // VOP2 V_MAD_F32 vDst(VGPR170) src0(VGPR336) src1(VGPR339) src2(VGPR170) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR171) src0(VGPR340) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR171) src0(VGPR334) src1(VGPR171) // VOP2 V_MAD_F32 vDst(VGPR171) src0(VGPR337) src1(VGPR340) src2(VGPR171) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 754: OpVectorTimesScalar: FloatVector2: tmp754 << tmp718, const127 V_MOV_B32 vDst(VGPR332) src0(2_0_F) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR162) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR163) // VOP2 # 755: OpLoad: FloatVector2: tmp755 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELS_B32 vDst(VGPR335) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR336) src0(VGPR1) # 756: OpVectorTimesScalar: FloatVector2: tmp756 << tmp755, const106 V_MOV_B32 vDst(VGPR332) src0(1_0_F) V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR332) src1(VGPR336) // VOP2 # 757: OpFAdd: FloatVector2: tmp757 << tmp754, tmp756 V_ADD_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR337) // VOP2 V_ADD_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR338) // VOP2 # 758: OpLoad: FloatVector2: tmp758 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 759: OpVectorShuffle: FloatVector2: tmp759 << tmp758, tmp758, 1, 0 V_MOV_B32 vDst(VGPR337) src0(VGPR333) V_MOV_B32 vDst(VGPR338) src0(VGPR332) # 760: OpVectorTimesScalar: FloatVector2: tmp760 << tmp759, const127 V_MOV_B32 vDst(VGPR332) src0(2_0_F) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR337) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR338) // VOP2 # 761: OpExtInst(Cos): FloatVector2: tmp761 << tmp760 V_MUL_F32 vDst(VGPR337) src0(LITERAL_CONST) src1(VGPR333) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR337) src0(VGPR337) V_MUL_F32 vDst(VGPR338) src0(LITERAL_CONST) src1(VGPR334) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR338) src0(VGPR338) V_COS_F32 vDst(VGPR337) src0(VGPR337) V_COS_F32 vDst(VGPR338) src0(VGPR338) # 762: OpVectorTimesScalar: FloatVector2: tmp762 << tmp761, const748 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3ecccccd V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR337) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR338) // VOP2 # 763: OpFAdd: FloatVector2: tmp763 << tmp757, tmp762 V_ADD_F32 vDst(VGPR337) src0(VGPR335) src1(VGPR333) // VOP2 V_ADD_F32 vDst(VGPR338) src0(VGPR336) src1(VGPR334) // VOP2 # 764: OpCompositeExtract: Float: tmp764 << tmp763, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR337) # 765: OpCompositeExtract: Float: tmp765 << tmp763, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR338) # 766: OpCompositeConstruct: FloatVector3: tmp766 << tmp764, tmp765, const100 V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR333) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR336) src0(SGPR241) # OpStore: : tmp766 >> param767 V_MOV_B32 vDst(VGPR153) src0(VGPR334) V_MOV_B32 vDst(VGPR154) src0(VGPR335) V_MOV_B32 vDst(VGPR155) src0(VGPR336) # 768: OpFunctionCall: Float: fbm3(vf3;(param767) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x99 # VGPR[696:698] S_MOV_B64 sDst(SGPR160) src0(EXEC) S_MOV_B32 sDst(SGPR57) src0(LITERAL_CONST) const: 0xac # VGPR793 # Indirect branch to fbm3(vf3;: -5228 S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_SUB_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x146c S_SUBB_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR160) # .lbl45 # 769: OpFAdd: Float: tmp769 << const303, fbm3(vf3; V_ADD_F32 vDst(VGPR332) src0(0_5_F) src1(VGPR172) // VOP2 # 770: OpExtInst(SmoothStep): Float: tmp770 << const748, const151, tmp769 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3f4ccccd V_CMP_GE_F32 src0(VGPR333) src1(VGPR332) # CF Block: Merge: .lbl49 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl50, false: .lbl46 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl46 Label: .lbl50 V_MOV_B32 vDst(VGPR335) src0(0) Label: .lbl46 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl49 V_CMP_LE_F32 src0(VGPR334) src1(VGPR332) # CF Block: Merge: .lbl48 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl51, false: .lbl47 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl47 Label: .lbl51 V_MOV_B32 vDst(VGPR335) src0(1_0_F) Label: .lbl47 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl48 V_SUBREV_F32 vDst(VGPR336) src0(VGPR333) src1(VGPR334) // VOP2 V_RCP_F32 vDst(VGPR336) src0(VGPR336) V_SUBREV_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR335) src1(VGPR336) // VOP2 V_MAX_F32 vDst(VGPR336) src0(0) src1(VGPR336) // VOP2 V_MIN_F32 vDst(VGPR336) src0(1_0_F) src1(VGPR336) // VOP2 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR335) src0(2_0_F) src1(VGPR336) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR336) src0(VGPR336) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR336) src1(VGPR335) // VOP2 Label: .lbl48 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) Label: .lbl49 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) # 771: OpFSub: Float: tmp771 << const106, tmp770 V_SUB_F32 vDst(VGPR332) src0(1_0_F) src1(VGPR335) // VOP2 # 772: OpCompositeConstruct: FloatVector3: tmp772 << tmp771, tmp771, tmp771 V_MOV_B32 vDst(VGPR333) src0(VGPR332) V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR332) # 773: OpExtInst(FMix): FloatVector3: tmp773 << const750, const752, tmp772 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR338) src0(LITERAL_CONST) const: 0x3e75c28f V_MOV_B32 vDst(VGPR339) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR340) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR341) src0(LITERAL_CONST) const: 0x3f0f5c29 V_SUBREV_F32 vDst(VGPR173) src0(VGPR333) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR173) src0(VGPR336) src1(VGPR173) // VOP2 V_MAD_F32 vDst(VGPR173) src0(VGPR339) src1(VGPR333) src2(VGPR173) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR174) src0(VGPR334) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR174) src0(VGPR337) src1(VGPR174) // VOP2 V_MAD_F32 vDst(VGPR174) src0(VGPR340) src1(VGPR334) src2(VGPR174) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR175) src0(VGPR335) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR175) src0(VGPR338) src1(VGPR175) // VOP2 V_MAD_F32 vDst(VGPR175) src0(VGPR341) src1(VGPR335) src2(VGPR175) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 774: OpLoad: FloatVector2: tmp774 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 775: OpVectorTimesScalar: FloatVector2: tmp775 << tmp774, const671 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3f333333 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR333) // VOP2 # 776: OpCompositeExtract: Float: tmp776 << tmp775, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR335) # 777: OpCompositeExtract: Float: tmp777 << tmp775, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR336) # 778: OpCompositeConstruct: FloatVector3: tmp778 << tmp776, tmp777, const100 V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR333) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR336) src0(SGPR241) # OpStore: : tmp778 >> param779 V_MOV_B32 vDst(VGPR156) src0(VGPR334) V_MOV_B32 vDst(VGPR157) src0(VGPR335) V_MOV_B32 vDst(VGPR158) src0(VGPR336) # 780: OpFunctionCall: Float: fbm3(vf3;(param779) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x9c # VGPR[699:701] S_MOV_B64 sDst(SGPR162) src0(EXEC) S_MOV_B32 sDst(SGPR57) src0(LITERAL_CONST) const: 0xb0 # VGPR823 # Indirect branch to fbm3(vf3;: -5620 S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_SUB_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x15f4 S_SUBB_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR162) # .lbl52 # 781: OpFMul: Float: tmp781 << fbm3(vf3;, const106 V_MOV_B32 vDst(VGPR332) src0(1_0_F) V_MUL_F32 vDst(VGPR333) src0(VGPR176) src1(VGPR332) // VOP2 # 782: OpExtInst(FMax): Float: tmp782 << const100, tmp781 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 783: OpCompositeConstruct: FloatVector3: tmp783 << tmp782, tmp782, tmp782 V_MOV_B32 vDst(VGPR335) src0(VGPR334) V_MOV_B32 vDst(VGPR336) src0(VGPR334) V_MOV_B32 vDst(VGPR337) src0(VGPR334) # 784: OpFAdd: FloatVector3: tmp784 << tmp773, tmp783 V_ADD_F32 vDst(VGPR177) src0(VGPR173) src1(VGPR335) // VOP2 V_ADD_F32 vDst(VGPR178) src0(VGPR174) src1(VGPR336) // VOP2 V_ADD_F32 vDst(VGPR179) src0(VGPR175) src1(VGPR337) // VOP2 # 785: OpLoad: FloatVector2: tmp785 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 786: OpFNegate: FloatVector2: tmp786 << tmp785 V_MUL_F32 vDst(VGPR334) src0(M1_0_F) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR335) src0(M1_0_F) src1(VGPR333) // VOP2 # 787: OpCompositeExtract: Float: tmp787 << tmp786, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR334) # 788: OpCompositeExtract: Float: tmp788 << tmp786, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR335) # 789: OpCompositeConstruct: FloatVector3: tmp789 << tmp787, tmp788, const100 V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR333) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR336) src0(SGPR241) # OpStore: : tmp789 >> param790 V_MOV_B32 vDst(VGPR159) src0(VGPR334) V_MOV_B32 vDst(VGPR160) src0(VGPR335) V_MOV_B32 vDst(VGPR161) src0(VGPR336) # 791: OpFunctionCall: Float: fbm3(vf3;(param790) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x9f # VGPR[702:704] S_MOV_B64 sDst(SGPR164) src0(EXEC) S_MOV_B32 sDst(SGPR57) src0(LITERAL_CONST) const: 0xb4 # VGPR844 # Indirect branch to fbm3(vf3;: -5776 S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_SUB_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x1690 S_SUBB_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR164) # .lbl53 # 792: OpExtInst(SmoothStep): Float: tmp792 << const489, const523, fbm3(vf3; V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3e4ccccd V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3e99999a V_CMP_GE_F32 src0(VGPR332) src1(VGPR180) # CF Block: Merge: .lbl57 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl58, false: .lbl54 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl54 Label: .lbl58 V_MOV_B32 vDst(VGPR334) src0(0) Label: .lbl54 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl57 V_CMP_LE_F32 src0(VGPR333) src1(VGPR180) # CF Block: Merge: .lbl56 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl59, false: .lbl55 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl55 Label: .lbl59 V_MOV_B32 vDst(VGPR334) src0(1_0_F) Label: .lbl55 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl56 V_SUBREV_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 V_RCP_F32 vDst(VGPR335) src0(VGPR335) V_SUBREV_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR180) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR335) // VOP2 V_MAX_F32 vDst(VGPR335) src0(0) src1(VGPR335) // VOP2 V_MIN_F32 vDst(VGPR335) src0(1_0_F) src1(VGPR335) // VOP2 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR334) src0(2_0_F) src1(VGPR335) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR335) src0(VGPR335) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR335) src1(VGPR334) // VOP2 Label: .lbl56 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) Label: .lbl57 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) # 793: OpCompositeConstruct: FloatVector3: tmp793 << tmp792, tmp792, tmp792 V_MOV_B32 vDst(VGPR335) src0(VGPR334) V_MOV_B32 vDst(VGPR336) src0(VGPR334) V_MOV_B32 vDst(VGPR337) src0(VGPR334) # 794: OpVectorTimesScalar: FloatVector3: tmp794 << tmp793, const489 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3e4ccccd V_MUL_F32 vDst(VGPR338) src0(VGPR332) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR332) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR332) src1(VGPR337) // VOP2 # 795: OpFAdd: FloatVector3: tmp795 << tmp784, tmp794 V_ADD_F32 vDst(VGPR332) src0(VGPR177) src1(VGPR338) // VOP2 V_ADD_F32 vDst(VGPR333) src0(VGPR178) src1(VGPR339) // VOP2 V_ADD_F32 vDst(VGPR334) src0(VGPR179) src1(VGPR340) // VOP2 # 798: OpCompositeConstruct: FloatVector3: tmp798 << const303, const303, const303 V_MOV_B32 vDst(VGPR335) src0(0_5_F) V_MOV_B32 vDst(VGPR336) src0(0_5_F) V_MOV_B32 vDst(VGPR337) src0(0_5_F) # 799: OpExtInst(FMix): FloatVector3: tmp799 << tmp795, const735, tmp798 V_MOV_B32 vDst(VGPR338) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR339) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR340) src0(LITERAL_CONST) const: 0x3d4ccccd V_SUBREV_F32 vDst(VGPR341) src0(VGPR335) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR341) src0(VGPR332) src1(VGPR341) // VOP2 V_MAD_F32 vDst(VGPR341) src0(VGPR338) src1(VGPR335) src2(VGPR341) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR342) src0(VGPR336) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR342) src0(VGPR333) src1(VGPR342) // VOP2 V_MAD_F32 vDst(VGPR342) src0(VGPR339) src1(VGPR336) src2(VGPR342) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR343) src0(VGPR337) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR343) src0(VGPR334) src1(VGPR343) // VOP2 V_MAD_F32 vDst(VGPR343) src0(VGPR340) src1(VGPR337) src2(VGPR343) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 802: OpFSub: Float: tmp802 << const303, const714 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR336) src0(0_5_F) src1(VGPR335) // VOP2 # 803: OpAccessChain: Float*: c1[1] # 804: OpCompositeExtract: Float: tmp804 << tmp723, 1 V_MOV_B32 vDst(VGPR335) src0(VGPR165) # 805: OpExtInst(FAbs): Float: tmp805 << tmp804 V_ADD_F32 vDst(VGPR337) src0(VGPR335) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 806: OpExtInst(SmoothStep): Float: tmp806 << tmp802, const303, tmp805 V_MOV_B32 vDst(VGPR335) src0(0_5_F) V_CMP_GE_F32 src0(VGPR336) src1(VGPR337) # CF Block: Merge: .lbl63 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl64, false: .lbl60 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl60 Label: .lbl64 V_MOV_B32 vDst(VGPR338) src0(0) Label: .lbl60 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl63 V_CMP_LE_F32 src0(VGPR335) src1(VGPR337) # CF Block: Merge: .lbl62 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl65, false: .lbl61 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl61 Label: .lbl65 V_MOV_B32 vDst(VGPR338) src0(1_0_F) Label: .lbl61 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl62 V_SUBREV_F32 vDst(VGPR339) src0(VGPR336) src1(VGPR335) // VOP2 V_RCP_F32 vDst(VGPR339) src0(VGPR339) V_SUBREV_F32 vDst(VGPR338) src0(VGPR336) src1(VGPR337) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR338) src1(VGPR339) // VOP2 V_MAX_F32 vDst(VGPR339) src0(0) src1(VGPR339) // VOP2 V_MIN_F32 vDst(VGPR339) src0(1_0_F) src1(VGPR339) // VOP2 V_MOV_B32 vDst(VGPR338) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR338) src0(2_0_F) src1(VGPR339) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR339) src0(VGPR339) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR339) src1(VGPR338) // VOP2 Label: .lbl62 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) Label: .lbl63 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) # 808: OpFSub: Float: tmp808 << const303, const714 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR336) src0(0_5_F) src1(VGPR335) // VOP2 # 809: OpAccessChain: Float*: c1[0] # 810: OpCompositeExtract: Float: tmp810 << tmp723, 0 V_MOV_B32 vDst(VGPR335) src0(VGPR164) # 811: OpExtInst(FAbs): Float: tmp811 << tmp810 V_ADD_F32 vDst(VGPR337) src0(VGPR335) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 812: OpExtInst(SmoothStep): Float: tmp812 << tmp808, const303, tmp811 V_MOV_B32 vDst(VGPR335) src0(0_5_F) V_CMP_GE_F32 src0(VGPR336) src1(VGPR337) # CF Block: Merge: .lbl69 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl70, false: .lbl66 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl66 Label: .lbl70 V_MOV_B32 vDst(VGPR339) src0(0) Label: .lbl66 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl69 V_CMP_LE_F32 src0(VGPR335) src1(VGPR337) # CF Block: Merge: .lbl68 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl71, false: .lbl67 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl67 Label: .lbl71 V_MOV_B32 vDst(VGPR339) src0(1_0_F) Label: .lbl67 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl68 V_SUBREV_F32 vDst(VGPR340) src0(VGPR336) src1(VGPR335) // VOP2 V_RCP_F32 vDst(VGPR340) src0(VGPR340) V_SUBREV_F32 vDst(VGPR339) src0(VGPR336) src1(VGPR337) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR339) src1(VGPR340) // VOP2 V_MAX_F32 vDst(VGPR340) src0(0) src1(VGPR340) // VOP2 V_MIN_F32 vDst(VGPR340) src0(1_0_F) src1(VGPR340) // VOP2 V_MOV_B32 vDst(VGPR339) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR339) src0(2_0_F) src1(VGPR340) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR340) src0(VGPR340) src1(VGPR340) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR340) src1(VGPR339) // VOP2 Label: .lbl68 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) Label: .lbl69 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) # 813: OpExtInst(FMax): Float: tmp813 << tmp806, tmp812 V_MAX_F32 vDst(VGPR335) src0(VGPR338) src1(VGPR339) // VOP2 # 816: OpFSub: Float: tmp816 << const303, const714 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR337) src0(0_5_F) src1(VGPR336) // VOP2 # 817: OpAccessChain: Float*: rc1[1] # 818: OpCompositeExtract: Float: tmp818 << tmp733, 1 V_MOV_B32 vDst(VGPR336) src0(VGPR167) # 819: OpExtInst(FAbs): Float: tmp819 << tmp818 V_ADD_F32 vDst(VGPR338) src0(VGPR336) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 820: OpExtInst(SmoothStep): Float: tmp820 << tmp816, const303, tmp819 V_MOV_B32 vDst(VGPR336) src0(0_5_F) V_CMP_GE_F32 src0(VGPR337) src1(VGPR338) # CF Block: Merge: .lbl75 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl76, false: .lbl72 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl72 Label: .lbl76 V_MOV_B32 vDst(VGPR339) src0(0) Label: .lbl72 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl75 V_CMP_LE_F32 src0(VGPR336) src1(VGPR338) # CF Block: Merge: .lbl74 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl77, false: .lbl73 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl73 Label: .lbl77 V_MOV_B32 vDst(VGPR339) src0(1_0_F) Label: .lbl73 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl74 V_SUBREV_F32 vDst(VGPR340) src0(VGPR337) src1(VGPR336) // VOP2 V_RCP_F32 vDst(VGPR340) src0(VGPR340) V_SUBREV_F32 vDst(VGPR339) src0(VGPR337) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR339) src1(VGPR340) // VOP2 V_MAX_F32 vDst(VGPR340) src0(0) src1(VGPR340) // VOP2 V_MIN_F32 vDst(VGPR340) src0(1_0_F) src1(VGPR340) // VOP2 V_MOV_B32 vDst(VGPR339) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR339) src0(2_0_F) src1(VGPR340) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR340) src0(VGPR340) src1(VGPR340) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR340) src1(VGPR339) // VOP2 Label: .lbl74 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) Label: .lbl75 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) # 822: OpFSub: Float: tmp822 << const303, const714 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x3c75c28f V_SUB_F32 vDst(VGPR337) src0(0_5_F) src1(VGPR336) // VOP2 # 823: OpAccessChain: Float*: rc1[0] # 824: OpCompositeExtract: Float: tmp824 << tmp733, 0 V_MOV_B32 vDst(VGPR336) src0(VGPR166) # 825: OpExtInst(FAbs): Float: tmp825 << tmp824 V_ADD_F32 vDst(VGPR338) src0(VGPR336) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 826: OpExtInst(SmoothStep): Float: tmp826 << tmp822, const303, tmp825 V_MOV_B32 vDst(VGPR336) src0(0_5_F) V_CMP_GE_F32 src0(VGPR337) src1(VGPR338) # CF Block: Merge: .lbl81 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl82, false: .lbl78 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl78 Label: .lbl82 V_MOV_B32 vDst(VGPR340) src0(0) Label: .lbl78 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl81 V_CMP_LE_F32 src0(VGPR336) src1(VGPR338) # CF Block: Merge: .lbl80 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl83, false: .lbl79 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl79 Label: .lbl83 V_MOV_B32 vDst(VGPR340) src0(1_0_F) Label: .lbl79 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR156) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl80 V_SUBREV_F32 vDst(VGPR344) src0(VGPR337) src1(VGPR336) // VOP2 V_RCP_F32 vDst(VGPR344) src0(VGPR344) V_SUBREV_F32 vDst(VGPR340) src0(VGPR337) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR344) src0(VGPR340) src1(VGPR344) // VOP2 V_MAX_F32 vDst(VGPR344) src0(0) src1(VGPR344) // VOP2 V_MIN_F32 vDst(VGPR344) src0(1_0_F) src1(VGPR344) // VOP2 V_MOV_B32 vDst(VGPR340) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR340) src0(2_0_F) src1(VGPR344) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR344) src0(VGPR344) src1(VGPR344) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR344) src1(VGPR340) // VOP2 Label: .lbl80 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) Label: .lbl81 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) # 827: OpExtInst(FMax): Float: tmp827 << tmp820, tmp826 V_MAX_F32 vDst(VGPR336) src0(VGPR339) src1(VGPR340) // VOP2 # 832: OpCompositeConstruct: FloatVector3: tmp832 << tmp827, tmp827, tmp827 V_MOV_B32 vDst(VGPR337) src0(VGPR336) V_MOV_B32 vDst(VGPR338) src0(VGPR336) V_MOV_B32 vDst(VGPR339) src0(VGPR336) # 833: OpExtInst(FMix): FloatVector3: tmp833 << tmp799, tmp746, tmp832 V_SUBREV_F32 vDst(VGPR344) src0(VGPR337) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR344) src0(VGPR341) src1(VGPR344) // VOP2 V_MAD_F32 vDst(VGPR344) src0(VGPR169) src1(VGPR337) src2(VGPR344) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR345) src0(VGPR338) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR345) src0(VGPR342) src1(VGPR345) // VOP2 V_MAD_F32 vDst(VGPR345) src0(VGPR170) src1(VGPR338) src2(VGPR345) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR346) src0(VGPR339) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR346) src0(VGPR343) src1(VGPR346) // VOP2 V_MAD_F32 vDst(VGPR346) src0(VGPR171) src1(VGPR339) src2(VGPR346) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 836: OpExtInst(FMax): Float: tmp836 << tmp827, tmp813 V_MAX_F32 vDst(VGPR337) src0(VGPR336) src1(VGPR335) // VOP2 # 837: OpCompositeConstruct: FloatVector3: tmp837 << tmp836, tmp836, tmp836 V_MOV_B32 vDst(VGPR338) src0(VGPR337) V_MOV_B32 vDst(VGPR339) src0(VGPR337) V_MOV_B32 vDst(VGPR340) src0(VGPR337) # 838: OpExtInst(FMix): FloatVector3: tmp838 << tmp795, tmp833, tmp837 V_SUBREV_F32 vDst(VGPR341) src0(VGPR338) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR341) src0(VGPR332) src1(VGPR341) // VOP2 V_MAD_F32 vDst(VGPR341) src0(VGPR344) src1(VGPR338) src2(VGPR341) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR342) src0(VGPR339) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR342) src0(VGPR333) src1(VGPR342) // VOP2 V_MAD_F32 vDst(VGPR342) src0(VGPR345) src1(VGPR339) src2(VGPR342) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR343) src0(VGPR340) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR343) src0(VGPR334) src1(VGPR343) // VOP2 V_MAD_F32 vDst(VGPR343) src0(VGPR346) src1(VGPR340) src2(VGPR343) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 839: OpVectorTimesScalar: FloatVector3: tmp839 << tmp838, const151 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f4ccccd V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR341) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR342) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR343) // VOP2 # OpReturnValue: : << tmp839 S_MOV_B32 sDst(M0) src0(SGPR147) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR333) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR334) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR335) S_SETPC_B64 sDst(SGPR152) src0(SGPR152) # FloatVector3 cameraPos(f1;(Float* t) Function: FloatVector3 cameraPos(f1;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb77 Label: lb77 # 842: OpLoad: Float: tmp842 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR168) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 843: OpFMul: Float: tmp843 << tmp842, const704 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 845: OpLoad: Float: tmp845 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR168) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 846: OpFMul: Float: tmp846 << tmp845, const377 V_MOV_B32 vDst(VGPR333) src0(4_0_F) V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 # 847: OpExtInst(Cos): Float: tmp847 << tmp846 V_MUL_F32 vDst(VGPR332) src0(LITERAL_CONST) src1(VGPR335) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR332) src0(VGPR332) V_COS_F32 vDst(VGPR332) src0(VGPR332) # 849: OpFMul: Float: tmp849 << tmp847, const848 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3cf5c28f V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 # 850: OpFAdd: Float: tmp850 << const844, tmp849 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40c00000 V_ADD_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR335) // VOP2 # 851: OpCompositeConstruct: FloatVector3: tmp851 << tmp843, tmp850, const100 V_MOV_B32 vDst(VGPR335) src0(VGPR334) V_MOV_B32 vDst(VGPR336) src0(VGPR333) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR337) src0(SGPR241) # OpReturnValue: : << tmp851 S_MOV_B32 sDst(M0) src0(SGPR155) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR335) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR336) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR337) S_SETPC_B64 sDst(SGPR166) src0(SGPR166) # FloatVector3 targetPos(f1;(Float* ti) Function: FloatVector3 targetPos(f1;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb80 Label: lb80 # 855: OpLoad: Float: tmp855 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR172) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 856: OpLoad: Float: tmp856 << t_per_target # 857: OpFMul: Float: tmp857 << tmp855, tmp856 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR26) // VOP2 # OpStore: : tmp857 >> param858 V_MOV_B32 vDst(VGPR181) src0(VGPR333) # 859: OpFunctionCall: FloatVector3: cameraPos(f1;(param858) S_ADD_U32 sDst(SGPR168) src0(LITERAL_CONST) src1(0) const: 0xb5 # VGPR933 S_MOV_B64 sDst(SGPR174) src0(EXEC) S_MOV_B32 sDst(SGPR155) src0(LITERAL_CONST) const: 0xb6 # VGPR[936:938] # Indirect branch to cameraPos(f1;: -176 S_GETPC_B64 sDst(SGPR166) src0(SGPR166) S_SUB_U32 sDst(SGPR166) src0(SGPR166) src1(LITERAL_CONST) const: 0xb0 S_SUBB_U32 sDst(SGPR167) src0(SGPR167) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR166) src0(SGPR166) S_MOV_B64 sDst(EXEC) src0(SGPR174) # .lbl84 # 861: OpFMul: FloatVector3: tmp861 << cameraPos(f1;, const860 V_MOV_B32 vDst(VGPR334) src0(1_0_F) V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x00000000 V_MUL_F32 vDst(VGPR337) src0(VGPR182) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR183) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR184) src1(VGPR336) // VOP2 # 862: OpLoad: Float: tmp862 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR172) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 864: OpFMul: Float: tmp864 << tmp862, const863 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x41a00000 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 865: OpExtInst(Cos): Float: tmp865 << tmp864 V_MUL_F32 vDst(VGPR332) src0(LITERAL_CONST) src1(VGPR334) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR332) src0(VGPR332) V_COS_F32 vDst(VGPR332) src0(VGPR332) # 866: OpFMul: Float: tmp866 << tmp865, const377 V_MOV_B32 vDst(VGPR333) src0(4_0_F) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 868: OpLoad: Float: tmp868 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR172) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 870: OpFMul: Float: tmp870 << tmp868, const869 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x41600000 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 # 871: OpExtInst(Cos): Float: tmp871 << tmp870 V_MUL_F32 vDst(VGPR332) src0(LITERAL_CONST) src1(VGPR335) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR332) src0(VGPR332) V_COS_F32 vDst(VGPR332) src0(VGPR332) # 872: OpFMul: Float: tmp872 << tmp871, const109 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 # 873: OpFAdd: Float: tmp873 << const867, tmp872 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0xc0e00000 V_ADD_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR335) // VOP2 # 874: OpCompositeConstruct: FloatVector3: tmp874 << tmp866, const100, tmp873 V_MOV_B32 vDst(VGPR340) src0(VGPR334) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR341) src0(SGPR241) V_MOV_B32 vDst(VGPR342) src0(VGPR333) # 875: OpFAdd: FloatVector3: tmp875 << tmp861, tmp874 V_ADD_F32 vDst(VGPR343) src0(VGPR337) src1(VGPR340) // VOP2 V_ADD_F32 vDst(VGPR344) src0(VGPR338) src1(VGPR341) // VOP2 V_ADD_F32 vDst(VGPR345) src0(VGPR339) src1(VGPR342) // VOP2 # OpStore: : tmp875 >> target V_MOV_B32 vDst(VGPR332) src0(VGPR343) V_MOV_B32 vDst(VGPR333) src0(VGPR344) V_MOV_B32 vDst(VGPR334) src0(VGPR345) # 876: OpLoad: FloatVector3: tmp876 << target # 877: OpVectorShuffle: FloatVector2: tmp877 << tmp876, tmp876, 0, 2 V_MOV_B32 vDst(VGPR335) src0(VGPR332) V_MOV_B32 vDst(VGPR336) src0(VGPR334) # 878: OpCompositeConstruct: FloatVector2: tmp878 << const109, const109 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR337) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR338) src0(SGPR241) # 879: OpFDiv: FloatVector2: tmp879 << tmp877, tmp878 V_RCP_F32 vDst(VGPR339) src0(VGPR337) V_RCP_F32 vDst(VGPR340) src0(VGPR338) V_MUL_F32 vDst(VGPR339) src0(VGPR335) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR336) src1(VGPR340) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR339) src0(VGPR339) src1(VGPR337) src2(VGPR335) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR340) src0(VGPR340) src1(VGPR338) src2(VGPR336) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 880: OpExtInst(Floor): FloatVector2: tmp880 << tmp879 V_FLOOR_F32 vDst(VGPR335) src0(VGPR339) V_FLOOR_F32 vDst(VGPR336) src0(VGPR340) # 881: OpVectorTimesScalar: FloatVector2: tmp881 << tmp880, const109 V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR338) src0(VGPR337) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR337) src1(VGPR336) // VOP2 # 882: OpFAdd: FloatVector2: tmp882 << tmp881, const667 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x3fc00000 V_ADD_F32 vDst(VGPR340) src0(VGPR338) src1(VGPR335) // VOP2 V_ADD_F32 vDst(VGPR341) src0(VGPR339) src1(VGPR336) // VOP2 # 883: OpLoad: FloatVector3: tmp883 << target # 884: OpVectorShuffle: FloatVector3: tmp884 << tmp883, tmp882, 3, 1, 4 V_MOV_B32 vDst(VGPR335) src0(VGPR340) V_MOV_B32 vDst(VGPR336) src0(VGPR333) V_MOV_B32 vDst(VGPR337) src0(VGPR341) # OpStore: : tmp884 >> target V_MOV_B32 vDst(VGPR332) src0(VGPR335) V_MOV_B32 vDst(VGPR333) src0(VGPR336) V_MOV_B32 vDst(VGPR334) src0(VGPR337) # 885: OpLoad: FloatVector3: tmp885 << target # OpReturnValue: : << tmp885 S_MOV_B32 sDst(M0) src0(SGPR169) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR332) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR333) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR334) S_SETPC_B64 sDst(SGPR170) src0(SGPR170) # Float cameraZoom(f1;(Float* ti) Function: Float cameraZoom(f1;() S_MOV_B64 sDst(SGPR242) src0(EXEC) # lb83 Label: lb83 # 889: OpLoad: Float: tmp889 << ti S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR178) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 890: OpFMul: Float: tmp890 << tmp889, const633 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x41f00000 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 891: OpExtInst(Cos): Float: tmp891 << tmp890 V_MUL_F32 vDst(VGPR332) src0(LITERAL_CONST) src1(VGPR334) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR332) src0(VGPR332) V_COS_F32 vDst(VGPR332) src0(VGPR332) # 892: OpFMul: Float: tmp892 << const303, tmp891 V_MUL_F32 vDst(VGPR333) src0(0_5_F) src1(VGPR332) // VOP2 # 893: OpFAdd: Float: tmp893 << const303, tmp892 V_ADD_F32 vDst(VGPR332) src0(0_5_F) src1(VGPR333) // VOP2 # 894: OpExtInst(FMix): Float: tmp894 << const109, const888, tmp893 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x40600000 V_SUBREV_F32 vDst(VGPR335) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR335) // VOP2 V_MAD_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR332) src2(VGPR335) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 896: OpFMul: Float: tmp896 << tmp894, const895 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3fb33333 V_MUL_F32 vDst(VGPR333) src0(VGPR335) src1(VGPR332) // VOP2 # OpReturnValue: : << tmp896 S_MOV_B32 sDst(M0) src0(SGPR173) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR333) S_SETPC_B64 sDst(SGPR176) src0(SGPR176) # FloatVector3 trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* t, Float* max_t) Function: FloatVector3 trace(vf3;vf3;f1;f1;(, FloatVector3 cameraZoom(f1;.rd, Float cameraZoom(f1;.t, Float cameraZoom(f1;.max_t) S_MOV_B64 sDst(SGPR186) src0(EXEC) # lb90 Label: lb90 # OpStore: : const471 >> i S_MOV_B32 sDst(SGPR240) src0(0) # OpBranch: to lb900 # lb900 Label: lb900 # OpLoopMerge: (merge: lb902, continue: lb903) # CF Block: Merge: lb902, Continue: lb903 S_MOV_B64 sDst(SGPR188) src0(EXEC) S_MOV_B64 sDst(SGPR190) src0(EXEC) S_MOV_B64 sDst(SGPR192) src0(EXEC) Label: lb900Loop # OpBranch: to lb904 # lb904 Label: lb904 # 905: OpLoad: Int: tmp905 << i Decorators: RelaxedPrecision # 907: OpSLessThan: Bool: tmp907 << tmp905, const906 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000064 V_CMP_LT_I32 dst(SGPR242) src0(SGPR240) src1(VGPR332) // VOP3a # OpBranchConditional: if(tmp907) then branch to lb901, else branch to lb902 # CF Block: Cond Branch: true: lb901, false: lb902 S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 95 lb902 # lb901 Label: lb901 S_MOV_B64 sDst(SGPR190) src0(EXEC) S_MOV_B64 sDst(SGPR192) src0(EXEC) # 909: OpLoad: FloatVector3: tmp909 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR182) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) # 910: OpLoad: FloatVector3: tmp910 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR183) const: 0x0 V_MOVRELS_B32 vDst(VGPR335) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR336) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR337) src0(VGPR2) # 911: OpLoad: Float: tmp911 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR184) const: 0x0 V_MOVRELS_B32 vDst(VGPR338) src0(VGPR0) # 912: OpVectorTimesScalar: FloatVector3: tmp912 << tmp910, tmp911 V_MUL_F32 vDst(VGPR339) src0(VGPR338) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR338) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR341) src0(VGPR338) src1(VGPR337) // VOP2 # 913: OpFAdd: FloatVector3: tmp913 << tmp909, tmp912 V_ADD_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR339) // VOP2 V_ADD_F32 vDst(VGPR336) src0(VGPR333) src1(VGPR340) // VOP2 V_ADD_F32 vDst(VGPR337) src0(VGPR334) src1(VGPR341) // VOP2 # OpStore: : tmp913 >> param914 V_MOV_B32 vDst(VGPR185) src0(VGPR335) V_MOV_B32 vDst(VGPR186) src0(VGPR336) V_MOV_B32 vDst(VGPR187) src0(VGPR337) # 915: OpFunctionCall: Float: de(vf3;(param914) S_ADD_U32 sDst(SGPR146) src0(LITERAL_CONST) src1(0) const: 0xb9 # VGPR[998:1000] S_MOV_B64 sDst(SGPR194) src0(EXEC) S_MOV_B32 sDst(SGPR133) src0(LITERAL_CONST) const: 0xd7 # VGPR1045 # Indirect branch to de(vf3;: -4168 S_GETPC_B64 sDst(SGPR144) src0(SGPR144) S_SUB_U32 sDst(SGPR144) src0(SGPR144) src1(LITERAL_CONST) const: 0x1048 S_SUBB_U32 sDst(SGPR145) src0(SGPR145) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR144) src0(SGPR144) S_MOV_B64 sDst(EXEC) src0(SGPR194) # .lbl85 # 916: OpLoad: Float: tmp916 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR184) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 917: OpLoad: Float: tmp917 << max_t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR185) const: 0x0 V_MOVRELS_B32 vDst(VGPR333) src0(VGPR0) # 918: OpFOrdGreaterThan: Bool: tmp918 << tmp916, tmp917 V_CMP_GT_F32 dst(SGPR242) src0(VGPR332) src1(VGPR333) // VOP3a # OpSelectionMerge: (merge: lb920) # CF Block: Merge: lb920 S_MOV_B64 sDst(SGPR244) src0(EXEC) # OpBranchConditional: if(tmp918) then branch to lb919, else branch to lb920 # CF Block: Cond Branch: true: lb919, false: lb920 S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 13 lb920 # lb919 Label: lb919 # OpReturnValue: : << const921 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR242) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR243) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(M0) src0(SGPR179) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR241) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR242) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR243) S_ANDN2_B64 sDst(SGPR186) src0(SGPR186) src1(EXEC) S_ANDN2_B64 sDst(SGPR190) src0(SGPR190) src1(EXEC) S_ANDN2_B64 sDst(SGPR192) src0(SGPR192) src1(EXEC) # lb920 Label: lb920 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR192) # 924: OpExtInst(FAbs): Float: tmp924 << de(vf3; V_ADD_F32 vDst(VGPR332) src0(VGPR215) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 926: OpFOrdLessThan: Bool: tmp926 << tmp924, const925 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x38d1b717 V_CMP_LT_F32 dst(SGPR242) src0(VGPR332) src1(VGPR333) // VOP3a # OpSelectionMerge: (merge: lb928) # CF Block: Merge: lb928 S_MOV_B64 sDst(SGPR244) src0(EXEC) # OpBranchConditional: if(tmp926) then branch to lb927, else branch to lb928 # CF Block: Cond Branch: true: lb927, false: lb928 S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 3 lb928 # lb927 Label: lb927 # OpBranch: to lb902 S_ANDN2_B64 sDst(SGPR190) src0(SGPR190) src1(EXEC) S_ANDN2_B64 sDst(SGPR192) src0(SGPR192) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR192) src1(EXEC) # lb928 Label: lb928 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR192) # 930: OpLoad: Float: tmp930 << max_t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR185) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 931: OpFAdd: Float: tmp931 << tmp930, const637 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3a83126f V_ADD_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 932: OpLoad: Float: tmp932 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR184) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) # 934: OpFAdd: Float: tmp934 << tmp932, de(vf3; V_ADD_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR215) // VOP2 # 935: OpExtInst(FMin): Float: tmp935 << tmp931, tmp934 V_MIN_F32 vDst(VGPR332) src0(VGPR334) src1(VGPR333) // VOP2 # OpStore: : tmp935 >> t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR184) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR332) # OpBranch: to lb903 # lb903 Label: lb903 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR190) # 936: OpLoad: Int: tmp936 << i Decorators: RelaxedPrecision # 937: OpIAdd: Int: tmp937 << tmp936, const285 Decorators: RelaxedPrecision S_MOV_B32 sDst(SGPR241) src0(1_INT) S_ADD_I32 sDst(SGPR242) src0(SGPR240) src1(SGPR241) # OpStore: : tmp937 >> i S_MOV_B32 sDst(SGPR240) src0(SGPR242) # OpBranch: to lb900 S_BRANCH -101 lb900Loop # lb902 Label: lb902 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR188) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR186) # 939: OpLoad: FloatVector3: tmp939 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR182) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) # 940: OpLoad: FloatVector3: tmp940 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR183) const: 0x0 V_MOVRELS_B32 vDst(VGPR335) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR336) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR337) src0(VGPR2) # 941: OpLoad: Float: tmp941 << t S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR184) const: 0x0 V_MOVRELS_B32 vDst(VGPR338) src0(VGPR0) # 942: OpVectorTimesScalar: FloatVector3: tmp942 << tmp940, tmp941 V_MUL_F32 vDst(VGPR339) src0(VGPR338) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR338) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR341) src0(VGPR338) src1(VGPR337) // VOP2 # 943: OpFAdd: FloatVector3: tmp943 << tmp939, tmp942 V_ADD_F32 vDst(VGPR216) src0(VGPR332) src1(VGPR339) // VOP2 V_ADD_F32 vDst(VGPR217) src0(VGPR333) src1(VGPR340) // VOP2 V_ADD_F32 vDst(VGPR218) src0(VGPR334) src1(VGPR341) // VOP2 # OpStore: : const946 >> col S_MOV_B32 sDst(SGPR243) src0(LITERAL_CONST) const: 0x3ca3d70a S_MOV_B32 sDst(SGPR244) src0(LITERAL_CONST) const: 0x3c23d70a S_MOV_B32 sDst(SGPR245) src0(LITERAL_CONST) const: 0x3ba3d70a V_MOV_B32 vDst(VGPR188) src0(SGPR243) V_MOV_B32 vDst(VGPR189) src0(SGPR244) V_MOV_B32 vDst(VGPR190) src0(SGPR245) # OpStore: : tmp943 >> param949 V_MOV_B32 vDst(VGPR191) src0(VGPR216) V_MOV_B32 vDst(VGPR192) src0(VGPR217) V_MOV_B32 vDst(VGPR193) src0(VGPR218) # 951: OpFunctionCall: Float: de(vf3;(param949) S_ADD_U32 sDst(SGPR146) src0(LITERAL_CONST) src1(0) const: 0xbf # VGPR[1004:1006] S_MOV_B64 sDst(SGPR196) src0(EXEC) S_MOV_B32 sDst(SGPR133) src0(LITERAL_CONST) const: 0xdb # VGPR1077 # Indirect branch to de(vf3;: -4584 S_GETPC_B64 sDst(SGPR144) src0(SGPR144) S_SUB_U32 sDst(SGPR144) src0(SGPR144) src1(LITERAL_CONST) const: 0x11e8 S_SUBB_U32 sDst(SGPR145) src0(SGPR145) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR144) src0(SGPR144) S_MOV_B64 sDst(EXEC) src0(SGPR196) # .lbl86 # 955: OpCompositeConstruct: FloatVector3: tmp955 << const637, const100, const100 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR332) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR333) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR334) src0(SGPR241) # 956: OpFAdd: FloatVector3: tmp956 << tmp943, tmp955 V_ADD_F32 vDst(VGPR335) src0(VGPR216) src1(VGPR332) // VOP2 V_ADD_F32 vDst(VGPR336) src0(VGPR217) src1(VGPR333) // VOP2 V_ADD_F32 vDst(VGPR337) src0(VGPR218) src1(VGPR334) // VOP2 # OpStore: : tmp956 >> param957 V_MOV_B32 vDst(VGPR194) src0(VGPR335) V_MOV_B32 vDst(VGPR195) src0(VGPR336) V_MOV_B32 vDst(VGPR196) src0(VGPR337) # 958: OpFunctionCall: Float: de(vf3;(param957) S_ADD_U32 sDst(SGPR146) src0(LITERAL_CONST) src1(0) const: 0xc2 # VGPR[1007:1009] S_MOV_B64 sDst(SGPR198) src0(EXEC) S_MOV_B32 sDst(SGPR133) src0(LITERAL_CONST) const: 0xdc # VGPR1087 # Indirect branch to de(vf3;: -4692 S_GETPC_B64 sDst(SGPR144) src0(SGPR144) S_SUB_U32 sDst(SGPR144) src0(SGPR144) src1(LITERAL_CONST) const: 0x1254 S_SUBB_U32 sDst(SGPR145) src0(SGPR145) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR144) src0(SGPR144) S_MOV_B64 sDst(EXEC) src0(SGPR198) # .lbl87 # 960: OpFSub: Float: tmp960 << de(vf3;, de(vf3; V_SUB_F32 vDst(VGPR221) src0(VGPR220) src1(VGPR219) // VOP2 # 963: OpCompositeConstruct: FloatVector3: tmp963 << const100, const637, const100 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR332) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR333) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR334) src0(SGPR241) # 964: OpFAdd: FloatVector3: tmp964 << tmp943, tmp963 V_ADD_F32 vDst(VGPR335) src0(VGPR216) src1(VGPR332) // VOP2 V_ADD_F32 vDst(VGPR336) src0(VGPR217) src1(VGPR333) // VOP2 V_ADD_F32 vDst(VGPR337) src0(VGPR218) src1(VGPR334) // VOP2 # OpStore: : tmp964 >> param965 V_MOV_B32 vDst(VGPR197) src0(VGPR335) V_MOV_B32 vDst(VGPR198) src0(VGPR336) V_MOV_B32 vDst(VGPR199) src0(VGPR337) # 966: OpFunctionCall: Float: de(vf3;(param965) S_ADD_U32 sDst(SGPR146) src0(LITERAL_CONST) src1(0) const: 0xc5 # VGPR[1010:1012] S_MOV_B64 sDst(SGPR200) src0(EXEC) S_MOV_B32 sDst(SGPR133) src0(LITERAL_CONST) const: 0xde # VGPR1098 # Indirect branch to de(vf3;: -4804 S_GETPC_B64 sDst(SGPR144) src0(SGPR144) S_SUB_U32 sDst(SGPR144) src0(SGPR144) src1(LITERAL_CONST) const: 0x12c4 S_SUBB_U32 sDst(SGPR145) src0(SGPR145) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR144) src0(SGPR144) S_MOV_B64 sDst(EXEC) src0(SGPR200) # .lbl88 # 968: OpFSub: Float: tmp968 << de(vf3;, de(vf3; V_SUB_F32 vDst(VGPR223) src0(VGPR222) src1(VGPR219) // VOP2 # 971: OpCompositeConstruct: FloatVector3: tmp971 << const100, const100, const637 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR332) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR333) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR334) src0(SGPR241) # 972: OpFAdd: FloatVector3: tmp972 << tmp943, tmp971 V_ADD_F32 vDst(VGPR335) src0(VGPR216) src1(VGPR332) // VOP2 V_ADD_F32 vDst(VGPR336) src0(VGPR217) src1(VGPR333) // VOP2 V_ADD_F32 vDst(VGPR337) src0(VGPR218) src1(VGPR334) // VOP2 # OpStore: : tmp972 >> param973 V_MOV_B32 vDst(VGPR200) src0(VGPR335) V_MOV_B32 vDst(VGPR201) src0(VGPR336) V_MOV_B32 vDst(VGPR202) src0(VGPR337) # 974: OpFunctionCall: Float: de(vf3;(param973) S_ADD_U32 sDst(SGPR146) src0(LITERAL_CONST) src1(0) const: 0xc8 # VGPR[1013:1015] S_MOV_B64 sDst(SGPR202) src0(EXEC) S_MOV_B32 sDst(SGPR133) src0(LITERAL_CONST) const: 0xe0 # VGPR1109 # Indirect branch to de(vf3;: -4916 S_GETPC_B64 sDst(SGPR144) src0(SGPR144) S_SUB_U32 sDst(SGPR144) src0(SGPR144) src1(LITERAL_CONST) const: 0x1334 S_SUBB_U32 sDst(SGPR145) src0(SGPR145) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR144) src0(SGPR144) S_MOV_B64 sDst(EXEC) src0(SGPR202) # .lbl89 # 976: OpFSub: Float: tmp976 << de(vf3;, de(vf3; V_SUB_F32 vDst(VGPR332) src0(VGPR224) src1(VGPR219) // VOP2 # 977: OpCompositeConstruct: FloatVector3: tmp977 << tmp960, tmp968, tmp976 V_MOV_B32 vDst(VGPR333) src0(VGPR221) V_MOV_B32 vDst(VGPR334) src0(VGPR223) V_MOV_B32 vDst(VGPR335) src0(VGPR332) # 978: OpExtInst(Normalize): FloatVector3: tmp978 << tmp977 V_MUL_F32 vDst(VGPR332) src0(VGPR333) src1(VGPR333) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR334) src1(VGPR334) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR335) src1(VGPR335) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR332) src0(VGPR332) V_MUL_F32 vDst(VGPR225) src0(VGPR333) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR226) src0(VGPR334) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR227) src0(VGPR335) src1(VGPR332) // VOP2 # 980: OpLoad: FloatVector3: tmp980 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR183) const: 0x0 V_MOVRELS_B32 vDst(VGPR228) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR229) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR230) src0(VGPR2) # 982: OpLoad: FloatVector3: tmp982 << l # 983: OpLoad: FloatVector3: tmp983 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR183) const: 0x0 V_MOVRELS_B32 vDst(VGPR336) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR337) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR338) src0(VGPR2) # 984: OpFSub: FloatVector3: tmp984 << tmp982, tmp983 V_SUB_F32 vDst(VGPR332) src0(VGPR27) src1(VGPR336) // VOP2 V_SUB_F32 vDst(VGPR333) src0(VGPR28) src1(VGPR337) // VOP2 V_SUB_F32 vDst(VGPR334) src0(VGPR29) src1(VGPR338) // VOP2 # 985: OpExtInst(Normalize): FloatVector3: tmp985 << tmp984 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR332) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR333) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR334) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR335) src0(VGPR335) V_MUL_F32 vDst(VGPR231) src0(VGPR332) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR232) src0(VGPR333) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR233) src0(VGPR334) src1(VGPR335) // VOP2 # 986: OpLoad: Float: tmp986 << is_choc # 987: OpFOrdLessThan: Bool: tmp987 << tmp986, const303 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_CMP_LT_F32 dst(SGPR246) src0(VGPR25) src1(VGPR332) // VOP3a # OpSelectionMerge: (merge: lb989) # CF Block: Merge: lb989 S_MOV_B64 sDst(SGPR204) src0(EXEC) # OpBranchConditional: if(tmp987) then branch to lb988, else branch to lb1078 # CF Block: Cond Branch: true: lb988, false: lb1078 S_AND_B64 sDst(EXEC) src0(SGPR246) src1(EXEC) S_CBRANCH_EXECZ 324 lb1078 # lb988 Label: lb988 # 990: OpAccessChain: Float*: rp[0] # 991: OpCompositeExtract: Float: tmp991 << tmp943, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR216) # 992: OpFDiv: Float: tmp992 << tmp991, const109 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x40400000 V_RCP_F32 vDst(VGPR334) src0(VGPR333) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR334) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR334) src0(VGPR334) src1(VGPR333) src2(VGPR332) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 993: OpExtInst(Floor): Float: tmp993 << tmp992 V_FLOOR_F32 vDst(VGPR332) src0(VGPR334) # 994: OpFMod: Float: tmp994 << tmp993, const127 V_MOV_B32 vDst(VGPR333) src0(2_0_F) V_RCP_F32 vDst(VGPR334) src0(VGPR333) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR334) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR334) src0(VGPR334) src1(VGPR333) src2(VGPR332) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR334) src0(VGPR334) V_MAD_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR334) src2(VGPR332) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 995: OpFOrdGreaterThan: Bool: tmp995 << tmp994, const303 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_CMP_GT_F32 dst(SGPR242) src0(VGPR334) src1(VGPR332) // VOP3a # OpSelectionMerge: (merge: lb997) # CF Block: Merge: lb997 S_MOV_B64 sDst(SGPR206) src0(EXEC) # OpBranchConditional: if(tmp995) then branch to lb996, else branch to lb1034 # CF Block: Cond Branch: true: lb996, false: lb1034 S_AND_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_CBRANCH_EXECZ 140 lb1034 # lb996 Label: lb996 # 1000: OpVectorShuffle: FloatVector2: tmp1000 << tmp943, tmp943, 0, 2 V_MOV_B32 vDst(VGPR332) src0(VGPR216) V_MOV_B32 vDst(VGPR333) src0(VGPR218) # 1002: OpVectorShuffle: FloatVector2: tmp1002 << tmp943, tmp943, 0, 2 V_MOV_B32 vDst(VGPR334) src0(VGPR216) V_MOV_B32 vDst(VGPR335) src0(VGPR218) # 1003: OpCompositeConstruct: FloatVector2: tmp1003 << const109, const109 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR336) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR337) src0(SGPR241) # 1004: OpFDiv: FloatVector2: tmp1004 << tmp1002, tmp1003 V_RCP_F32 vDst(VGPR338) src0(VGPR336) V_RCP_F32 vDst(VGPR339) src0(VGPR337) V_MUL_F32 vDst(VGPR338) src0(VGPR334) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR335) src1(VGPR339) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR338) src0(VGPR338) src1(VGPR336) src2(VGPR334) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR339) src0(VGPR339) src1(VGPR337) src2(VGPR335) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1005: OpExtInst(Floor): FloatVector2: tmp1005 << tmp1004 V_FLOOR_F32 vDst(VGPR334) src0(VGPR338) V_FLOOR_F32 vDst(VGPR335) src0(VGPR339) # 1006: OpVectorTimesScalar: FloatVector2: tmp1006 << tmp1005, const109 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR337) src0(VGPR336) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR336) src1(VGPR335) // VOP2 # 1007: OpFAdd: FloatVector2: tmp1007 << tmp1006, const667 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3fc00000 V_ADD_F32 vDst(VGPR339) src0(VGPR337) src1(VGPR334) // VOP2 V_ADD_F32 vDst(VGPR340) src0(VGPR338) src1(VGPR335) // VOP2 # 1008: OpExtInst(Distance): Float: tmp1008 << tmp1000, tmp1007 V_SUB_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR339) // VOP2 V_SUB_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR340) // VOP2 V_MUL_F32 vDst(VGPR332) src0(VGPR334) src1(VGPR334) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR335) src1(VGPR335) // VOP2 V_SQRT_F32 vDst(VGPR332) src0(VGPR332) # 1009: OpFMul: Float: tmp1009 << tmp1008, const704 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 1010: OpExtInst(Pow): Float: tmp1010 << tmp1009, const127 V_MOV_B32 vDst(VGPR332) src0(2_0_F) V_LOG_F32 vDst(VGPR333) src0(VGPR334) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR333) // VOP2 V_EXP_F32 vDst(VGPR333) src0(VGPR333) # 1019: OpFAdd: Float: tmp1019 << const303, tmp1010 V_ADD_F32 vDst(VGPR234) src0(0_5_F) src1(VGPR333) // VOP2 # 1021: OpFAdd: Float: tmp1021 << const704, tmp1010 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f19999a V_ADD_F32 vDst(VGPR235) src0(VGPR332) src1(VGPR333) // VOP2 # 1023: OpVectorShuffle: FloatVector2: tmp1023 << tmp943, tmp943, 0, 2 V_MOV_B32 vDst(VGPR334) src0(VGPR216) V_MOV_B32 vDst(VGPR335) src0(VGPR218) # 1024: OpVectorTimesScalar: FloatVector2: tmp1024 << tmp1023, const621 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR335) // VOP2 # 1025: OpCompositeExtract: Float: tmp1025 << tmp1024, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR336) # 1026: OpCompositeExtract: Float: tmp1026 << tmp1024, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR337) # 1027: OpCompositeConstruct: FloatVector3: tmp1027 << tmp1025, tmp1026, const100 V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR333) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR336) src0(SGPR241) # OpStore: : tmp1027 >> param1028 V_MOV_B32 vDst(VGPR203) src0(VGPR334) V_MOV_B32 vDst(VGPR204) src0(VGPR335) V_MOV_B32 vDst(VGPR205) src0(VGPR336) # 1029: OpFunctionCall: Float: fbm3(vf3;(param1028) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0xcb # VGPR[1019:1021] S_MOV_B64 sDst(SGPR208) src0(EXEC) S_MOV_B32 sDst(SGPR57) src0(LITERAL_CONST) const: 0xec # VGPR1179 # Indirect branch to fbm3(vf3;: -9004 S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_SUB_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x232c S_SUBB_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR208) # .lbl90 # 1030: OpFAdd: Float: tmp1030 << const748, fbm3(vf3; V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3ecccccd V_ADD_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR236) // VOP2 # 1031: OpExtInst(SmoothStep): Float: tmp1031 << tmp1019, tmp1021, tmp1030 V_CMP_GE_F32 src0(VGPR234) src1(VGPR333) # CF Block: Merge: .lbl94 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl95, false: .lbl91 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl91 Label: .lbl95 V_MOV_B32 vDst(VGPR332) src0(0) Label: .lbl91 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR186) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl94 V_CMP_LE_F32 src0(VGPR235) src1(VGPR333) # CF Block: Merge: .lbl93 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl96, false: .lbl92 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl92 Label: .lbl96 V_MOV_B32 vDst(VGPR332) src0(1_0_F) Label: .lbl92 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR186) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl93 V_SUBREV_F32 vDst(VGPR334) src0(VGPR234) src1(VGPR235) // VOP2 V_RCP_F32 vDst(VGPR334) src0(VGPR334) V_SUBREV_F32 vDst(VGPR332) src0(VGPR234) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR334) // VOP2 V_MAX_F32 vDst(VGPR334) src0(0) src1(VGPR334) // VOP2 V_MIN_F32 vDst(VGPR334) src0(1_0_F) src1(VGPR334) // VOP2 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR332) src0(2_0_F) src1(VGPR334) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR334) src0(VGPR334) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR332) src0(VGPR334) src1(VGPR332) // VOP2 Label: .lbl93 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR186) Label: .lbl94 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR186) # 1032: OpCompositeConstruct: FloatVector3: tmp1032 << tmp1031, tmp1031, tmp1031 V_MOV_B32 vDst(VGPR335) src0(VGPR332) V_MOV_B32 vDst(VGPR336) src0(VGPR332) V_MOV_B32 vDst(VGPR337) src0(VGPR332) # 1033: OpExtInst(FMix): FloatVector3: tmp1033 << const1013, const1017, tmp1032 V_MOV_B32 vDst(VGPR338) src0(4_0_F) V_MOV_B32 vDst(VGPR339) src0(4_0_F) V_MOV_B32 vDst(VGPR340) src0(LITERAL_CONST) const: 0x40266666 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f47ae14 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3eb851ec V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3df5c28f V_SUBREV_F32 vDst(VGPR341) src0(VGPR335) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR341) src0(VGPR338) src1(VGPR341) // VOP2 V_MAD_F32 vDst(VGPR341) src0(VGPR332) src1(VGPR335) src2(VGPR341) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR342) src0(VGPR336) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR342) src0(VGPR339) src1(VGPR342) // VOP2 V_MAD_F32 vDst(VGPR342) src0(VGPR333) src1(VGPR336) src2(VGPR342) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR343) src0(VGPR337) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR343) src0(VGPR340) src1(VGPR343) // VOP2 V_MAD_F32 vDst(VGPR343) src0(VGPR334) src1(VGPR337) src2(VGPR343) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1033 >> chocolour V_MOV_B32 vDst(VGPR332) src0(VGPR341) V_MOV_B32 vDst(VGPR333) src0(VGPR342) V_MOV_B32 vDst(VGPR334) src0(VGPR343) # OpBranch: to lb997 # lb1034 Label: lb1034 S_ANDN2_B64 sDst(EXEC) src0(SGPR206) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR186) src1(EXEC) S_CBRANCH_EXECZ 86 lb997 # 1036: OpAccessChain: Float*: rp[0] # 1037: OpCompositeExtract: Float: tmp1037 << tmp943, 0 V_MOV_B32 vDst(VGPR335) src0(VGPR216) # 1038: OpFMul: Float: tmp1038 << tmp1037, const621 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR337) src0(VGPR335) src1(VGPR336) // VOP2 # 1039: OpAccessChain: Float*: rp[2] # 1040: OpCompositeExtract: Float: tmp1040 << tmp943, 2 V_MOV_B32 vDst(VGPR335) src0(VGPR218) # 1041: OpFMul: Float: tmp1041 << tmp1040, const401 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR338) src0(VGPR335) src1(VGPR336) // VOP2 # 1042: OpExtInst(Sin): Float: tmp1042 << tmp1041 V_MUL_F32 vDst(VGPR335) src0(LITERAL_CONST) src1(VGPR338) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR335) src0(VGPR335) V_SIN_F32 vDst(VGPR335) src0(VGPR335) # 1043: OpFAdd: Float: tmp1043 << tmp1038, tmp1042 V_ADD_F32 vDst(VGPR336) src0(VGPR337) src1(VGPR335) // VOP2 # 1044: OpExtInst(Cos): Float: tmp1044 << tmp1043 V_MUL_F32 vDst(VGPR335) src0(LITERAL_CONST) src1(VGPR336) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR335) src0(VGPR335) V_COS_F32 vDst(VGPR335) src0(VGPR335) # 1045: OpFMul: Float: tmp1045 << const303, tmp1044 V_MUL_F32 vDst(VGPR336) src0(0_5_F) src1(VGPR335) // VOP2 # 1046: OpFAdd: Float: tmp1046 << const303, tmp1045 V_ADD_F32 vDst(VGPR335) src0(0_5_F) src1(VGPR336) // VOP2 # 1047: OpExtInst(SmoothStep): Float: tmp1047 << const671, const435, tmp1046 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x3f666666 V_CMP_GE_F32 src0(VGPR336) src1(VGPR335) # CF Block: Merge: .lbl100 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl101, false: .lbl97 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl97 Label: .lbl101 V_MOV_B32 vDst(VGPR338) src0(0) Label: .lbl97 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR186) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl100 V_CMP_LE_F32 src0(VGPR337) src1(VGPR335) # CF Block: Merge: .lbl99 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl102, false: .lbl98 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl98 Label: .lbl102 V_MOV_B32 vDst(VGPR338) src0(1_0_F) Label: .lbl98 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR186) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl99 V_SUBREV_F32 vDst(VGPR339) src0(VGPR336) src1(VGPR337) // VOP2 V_RCP_F32 vDst(VGPR339) src0(VGPR339) V_SUBREV_F32 vDst(VGPR338) src0(VGPR336) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR338) src1(VGPR339) // VOP2 V_MAX_F32 vDst(VGPR339) src0(0) src1(VGPR339) // VOP2 V_MIN_F32 vDst(VGPR339) src0(1_0_F) src1(VGPR339) // VOP2 V_MOV_B32 vDst(VGPR338) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR338) src0(2_0_F) src1(VGPR339) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR339) src0(VGPR339) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR339) src1(VGPR338) // VOP2 Label: .lbl99 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR186) Label: .lbl100 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR186) # 1048: OpCompositeConstruct: FloatVector3: tmp1048 << tmp1047, tmp1047, tmp1047 V_MOV_B32 vDst(VGPR335) src0(VGPR338) V_MOV_B32 vDst(VGPR336) src0(VGPR338) V_MOV_B32 vDst(VGPR337) src0(VGPR338) # 1049: OpExtInst(FMix): FloatVector3: tmp1049 << const1035, const1013, tmp1048 V_MOV_B32 vDst(VGPR338) src0(LITERAL_CONST) const: 0x3fa66666 V_MOV_B32 vDst(VGPR339) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR340) src0(LITERAL_CONST) const: 0x3e4ccccd V_MOV_B32 vDst(VGPR341) src0(4_0_F) V_MOV_B32 vDst(VGPR342) src0(4_0_F) V_MOV_B32 vDst(VGPR343) src0(LITERAL_CONST) const: 0x40266666 V_SUBREV_F32 vDst(VGPR344) src0(VGPR335) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR344) src0(VGPR338) src1(VGPR344) // VOP2 V_MAD_F32 vDst(VGPR344) src0(VGPR341) src1(VGPR335) src2(VGPR344) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR345) src0(VGPR336) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR345) src0(VGPR339) src1(VGPR345) // VOP2 V_MAD_F32 vDst(VGPR345) src0(VGPR342) src1(VGPR336) src2(VGPR345) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR346) src0(VGPR337) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR346) src0(VGPR340) src1(VGPR346) // VOP2 V_MAD_F32 vDst(VGPR346) src0(VGPR343) src1(VGPR337) src2(VGPR346) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1049 >> chocolour V_MOV_B32 vDst(VGPR332) src0(VGPR344) V_MOV_B32 vDst(VGPR333) src0(VGPR345) V_MOV_B32 vDst(VGPR334) src0(VGPR346) # OpBranch: to lb997 # lb997 Label: lb997 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR206) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR186) # 1050: OpLoad: FloatVector3: tmp1050 << chocolour # 1051: OpVectorTimesScalar: FloatVector3: tmp1051 << tmp1050, const576 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3dcccccd V_MUL_F32 vDst(VGPR336) src0(VGPR335) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR335) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR335) src1(VGPR334) // VOP2 # 1053: OpLoad: FloatVector3: tmp1053 << l # 1054: OpDot: Float: tmp1054 << tmp978, tmp1053 V_MUL_F32 vDst(VGPR332) src0(VGPR225) src1(VGPR27) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR226) src1(VGPR28) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR227) src1(VGPR29) // VOP2 # 1055: OpFMul: Float: tmp1055 << const303, tmp1054 V_MUL_F32 vDst(VGPR333) src0(0_5_F) src1(VGPR332) // VOP2 # 1056: OpFAdd: Float: tmp1056 << const303, tmp1055 V_ADD_F32 vDst(VGPR332) src0(0_5_F) src1(VGPR333) // VOP2 # 1057: OpCompositeConstruct: FloatVector3: tmp1057 << tmp1056, tmp1056, tmp1056 V_MOV_B32 vDst(VGPR333) src0(VGPR332) V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR332) # 1058: OpFMul: FloatVector3: tmp1058 << tmp1051, tmp1057 V_MUL_F32 vDst(VGPR339) src0(VGPR336) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR337) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR341) src0(VGPR338) src1(VGPR335) // VOP2 # 1062: OpDot: Float: tmp1062 << tmp985, tmp978 V_MUL_F32 vDst(VGPR332) src0(VGPR231) src1(VGPR225) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR232) src1(VGPR226) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR233) src1(VGPR227) // VOP2 # 1063: OpFMul: Float: tmp1063 << const303, tmp1062 V_MUL_F32 vDst(VGPR333) src0(0_5_F) src1(VGPR332) // VOP2 # 1064: OpFAdd: Float: tmp1064 << const303, tmp1063 V_ADD_F32 vDst(VGPR332) src0(0_5_F) src1(VGPR333) // VOP2 # 1065: OpExtInst(FClamp): Float: tmp1065 << tmp1064, const100, const106 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR334) src0(1_0_F) V_MAX_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 V_MIN_F32 vDst(VGPR335) src0(VGPR335) src1(VGPR334) // VOP2 # 1066: OpExtInst(Pow): Float: tmp1066 << tmp1065, const863 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x41a00000 V_LOG_F32 vDst(VGPR333) src0(VGPR335) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR333) // VOP2 V_EXP_F32 vDst(VGPR333) src0(VGPR333) # 1067: OpCompositeConstruct: FloatVector3: tmp1067 << tmp1066, tmp1066, tmp1066 V_MOV_B32 vDst(VGPR334) src0(VGPR333) V_MOV_B32 vDst(VGPR335) src0(VGPR333) V_MOV_B32 vDst(VGPR336) src0(VGPR333) # 1068: OpFMul: FloatVector3: tmp1068 << const1059, tmp1067 V_MOV_B32 vDst(VGPR342) src0(LITERAL_CONST) const: 0x3d75c28f V_MOV_B32 vDst(VGPR343) src0(LITERAL_CONST) const: 0x3d75c28f V_MOV_B32 vDst(VGPR344) src0(LITERAL_CONST) const: 0x3cf5c28f V_MUL_F32 vDst(VGPR345) src0(VGPR342) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR346) src0(VGPR343) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR347) src0(VGPR344) src1(VGPR336) // VOP2 # 1069: OpFAdd: FloatVector3: tmp1069 << tmp1058, tmp1068 V_ADD_F32 vDst(VGPR332) src0(VGPR339) src1(VGPR345) // VOP2 V_ADD_F32 vDst(VGPR333) src0(VGPR340) src1(VGPR346) // VOP2 V_ADD_F32 vDst(VGPR334) src0(VGPR341) src1(VGPR347) // VOP2 # 1071: OpLoad: FloatVector3: tmp1071 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR183) const: 0x0 V_MOVRELS_B32 vDst(VGPR335) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR336) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR337) src0(VGPR2) # 1072: OpFNegate: FloatVector3: tmp1072 << tmp1071 V_MUL_F32 vDst(VGPR338) src0(M1_0_F) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR339) src0(M1_0_F) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR340) src0(M1_0_F) src1(VGPR337) // VOP2 # 1073: OpDot: Float: tmp1073 << tmp978, tmp1072 V_MUL_F32 vDst(VGPR335) src0(VGPR225) src1(VGPR338) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR226) src1(VGPR339) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR227) src1(VGPR340) // VOP2 # 1074: OpExtInst(Pow): Float: tmp1074 << tmp1073, const127 V_MOV_B32 vDst(VGPR336) src0(2_0_F) V_LOG_F32 vDst(VGPR337) src0(VGPR335) V_MUL_F32 vDst(VGPR337) src0(VGPR336) src1(VGPR337) // VOP2 V_EXP_F32 vDst(VGPR337) src0(VGPR337) # 1075: OpFMul: Float: tmp1075 << const704, tmp1074 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x3f19999a V_MUL_F32 vDst(VGPR336) src0(VGPR335) src1(VGPR337) // VOP2 # 1076: OpFAdd: Float: tmp1076 << const106, tmp1075 V_ADD_F32 vDst(VGPR335) src0(1_0_F) src1(VGPR336) // VOP2 # 1077: OpVectorTimesScalar: FloatVector3: tmp1077 << tmp1069, tmp1076 V_MUL_F32 vDst(VGPR336) src0(VGPR335) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR335) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR335) src1(VGPR334) // VOP2 # OpStore: : tmp1077 >> col V_MOV_B32 vDst(VGPR188) src0(VGPR336) V_MOV_B32 vDst(VGPR189) src0(VGPR337) V_MOV_B32 vDst(VGPR190) src0(VGPR338) # OpBranch: to lb989 # lb1078 Label: lb1078 S_ANDN2_B64 sDst(EXEC) src0(SGPR204) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR186) src1(EXEC) S_CBRANCH_EXECZ 93 lb989 # OpStore: : tmp978 >> param1079 V_MOV_B32 vDst(VGPR206) src0(VGPR225) V_MOV_B32 vDst(VGPR207) src0(VGPR226) V_MOV_B32 vDst(VGPR208) src0(VGPR227) # OpStore: : tmp943 >> param1081 V_MOV_B32 vDst(VGPR209) src0(VGPR216) V_MOV_B32 vDst(VGPR210) src0(VGPR217) V_MOV_B32 vDst(VGPR211) src0(VGPR218) # OpStore: : tmp980 >> param1083 V_MOV_B32 vDst(VGPR212) src0(VGPR228) V_MOV_B32 vDst(VGPR213) src0(VGPR229) V_MOV_B32 vDst(VGPR214) src0(VGPR230) # 1085: OpFunctionCall: FloatVector3: gummy(vf3;vf3;vf3;(param1079, param1081, param1083) S_ADD_U32 sDst(SGPR130) src0(LITERAL_CONST) src1(0) const: 0xce # VGPR[1022:1024] S_ADD_U32 sDst(SGPR131) src0(LITERAL_CONST) src1(0) const: 0xd1 # VGPR[1025:1027] S_ADD_U32 sDst(SGPR132) src0(LITERAL_CONST) src1(0) const: 0xd4 # VGPR[1028:1030] S_MOV_B64 sDst(SGPR210) src0(EXEC) S_MOV_B32 sDst(SGPR123) src0(LITERAL_CONST) const: 0xed # VGPR[1271:1273] # Indirect branch to gummy(vf3;vf3;vf3;: -7860 S_GETPC_B64 sDst(SGPR128) src0(SGPR128) S_SUB_U32 sDst(SGPR128) src0(SGPR128) src1(LITERAL_CONST) const: 0x1eb4 S_SUBB_U32 sDst(SGPR129) src0(SGPR129) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR128) src0(SGPR128) S_MOV_B64 sDst(EXEC) src0(SGPR210) # .lbl103 # 1086: OpVectorTimesScalar: FloatVector3: tmp1086 << gummy(vf3;vf3;vf3;, const401 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR237) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR238) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR239) // VOP2 # 1089: OpDot: Float: tmp1089 << tmp985, tmp978 V_MUL_F32 vDst(VGPR332) src0(VGPR231) src1(VGPR225) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR232) src1(VGPR226) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR233) src1(VGPR227) // VOP2 # 1090: OpFMul: Float: tmp1090 << const303, tmp1089 V_MUL_F32 vDst(VGPR336) src0(0_5_F) src1(VGPR332) // VOP2 # 1091: OpFAdd: Float: tmp1091 << const303, tmp1090 V_ADD_F32 vDst(VGPR332) src0(0_5_F) src1(VGPR336) // VOP2 # 1092: OpExtInst(FClamp): Float: tmp1092 << tmp1091, const100, const106 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR337) src0(1_0_F) V_MAX_F32 vDst(VGPR338) src0(VGPR332) src1(VGPR336) // VOP2 V_MIN_F32 vDst(VGPR338) src0(VGPR338) src1(VGPR337) // VOP2 # 1094: OpExtInst(Pow): Float: tmp1094 << tmp1092, const1093 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x43800000 V_LOG_F32 vDst(VGPR336) src0(VGPR338) V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR336) // VOP2 V_EXP_F32 vDst(VGPR336) src0(VGPR336) # 1095: OpExtInst(SmoothStep): Float: tmp1095 << const303, const704, tmp1094 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f19999a V_CMP_GE_F32 src0(0_5_F) src1(VGPR336) # CF Block: Merge: .lbl107 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl108, false: .lbl104 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl104 Label: .lbl108 V_MOV_B32 vDst(VGPR337) src0(0) Label: .lbl104 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR186) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl107 V_CMP_LE_F32 src0(VGPR332) src1(VGPR336) # CF Block: Merge: .lbl106 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl109, false: .lbl105 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl105 Label: .lbl109 V_MOV_B32 vDst(VGPR337) src0(1_0_F) Label: .lbl105 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR186) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl106 V_SUBREV_F32 vDst(VGPR338) src0(0_5_F) src1(VGPR332) // VOP2 V_RCP_F32 vDst(VGPR338) src0(VGPR338) V_SUBREV_F32 vDst(VGPR337) src0(0_5_F) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR337) src1(VGPR338) // VOP2 V_MAX_F32 vDst(VGPR338) src0(0) src1(VGPR338) // VOP2 V_MIN_F32 vDst(VGPR338) src0(1_0_F) src1(VGPR338) // VOP2 V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR337) src0(2_0_F) src1(VGPR338) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR338) src0(VGPR338) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR338) src1(VGPR337) // VOP2 Label: .lbl106 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR186) Label: .lbl107 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR186) # 1096: OpCompositeConstruct: FloatVector3: tmp1096 << tmp1095, tmp1095, tmp1095 V_MOV_B32 vDst(VGPR338) src0(VGPR337) V_MOV_B32 vDst(VGPR339) src0(VGPR337) V_MOV_B32 vDst(VGPR340) src0(VGPR337) # 1097: OpVectorTimesScalar: FloatVector3: tmp1097 << tmp1096, const576 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3dcccccd V_MUL_F32 vDst(VGPR341) src0(VGPR332) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR342) src0(VGPR332) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR343) src0(VGPR332) src1(VGPR340) // VOP2 # 1098: OpFAdd: FloatVector3: tmp1098 << tmp1086, tmp1097 V_ADD_F32 vDst(VGPR336) src0(VGPR333) src1(VGPR341) // VOP2 V_ADD_F32 vDst(VGPR337) src0(VGPR334) src1(VGPR342) // VOP2 V_ADD_F32 vDst(VGPR338) src0(VGPR335) src1(VGPR343) // VOP2 # OpStore: : tmp1098 >> col V_MOV_B32 vDst(VGPR188) src0(VGPR336) V_MOV_B32 vDst(VGPR189) src0(VGPR337) V_MOV_B32 vDst(VGPR190) src0(VGPR338) # OpBranch: to lb989 # lb989 Label: lb989 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR204) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR186) # 1099: OpAccessChain: Float*: rp[1] # 1100: OpCompositeExtract: Float: tmp1100 << tmp943, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR217) # 1101: OpExtInst(FMax): Float: tmp1101 << const100, tmp1100 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) // VOP2 # 1102: OpExtInst(Pow): Float: tmp1102 << tmp1101, const303 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_LOG_F32 vDst(VGPR333) src0(VGPR334) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR333) // VOP2 V_EXP_F32 vDst(VGPR333) src0(VGPR333) # 1103: OpExtInst(FMix): Float: tmp1103 << const106, tmp1102, const704 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f19999a V_SUBREV_F32 vDst(VGPR334) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR334) src0(1_0_F) src1(VGPR334) // VOP2 V_MAD_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) src2(VGPR334) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1104: OpLoad: FloatVector3: tmp1104 << col # 1105: OpVectorTimesScalar: FloatVector3: tmp1105 << tmp1104, tmp1103 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR188) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR189) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR334) src1(VGPR190) // VOP2 # OpStore: : tmp1105 >> col V_MOV_B32 vDst(VGPR188) src0(VGPR335) V_MOV_B32 vDst(VGPR189) src0(VGPR336) V_MOV_B32 vDst(VGPR190) src0(VGPR337) # 1106: OpLoad: FloatVector3: tmp1106 << col # OpReturnValue: : << tmp1106 S_MOV_B32 sDst(M0) src0(SGPR179) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR188) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR189) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR190) S_SETPC_B64 sDst(SGPR180) src0(SGPR180) # Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) Function: Void mainImage(vf4;vf2;(, FloatVector2 main.fragCoord) S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb97 Label: lb97 # 1111: OpLoad: Float: tmp1111 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR241) S_WAITCNT 0 # OpStore: : tmp1111 >> time V_MOV_B32 vDst(VGPR22) src0(SGPR241) # 1112: OpLoad: FloatVector2: tmp1112 << fragCoord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) # 1115: OpLoad: FloatVector3: tmp1115 << iResolution S_LOAD_DWORDX2_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR[246:247]) S_WAITCNT 0 S_LOAD_DWORD_IMM offset(12) sBase(SGPR[0:1]) sDst(SGPR248) S_WAITCNT 0 # 1116: OpVectorShuffle: FloatVector2: tmp1116 << tmp1115, tmp1115, 0, 1 V_MOV_B32 vDst(VGPR334) src0(SGPR246) V_MOV_B32 vDst(VGPR335) src0(SGPR247) # 1117: OpFDiv: FloatVector2: tmp1117 << tmp1112, tmp1116 V_RCP_F32 vDst(VGPR336) src0(VGPR334) V_RCP_F32 vDst(VGPR337) src0(VGPR335) V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR333) src1(VGPR337) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR336) src0(VGPR336) src1(VGPR334) src2(VGPR332) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR337) src0(VGPR337) src1(VGPR335) src2(VGPR333) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1118: OpVectorTimesScalar: FloatVector2: tmp1118 << tmp1117, const127 V_MOV_B32 vDst(VGPR332) src0(2_0_F) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR336) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR337) // VOP2 # 1119: OpFSub: FloatVector2: tmp1119 << tmp1118, const342 V_MOV_B32 vDst(VGPR335) src0(1_0_F) V_MOV_B32 vDst(VGPR336) src0(1_0_F) V_SUB_F32 vDst(VGPR337) src0(VGPR333) src1(VGPR335) // VOP2 V_SUB_F32 vDst(VGPR338) src0(VGPR334) src1(VGPR336) // VOP2 # OpStore: : tmp1119 >> tc V_MOV_B32 vDst(VGPR20) src0(VGPR337) V_MOV_B32 vDst(VGPR21) src0(VGPR338) # 1121: OpLoad: Float: tmp1121 << time # 1122: OpLoad: Float: tmp1122 << t_per_target # 1123: OpFDiv: Float: tmp1123 << tmp1121, tmp1122 V_RCP_F32 vDst(VGPR332) src0(VGPR26) V_MUL_F32 vDst(VGPR332) src0(VGPR22) src1(VGPR332) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR332) src0(VGPR332) src1(VGPR26) src2(VGPR22) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1124: OpExtInst(Floor): Float: tmp1124 << tmp1123 V_FLOOR_F32 vDst(VGPR278) src0(VGPR332) # 1126: OpLoad: Float: tmp1126 << time # 1127: OpLoad: Float: tmp1127 << t_per_target # 1128: OpFDiv: Float: tmp1128 << tmp1126, tmp1127 V_RCP_F32 vDst(VGPR332) src0(VGPR26) V_MUL_F32 vDst(VGPR332) src0(VGPR22) src1(VGPR332) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR332) src0(VGPR332) src1(VGPR26) src2(VGPR22) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1129: OpExtInst(Fract): Float: tmp1129 << tmp1128 V_FRACT_F32 vDst(VGPR279) src0(VGPR332) # 1132: OpLoad: Float: tmp1132 << time # OpStore: : tmp1132 >> param1131 V_MOV_B32 vDst(VGPR240) src0(VGPR22) # 1133: OpFunctionCall: FloatVector3: cameraPos(f1;(param1131) S_ADD_U32 sDst(SGPR168) src0(LITERAL_CONST) src1(0) const: 0xf0 # VGPR1309 S_MOV_B64 sDst(SGPR214) src0(EXEC) S_MOV_B32 sDst(SGPR155) src0(LITERAL_CONST) const: 0x118 # VGPR[1367:1369] # Indirect branch to cameraPos(f1;: -3736 S_GETPC_B64 sDst(SGPR166) src0(SGPR166) S_SUB_U32 sDst(SGPR166) src0(SGPR166) src1(LITERAL_CONST) const: 0xe98 S_SUBB_U32 sDst(SGPR167) src0(SGPR167) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR166) src0(SGPR166) S_MOV_B64 sDst(EXEC) src0(SGPR214) # .lbl110 # 1136: OpFSub: Float: tmp1136 << tmp1124, const106 V_MOV_B32 vDst(VGPR332) src0(1_0_F) V_SUB_F32 vDst(VGPR333) src0(VGPR278) src1(VGPR332) // VOP2 # OpStore: : tmp1136 >> param1137 V_MOV_B32 vDst(VGPR241) src0(VGPR333) # 1138: OpFunctionCall: FloatVector3: targetPos(f1;(param1137) S_ADD_U32 sDst(SGPR172) src0(LITERAL_CONST) src1(0) const: 0xf1 # VGPR1310 S_MOV_B64 sDst(SGPR216) src0(EXEC) S_MOV_B32 sDst(SGPR169) src0(LITERAL_CONST) const: 0x11b # VGPR[1372:1374] # Indirect branch to targetPos(f1;: -3668 S_GETPC_B64 sDst(SGPR170) src0(SGPR170) S_SUB_U32 sDst(SGPR170) src0(SGPR170) src1(LITERAL_CONST) const: 0xe54 S_SUBB_U32 sDst(SGPR171) src0(SGPR171) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR170) src0(SGPR170) S_MOV_B64 sDst(EXEC) src0(SGPR216) # .lbl111 # OpStore: : tmp1124 >> param1139 V_MOV_B32 vDst(VGPR242) src0(VGPR278) # 1141: OpFunctionCall: FloatVector3: targetPos(f1;(param1139) S_ADD_U32 sDst(SGPR172) src0(LITERAL_CONST) src1(0) const: 0xf2 # VGPR1311 S_MOV_B64 sDst(SGPR218) src0(EXEC) S_MOV_B32 sDst(SGPR169) src0(LITERAL_CONST) const: 0x11e # VGPR[1375:1377] # Indirect branch to targetPos(f1;: -3720 S_GETPC_B64 sDst(SGPR170) src0(SGPR170) S_SUB_U32 sDst(SGPR170) src0(SGPR170) src1(LITERAL_CONST) const: 0xe88 S_SUBB_U32 sDst(SGPR171) src0(SGPR171) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR170) src0(SGPR170) S_MOV_B64 sDst(EXEC) src0(SGPR218) # .lbl112 # 1143: OpExtInst(SmoothStep): Float: tmp1143 << const523, const671, tmp1129 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3e99999a V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3f333333 V_CMP_GE_F32 src0(VGPR332) src1(VGPR279) # CF Block: Merge: .lbl116 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl117, false: .lbl113 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl113 Label: .lbl117 V_MOV_B32 vDst(VGPR334) src0(0) Label: .lbl113 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl116 V_CMP_LE_F32 src0(VGPR333) src1(VGPR279) # CF Block: Merge: .lbl115 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl118, false: .lbl114 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl114 Label: .lbl118 V_MOV_B32 vDst(VGPR334) src0(1_0_F) Label: .lbl114 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl115 V_SUBREV_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 V_RCP_F32 vDst(VGPR335) src0(VGPR335) V_SUBREV_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR279) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR335) // VOP2 V_MAX_F32 vDst(VGPR335) src0(0) src1(VGPR335) // VOP2 V_MIN_F32 vDst(VGPR335) src0(1_0_F) src1(VGPR335) // VOP2 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR334) src0(2_0_F) src1(VGPR335) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR335) src0(VGPR335) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR335) src1(VGPR334) // VOP2 Label: .lbl115 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) Label: .lbl116 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) # 1144: OpCompositeConstruct: FloatVector3: tmp1144 << tmp1143, tmp1143, tmp1143 V_MOV_B32 vDst(VGPR335) src0(VGPR334) V_MOV_B32 vDst(VGPR336) src0(VGPR334) V_MOV_B32 vDst(VGPR337) src0(VGPR334) # 1145: OpExtInst(FMix): FloatVector3: tmp1145 << targetPos(f1;, targetPos(f1;, tmp1144 V_SUBREV_F32 vDst(VGPR332) src0(VGPR335) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR332) src0(VGPR283) src1(VGPR332) // VOP2 V_MAD_F32 vDst(VGPR332) src0(VGPR286) src1(VGPR335) src2(VGPR332) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR333) src0(VGPR336) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR333) src0(VGPR284) src1(VGPR333) // VOP2 V_MAD_F32 vDst(VGPR333) src0(VGPR287) src1(VGPR336) src2(VGPR333) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR334) src0(VGPR337) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR334) src0(VGPR285) src1(VGPR334) // VOP2 V_MAD_F32 vDst(VGPR334) src0(VGPR288) src1(VGPR337) src2(VGPR334) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1149: OpFSub: FloatVector3: tmp1149 << tmp1145, cameraPos(f1; V_SUB_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR280) // VOP2 V_SUB_F32 vDst(VGPR336) src0(VGPR333) src1(VGPR281) // VOP2 V_SUB_F32 vDst(VGPR337) src0(VGPR334) src1(VGPR282) // VOP2 # 1150: OpExtInst(Normalize): FloatVector3: tmp1150 << tmp1149 V_MUL_F32 vDst(VGPR332) src0(VGPR335) src1(VGPR335) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR336) src1(VGPR336) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR337) src1(VGPR337) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR332) src0(VGPR332) V_MUL_F32 vDst(VGPR338) src0(VGPR335) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR336) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR337) src1(VGPR332) // VOP2 # 1154: OpExtInst(Cross): FloatVector3: tmp1154 << tmp1150, const1153 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR333) src0(1_0_F) V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x00000000 V_MUL_F32 vDst(VGPR335) src0(VGPR339) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR340) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR338) src1(VGPR333) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR340) src1(VGPR333) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR336) src0(VGPR338) src1(VGPR334) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR337) src0(VGPR339) src1(VGPR332) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 1155: OpExtInst(Normalize): FloatVector3: tmp1155 << tmp1154 V_MUL_F32 vDst(VGPR332) src0(VGPR335) src1(VGPR335) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR336) src1(VGPR336) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR337) src1(VGPR337) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR332) src0(VGPR332) V_MUL_F32 vDst(VGPR341) src0(VGPR335) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR342) src0(VGPR336) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR343) src0(VGPR337) src1(VGPR332) // VOP2 # OpStore: : tmp1155 >> camu V_MOV_B32 vDst(VGPR332) src0(VGPR341) V_MOV_B32 vDst(VGPR333) src0(VGPR342) V_MOV_B32 vDst(VGPR334) src0(VGPR343) # 1157: OpLoad: FloatVector3: tmp1157 << camu # 1159: OpExtInst(Cross): FloatVector3: tmp1159 << tmp1157, tmp1150 V_MUL_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR340) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR339) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR339) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR340) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR337) src0(VGPR333) src1(VGPR338) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 1160: OpExtInst(Normalize): FloatVector3: tmp1160 << tmp1159 V_MUL_F32 vDst(VGPR341) src0(VGPR335) src1(VGPR335) // VOP2 V_MAC_F32 vDst(VGPR341) src0(VGPR336) src1(VGPR336) // VOP2 V_MAC_F32 vDst(VGPR341) src0(VGPR337) src1(VGPR337) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR341) src0(VGPR341) V_MUL_F32 vDst(VGPR342) src0(VGPR335) src1(VGPR341) // VOP2 V_MUL_F32 vDst(VGPR343) src0(VGPR336) src1(VGPR341) // VOP2 V_MUL_F32 vDst(VGPR344) src0(VGPR337) src1(VGPR341) // VOP2 # 1163: OpExtInst(Cross): FloatVector3: tmp1163 << tmp1150, tmp1160 V_MUL_F32 vDst(VGPR335) src0(VGPR339) src1(VGPR344) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR340) src1(VGPR342) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR338) src1(VGPR343) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR340) src1(VGPR343) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR336) src0(VGPR338) src1(VGPR344) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAC_F32 vDst(VGPR337) src0(VGPR339) src1(VGPR342) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 1164: OpExtInst(Normalize): FloatVector3: tmp1164 << tmp1163 V_MUL_F32 vDst(VGPR341) src0(VGPR335) src1(VGPR335) // VOP2 V_MAC_F32 vDst(VGPR341) src0(VGPR336) src1(VGPR336) // VOP2 V_MAC_F32 vDst(VGPR341) src0(VGPR337) src1(VGPR337) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR341) src0(VGPR341) V_MUL_F32 vDst(VGPR345) src0(VGPR335) src1(VGPR341) // VOP2 V_MUL_F32 vDst(VGPR346) src0(VGPR336) src1(VGPR341) // VOP2 V_MUL_F32 vDst(VGPR347) src0(VGPR337) src1(VGPR341) // VOP2 # OpStore: : tmp1164 >> camu V_MOV_B32 vDst(VGPR332) src0(VGPR345) V_MOV_B32 vDst(VGPR333) src0(VGPR346) V_MOV_B32 vDst(VGPR334) src0(VGPR347) # 1168: OpLoad: FloatVector3: tmp1168 << camu # 1171: OpCompositeExtract: Float: tmp1171 << tmp1168, 0 V_MOV_B32 vDst(VGPR335) src0(VGPR332) # 1172: OpCompositeExtract: Float: tmp1172 << tmp1168, 1 V_MOV_B32 vDst(VGPR336) src0(VGPR333) # 1173: OpCompositeExtract: Float: tmp1173 << tmp1168, 2 V_MOV_B32 vDst(VGPR337) src0(VGPR334) # 1174: OpCompositeExtract: Float: tmp1174 << tmp1160, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR342) # 1175: OpCompositeExtract: Float: tmp1175 << tmp1160, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR343) # 1176: OpCompositeExtract: Float: tmp1176 << tmp1160, 2 V_MOV_B32 vDst(VGPR334) src0(VGPR344) # 1177: OpCompositeExtract: Float: tmp1177 << tmp1150, 0 V_MOV_B32 vDst(VGPR341) src0(VGPR338) # 1178: OpCompositeExtract: Float: tmp1178 << tmp1150, 1 V_MOV_B32 vDst(VGPR342) src0(VGPR339) # 1179: OpCompositeExtract: Float: tmp1179 << tmp1150, 2 V_MOV_B32 vDst(VGPR343) src0(VGPR340) # 1180: OpCompositeConstruct: FloatVector3: tmp1180 << tmp1171, tmp1172, tmp1173 V_MOV_B32 vDst(VGPR338) src0(VGPR335) V_MOV_B32 vDst(VGPR339) src0(VGPR336) V_MOV_B32 vDst(VGPR340) src0(VGPR337) # 1181: OpCompositeConstruct: FloatVector3: tmp1181 << tmp1174, tmp1175, tmp1176 V_MOV_B32 vDst(VGPR344) src0(VGPR332) V_MOV_B32 vDst(VGPR345) src0(VGPR333) V_MOV_B32 vDst(VGPR346) src0(VGPR334) # 1182: OpCompositeConstruct: FloatVector3: tmp1182 << tmp1177, tmp1178, tmp1179 V_MOV_B32 vDst(VGPR347) src0(VGPR341) V_MOV_B32 vDst(VGPR348) src0(VGPR342) V_MOV_B32 vDst(VGPR349) src0(VGPR343) # 1183: OpCompositeConstruct: FloatMatrix3x3: tmp1183 << tmp1180, tmp1181, tmp1182 V_MOV_B32 vDst(VGPR289) src0(VGPR338) V_MOV_B32 vDst(VGPR290) src0(VGPR339) V_MOV_B32 vDst(VGPR291) src0(VGPR340) V_MOV_B32 vDst(VGPR292) src0(VGPR344) V_MOV_B32 vDst(VGPR293) src0(VGPR345) V_MOV_B32 vDst(VGPR294) src0(VGPR346) V_MOV_B32 vDst(VGPR295) src0(VGPR347) V_MOV_B32 vDst(VGPR296) src0(VGPR348) V_MOV_B32 vDst(VGPR297) src0(VGPR349) # 1185: OpLoad: FloatVector2: tmp1185 << tc # 1186: OpVectorTimesScalar: FloatVector2: tmp1186 << tmp1185, const303 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR20) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR21) // VOP2 # 1187: OpFAdd: FloatVector2: tmp1187 << tmp1186, const391 V_MOV_B32 vDst(VGPR335) src0(0_5_F) V_MOV_B32 vDst(VGPR336) src0(0_5_F) V_ADD_F32 vDst(VGPR298) src0(VGPR333) src1(VGPR335) // VOP2 V_ADD_F32 vDst(VGPR299) src0(VGPR334) src1(VGPR336) // VOP2 # 1189: OpLoad: FloatVector2: tmp1189 << tc # OpStore: : tmp1189 >> p V_MOV_B32 vDst(VGPR243) src0(VGPR20) V_MOV_B32 vDst(VGPR244) src0(VGPR21) # 1192: OpAccessChain: Float*: iResolution[0] # 1193: OpLoad: Float: tmp1193 << iResolution[0] S_LOAD_DWORD_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR241) S_WAITCNT 0 # 1194: OpAccessChain: Float*: iResolution[1] # 1195: OpLoad: Float: tmp1195 << iResolution[1] S_LOAD_DWORD_IMM offset(8) sBase(SGPR[0:1]) sDst(SGPR242) S_WAITCNT 0 # 1196: OpFDiv: Float: tmp1196 << tmp1193, tmp1195 V_MOV_B32 vDst(VGPR332) src0(SGPR242) V_RCP_F32 vDst(VGPR333) src0(VGPR332) V_MUL_F32 vDst(VGPR333) src0(SGPR241) src1(VGPR333) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR333) src0(VGPR333) src1(VGPR332) src2(SGPR241) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1197: OpAccessChain: Float*: p[0] # 1198: OpLoad: Float: tmp1198 << p[0] V_MOV_B32 vDst(VGPR332) src0(VGPR243) # 1199: OpFMul: Float: tmp1199 << tmp1198, tmp1196 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 1200: OpAccessChain: Float*: p[0] # OpStore: : tmp1199 >> p[0] V_MOV_B32 vDst(VGPR243) src0(VGPR334) # 1203: OpFSub: Float: tmp1203 << tmp1124, const106 V_MOV_B32 vDst(VGPR332) src0(1_0_F) V_SUB_F32 vDst(VGPR333) src0(VGPR278) src1(VGPR332) // VOP2 # OpStore: : tmp1203 >> param1204 V_MOV_B32 vDst(VGPR245) src0(VGPR333) # 1205: OpFunctionCall: Float: cameraZoom(f1;(param1204) S_ADD_U32 sDst(SGPR178) src0(LITERAL_CONST) src1(0) const: 0xf5 # VGPR1317 S_MOV_B64 sDst(SGPR220) src0(EXEC) S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x12c # VGPR1459 # Indirect branch to cameraZoom(f1;: -4056 S_GETPC_B64 sDst(SGPR176) src0(SGPR176) S_SUB_U32 sDst(SGPR176) src0(SGPR176) src1(LITERAL_CONST) const: 0xfd8 S_SUBB_U32 sDst(SGPR177) src0(SGPR177) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR176) src0(SGPR176) S_MOV_B64 sDst(EXEC) src0(SGPR220) # .lbl119 # OpStore: : tmp1124 >> param1206 V_MOV_B32 vDst(VGPR246) src0(VGPR278) # 1208: OpFunctionCall: Float: cameraZoom(f1;(param1206) S_ADD_U32 sDst(SGPR178) src0(LITERAL_CONST) src1(0) const: 0xf6 # VGPR1318 S_MOV_B64 sDst(SGPR222) src0(EXEC) S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x12d # VGPR1460 # Indirect branch to cameraZoom(f1;: -4108 S_GETPC_B64 sDst(SGPR176) src0(SGPR176) S_SUB_U32 sDst(SGPR176) src0(SGPR176) src1(LITERAL_CONST) const: 0x100c S_SUBB_U32 sDst(SGPR177) src0(SGPR177) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR176) src0(SGPR176) S_MOV_B64 sDst(EXEC) src0(SGPR222) # .lbl120 # 1210: OpExtInst(SmoothStep): Float: tmp1210 << const671, const435, tmp1129 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3f666666 V_CMP_GE_F32 src0(VGPR332) src1(VGPR279) # CF Block: Merge: .lbl124 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl125, false: .lbl121 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl121 Label: .lbl125 V_MOV_B32 vDst(VGPR334) src0(0) Label: .lbl121 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl124 V_CMP_LE_F32 src0(VGPR333) src1(VGPR279) # CF Block: Merge: .lbl123 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl126, false: .lbl122 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl122 Label: .lbl126 V_MOV_B32 vDst(VGPR334) src0(1_0_F) Label: .lbl122 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl123 V_SUBREV_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 V_RCP_F32 vDst(VGPR335) src0(VGPR335) V_SUBREV_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR279) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR335) // VOP2 V_MAX_F32 vDst(VGPR335) src0(0) src1(VGPR335) // VOP2 V_MIN_F32 vDst(VGPR335) src0(1_0_F) src1(VGPR335) // VOP2 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR334) src0(2_0_F) src1(VGPR335) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR335) src0(VGPR335) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR335) src1(VGPR334) // VOP2 Label: .lbl123 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) Label: .lbl124 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) # 1211: OpExtInst(FMix): Float: tmp1211 << cameraZoom(f1;, cameraZoom(f1;, tmp1210 V_SUBREV_F32 vDst(VGPR332) src0(VGPR334) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR332) src0(VGPR300) src1(VGPR332) // VOP2 V_MAD_F32 vDst(VGPR332) src0(VGPR301) src1(VGPR334) src2(VGPR332) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1214: OpLoad: FloatVector2: tmp1214 << p # 1216: OpCompositeExtract: Float: tmp1216 << tmp1214, 0 V_MOV_B32 vDst(VGPR333) src0(VGPR243) # 1217: OpCompositeExtract: Float: tmp1217 << tmp1214, 1 V_MOV_B32 vDst(VGPR334) src0(VGPR244) # 1218: OpCompositeConstruct: FloatVector3: tmp1218 << tmp1216, tmp1217, tmp1211 V_MOV_B32 vDst(VGPR335) src0(VGPR333) V_MOV_B32 vDst(VGPR336) src0(VGPR334) V_MOV_B32 vDst(VGPR337) src0(VGPR332) # 1219: OpExtInst(Normalize): FloatVector3: tmp1219 << tmp1218 V_MUL_F32 vDst(VGPR332) src0(VGPR335) src1(VGPR335) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR336) src1(VGPR336) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR337) src1(VGPR337) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR332) src0(VGPR332) V_MUL_F32 vDst(VGPR338) src0(VGPR335) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR336) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR340) src0(VGPR337) src1(VGPR332) // VOP2 # 1220: OpMatrixTimesVector: FloatVector3: tmp1220 << tmp1183, tmp1219 V_MUL_F32 vDst(VGPR302) src0(VGPR289) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR303) src0(VGPR290) src1(VGPR338) // VOP2 V_MUL_F32 vDst(VGPR304) src0(VGPR291) src1(VGPR338) // VOP2 V_MAC_F32 vDst(VGPR302) src0(VGPR292) src1(VGPR339) // VOP2 V_MAC_F32 vDst(VGPR303) src0(VGPR293) src1(VGPR339) // VOP2 V_MAC_F32 vDst(VGPR304) src0(VGPR294) src1(VGPR339) // VOP2 V_MAC_F32 vDst(VGPR302) src0(VGPR295) src1(VGPR340) // VOP2 V_MAC_F32 vDst(VGPR303) src0(VGPR296) src1(VGPR340) // VOP2 V_MAC_F32 vDst(VGPR304) src0(VGPR297) src1(VGPR340) // VOP2 # 1222: OpAccessChain: Float*: ro[1] # 1223: OpCompositeExtract: Float: tmp1223 << cameraPos(f1;, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR281) # 1224: OpFSub: Float: tmp1224 << const106, tmp1223 V_SUB_F32 vDst(VGPR333) src0(1_0_F) src1(VGPR332) // VOP2 # 1225: OpAccessChain: Float*: rd[1] # 1226: OpCompositeExtract: Float: tmp1226 << tmp1220, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR303) # 1227: OpFDiv: Float: tmp1227 << tmp1224, tmp1226 V_RCP_F32 vDst(VGPR334) src0(VGPR332) V_MUL_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR334) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR334) src0(VGPR334) src1(VGPR332) src2(VGPR333) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1228: OpExtInst(FMax): Float: tmp1228 << const100, tmp1227 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR334) // VOP2 # OpStore: : tmp1228 >> t V_MOV_B32 vDst(VGPR247) src0(VGPR333) # 1231: OpAccessChain: Float*: ro[1] # 1232: OpCompositeExtract: Float: tmp1232 << cameraPos(f1;, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR281) # 1233: OpFSub: Float: tmp1233 << const1230, tmp1232 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0xbc23d70a V_SUB_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) // VOP2 # 1234: OpAccessChain: Float*: rd[1] # 1235: OpCompositeExtract: Float: tmp1235 << tmp1220, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR303) # 1236: OpFDiv: Float: tmp1236 << tmp1233, tmp1235 V_RCP_F32 vDst(VGPR333) src0(VGPR332) V_MUL_F32 vDst(VGPR333) src0(VGPR334) src1(VGPR333) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR333) src0(VGPR333) src1(VGPR332) src2(VGPR334) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1237: OpExtInst(FMax): Float: tmp1237 << const100, tmp1236 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR305) src0(VGPR332) src1(VGPR333) // VOP2 # OpStore: : cameraPos(f1; >> param1239 V_MOV_B32 vDst(VGPR251) src0(VGPR280) V_MOV_B32 vDst(VGPR252) src0(VGPR281) V_MOV_B32 vDst(VGPR253) src0(VGPR282) # OpStore: : tmp1220 >> param1241 V_MOV_B32 vDst(VGPR254) src0(VGPR302) V_MOV_B32 vDst(VGPR255) src0(VGPR303) V_MOV_B32 vDst(VGPR256) src0(VGPR304) # 1244: OpLoad: Float: tmp1244 << t # OpStore: : tmp1244 >> param1243 V_MOV_B32 vDst(VGPR257) src0(VGPR247) # OpStore: : tmp1237 >> param1245 V_MOV_B32 vDst(VGPR258) src0(VGPR305) # 1247: OpFunctionCall: FloatVector3: trace(vf3;vf3;f1;f1;(param1239, param1241, param1243, param1245) S_ADD_U32 sDst(SGPR182) src0(LITERAL_CONST) src1(0) const: 0xfb # VGPR[1323:1325] S_ADD_U32 sDst(SGPR183) src0(LITERAL_CONST) src1(0) const: 0xfe # VGPR[1326:1328] S_ADD_U32 sDst(SGPR184) src0(LITERAL_CONST) src1(0) const: 0x101 # VGPR1329 S_ADD_U32 sDst(SGPR185) src0(LITERAL_CONST) src1(0) const: 0x102 # VGPR1330 S_MOV_B64 sDst(SGPR224) src0(EXEC) S_MOV_B32 sDst(SGPR179) src0(LITERAL_CONST) const: 0x132 # VGPR[1491:1493] # Indirect branch to trace(vf3;vf3;f1;f1;: -4440 S_GETPC_B64 sDst(SGPR180) src0(SGPR180) S_SUB_U32 sDst(SGPR180) src0(SGPR180) src1(LITERAL_CONST) const: 0x1158 S_SUBB_U32 sDst(SGPR181) src0(SGPR181) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR180) src0(SGPR180) S_MOV_B64 sDst(EXEC) src0(SGPR224) # .lbl127 # 1248: OpLoad: Float: tmp1248 << param1243 # OpStore: : tmp1248 >> t V_MOV_B32 vDst(VGPR247) src0(VGPR257) # OpStore: : trace(vf3;vf3;f1;f1; >> col V_MOV_B32 vDst(VGPR248) src0(VGPR306) V_MOV_B32 vDst(VGPR249) src0(VGPR307) V_MOV_B32 vDst(VGPR250) src0(VGPR308) # 1252: OpLoad: Float: tmp1252 << t # 1253: OpVectorTimesScalar: FloatVector3: tmp1253 << tmp1220, tmp1252 V_MUL_F32 vDst(VGPR334) src0(VGPR247) src1(VGPR302) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR247) src1(VGPR303) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR247) src1(VGPR304) // VOP2 # 1254: OpFAdd: FloatVector3: tmp1254 << cameraPos(f1;, tmp1253 V_ADD_F32 vDst(VGPR309) src0(VGPR280) src1(VGPR334) // VOP2 V_ADD_F32 vDst(VGPR310) src0(VGPR281) src1(VGPR335) // VOP2 V_ADD_F32 vDst(VGPR311) src0(VGPR282) src1(VGPR336) // VOP2 # 1255: OpAccessChain: Float*: rp[1] # 1256: OpCompositeExtract: Float: tmp1256 << tmp1254, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR310) # 1257: OpFMul: Float: tmp1257 << tmp1256, const127 V_MOV_B32 vDst(VGPR333) src0(2_0_F) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR333) // VOP2 # 1258: OpExtInst(FClamp): Float: tmp1258 << tmp1257, const100, const106 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR333) src0(1_0_F) V_MAX_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR332) // VOP2 V_MIN_F32 vDst(VGPR335) src0(VGPR335) src1(VGPR333) // VOP2 # OpStore: : tmp1258 >> icing_factor V_MOV_B32 vDst(VGPR30) src0(VGPR335) # 1259: OpLoad: Float: tmp1259 << t # 1260: OpFOrdGreaterThan: Bool: tmp1260 << tmp1259, const100 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_CMP_GT_F32 dst(SGPR242) src0(VGPR247) src1(VGPR332) // VOP3a # 1262: OpLoad: Float: tmp1262 << t # 1263: OpFOrdLessThan: Bool: tmp1263 << tmp1237, tmp1262 V_CMP_LT_F32 dst(SGPR244) src0(VGPR305) src1(VGPR247) // VOP3a # 1264: OpLogicalAnd: Bool: tmp1264 << tmp1260, tmp1263 S_AND_B64 sDst(SGPR246) src0(SGPR242) src1(SGPR244) # OpSelectionMerge: (merge: lb1266) # CF Block: Merge: lb1266 S_MOV_B64 sDst(SGPR226) src0(EXEC) # OpBranchConditional: if(tmp1264) then branch to lb1265, else branch to lb1266 # CF Block: Cond Branch: true: lb1265, false: lb1266 S_AND_B64 sDst(EXEC) src0(SGPR246) src1(EXEC) S_CBRANCH_EXECZ 325 lb1266 # lb1265 Label: lb1265 # 1269: OpVectorShuffle: FloatVector2: tmp1269 << cameraPos(f1;, cameraPos(f1;, 0, 2 V_MOV_B32 vDst(VGPR332) src0(VGPR280) V_MOV_B32 vDst(VGPR333) src0(VGPR282) # 1271: OpVectorShuffle: FloatVector2: tmp1271 << tmp1220, tmp1220, 0, 2 V_MOV_B32 vDst(VGPR334) src0(VGPR302) V_MOV_B32 vDst(VGPR335) src0(VGPR304) # 1273: OpVectorTimesScalar: FloatVector2: tmp1273 << tmp1271, tmp1237 V_MUL_F32 vDst(VGPR336) src0(VGPR305) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR305) src1(VGPR335) // VOP2 # 1274: OpFAdd: FloatVector2: tmp1274 << tmp1269, tmp1273 V_ADD_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR336) // VOP2 V_ADD_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR337) // VOP2 # OpStore: : tmp1274 >> c V_MOV_B32 vDst(VGPR259) src0(VGPR334) V_MOV_B32 vDst(VGPR260) src0(VGPR335) # 1276: OpLoad: FloatVector2: tmp1276 << c # 1277: OpVectorTimesScalar: FloatVector2: tmp1277 << tmp1276, const151 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f4ccccd V_MUL_F32 vDst(VGPR312) src0(VGPR332) src1(VGPR259) // VOP2 V_MUL_F32 vDst(VGPR313) src0(VGPR332) src1(VGPR260) // VOP2 # 1279: OpAccessChain: Float*: xc[0] # 1280: OpCompositeExtract: Float: tmp1280 << tmp1277, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR312) # 1281: OpAccessChain: Float*: xc[1] # 1282: OpCompositeExtract: Float: tmp1282 << tmp1277, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR313) # 1283: OpExtInst(Fract): Float: tmp1283 << tmp1282 V_FRACT_F32 vDst(VGPR334) src0(VGPR333) # 1284: OpExtInst(Step): Float: tmp1284 << const303, tmp1283 V_CMP_GT_F32 src0(0_5_F) src1(VGPR334) # CF Block: Merge: .lbl129 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl130, false: .lbl128 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl128 Label: .lbl130 V_MOV_B32 vDst(VGPR333) src0(0) Label: .lbl128 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl129 V_MOV_B32 vDst(VGPR333) src0(1_0_F) Label: .lbl129 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) # 1285: OpFMul: Float: tmp1285 << const303, tmp1284 V_MUL_F32 vDst(VGPR334) src0(0_5_F) src1(VGPR333) // VOP2 # 1286: OpFAdd: Float: tmp1286 << tmp1280, tmp1285 V_ADD_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR334) // VOP2 # 1287: OpExtInst(Fract): Float: tmp1287 << tmp1286 V_FRACT_F32 vDst(VGPR332) src0(VGPR333) # 1288: OpExtInst(Step): Float: tmp1288 << const303, tmp1287 V_CMP_GT_F32 src0(0_5_F) src1(VGPR332) # CF Block: Merge: .lbl132 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl133, false: .lbl131 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl131 Label: .lbl133 V_MOV_B32 vDst(VGPR332) src0(0) Label: .lbl131 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl132 V_MOV_B32 vDst(VGPR332) src0(1_0_F) Label: .lbl132 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) # 1294: OpCompositeConstruct: FloatVector3: tmp1294 << tmp1288, tmp1288, tmp1288 V_MOV_B32 vDst(VGPR333) src0(VGPR332) V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR332) # 1295: OpExtInst(FMix): FloatVector3: tmp1295 << const1290, const1292, tmp1294 V_MOV_B32 vDst(VGPR336) src0(1_0_F) V_MOV_B32 vDst(VGPR337) src0(1_0_F) V_MOV_B32 vDst(VGPR338) src0(1_0_F) V_MOV_B32 vDst(VGPR339) src0(0_5_F) V_MOV_B32 vDst(VGPR340) src0(0_5_F) V_MOV_B32 vDst(VGPR341) src0(LITERAL_CONST) const: 0x3e800000 V_SUBREV_F32 vDst(VGPR342) src0(VGPR333) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR342) src0(VGPR336) src1(VGPR342) // VOP2 V_MAD_F32 vDst(VGPR342) src0(VGPR339) src1(VGPR333) src2(VGPR342) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR343) src0(VGPR334) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR343) src0(VGPR337) src1(VGPR343) // VOP2 V_MAD_F32 vDst(VGPR343) src0(VGPR340) src1(VGPR334) src2(VGPR343) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR344) src0(VGPR335) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR344) src0(VGPR338) src1(VGPR344) // VOP2 V_MAD_F32 vDst(VGPR344) src0(VGPR341) src1(VGPR335) src2(VGPR344) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1295 >> cc V_MOV_B32 vDst(VGPR261) src0(VGPR342) V_MOV_B32 vDst(VGPR262) src0(VGPR343) V_MOV_B32 vDst(VGPR263) src0(VGPR344) # 1296: OpLoad: FloatVector3: tmp1296 << cc # 1299: OpVectorTimesScalar: FloatVector2: tmp1299 << tmp1277, const621 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR312) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR313) // VOP2 # 1300: OpAccessChain: Float*: xc[1] # 1301: OpCompositeExtract: Float: tmp1301 << tmp1277, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR313) # 1302: OpFMul: Float: tmp1302 << tmp1301, const127 V_MOV_B32 vDst(VGPR335) src0(2_0_F) V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR335) // VOP2 # 1303: OpExtInst(Cos): Float: tmp1303 << tmp1302 V_MUL_F32 vDst(VGPR332) src0(LITERAL_CONST) src1(VGPR336) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR332) src0(VGPR332) V_COS_F32 vDst(VGPR332) src0(VGPR332) # 1304: OpFMul: Float: tmp1304 << tmp1303, const109 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR335) // VOP2 # 1305: OpAccessChain: Float*: xc[0] # 1306: OpCompositeExtract: Float: tmp1306 << tmp1277, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR312) # 1307: OpFMul: Float: tmp1307 << tmp1306, const106 V_MOV_B32 vDst(VGPR335) src0(1_0_F) V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR335) // VOP2 # 1308: OpExtInst(Cos): Float: tmp1308 << tmp1307 V_MUL_F32 vDst(VGPR332) src0(LITERAL_CONST) src1(VGPR337) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR332) src0(VGPR332) V_COS_F32 vDst(VGPR332) src0(VGPR332) # 1309: OpFMul: Float: tmp1309 << tmp1308, const377 V_MOV_B32 vDst(VGPR335) src0(4_0_F) V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR335) // VOP2 # 1310: OpCompositeConstruct: FloatVector2: tmp1310 << tmp1304, tmp1309 V_MOV_B32 vDst(VGPR338) src0(VGPR336) V_MOV_B32 vDst(VGPR339) src0(VGPR337) # 1311: OpFAdd: FloatVector2: tmp1311 << tmp1299, tmp1310 V_ADD_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR338) // VOP2 V_ADD_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR339) // VOP2 # OpStore: : tmp1311 >> param1312 V_MOV_B32 vDst(VGPR264) src0(VGPR335) V_MOV_B32 vDst(VGPR265) src0(VGPR336) # 1313: OpFunctionCall: Float: smN2(vf2;(param1312) S_ADD_U32 sDst(SGPR50) src0(LITERAL_CONST) src1(0) const: 0x108 # VGPR[1336:1337] S_MOV_B64 sDst(SGPR228) src0(EXEC) S_MOV_B32 sDst(SGPR31) src0(LITERAL_CONST) const: 0x13a # VGPR1557 # Indirect branch to smN2(vf2;: -12776 S_GETPC_B64 sDst(SGPR48) src0(SGPR48) S_SUB_U32 sDst(SGPR48) src0(SGPR48) src1(LITERAL_CONST) const: 0x31e8 S_SUBB_U32 sDst(SGPR49) src0(SGPR49) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR48) src0(SGPR48) S_MOV_B64 sDst(EXEC) src0(SGPR228) # .lbl134 # 1314: OpFMul: Float: tmp1314 << const303, smN2(vf2; V_MUL_F32 vDst(VGPR332) src0(0_5_F) src1(VGPR314) // VOP2 # 1315: OpFAdd: Float: tmp1315 << const523, tmp1314 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3e99999a V_ADD_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) // VOP2 # 1316: OpExtInst(Pow): Float: tmp1316 << tmp1315, const377 V_MOV_B32 vDst(VGPR332) src0(4_0_F) V_LOG_F32 vDst(VGPR333) src0(VGPR334) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR333) // VOP2 V_EXP_F32 vDst(VGPR333) src0(VGPR333) # 1317: OpCompositeConstruct: FloatVector3: tmp1317 << tmp1316, tmp1316, tmp1316 V_MOV_B32 vDst(VGPR334) src0(VGPR333) V_MOV_B32 vDst(VGPR335) src0(VGPR333) V_MOV_B32 vDst(VGPR336) src0(VGPR333) # 1318: OpExtInst(FMix): FloatVector3: tmp1318 << tmp1296, const1297, tmp1317 V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x3f666666 V_MOV_B32 vDst(VGPR338) src0(LITERAL_CONST) const: 0x3f666666 V_MOV_B32 vDst(VGPR339) src0(0_5_F) V_SUBREV_F32 vDst(VGPR340) src0(VGPR334) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR340) src0(VGPR261) src1(VGPR340) // VOP2 V_MAD_F32 vDst(VGPR340) src0(VGPR337) src1(VGPR334) src2(VGPR340) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR341) src0(VGPR335) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR341) src0(VGPR262) src1(VGPR341) // VOP2 V_MAD_F32 vDst(VGPR341) src0(VGPR338) src1(VGPR335) src2(VGPR341) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR342) src0(VGPR336) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR342) src0(VGPR263) src1(VGPR342) // VOP2 V_MAD_F32 vDst(VGPR342) src0(VGPR339) src1(VGPR336) src2(VGPR342) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1318 >> cc V_MOV_B32 vDst(VGPR261) src0(VGPR340) V_MOV_B32 vDst(VGPR262) src0(VGPR341) V_MOV_B32 vDst(VGPR263) src0(VGPR342) # 1320: OpLoad: FloatVector3: tmp1320 << l # 1322: OpFSub: FloatVector3: tmp1322 << tmp1320, tmp1220 V_SUB_F32 vDst(VGPR332) src0(VGPR27) src1(VGPR302) // VOP2 V_SUB_F32 vDst(VGPR333) src0(VGPR28) src1(VGPR303) // VOP2 V_SUB_F32 vDst(VGPR334) src0(VGPR29) src1(VGPR304) // VOP2 # 1323: OpExtInst(Normalize): FloatVector3: tmp1323 << tmp1322 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR332) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR333) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR334) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR335) src0(VGPR335) V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR333) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR334) src1(VGPR335) // VOP2 # 1326: OpExtInst(Reflect): FloatVector3: tmp1326 << tmp1220, const1153 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR333) src0(1_0_F) V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x00000000 V_MUL_F32 vDst(VGPR335) src0(VGPR302) src1(VGPR332) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR303) src1(VGPR333) // VOP2 V_MAC_F32 vDst(VGPR335) src0(VGPR304) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR335) src0(2_0_F) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR333) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR334) src1(VGPR335) // VOP2 V_SUB_F32 vDst(VGPR336) src0(VGPR302) src1(VGPR336) // VOP2 V_SUB_F32 vDst(VGPR337) src0(VGPR303) src1(VGPR337) // VOP2 V_SUB_F32 vDst(VGPR338) src0(VGPR304) src1(VGPR338) // VOP2 # 1329: OpVectorTimesScalar: FloatVector2: tmp1329 << tmp1277, const303 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR312) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR313) // VOP2 # OpStore: : const127 >> param1330 V_MOV_B32 vDst(VGPR266) src0(2_0_F) # OpStore: : tmp1329 >> param1331 V_MOV_B32 vDst(VGPR267) src0(VGPR333) V_MOV_B32 vDst(VGPR268) src0(VGPR334) # 1332: OpFunctionCall: FloatVector2: rotate(f1;vf2;(param1330, param1331) S_ADD_U32 sDst(SGPR76) src0(LITERAL_CONST) src1(0) const: 0x10a # VGPR1338 S_ADD_U32 sDst(SGPR77) src0(LITERAL_CONST) src1(0) const: 0x10b # VGPR[1339:1340] S_MOV_B64 sDst(SGPR230) src0(EXEC) S_MOV_B32 sDst(SGPR63) src0(LITERAL_CONST) const: 0x13b # VGPR[1589:1590] # Indirect branch to rotate(f1;vf2;: -12640 S_GETPC_B64 sDst(SGPR74) src0(SGPR74) S_SUB_U32 sDst(SGPR74) src0(SGPR74) src1(LITERAL_CONST) const: 0x3160 S_SUBB_U32 sDst(SGPR75) src0(SGPR75) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR74) src0(SGPR74) S_MOV_B64 sDst(EXEC) src0(SGPR230) # .lbl135 # OpStore: : rotate(f1;vf2; >> param1333 V_MOV_B32 vDst(VGPR269) src0(VGPR315) V_MOV_B32 vDst(VGPR270) src0(VGPR316) # 1334: OpFunctionCall: FloatVector3: marble(vf2;(param1333) S_ADD_U32 sDst(SGPR154) src0(LITERAL_CONST) src1(0) const: 0x10d # VGPR[1341:1342] S_MOV_B64 sDst(SGPR232) src0(EXEC) S_MOV_B32 sDst(SGPR147) src0(LITERAL_CONST) const: 0x13d # VGPR[1591:1593] # Indirect branch to marble(vf2;: -8328 S_GETPC_B64 sDst(SGPR152) src0(SGPR152) S_SUB_U32 sDst(SGPR152) src0(SGPR152) src1(LITERAL_CONST) const: 0x2088 S_SUBB_U32 sDst(SGPR153) src0(SGPR153) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR152) src0(SGPR152) S_MOV_B64 sDst(EXEC) src0(SGPR232) # .lbl136 # OpStore: : marble(vf2; >> cc V_MOV_B32 vDst(VGPR261) src0(VGPR317) V_MOV_B32 vDst(VGPR262) src0(VGPR318) V_MOV_B32 vDst(VGPR263) src0(VGPR319) # 1335: OpLoad: FloatVector2: tmp1335 << c # 1336: OpCompositeConstruct: FloatVector2: tmp1336 << const109, const109 S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR335) src0(SGPR241) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x40400000 V_MOV_B32 vDst(VGPR336) src0(SGPR241) # 1337: OpFDiv: FloatVector2: tmp1337 << tmp1335, tmp1336 V_RCP_F32 vDst(VGPR332) src0(VGPR335) V_RCP_F32 vDst(VGPR333) src0(VGPR336) V_MUL_F32 vDst(VGPR332) src0(VGPR259) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR333) src0(VGPR260) src1(VGPR333) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR332) src0(VGPR332) src1(VGPR335) src2(VGPR259) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR333) src0(VGPR333) src1(VGPR336) src2(VGPR260) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1338: OpExtInst(Fract): FloatVector2: tmp1338 << tmp1337 V_FRACT_F32 vDst(VGPR334) src0(VGPR332) V_FRACT_F32 vDst(VGPR335) src0(VGPR333) # OpStore: : tmp1338 >> c V_MOV_B32 vDst(VGPR259) src0(VGPR334) V_MOV_B32 vDst(VGPR260) src0(VGPR335) # 1339: OpLoad: FloatVector3: tmp1339 << cc # 1340: OpVectorTimesScalar: FloatVector3: tmp1340 << tmp1339, const151 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f4ccccd V_MUL_F32 vDst(VGPR320) src0(VGPR332) src1(VGPR261) // VOP2 V_MUL_F32 vDst(VGPR321) src0(VGPR332) src1(VGPR262) // VOP2 V_MUL_F32 vDst(VGPR322) src0(VGPR332) src1(VGPR263) // VOP2 # 1342: OpLoad: Float: tmp1342 << colour # OpStore: : tmp1342 >> param1341 V_MOV_B32 vDst(VGPR271) src0(VGPR23) # 1343: OpFunctionCall: FloatVector3: gumColour(f1;(param1341) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x10f # VGPR1343 S_MOV_B64 sDst(SGPR234) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x143 # VGPR[1606:1608] # Indirect branch to gumColour(f1;: -14996 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x3a94 S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR234) # .lbl137 # 1344: OpVectorTimesScalar: FloatVector3: tmp1344 << gumColour(f1;, const127 V_MOV_B32 vDst(VGPR332) src0(2_0_F) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR323) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR324) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR325) // VOP2 # 1345: OpLoad: Float: tmp1345 << is_choc # 1346: OpVectorTimesScalar: FloatVector3: tmp1346 << tmp1344, tmp1345 V_MUL_F32 vDst(VGPR336) src0(VGPR25) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR25) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR338) src0(VGPR25) src1(VGPR335) // VOP2 # 1349: OpLoad: FloatVector2: tmp1349 << c # 1350: OpExtInst(Distance): Float: tmp1350 << const391, tmp1349 V_MOV_B32 vDst(VGPR332) src0(0_5_F) V_MOV_B32 vDst(VGPR333) src0(0_5_F) V_SUB_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR259) // VOP2 V_SUB_F32 vDst(VGPR335) src0(VGPR333) src1(VGPR260) // VOP2 V_MUL_F32 vDst(VGPR332) src0(VGPR334) src1(VGPR334) // VOP2 V_MAC_F32 vDst(VGPR332) src0(VGPR335) src1(VGPR335) // VOP2 V_SQRT_F32 vDst(VGPR332) src0(VGPR332) # 1351: OpLoad: Float: tmp1351 << ss # 1352: OpFDiv: Float: tmp1352 << tmp1350, tmp1351 V_RCP_F32 vDst(VGPR333) src0(VGPR24) V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR333) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR333) src0(VGPR333) src1(VGPR24) src2(VGPR332) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1353: OpExtInst(SmoothStep): Float: tmp1353 << const1347, const1348, tmp1352 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3ea8f5c3 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x3f07ae14 V_CMP_GE_F32 src0(VGPR332) src1(VGPR333) # CF Block: Merge: .lbl141 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl142, false: .lbl138 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl138 Label: .lbl142 V_MOV_B32 vDst(VGPR335) src0(0) Label: .lbl138 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl141 V_CMP_LE_F32 src0(VGPR334) src1(VGPR333) # CF Block: Merge: .lbl140 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl143, false: .lbl139 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl139 Label: .lbl143 V_MOV_B32 vDst(VGPR335) src0(1_0_F) Label: .lbl139 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl140 V_SUBREV_F32 vDst(VGPR339) src0(VGPR332) src1(VGPR334) // VOP2 V_RCP_F32 vDst(VGPR339) src0(VGPR339) V_SUBREV_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR333) // VOP2 V_MUL_F32 vDst(VGPR339) src0(VGPR335) src1(VGPR339) // VOP2 V_MAX_F32 vDst(VGPR339) src0(0) src1(VGPR339) // VOP2 V_MIN_F32 vDst(VGPR339) src0(1_0_F) src1(VGPR339) // VOP2 V_MOV_B32 vDst(VGPR335) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR335) src0(2_0_F) src1(VGPR339) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR339) src0(VGPR339) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR339) src1(VGPR335) // VOP2 Label: .lbl140 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) Label: .lbl141 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) # 1354: OpCompositeConstruct: FloatVector3: tmp1354 << tmp1353, tmp1353, tmp1353 V_MOV_B32 vDst(VGPR332) src0(VGPR335) V_MOV_B32 vDst(VGPR333) src0(VGPR335) V_MOV_B32 vDst(VGPR334) src0(VGPR335) # 1355: OpExtInst(FMix): FloatVector3: tmp1355 << tmp1346, const1290, tmp1354 V_MOV_B32 vDst(VGPR339) src0(1_0_F) V_MOV_B32 vDst(VGPR340) src0(1_0_F) V_MOV_B32 vDst(VGPR341) src0(1_0_F) V_SUBREV_F32 vDst(VGPR342) src0(VGPR332) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR342) src0(VGPR336) src1(VGPR342) // VOP2 V_MAD_F32 vDst(VGPR342) src0(VGPR339) src1(VGPR332) src2(VGPR342) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR343) src0(VGPR333) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR343) src0(VGPR337) src1(VGPR343) // VOP2 V_MAD_F32 vDst(VGPR343) src0(VGPR340) src1(VGPR333) src2(VGPR343) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR344) src0(VGPR334) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR344) src0(VGPR338) src1(VGPR344) // VOP2 V_MAD_F32 vDst(VGPR344) src0(VGPR341) src1(VGPR334) src2(VGPR344) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1356: OpFMul: FloatVector3: tmp1356 << tmp1340, tmp1355 V_MUL_F32 vDst(VGPR332) src0(VGPR320) src1(VGPR342) // VOP2 V_MUL_F32 vDst(VGPR333) src0(VGPR321) src1(VGPR343) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR322) src1(VGPR344) // VOP2 # OpStore: : tmp1356 >> col V_MOV_B32 vDst(VGPR248) src0(VGPR332) V_MOV_B32 vDst(VGPR249) src0(VGPR333) V_MOV_B32 vDst(VGPR250) src0(VGPR334) # OpStore: : const106 >> icing_factor V_MOV_B32 vDst(VGPR30) src0(1_0_F) # OpBranch: to lb1266 # lb1266 Label: lb1266 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR226) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) # 1360: OpAccessChain: Float*: iMouse[0] # 1361: OpLoad: Float: tmp1361 << iMouse[0] S_LOAD_DWORD_IMM offset(16) sBase(SGPR[0:1]) sDst(SGPR241) S_WAITCNT 0 # 1362: OpAccessChain: Float*: iResolution[0] # 1363: OpLoad: Float: tmp1363 << iResolution[0] S_LOAD_DWORD_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR242) S_WAITCNT 0 # 1364: OpFDiv: Float: tmp1364 << tmp1361, tmp1363 V_MOV_B32 vDst(VGPR332) src0(SGPR242) V_RCP_F32 vDst(VGPR333) src0(VGPR332) V_MUL_F32 vDst(VGPR333) src0(SGPR241) src1(VGPR333) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR333) src0(VGPR333) src1(VGPR332) src2(SGPR241) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 1365: OpLoad: Float: tmp1365 << icing_factor # 1366: OpFMul: Float: tmp1366 << tmp1364, tmp1365 V_MUL_F32 vDst(VGPR332) src0(VGPR333) src1(VGPR30) // VOP2 # 1367: OpFSub: Float: tmp1367 << const106, tmp1366 V_SUB_F32 vDst(VGPR326) src0(1_0_F) src1(VGPR332) // VOP2 # 1368: OpLoad: FloatVector3: tmp1368 << col # 1371: OpFMul: Float: tmp1371 << const1369, tmp1367 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0xbe800000 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR326) // VOP2 # 1373: OpFAdd: Float: tmp1373 << tmp1371, const1372 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3eb33333 V_ADD_F32 vDst(VGPR327) src0(VGPR333) src1(VGPR332) // VOP2 # 1375: OpVectorShuffle: FloatVector2: tmp1375 << tmp1254, tmp1254, 0, 2 V_MOV_B32 vDst(VGPR334) src0(VGPR309) V_MOV_B32 vDst(VGPR335) src0(VGPR311) # 1377: OpVectorTimesScalar: FloatVector2: tmp1377 << tmp1375, const1376 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x40866666 V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR335) // VOP2 # 1378: OpCompositeExtract: Float: tmp1378 << tmp1377, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR336) # 1379: OpCompositeExtract: Float: tmp1379 << tmp1377, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR337) # 1380: OpCompositeConstruct: FloatVector3: tmp1380 << tmp1378, tmp1379, const100 V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR333) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR336) src0(SGPR241) # OpStore: : tmp1380 >> param1381 V_MOV_B32 vDst(VGPR272) src0(VGPR334) V_MOV_B32 vDst(VGPR273) src0(VGPR335) V_MOV_B32 vDst(VGPR274) src0(VGPR336) # 1382: OpFunctionCall: Float: fbm3(vf3;(param1381) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x110 # VGPR[1344:1346] S_MOV_B64 sDst(SGPR236) src0(EXEC) S_MOV_B32 sDst(SGPR57) src0(LITERAL_CONST) const: 0x148 # VGPR1657 # Indirect branch to fbm3(vf3;: -13612 S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_SUB_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x352c S_SUBB_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR236) # .lbl144 # 1383: OpFAdd: Float: tmp1383 << tmp1373, fbm3(vf3; V_ADD_F32 vDst(VGPR332) src0(VGPR327) src1(VGPR328) // VOP2 # 1384: OpExtInst(SmoothStep): Float: tmp1384 << const303, const671, tmp1383 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3f333333 V_CMP_GE_F32 src0(0_5_F) src1(VGPR332) # CF Block: Merge: .lbl148 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl149, false: .lbl145 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl145 Label: .lbl149 V_MOV_B32 vDst(VGPR334) src0(0) Label: .lbl145 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl148 V_CMP_LE_F32 src0(VGPR333) src1(VGPR332) # CF Block: Merge: .lbl147 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl150, false: .lbl146 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl146 Label: .lbl150 V_MOV_B32 vDst(VGPR334) src0(1_0_F) Label: .lbl146 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl147 V_SUBREV_F32 vDst(VGPR335) src0(0_5_F) src1(VGPR333) // VOP2 V_RCP_F32 vDst(VGPR335) src0(VGPR335) V_SUBREV_F32 vDst(VGPR334) src0(0_5_F) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR335) // VOP2 V_MAX_F32 vDst(VGPR335) src0(0) src1(VGPR335) // VOP2 V_MIN_F32 vDst(VGPR335) src0(1_0_F) src1(VGPR335) // VOP2 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR334) src0(2_0_F) src1(VGPR335) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR335) src0(VGPR335) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR335) src1(VGPR334) // VOP2 Label: .lbl147 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) Label: .lbl148 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) # 1385: OpFMul: Float: tmp1385 << const435, tmp1384 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f666666 V_MUL_F32 vDst(VGPR329) src0(VGPR332) src1(VGPR334) // VOP2 # 1387: OpFMul: Float: tmp1387 << const1369, tmp1367 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0xbe800000 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR326) // VOP2 # 1388: OpFAdd: Float: tmp1388 << tmp1387, const523 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3e99999a V_ADD_F32 vDst(VGPR330) src0(VGPR333) src1(VGPR332) // VOP2 # 1390: OpVectorShuffle: FloatVector2: tmp1390 << tmp1254, tmp1254, 0, 2 V_MOV_B32 vDst(VGPR334) src0(VGPR309) V_MOV_B32 vDst(VGPR335) src0(VGPR311) # 1392: OpVectorTimesScalar: FloatVector2: tmp1392 << tmp1390, const1391 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x4121999a V_MUL_F32 vDst(VGPR336) src0(VGPR332) src1(VGPR334) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR332) src1(VGPR335) // VOP2 # 1393: OpCompositeExtract: Float: tmp1393 << tmp1392, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR336) # 1394: OpCompositeExtract: Float: tmp1394 << tmp1392, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR337) # 1395: OpCompositeConstruct: FloatVector3: tmp1395 << tmp1393, tmp1394, const100 V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR333) S_MOV_B32 sDst(SGPR241) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR336) src0(SGPR241) # OpStore: : tmp1395 >> param1396 V_MOV_B32 vDst(VGPR275) src0(VGPR334) V_MOV_B32 vDst(VGPR276) src0(VGPR335) V_MOV_B32 vDst(VGPR277) src0(VGPR336) # 1397: OpFunctionCall: Float: fbm3(vf3;(param1396) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x113 # VGPR[1347:1349] S_MOV_B64 sDst(SGPR238) src0(EXEC) S_MOV_B32 sDst(SGPR57) src0(LITERAL_CONST) const: 0x14b # VGPR1679 # Indirect branch to fbm3(vf3;: -13900 S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_SUB_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x364c S_SUBB_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR238) # .lbl151 # 1398: OpFAdd: Float: tmp1398 << tmp1388, fbm3(vf3; V_ADD_F32 vDst(VGPR332) src0(VGPR330) src1(VGPR331) // VOP2 # 1399: OpExtInst(SmoothStep): Float: tmp1399 << const303, const671, tmp1398 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x3f333333 V_CMP_GE_F32 src0(0_5_F) src1(VGPR332) # CF Block: Merge: .lbl155 S_MOV_B64 sDst(SGPR242) src0(EXEC) # CF Block: Cond Branch: true: .lbl156, false: .lbl152 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl152 Label: .lbl156 V_MOV_B32 vDst(VGPR334) src0(0) Label: .lbl152 S_ANDN2_B64 sDst(EXEC) src0(SGPR242) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 22 .lbl155 V_CMP_LE_F32 src0(VGPR333) src1(VGPR332) # CF Block: Merge: .lbl154 S_MOV_B64 sDst(SGPR244) src0(EXEC) # CF Block: Cond Branch: true: .lbl157, false: .lbl153 S_AND_B64 sDst(EXEC) src0(VCC) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl153 Label: .lbl157 V_MOV_B32 vDst(VGPR334) src0(1_0_F) Label: .lbl153 S_ANDN2_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 12 .lbl154 V_SUBREV_F32 vDst(VGPR335) src0(0_5_F) src1(VGPR333) // VOP2 V_RCP_F32 vDst(VGPR335) src0(VGPR335) V_SUBREV_F32 vDst(VGPR334) src0(0_5_F) src1(VGPR332) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR335) // VOP2 V_MAX_F32 vDst(VGPR335) src0(0) src1(VGPR335) // VOP2 V_MIN_F32 vDst(VGPR335) src0(1_0_F) src1(VGPR335) // VOP2 V_MOV_B32 vDst(VGPR334) src0(LITERAL_CONST) const: 0x40400000 V_MAC_F32 vDst(VGPR334) src0(2_0_F) src1(VGPR335) src2(N/A) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MUL_F32 vDst(VGPR335) src0(VGPR335) src1(VGPR335) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR335) src1(VGPR334) // VOP2 Label: .lbl154 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR244) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) Label: .lbl155 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR212) # 1400: OpFMul: Float: tmp1400 << const435, tmp1399 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3f666666 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR334) // VOP2 # 1401: OpFAdd: Float: tmp1401 << tmp1385, tmp1400 V_ADD_F32 vDst(VGPR332) src0(VGPR329) src1(VGPR333) // VOP2 # 1402: OpCompositeConstruct: FloatVector3: tmp1402 << tmp1401, tmp1401, tmp1401 V_MOV_B32 vDst(VGPR333) src0(VGPR332) V_MOV_B32 vDst(VGPR334) src0(VGPR332) V_MOV_B32 vDst(VGPR335) src0(VGPR332) # 1403: OpExtInst(FMix): FloatVector3: tmp1403 << tmp1368, const1290, tmp1402 V_MOV_B32 vDst(VGPR336) src0(1_0_F) V_MOV_B32 vDst(VGPR337) src0(1_0_F) V_MOV_B32 vDst(VGPR338) src0(1_0_F) V_SUBREV_F32 vDst(VGPR339) src0(VGPR333) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR339) src0(VGPR248) src1(VGPR339) // VOP2 V_MAD_F32 vDst(VGPR339) src0(VGPR336) src1(VGPR333) src2(VGPR339) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR340) src0(VGPR334) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR340) src0(VGPR249) src1(VGPR340) // VOP2 V_MAD_F32 vDst(VGPR340) src0(VGPR337) src1(VGPR334) src2(VGPR340) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR341) src0(VGPR335) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR341) src0(VGPR250) src1(VGPR341) // VOP2 V_MAD_F32 vDst(VGPR341) src0(VGPR338) src1(VGPR335) src2(VGPR341) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp1403 >> col V_MOV_B32 vDst(VGPR248) src0(VGPR339) V_MOV_B32 vDst(VGPR249) src0(VGPR340) V_MOV_B32 vDst(VGPR250) src0(VGPR341) # 1404: OpLoad: FloatVector3: tmp1404 << col # 1405: OpVectorTimesScalar: FloatVector3: tmp1405 << tmp1404, const895 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3fb33333 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR248) // VOP2 V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR249) // VOP2 V_MUL_F32 vDst(VGPR335) src0(VGPR332) src1(VGPR250) // VOP2 # 1406: OpExtInst(Sqrt): FloatVector3: tmp1406 << tmp1405 V_SQRT_F32 vDst(VGPR336) src0(VGPR333) V_SQRT_F32 vDst(VGPR337) src0(VGPR334) V_SQRT_F32 vDst(VGPR338) src0(VGPR335) # 1407: OpLoad: FloatVector4: tmp1407 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELS_B32 vDst(VGPR332) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR333) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR334) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR335) src0(VGPR3) # 1408: OpVectorShuffle: FloatVector4: tmp1408 << tmp1407, tmp1406, 4, 5, 6, 3 V_MOV_B32 vDst(VGPR339) src0(VGPR336) V_MOV_B32 vDst(VGPR340) src0(VGPR337) V_MOV_B32 vDst(VGPR341) src0(VGPR338) V_MOV_B32 vDst(VGPR342) src0(VGPR335) # OpStore: : tmp1408 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR339) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR340) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR341) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR342) # 1410: OpAccessChain: Float*: q[0] # 1411: OpCompositeExtract: Float: tmp1411 << tmp1187, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR298) # 1412: OpFMul: Float: tmp1412 << const1409, tmp1411 V_MOV_B32 vDst(VGPR333) src0(LITERAL_CONST) const: 0x41800000 V_MUL_F32 vDst(VGPR334) src0(VGPR333) src1(VGPR332) // VOP2 # 1413: OpAccessChain: Float*: q[1] # 1414: OpCompositeExtract: Float: tmp1414 << tmp1187, 1 V_MOV_B32 vDst(VGPR332) src0(VGPR299) # 1415: OpFMul: Float: tmp1415 << tmp1412, tmp1414 V_MUL_F32 vDst(VGPR333) src0(VGPR334) src1(VGPR332) // VOP2 # 1416: OpAccessChain: Float*: q[0] # 1417: OpCompositeExtract: Float: tmp1417 << tmp1187, 0 V_MOV_B32 vDst(VGPR332) src0(VGPR298) # 1418: OpFSub: Float: tmp1418 << const106, tmp1417 V_SUB_F32 vDst(VGPR334) src0(1_0_F) src1(VGPR332) // VOP2 # 1419: OpFMul: Float: tmp1419 << tmp1415, tmp1418 V_MUL_F32 vDst(VGPR332) src0(VGPR333) src1(VGPR334) // VOP2 # 1420: OpAccessChain: Float*: q[1] # 1421: OpCompositeExtract: Float: tmp1421 << tmp1187, 1 V_MOV_B32 vDst(VGPR333) src0(VGPR299) # 1422: OpFSub: Float: tmp1422 << const106, tmp1421 V_SUB_F32 vDst(VGPR334) src0(1_0_F) src1(VGPR333) // VOP2 # 1423: OpFMul: Float: tmp1423 << tmp1419, tmp1422 V_MUL_F32 vDst(VGPR333) src0(VGPR332) src1(VGPR334) // VOP2 # 1424: OpExtInst(Pow): Float: tmp1424 << tmp1423, const576 V_MOV_B32 vDst(VGPR332) src0(LITERAL_CONST) const: 0x3dcccccd V_LOG_F32 vDst(VGPR334) src0(VGPR333) V_MUL_F32 vDst(VGPR334) src0(VGPR332) src1(VGPR334) // VOP2 V_EXP_F32 vDst(VGPR334) src0(VGPR334) # 1425: OpLoad: FloatVector4: tmp1425 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELS_B32 vDst(VGPR335) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR336) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR337) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR338) src0(VGPR3) # 1426: OpVectorShuffle: FloatVector3: tmp1426 << tmp1425, tmp1425, 0, 1, 2 V_MOV_B32 vDst(VGPR339) src0(VGPR335) V_MOV_B32 vDst(VGPR340) src0(VGPR336) V_MOV_B32 vDst(VGPR341) src0(VGPR337) # 1427: OpVectorTimesScalar: FloatVector3: tmp1427 << tmp1426, tmp1424 V_MUL_F32 vDst(VGPR335) src0(VGPR334) src1(VGPR339) // VOP2 V_MUL_F32 vDst(VGPR336) src0(VGPR334) src1(VGPR340) // VOP2 V_MUL_F32 vDst(VGPR337) src0(VGPR334) src1(VGPR341) // VOP2 # 1428: OpLoad: FloatVector4: tmp1428 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELS_B32 vDst(VGPR338) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR339) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR340) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR341) src0(VGPR3) # 1429: OpVectorShuffle: FloatVector4: tmp1429 << tmp1428, tmp1427, 4, 5, 6, 3 V_MOV_B32 vDst(VGPR342) src0(VGPR335) V_MOV_B32 vDst(VGPR343) src0(VGPR336) V_MOV_B32 vDst(VGPR344) src0(VGPR337) V_MOV_B32 vDst(VGPR345) src0(VGPR341) # OpStore: : tmp1429 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR342) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR343) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR344) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR345) # OpReturn: S_SETPC_B64 sDst(SGPR10) src0(SGPR10) Generating the final byte-code... ERROR: Code generation failed. Error log: Need 258 SGPRs, which exceeds the maximum of 102 Need 350 VGPRs, which exceeds the maximum of 256 Done.