W3DNShaderInfo - Get shader information Verbose mode Shader: 4.frag.spv Compiling 4.frag.spv failed (23) with error: shader compilation failed due to errors Log: Shader size: 15924 bytes Parsing SPIR-V code Module Version: 1.2.0 Generator Magic Number: 0x80003 Upper bound on ids: 683 Parsed instructions: OpCapability: : Shader 1: OpExtInstImport: : GLSL.std.450 OpMemoryModel: : addressing: Logical, memory: GLSL450 4: OpEntryPoint: : main, execution model: Fragment 4: OpExecutionMode: : OriginLowerLeft OpSource: : ESSL ver 310 4: OpName: : main 11: OpName: : sdCross(vf3; 10: OpName: : p 14: OpName: : sdCrossRep(vf3; 13: OpName: : p 20: OpName: : sdCrossRepScale(vf3;f1; 18: OpName: : p 19: OpName: : s 25: OpName: : differenceSDF(f1;f1; 23: OpName: : distA 24: OpName: : distB 32: OpName: : sdCylinder(vf3;vf2; 30: OpName: : p 31: OpName: : h 37: OpName: : opU(vf2;vf2; 35: OpName: : d1 36: OpName: : d2 40: OpName: : diso(vf3; 39: OpName: : p 43: OpName: : DE(vf3; 42: OpName: : p 48: OpName: : march(vf3;vf3; 46: OpName: : ro 47: OpName: : rd 54: OpName: : getShadow(vf3;vf3;vf3; 51: OpName: : p 52: OpName: : n 53: OpName: : ld 58: OpName: : getNorm(vf3; 57: OpName: : p 63: OpName: : light(vf3;vf3; 61: OpName: : p 62: OpName: : n 69: OpName: : getSphereColor(i1; 68: OpName: : i 76: OpName: : mainImage(vf4;vf2; 74: OpName: : fragColor 75: OpName: : fragCoord 79: OpName: : lDir0 83: OpName: : lDir1 87: OpName: : lCol0 92: OpName: : lCol1 97: OpName: : d 130: OpName: : q 139: OpName: : param139 147: OpName: : param147 159: OpName: : d 191: OpName: : resp 198: OpName: : res 205: OpName: : sdcy1 208: OpName: : param208 211: OpName: : param211 213: OpName: : sdcy2 217: OpName: : param217 220: OpName: : param220 222: OpName: : dif1 223: OpName: : param223 225: OpName: : param225 231: OpName: : param231 233: OpName: : param233 239: OpName: : scale 241: OpName: : res 244: OpName: : dist 246: OpName: : param246 249: OpName: : i 260: OpName: : param260 262: OpName: : param262 274: OpName: : iTime 286: OpName: : param286 288: OpName: : param288 294: OpName: : param294 296: OpName: : param296 299: OpName: : NumCol 306: OpName: : t 307: OpName: : d 309: OpName: : it 310: OpName: : i 324: OpName: : param324 353: OpName: : t 354: OpName: : d 355: OpName: : i 369: OpName: : param369 389: OpName: : e 395: OpName: : param395 401: OpName: : param401 408: OpName: : param408 414: OpName: : param414 421: OpName: : param421 427: OpName: : param427 434: OpName: : col 437: OpName: : i 446: OpName: : ld 454: OpName: : diff 459: OpName: : param459 461: OpName: : param461 463: OpName: : param463 566: OpName: : time 569: OpName: : uv 572: OpName: : iResolution 581: OpName: : ro 592: OpName: : rd 598: OpName: : hit 599: OpName: : param599 601: OpName: : param601 604: OpName: : p 611: OpName: : nor 612: OpName: : param612 615: OpName: : col 622: OpName: : param622 624: OpName: : param624 634: OpName: : colobj 637: OpName: : param637 654: OpName: : color 656: OpName: : gl_FragCoord 657: OpName: : param657 658: OpName: : param658 664: OpName: : finalColor 667: OpName: : iMouse 668: OpName: : iDate 669: OpName: : iFrame 673: OpName: : iChannelResolution 677: OpName: : iChannel0 678: OpName: : iChannel1 679: OpName: : iChannel2 680: OpName: : iChannel3 68: OpDecorate: : RelaxedPrecision 249: OpDecorate: : RelaxedPrecision 256: OpDecorate: : RelaxedPrecision 270: OpDecorate: : RelaxedPrecision 272: OpDecorate: : RelaxedPrecision 310: OpDecorate: : RelaxedPrecision 316: OpDecorate: : RelaxedPrecision 339: OpDecorate: : RelaxedPrecision 340: OpDecorate: : RelaxedPrecision 355: OpDecorate: : RelaxedPrecision 361: OpDecorate: : RelaxedPrecision 381: OpDecorate: : RelaxedPrecision 382: OpDecorate: : RelaxedPrecision 437: OpDecorate: : RelaxedPrecision 443: OpDecorate: : RelaxedPrecision 447: OpDecorate: : RelaxedPrecision 469: OpDecorate: : RelaxedPrecision 478: OpDecorate: : RelaxedPrecision 479: OpDecorate: : RelaxedPrecision 485: OpDecorate: : RelaxedPrecision 491: OpDecorate: : RelaxedPrecision 497: OpDecorate: : RelaxedPrecision 503: OpDecorate: : RelaxedPrecision 510: OpDecorate: : RelaxedPrecision 517: OpDecorate: : RelaxedPrecision 523: OpDecorate: : RelaxedPrecision 528: OpDecorate: : RelaxedPrecision 535: OpDecorate: : RelaxedPrecision 545: OpDecorate: : RelaxedPrecision 552: OpDecorate: : RelaxedPrecision 558: OpDecorate: : RelaxedPrecision 656: OpDecorate: : BuiltIn(FragCoord) 677: OpDecorate: : RelaxedPrecision 677: OpDecorate: : DescriptorSet(0) 678: OpDecorate: : RelaxedPrecision 678: OpDecorate: : DescriptorSet(0) 679: OpDecorate: : RelaxedPrecision 679: OpDecorate: : DescriptorSet(0) 680: OpDecorate: : RelaxedPrecision 680: OpDecorate: : DescriptorSet(0) 317: OpDecorate: : RelaxedPrecision 681: OpDecorate: : RelaxedPrecision 257: OpDecorate: : RelaxedPrecision 2: OpTypeVoid: Void 3: OpTypeFunction: 2 << func() 6: OpTypeFloat: Float: 32 bits 7: OpTypeVector: ???Vector3: num-elements: 3, element type id: 6 8: OpTypePointer: ???Ptr: storage class: Function 9: OpTypeFunction: 6 << func(8) 16: OpTypePointer: ???Ptr: storage class: Function 17: OpTypeFunction: 6 << func(8, 16) 22: OpTypeFunction: 6 << func(16, 16) 27: OpTypeVector: ???Vector2: num-elements: 2, element type id: 6 28: OpTypePointer: ???Ptr: storage class: Function 29: OpTypeFunction: 6 << func(8, 28) 34: OpTypeFunction: 27 << func(28, 28) 45: OpTypeFunction: 27 << func(8, 8) 50: OpTypeFunction: 6 << func(8, 8, 8) 56: OpTypeFunction: 7 << func(8) 60: OpTypeFunction: 7 << func(8, 8) 65: OpTypeInt: Int: 32 bits, signed 66: OpTypePointer: ???Ptr: storage class: Function 67: OpTypeFunction: 7 << func(66) 71: OpTypeVector: ???Vector4: num-elements: 4, element type id: 6 72: OpTypePointer: ???Ptr: storage class: Function 73: OpTypeFunction: 2 << func(72, 28) 78: OpTypePointer: ???Ptr: storage class: Private 79: OpVariable: 78: var79: storage class: Private 80: OpConstant: 6 const80 = 0x3ed105ec 81: OpConstant: 6 const81 = 0x3f5105ec 82: OpConstantComposite: 7 const82 = {id:80, id:81, id:80} 83: OpVariable: 78: var83: storage class: Private 84: OpConstant: 6 const84 = 0xbed105ec 85: OpConstant: 6 const85 = 0xbf5105ec 86: OpConstantComposite: 7 const86 = {id:84, id:80, id:85} 87: OpVariable: 78: var87: storage class: Private 88: OpConstant: 6 const88 = 0x3f800000 89: OpConstant: 6 const89 = 0x3f4ccccd 90: OpConstant: 6 const90 = 0x3f000000 91: OpConstantComposite: 7 const91 = {id:88, id:89, id:90} 92: OpVariable: 78: var92: storage class: Private 93: OpConstant: 6 const93 = 0x3f19999a 94: OpConstantComposite: 7 const94 = {id:93, id:89, id:88} 98: OpTypeInt: UInt: 32 bits, unsigned 99: OpConstant: 98 const99 = 0x0 102: OpConstant: 98 const102 = 0x1 108: OpConstant: 98 const108 = 0x2 126: OpConstant: 6 const126 = 0x3eaaaaab 134: OpConstant: 6 const134 = 0x40000000 174: OpConstant: 6 const174 = 0x0 187: OpTypeBool: Bool 199: OpConstant: 6 const199 = 0x461c3c00 200: OpConstantComposite: 27 const200 = {id:199, id:174} 206: OpConstant: 6 const206 = 0x40c00000 207: OpConstantComposite: 27 const207 = {id:206, id:206} 214: OpConstant: 6 const214 = 0x3ff33333 215: OpConstant: 6 const215 = 0x40d8f5c3 216: OpConstantComposite: 27 const216 = {id:214, id:215} 229: OpConstant: 6 const229 = 0x41100000 240: OpConstant: 6 const240 = 0x3eb33333 242: OpConstant: 6 const242 = 0x461c3f9a 243: OpConstantComposite: 27 const243 = {id:242, id:174} 245: OpConstant: 6 const245 = 0xc479c000 250: OpConstant: 65 const250 = 0x0 257: OpConstant: 65 const257 = 0x5 267: OpConstant: 6 const267 = 0x40400000 271: OpConstant: 65 const271 = 0x1 273: OpTypePointer: ???Ptr: storage class: UniformConstant 274: OpVariable: 273: var274: storage class: UniformConstant 277: OpConstant: 6 const277 = 0x40a00000 279: OpConstant: 6 const279 = 0x3ecccccd 284: OpConstant: 6 const284 = 0x41000000 292: OpConstant: 6 const292 = 0x40e00000 298: OpTypePointer: ???Ptr: storage class: Private 299: OpVariable: 298: var299: storage class: Private 308: OpConstant: 6 const308 = 0x41a00000 317: OpConstant: 65 const317 = 0x64 329: OpConstant: 6 const329 = 0x3a83126f 343: OpConstant: 6 const343 = 0x42c80000 348: OpConstant: 6 const348 = 0x3b03126f 362: OpConstant: 65 const362 = 0x32 385: OpConstant: 6 const385 = 0x3dcccccd 390: OpConstantComposite: 27 const390 = {id:329, id:174} 435: OpConstant: 6 const435 = 0x3c23d70a 436: OpConstantComposite: 7 const436 = {id:435, id:435, id:435} 444: OpConstant: 65 const444 = 0x2 451: OpTypeVector: ???Vector3: num-elements: 3, element type id: 187 481: OpConstant: 6 const481 = 0x3f333333 489: OpConstantComposite: 7 const489 = {id:174, id:174, id:174} 495: OpConstantComposite: 7 const495 = {id:174, id:174, id:88} 501: OpConstantComposite: 7 const501 = {id:174, id:88, id:174} 504: OpConstant: 65 const504 = 0x3 508: OpConstantComposite: 7 const508 = {id:174, id:88, id:88} 511: OpConstant: 65 const511 = 0x4 515: OpConstantComposite: 7 const515 = {id:88, id:174, id:174} 521: OpConstantComposite: 7 const521 = {id:88, id:174, id:88} 524: OpConstant: 65 const524 = 0x6 529: OpConstant: 65 const529 = 0x7 533: OpConstantComposite: 7 const533 = {id:88, id:88, id:88} 536: OpConstant: 65 const536 = 0x8 540: OpConstant: 6 const540 = 0x3ed9999a 541: OpConstant: 6 const541 = 0x3f0f5c29 542: OpConstant: 6 const542 = 0x3f666666 543: OpConstantComposite: 7 const543 = {id:540, id:541, id:542} 546: OpConstant: 65 const546 = 0x9 550: OpConstantComposite: 7 const550 = {id:90, id:93, id:93} 553: OpConstant: 65 const553 = 0xa 559: OpConstant: 65 const559 = 0xb 563: OpConstantComposite: 7 const563 = {id:90, id:89, id:542} 571: OpTypePointer: ???Ptr: storage class: UniformConstant 572: OpVariable: 571: var572: storage class: UniformConstant 582: OpConstant: 6 const582 = 0xbf800000 587: OpConstant: 6 const587 = 0xc0a00000 655: OpTypePointer: ???Ptr: storage class: Input 656: OpVariable: 655: var656: storage class: Input 663: OpTypePointer: ???Ptr: storage class: Output 664: OpVariable: 663: var664: storage class: Output 666: OpTypePointer: ???Ptr: storage class: UniformConstant 667: OpVariable: 666: var667: storage class: UniformConstant 668: OpVariable: 666: var668: storage class: UniformConstant 669: OpVariable: 273: var669: storage class: UniformConstant 670: OpConstant: 98 const670 = 0x4 671: OpTypeArray: ???[]: length id: 670, element type id: 7 672: OpTypePointer: ???Ptr: storage class: UniformConstant 673: OpVariable: 672: var673: storage class: UniformConstant 674: OpTypeImage: Image(6): 2D, no-depth, sampled, ReadOnly 675: OpTypeSampledImage: SampledImage(674) 676: OpTypePointer: ???Ptr: storage class: UniformConstant 677: OpVariable: 676: var677: storage class: UniformConstant 678: OpVariable: 676: var678: storage class: UniformConstant 679: OpVariable: 676: var679: storage class: UniformConstant 680: OpVariable: 676: var680: storage class: UniformConstant 681: OpConstant: 65 const681 = 0x40 682: OpConstant: 6 const682 = 0x38d1b717 4: OpFunction: func4(type: 3) 5: OpLabel: 654: OpVariable: 72: var654: storage class: Function 657: OpVariable: 72: var657: storage class: Function 658: OpVariable: 28: var658: storage class: Function OpStore: : 82 >> 79 OpStore: : 86 >> 83 OpStore: : 91 >> 87 OpStore: : 94 >> 92 659: OpLoad: 71: tmp659 << 656 660: OpVectorShuffle: 27: tmp660 << 659, 659, 0, 1 OpStore: : 660 >> 658 661: OpFunctionCall: 2: tmp661(657, 658) 662: OpLoad: 71: tmp662 << 657 OpStore: : 662 >> 654 665: OpLoad: 71: tmp665 << 654 OpStore: : 665 >> 664 OpReturn: OpFunctionEnd: 11: OpFunction: func11(type: 9) 10: OpFunctionParameter: 8: var10: storage class: Function 12: OpLabel: 97: OpVariable: 8: var97: storage class: Function 95: OpLoad: 7: tmp95 << 10 96: OpExtInst(4): 7: tmp96 << 95 OpStore: : 96 >> 10 100: OpAccessChain: 16: 10[99] 101: OpLoad: 6: tmp101 << 100 103: OpAccessChain: 16: 10[102] 104: OpLoad: 6: tmp104 << 103 105: OpExtInst(40): 6: tmp105 << 101, 104 106: OpAccessChain: 16: 10[102] 107: OpLoad: 6: tmp107 << 106 109: OpAccessChain: 16: 10[108] 110: OpLoad: 6: tmp110 << 109 111: OpExtInst(40): 6: tmp111 << 107, 110 112: OpAccessChain: 16: 10[108] 113: OpLoad: 6: tmp113 << 112 114: OpAccessChain: 16: 10[99] 115: OpLoad: 6: tmp115 << 114 116: OpExtInst(40): 6: tmp116 << 113, 115 117: OpCompositeConstruct: 7: tmp117 << 105, 111, 116 OpStore: : 117 >> 97 118: OpAccessChain: 16: 97[99] 119: OpLoad: 6: tmp119 << 118 120: OpAccessChain: 16: 97[102] 121: OpLoad: 6: tmp121 << 120 122: OpAccessChain: 16: 97[108] 123: OpLoad: 6: tmp123 << 122 124: OpExtInst(37): 6: tmp124 << 121, 123 125: OpExtInst(37): 6: tmp125 << 119, 124 127: OpFSub: 6: tmp127 << 125, 126 OpReturnValue: : << 127 OpFunctionEnd: 14: OpFunction: func14(type: 9) 13: OpFunctionParameter: 8: var13: storage class: Function 15: OpLabel: 130: OpVariable: 8: var130: storage class: Function 139: OpVariable: 8: var139: storage class: Function 131: OpLoad: 7: tmp131 << 13 132: OpCompositeConstruct: 7: tmp132 << 88, 88, 88 133: OpFAdd: 7: tmp133 << 131, 132 135: OpCompositeConstruct: 7: tmp135 << 134, 134, 134 136: OpFMod: 7: tmp136 << 133, 135 137: OpCompositeConstruct: 7: tmp137 << 88, 88, 88 138: OpFSub: 7: tmp138 << 136, 137 OpStore: : 138 >> 130 140: OpLoad: 7: tmp140 << 130 OpStore: : 140 >> 139 141: OpFunctionCall: 6: tmp141(139) OpReturnValue: : << 141 OpFunctionEnd: 20: OpFunction: func20(type: 17) 18: OpFunctionParameter: 8: var18: storage class: Function 19: OpFunctionParameter: 16: var19: storage class: Function 21: OpLabel: 147: OpVariable: 8: var147: storage class: Function 144: OpLoad: 7: tmp144 << 18 145: OpLoad: 6: tmp145 << 19 146: OpVectorTimesScalar: 7: tmp146 << 144, 145 OpStore: : 146 >> 147 148: OpFunctionCall: 6: tmp148(147) 149: OpLoad: 6: tmp149 << 19 150: OpFDiv: 6: tmp150 << 148, 149 OpReturnValue: : << 150 OpFunctionEnd: 25: OpFunction: func25(type: 22) 23: OpFunctionParameter: 16: var23: storage class: Function 24: OpFunctionParameter: 16: var24: storage class: Function 26: OpLabel: 153: OpLoad: 6: tmp153 << 23 154: OpLoad: 6: tmp154 << 24 155: OpFNegate: 6: tmp155 << 154 156: OpExtInst(40): 6: tmp156 << 153, 155 OpReturnValue: : << 156 OpFunctionEnd: 32: OpFunction: func32(type: 29) 30: OpFunctionParameter: 8: var30: storage class: Function 31: OpFunctionParameter: 28: var31: storage class: Function 33: OpLabel: 159: OpVariable: 28: var159: storage class: Function 160: OpLoad: 7: tmp160 << 30 161: OpVectorShuffle: 27: tmp161 << 160, 160, 0, 2 162: OpExtInst(66): 6: tmp162 << 161 163: OpAccessChain: 16: 30[102] 164: OpLoad: 6: tmp164 << 163 165: OpCompositeConstruct: 27: tmp165 << 162, 164 166: OpExtInst(4): 27: tmp166 << 165 167: OpLoad: 27: tmp167 << 31 168: OpFSub: 27: tmp168 << 166, 167 OpStore: : 168 >> 159 169: OpAccessChain: 16: 159[99] 170: OpLoad: 6: tmp170 << 169 171: OpAccessChain: 16: 159[102] 172: OpLoad: 6: tmp172 << 171 173: OpExtInst(40): 6: tmp173 << 170, 172 175: OpExtInst(37): 6: tmp175 << 173, 174 176: OpLoad: 27: tmp176 << 159 177: OpCompositeConstruct: 27: tmp177 << 174, 174 178: OpExtInst(40): 27: tmp178 << 176, 177 179: OpExtInst(66): 6: tmp179 << 178 180: OpFAdd: 6: tmp180 << 175, 179 OpReturnValue: : << 180 OpFunctionEnd: 37: OpFunction: func37(type: 34) 35: OpFunctionParameter: 28: var35: storage class: Function 36: OpFunctionParameter: 28: var36: storage class: Function 38: OpLabel: 191: OpVariable: 28: var191: storage class: Function 183: OpAccessChain: 16: 35[99] 184: OpLoad: 6: tmp184 << 183 185: OpAccessChain: 16: 36[99] 186: OpLoad: 6: tmp186 << 185 188: OpFOrdLessThan: 187: tmp188 << 184, 186 OpSelectionMerge: (merge: 190) OpBranchConditional: if(188) then branch to 189, else branch to 193 189: OpLabel: 192: OpLoad: 27: tmp192 << 35 OpStore: : 192 >> 191 OpBranch: to 190 193: OpLabel: 194: OpLoad: 27: tmp194 << 36 OpStore: : 194 >> 191 OpBranch: to 190 190: OpLabel: 195: OpLoad: 27: tmp195 << 191 OpReturnValue: : << 195 OpFunctionEnd: 40: OpFunction: func40(type: 9) 39: OpFunctionParameter: 8: var39: storage class: Function 41: OpLabel: 198: OpVariable: 28: var198: storage class: Function 205: OpVariable: 16: var205: storage class: Function 208: OpVariable: 8: var208: storage class: Function 211: OpVariable: 28: var211: storage class: Function 213: OpVariable: 16: var213: storage class: Function 217: OpVariable: 8: var217: storage class: Function 220: OpVariable: 28: var220: storage class: Function 222: OpVariable: 16: var222: storage class: Function 223: OpVariable: 16: var223: storage class: Function 225: OpVariable: 16: var225: storage class: Function 231: OpVariable: 28: var231: storage class: Function 233: OpVariable: 28: var233: storage class: Function OpStore: : 200 >> 198 201: OpAccessChain: 16: 39[108] 202: OpLoad: 6: tmp202 << 201 203: OpFMod: 6: tmp203 << 202, 134 204: OpAccessChain: 16: 39[108] OpStore: : 203 >> 204 209: OpLoad: 7: tmp209 << 39 210: OpVectorShuffle: 7: tmp210 << 209, 209, 1, 2, 0 OpStore: : 210 >> 208 OpStore: : 207 >> 211 212: OpFunctionCall: 6: tmp212(208, 211) OpStore: : 212 >> 205 218: OpLoad: 7: tmp218 << 39 219: OpVectorShuffle: 7: tmp219 << 218, 218, 1, 2, 0 OpStore: : 219 >> 217 OpStore: : 216 >> 220 221: OpFunctionCall: 6: tmp221(217, 220) OpStore: : 221 >> 213 224: OpLoad: 6: tmp224 << 205 OpStore: : 224 >> 223 226: OpLoad: 6: tmp226 << 213 OpStore: : 226 >> 225 227: OpFunctionCall: 6: tmp227(223, 225) OpStore: : 227 >> 222 228: OpLoad: 6: tmp228 << 222 230: OpCompositeConstruct: 27: tmp230 << 228, 229 232: OpLoad: 27: tmp232 << 198 OpStore: : 232 >> 231 OpStore: : 230 >> 233 234: OpFunctionCall: 27: tmp234(231, 233) OpStore: : 234 >> 198 235: OpAccessChain: 16: 198[99] 236: OpLoad: 6: tmp236 << 235 OpReturnValue: : << 236 OpFunctionEnd: 43: OpFunction: func43(type: 9) 42: OpFunctionParameter: 8: var42: storage class: Function 44: OpLabel: 239: OpVariable: 16: var239: storage class: Function 241: OpVariable: 28: var241: storage class: Function 244: OpVariable: 16: var244: storage class: Function 246: OpVariable: 8: var246: storage class: Function 249: OpVariable: 66: var249: storage class: Function 260: OpVariable: 8: var260: storage class: Function 262: OpVariable: 16: var262: storage class: Function 286: OpVariable: 28: var286: storage class: Function 288: OpVariable: 28: var288: storage class: Function 294: OpVariable: 28: var294: storage class: Function 296: OpVariable: 28: var296: storage class: Function OpStore: : 240 >> 239 OpStore: : 243 >> 241 OpStore: : 245 >> 244 247: OpLoad: 7: tmp247 << 42 OpStore: : 247 >> 246 248: OpFunctionCall: 6: tmp248(246) OpStore: : 248 >> 244 OpStore: : 250 >> 249 OpBranch: to 251 251: OpLabel: OpLoopMerge: (merge: 253, continue: 254) OpBranch: to 255 255: OpLabel: 256: OpLoad: 65: tmp256 << 249 258: OpSLessThan: 187: tmp258 << 256, 257 OpBranchConditional: if(258) then branch to 252, else branch to 253 252: OpLabel: 259: OpLoad: 6: tmp259 << 244 261: OpLoad: 7: tmp261 << 42 OpStore: : 261 >> 260 263: OpLoad: 6: tmp263 << 239 OpStore: : 263 >> 262 264: OpFunctionCall: 6: tmp264(260, 262) 265: OpFNegate: 6: tmp265 << 264 266: OpExtInst(40): 6: tmp266 << 259, 265 OpStore: : 266 >> 244 268: OpLoad: 6: tmp268 << 239 269: OpFMul: 6: tmp269 << 268, 267 OpStore: : 269 >> 239 OpBranch: to 254 254: OpLabel: 270: OpLoad: 65: tmp270 << 249 272: OpIAdd: 65: tmp272 << 270, 271 OpStore: : 272 >> 249 OpBranch: to 251 253: OpLabel: 275: OpLoad: 6: tmp275 << 274 276: OpExtInst(8): 6: tmp276 << 275 278: OpFMod: 6: tmp278 << 276, 277 280: OpFOrdGreaterThan: 187: tmp280 << 278, 279 OpSelectionMerge: (merge: 282) OpBranchConditional: if(280) then branch to 281, else branch to 290 281: OpLabel: 283: OpLoad: 6: tmp283 << 244 285: OpCompositeConstruct: 27: tmp285 << 283, 284 287: OpLoad: 27: tmp287 << 241 OpStore: : 287 >> 286 OpStore: : 285 >> 288 289: OpFunctionCall: 27: tmp289(286, 288) OpStore: : 289 >> 241 OpBranch: to 282 290: OpLabel: 291: OpLoad: 6: tmp291 << 244 293: OpCompositeConstruct: 27: tmp293 << 291, 292 295: OpLoad: 27: tmp295 << 241 OpStore: : 295 >> 294 OpStore: : 293 >> 296 297: OpFunctionCall: 27: tmp297(294, 296) OpStore: : 297 >> 241 OpBranch: to 282 282: OpLabel: 300: OpAccessChain: 16: 241[102] 301: OpLoad: 6: tmp301 << 300 OpStore: : 301 >> 299 302: OpAccessChain: 16: 241[99] 303: OpLoad: 6: tmp303 << 302 OpReturnValue: : << 303 OpFunctionEnd: 48: OpFunction: func48(type: 45) 46: OpFunctionParameter: 8: var46: storage class: Function 47: OpFunctionParameter: 8: var47: storage class: Function 49: OpLabel: 306: OpVariable: 16: var306: storage class: Function 307: OpVariable: 16: var307: storage class: Function 309: OpVariable: 16: var309: storage class: Function 310: OpVariable: 66: var310: storage class: Function 324: OpVariable: 8: var324: storage class: Function OpStore: : 174 >> 306 OpStore: : 308 >> 307 OpStore: : 174 >> 309 OpStore: : 250 >> 310 OpBranch: to 311 311: OpLabel: OpLoopMerge: (merge: 313, continue: 314) OpBranch: to 315 315: OpLabel: 316: OpLoad: 65: tmp316 << 310 318: OpSLessThan: 187: tmp318 << 316, 317 OpBranchConditional: if(318) then branch to 312, else branch to 313 312: OpLabel: 319: OpLoad: 7: tmp319 << 46 320: OpLoad: 6: tmp320 << 306 321: OpLoad: 7: tmp321 << 47 322: OpVectorTimesScalar: 7: tmp322 << 321, 320 323: OpFAdd: 7: tmp323 << 319, 322 OpStore: : 323 >> 324 325: OpFunctionCall: 6: tmp325(324) OpStore: : 325 >> 307 326: OpLoad: 6: tmp326 << 306 327: OpFAdd: 6: tmp327 << 326, 325 OpStore: : 327 >> 306 328: OpLoad: 6: tmp328 << 307 330: OpFOrdLessThan: 187: tmp330 << 328, 329 331: OpLoad: 6: tmp331 << 306 332: OpFOrdGreaterThan: 187: tmp332 << 331, 308 333: OpLogicalOr: 187: tmp333 << 330, 332 OpSelectionMerge: (merge: 335) OpBranchConditional: if(333) then branch to 334, else branch to 335 334: OpLabel: OpBranch: to 313 335: OpLabel: 337: OpLoad: 6: tmp337 << 309 338: OpFAdd: 6: tmp338 << 337, 88 OpStore: : 338 >> 309 OpBranch: to 314 314: OpLabel: 339: OpLoad: 65: tmp339 << 310 340: OpIAdd: 65: tmp340 << 339, 271 OpStore: : 340 >> 310 OpBranch: to 311 313: OpLabel: 341: OpLoad: 6: tmp341 << 306 342: OpLoad: 6: tmp342 << 309 344: OpFDiv: 6: tmp344 << 342, 343 345: OpCompositeConstruct: 27: tmp345 << 341, 344 OpReturnValue: : << 345 OpFunctionEnd: 54: OpFunction: func54(type: 50) 51: OpFunctionParameter: 8: var51: storage class: Function 52: OpFunctionParameter: 8: var52: storage class: Function 53: OpFunctionParameter: 8: var53: storage class: Function 55: OpLabel: 353: OpVariable: 16: var353: storage class: Function 354: OpVariable: 16: var354: storage class: Function 355: OpVariable: 66: var355: storage class: Function 369: OpVariable: 8: var369: storage class: Function 349: OpLoad: 7: tmp349 << 52 350: OpVectorTimesScalar: 7: tmp350 << 349, 348 351: OpLoad: 7: tmp351 << 51 352: OpFAdd: 7: tmp352 << 351, 350 OpStore: : 352 >> 51 OpStore: : 174 >> 353 OpStore: : 308 >> 354 OpStore: : 250 >> 355 OpBranch: to 356 356: OpLabel: OpLoopMerge: (merge: 358, continue: 359) OpBranch: to 360 360: OpLabel: 361: OpLoad: 65: tmp361 << 355 363: OpSLessThan: 187: tmp363 << 361, 362 OpBranchConditional: if(363) then branch to 357, else branch to 358 357: OpLabel: 364: OpLoad: 7: tmp364 << 51 365: OpLoad: 6: tmp365 << 353 366: OpLoad: 7: tmp366 << 53 367: OpVectorTimesScalar: 7: tmp367 << 366, 365 368: OpFAdd: 7: tmp368 << 364, 367 OpStore: : 368 >> 369 370: OpFunctionCall: 6: tmp370(369) OpStore: : 370 >> 354 371: OpLoad: 6: tmp371 << 353 372: OpFAdd: 6: tmp372 << 371, 370 OpStore: : 372 >> 353 373: OpLoad: 6: tmp373 << 354 374: OpFOrdLessThan: 187: tmp374 << 373, 329 375: OpLoad: 6: tmp375 << 353 376: OpFOrdGreaterThan: 187: tmp376 << 375, 267 377: OpLogicalOr: 187: tmp377 << 374, 376 OpSelectionMerge: (merge: 379) OpBranchConditional: if(377) then branch to 378, else branch to 379 378: OpLabel: OpBranch: to 358 379: OpLabel: OpBranch: to 359 359: OpLabel: 381: OpLoad: 65: tmp381 << 355 382: OpIAdd: 65: tmp382 << 381, 271 OpStore: : 382 >> 355 OpBranch: to 356 358: OpLabel: 383: OpLoad: 6: tmp383 << 353 384: OpFOrdLessThanEqual: 187: tmp384 << 383, 267 386: OpSelect: 6: tmp386 << 384, 385, 88 OpReturnValue: : << 386 OpFunctionEnd: 58: OpFunction: func58(type: 56) 57: OpFunctionParameter: 8: var57: storage class: Function 59: OpLabel: 389: OpVariable: 28: var389: storage class: Function 395: OpVariable: 8: var395: storage class: Function 401: OpVariable: 8: var401: storage class: Function 408: OpVariable: 8: var408: storage class: Function 414: OpVariable: 8: var414: storage class: Function 421: OpVariable: 8: var421: storage class: Function 427: OpVariable: 8: var427: storage class: Function OpStore: : 390 >> 389 391: OpLoad: 7: tmp391 << 57 392: OpLoad: 27: tmp392 << 389 393: OpVectorShuffle: 7: tmp393 << 392, 392, 0, 1, 1 394: OpFAdd: 7: tmp394 << 391, 393 OpStore: : 394 >> 395 396: OpFunctionCall: 6: tmp396(395) 397: OpLoad: 7: tmp397 << 57 398: OpLoad: 27: tmp398 << 389 399: OpVectorShuffle: 7: tmp399 << 398, 398, 0, 1, 1 400: OpFSub: 7: tmp400 << 397, 399 OpStore: : 400 >> 401 402: OpFunctionCall: 6: tmp402(401) 403: OpFSub: 6: tmp403 << 396, 402 404: OpLoad: 7: tmp404 << 57 405: OpLoad: 27: tmp405 << 389 406: OpVectorShuffle: 7: tmp406 << 405, 405, 1, 0, 1 407: OpFAdd: 7: tmp407 << 404, 406 OpStore: : 407 >> 408 409: OpFunctionCall: 6: tmp409(408) 410: OpLoad: 7: tmp410 << 57 411: OpLoad: 27: tmp411 << 389 412: OpVectorShuffle: 7: tmp412 << 411, 411, 1, 0, 1 413: OpFSub: 7: tmp413 << 410, 412 OpStore: : 413 >> 414 415: OpFunctionCall: 6: tmp415(414) 416: OpFSub: 6: tmp416 << 409, 415 417: OpLoad: 7: tmp417 << 57 418: OpLoad: 27: tmp418 << 389 419: OpVectorShuffle: 7: tmp419 << 418, 418, 1, 1, 0 420: OpFAdd: 7: tmp420 << 417, 419 OpStore: : 420 >> 421 422: OpFunctionCall: 6: tmp422(421) 423: OpLoad: 7: tmp423 << 57 424: OpLoad: 27: tmp424 << 389 425: OpVectorShuffle: 7: tmp425 << 424, 424, 1, 1, 0 426: OpFSub: 7: tmp426 << 423, 425 OpStore: : 426 >> 427 428: OpFunctionCall: 6: tmp428(427) 429: OpFSub: 6: tmp429 << 422, 428 430: OpCompositeConstruct: 7: tmp430 << 403, 416, 429 431: OpExtInst(69): 7: tmp431 << 430 OpReturnValue: : << 431 OpFunctionEnd: 63: OpFunction: func63(type: 60) 61: OpFunctionParameter: 8: var61: storage class: Function 62: OpFunctionParameter: 8: var62: storage class: Function 64: OpLabel: 434: OpVariable: 8: var434: storage class: Function 437: OpVariable: 66: var437: storage class: Function 446: OpVariable: 8: var446: storage class: Function 454: OpVariable: 16: var454: storage class: Function 459: OpVariable: 8: var459: storage class: Function 461: OpVariable: 8: var461: storage class: Function 463: OpVariable: 8: var463: storage class: Function OpStore: : 436 >> 434 OpStore: : 250 >> 437 OpBranch: to 438 438: OpLabel: OpLoopMerge: (merge: 440, continue: 441) OpBranch: to 442 442: OpLabel: 443: OpLoad: 65: tmp443 << 437 445: OpSLessThan: 187: tmp445 << 443, 444 OpBranchConditional: if(445) then branch to 439, else branch to 440 439: OpLabel: 447: OpLoad: 65: tmp447 << 437 448: OpIEqual: 187: tmp448 << 447, 250 449: OpLoad: 7: tmp449 << 79 450: OpLoad: 7: tmp450 << 83 452: OpCompositeConstruct: 451: tmp452 << 448, 448, 448 453: OpSelect: 7: tmp453 << 452, 449, 450 OpStore: : 453 >> 446 455: OpLoad: 7: tmp455 << 62 456: OpLoad: 7: tmp456 << 446 457: OpDot: 6: tmp457 << 455, 456 458: OpExtInst(40): 6: tmp458 << 457, 174 OpStore: : 458 >> 454 460: OpLoad: 7: tmp460 << 61 OpStore: : 460 >> 459 462: OpLoad: 7: tmp462 << 62 OpStore: : 462 >> 461 464: OpLoad: 7: tmp464 << 446 OpStore: : 464 >> 463 465: OpFunctionCall: 6: tmp465(459, 461, 463) 466: OpLoad: 6: tmp466 << 454 467: OpFMul: 6: tmp467 << 466, 465 OpStore: : 467 >> 454 468: OpLoad: 6: tmp468 << 454 469: OpLoad: 65: tmp469 << 437 470: OpIEqual: 187: tmp470 << 469, 250 471: OpLoad: 7: tmp471 << 87 472: OpLoad: 7: tmp472 << 92 473: OpCompositeConstruct: 451: tmp473 << 470, 470, 470 474: OpSelect: 7: tmp474 << 473, 471, 472 475: OpVectorTimesScalar: 7: tmp475 << 474, 468 476: OpLoad: 7: tmp476 << 434 477: OpFAdd: 7: tmp477 << 476, 475 OpStore: : 477 >> 434 OpBranch: to 441 441: OpLabel: 478: OpLoad: 65: tmp478 << 437 479: OpIAdd: 65: tmp479 << 478, 271 OpStore: : 479 >> 437 OpBranch: to 438 440: OpLabel: 480: OpLoad: 7: tmp480 << 434 482: OpVectorTimesScalar: 7: tmp482 << 480, 481 OpReturnValue: : << 482 OpFunctionEnd: 69: OpFunction: func69(type: 67) 68: OpFunctionParameter: 66: var68: storage class: Function 70: OpLabel: 485: OpLoad: 65: tmp485 << 68 486: OpIEqual: 187: tmp486 << 485, 250 OpSelectionMerge: (merge: 488) OpBranchConditional: if(486) then branch to 487, else branch to 488 487: OpLabel: OpReturnValue: : << 489 488: OpLabel: 491: OpLoad: 65: tmp491 << 68 492: OpIEqual: 187: tmp492 << 491, 271 OpSelectionMerge: (merge: 494) OpBranchConditional: if(492) then branch to 493, else branch to 494 493: OpLabel: OpReturnValue: : << 495 494: OpLabel: 497: OpLoad: 65: tmp497 << 68 498: OpIEqual: 187: tmp498 << 497, 444 OpSelectionMerge: (merge: 500) OpBranchConditional: if(498) then branch to 499, else branch to 500 499: OpLabel: OpReturnValue: : << 501 500: OpLabel: 503: OpLoad: 65: tmp503 << 68 505: OpIEqual: 187: tmp505 << 503, 504 OpSelectionMerge: (merge: 507) OpBranchConditional: if(505) then branch to 506, else branch to 507 506: OpLabel: OpReturnValue: : << 508 507: OpLabel: 510: OpLoad: 65: tmp510 << 68 512: OpIEqual: 187: tmp512 << 510, 511 OpSelectionMerge: (merge: 514) OpBranchConditional: if(512) then branch to 513, else branch to 514 513: OpLabel: OpReturnValue: : << 515 514: OpLabel: 517: OpLoad: 65: tmp517 << 68 518: OpIEqual: 187: tmp518 << 517, 257 OpSelectionMerge: (merge: 520) OpBranchConditional: if(518) then branch to 519, else branch to 520 519: OpLabel: OpReturnValue: : << 521 520: OpLabel: 523: OpLoad: 65: tmp523 << 68 525: OpIEqual: 187: tmp525 << 523, 524 OpSelectionMerge: (merge: 527) OpBranchConditional: if(525) then branch to 526, else branch to 527 526: OpLabel: OpBranch: to 527 527: OpLabel: 528: OpLoad: 65: tmp528 << 68 530: OpIEqual: 187: tmp530 << 528, 529 OpSelectionMerge: (merge: 532) OpBranchConditional: if(530) then branch to 531, else branch to 532 531: OpLabel: OpReturnValue: : << 533 532: OpLabel: 535: OpLoad: 65: tmp535 << 68 537: OpIEqual: 187: tmp537 << 535, 536 OpSelectionMerge: (merge: 539) OpBranchConditional: if(537) then branch to 538, else branch to 539 538: OpLabel: OpReturnValue: : << 543 539: OpLabel: 545: OpLoad: 65: tmp545 << 68 547: OpIEqual: 187: tmp547 << 545, 546 OpSelectionMerge: (merge: 549) OpBranchConditional: if(547) then branch to 548, else branch to 549 548: OpLabel: OpReturnValue: : << 550 549: OpLabel: 552: OpLoad: 65: tmp552 << 68 554: OpIEqual: 187: tmp554 << 552, 553 OpSelectionMerge: (merge: 556) OpBranchConditional: if(554) then branch to 555, else branch to 556 555: OpLabel: OpReturnValue: : << 501 556: OpLabel: 558: OpLoad: 65: tmp558 << 68 560: OpIEqual: 187: tmp560 << 558, 559 OpSelectionMerge: (merge: 562) OpBranchConditional: if(560) then branch to 561, else branch to 562 561: OpLabel: OpReturnValue: : << 563 562: OpLabel: 565: OpUndef: 7: tmp565 << OpReturnValue: : << 565 OpFunctionEnd: 76: OpFunction: func76(type: 73) 74: OpFunctionParameter: 72: var74: storage class: Function 75: OpFunctionParameter: 28: var75: storage class: Function 77: OpLabel: 566: OpVariable: 16: var566: storage class: Function 569: OpVariable: 28: var569: storage class: Function 581: OpVariable: 8: var581: storage class: Function 592: OpVariable: 8: var592: storage class: Function 598: OpVariable: 28: var598: storage class: Function 599: OpVariable: 8: var599: storage class: Function 601: OpVariable: 8: var601: storage class: Function 604: OpVariable: 8: var604: storage class: Function 611: OpVariable: 8: var611: storage class: Function 612: OpVariable: 8: var612: storage class: Function 615: OpVariable: 8: var615: storage class: Function 616: OpVariable: 8: var616: storage class: Function 622: OpVariable: 8: var622: storage class: Function 624: OpVariable: 8: var624: storage class: Function 634: OpVariable: 8: var634: storage class: Function 637: OpVariable: 66: var637: storage class: Function 567: OpLoad: 6: tmp567 << 274 568: OpFMul: 6: tmp568 << 567, 90 OpStore: : 568 >> 566 570: OpLoad: 27: tmp570 << 75 573: OpLoad: 7: tmp573 << 572 574: OpVectorShuffle: 27: tmp574 << 573, 573, 0, 1 575: OpVectorTimesScalar: 27: tmp575 << 574, 90 576: OpFSub: 27: tmp576 << 570, 575 577: OpAccessChain: 273: 572[102] 578: OpLoad: 6: tmp578 << 577 579: OpCompositeConstruct: 27: tmp579 << 578, 578 580: OpFDiv: 27: tmp580 << 576, 579 OpStore: : 580 >> 569 583: OpLoad: 6: tmp583 << 274 584: OpExtInst(13): 6: tmp584 << 583 585: OpFMul: 6: tmp585 << 90, 584 586: OpFAdd: 6: tmp586 << 582, 585 588: OpLoad: 6: tmp588 << 274 589: OpFMul: 6: tmp589 << 588, 90 590: OpFAdd: 6: tmp590 << 587, 589 591: OpCompositeConstruct: 7: tmp591 << 174, 586, 590 OpStore: : 591 >> 581 593: OpLoad: 27: tmp593 << 569 594: OpCompositeExtract: 6: tmp594 << 593, 0 595: OpCompositeExtract: 6: tmp595 << 593, 1 596: OpCompositeConstruct: 7: tmp596 << 594, 595, 88 597: OpExtInst(69): 7: tmp597 << 596 OpStore: : 597 >> 592 600: OpLoad: 7: tmp600 << 581 OpStore: : 600 >> 599 602: OpLoad: 7: tmp602 << 592 OpStore: : 602 >> 601 603: OpFunctionCall: 27: tmp603(599, 601) OpStore: : 603 >> 598 605: OpLoad: 7: tmp605 << 581 606: OpAccessChain: 16: 598[99] 607: OpLoad: 6: tmp607 << 606 608: OpLoad: 7: tmp608 << 592 609: OpVectorTimesScalar: 7: tmp609 << 608, 607 610: OpFAdd: 7: tmp610 << 605, 609 OpStore: : 610 >> 604 613: OpLoad: 7: tmp613 << 604 OpStore: : 613 >> 612 614: OpFunctionCall: 7: tmp614(612) OpStore: : 614 >> 611 617: OpAccessChain: 16: 598[99] 618: OpLoad: 6: tmp618 << 617 619: OpFOrdLessThan: 187: tmp619 << 618, 308 OpSelectionMerge: (merge: 621) OpBranchConditional: if(619) then branch to 620, else branch to 627 620: OpLabel: 623: OpLoad: 7: tmp623 << 604 OpStore: : 623 >> 622 625: OpLoad: 7: tmp625 << 611 OpStore: : 625 >> 624 626: OpFunctionCall: 7: tmp626(622, 624) OpStore: : 626 >> 616 OpBranch: to 621 627: OpLabel: 628: OpLoad: 27: tmp628 << 569 629: OpExtInst(66): 6: tmp629 << 628 630: OpFSub: 6: tmp630 << 88, 629 631: OpFMul: 6: tmp631 << 385, 630 632: OpCompositeConstruct: 7: tmp632 << 631, 631, 631 OpStore: : 632 >> 616 OpBranch: to 621 621: OpLabel: 633: OpLoad: 7: tmp633 << 616 OpStore: : 633 >> 615 635: OpLoad: 6: tmp635 << 299 636: OpConvertFToS: 65: tmp636 << 635 OpStore: : 636 >> 637 638: OpFunctionCall: 7: tmp638(637) OpStore: : 638 >> 634 639: OpLoad: 7: tmp639 << 634 640: OpLoad: 7: tmp640 << 615 641: OpFMul: 7: tmp641 << 640, 639 OpStore: : 641 >> 615 642: OpAccessChain: 16: 598[102] 643: OpLoad: 6: tmp643 << 642 644: OpExtInst(26): 6: tmp644 << 643, 267 645: OpLoad: 7: tmp645 << 615 646: OpCompositeConstruct: 7: tmp646 << 644, 644, 644 647: OpFAdd: 7: tmp647 << 645, 646 OpStore: : 647 >> 615 648: OpLoad: 7: tmp648 << 615 649: OpExtInst(31): 7: tmp649 << 648 650: OpCompositeExtract: 6: tmp650 << 649, 0 651: OpCompositeExtract: 6: tmp651 << 649, 1 652: OpCompositeExtract: 6: tmp652 << 649, 2 653: OpCompositeConstruct: 71: tmp653 << 650, 651, 652, 88 OpStore: : 653 >> 74 OpReturn: OpFunctionEnd: Linking the instructions Initial Disassembly: Module Info: OpSource: : ESSL ver 310 1: OpExtInstImport: : GLSL.std.450 OpMemoryModel: : addressing: Logical, memory: GLSL450 Capabilities: OpCapability: : Shader Inputs: 656: OpVariable: FloatVector4*: gl_FragCoord: storage class: Input Decorators: BuiltIn(FragCoord) Outputs: 664: OpVariable: FloatVector4*: finalColor: storage class: Output Uniform Constants: 274: OpVariable: Float*: iTime: storage class: UniformConstant 572: OpVariable: FloatVector3*: iResolution: storage class: UniformConstant 667: OpVariable: FloatVector4*: iMouse: storage class: UniformConstant 668: OpVariable: FloatVector4*: iDate: storage class: UniformConstant 669: OpVariable: Float*: iFrame: storage class: UniformConstant 673: OpVariable: FloatVector3[4]*: iChannelResolution: storage class: UniformConstant Textures: 677: OpVariable: SampledImage(Image(Float))*: iChannel0: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 678: OpVariable: SampledImage(Image(Float))*: iChannel1: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 679: OpVariable: SampledImage(Image(Float))*: iChannel2: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 680: OpVariable: SampledImage(Image(Float))*: iChannel3: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) Entry Points: 4: OpEntryPoint: : main, execution model: Fragment, Function: Void main(), OriginLowerLeft Constants: 80: OpConstant: Float const80 = 0.408248 81: OpConstant: Float const81 = 0.816497 82: OpConstantComposite: FloatVector3 const82 = {0.408248, 0.816497, 0.408248} 84: OpConstant: Float const84 = -0.408248 85: OpConstant: Float const85 = -0.816497 86: OpConstantComposite: FloatVector3 const86 = {-0.408248, 0.408248, -0.816497} 88: OpConstant: Float const88 = 1 89: OpConstant: Float const89 = 0.8 90: OpConstant: Float const90 = 0.5 91: OpConstantComposite: FloatVector3 const91 = {1, 0.8, 0.5} 93: OpConstant: Float const93 = 0.6 94: OpConstantComposite: FloatVector3 const94 = {0.6, 0.8, 1} 99: OpConstant: UInt const99 = 0 102: OpConstant: UInt const102 = 1 108: OpConstant: UInt const108 = 2 126: OpConstant: Float const126 = 0.333333 134: OpConstant: Float const134 = 2 174: OpConstant: Float const174 = 0 199: OpConstant: Float const199 = 9999 200: OpConstantComposite: FloatVector2 const200 = {9999, 0} 206: OpConstant: Float const206 = 6 207: OpConstantComposite: FloatVector2 const207 = {6, 6} 214: OpConstant: Float const214 = 1.9 215: OpConstant: Float const215 = 6.78 216: OpConstantComposite: FloatVector2 const216 = {1.9, 6.78} 229: OpConstant: Float const229 = 9 240: OpConstant: Float const240 = 0.35 242: OpConstant: Float const242 = 9999.9 243: OpConstantComposite: FloatVector2 const243 = {9999.9, 0} 245: OpConstant: Float const245 = -999 250: OpConstant: Int const250 = 0 257: OpConstant: Int const257 = 5 Decorators: RelaxedPrecision 267: OpConstant: Float const267 = 3 271: OpConstant: Int const271 = 1 277: OpConstant: Float const277 = 5 279: OpConstant: Float const279 = 0.4 284: OpConstant: Float const284 = 8 292: OpConstant: Float const292 = 7 308: OpConstant: Float const308 = 20 317: OpConstant: Int const317 = 100 Decorators: RelaxedPrecision 329: OpConstant: Float const329 = 0.001 343: OpConstant: Float const343 = 100 348: OpConstant: Float const348 = 0.002 362: OpConstant: Int const362 = 50 385: OpConstant: Float const385 = 0.1 390: OpConstantComposite: FloatVector2 const390 = {0.001, 0} 435: OpConstant: Float const435 = 0.01 436: OpConstantComposite: FloatVector3 const436 = {0.01, 0.01, 0.01} 444: OpConstant: Int const444 = 2 481: OpConstant: Float const481 = 0.7 489: OpConstantComposite: FloatVector3 const489 = {0, 0, 0} 495: OpConstantComposite: FloatVector3 const495 = {0, 0, 1} 501: OpConstantComposite: FloatVector3 const501 = {0, 1, 0} 504: OpConstant: Int const504 = 3 508: OpConstantComposite: FloatVector3 const508 = {0, 1, 1} 511: OpConstant: Int const511 = 4 515: OpConstantComposite: FloatVector3 const515 = {1, 0, 0} 521: OpConstantComposite: FloatVector3 const521 = {1, 0, 1} 524: OpConstant: Int const524 = 6 529: OpConstant: Int const529 = 7 533: OpConstantComposite: FloatVector3 const533 = {1, 1, 1} 536: OpConstant: Int const536 = 8 540: OpConstant: Float const540 = 0.425 541: OpConstant: Float const541 = 0.56 542: OpConstant: Float const542 = 0.9 543: OpConstantComposite: FloatVector3 const543 = {0.425, 0.56, 0.9} 546: OpConstant: Int const546 = 9 550: OpConstantComposite: FloatVector3 const550 = {0.5, 0.6, 0.6} 553: OpConstant: Int const553 = 10 559: OpConstant: Int const559 = 11 563: OpConstantComposite: FloatVector3 const563 = {0.5, 0.8, 0.9} 582: OpConstant: Float const582 = -1 587: OpConstant: Float const587 = -5 670: OpConstant: UInt const670 = 4 681: OpConstant: Int const681 = 64 Decorators: RelaxedPrecision 682: OpConstant: Float const682 = 0.0001 Private Global Variables: 79: OpVariable: FloatVector3*: lDir0: storage class: Private 83: OpVariable: FloatVector3*: lDir1: storage class: Private 87: OpVariable: FloatVector3*: lCol0: storage class: Private 92: OpVariable: FloatVector3*: lCol1: storage class: Private 299: OpVariable: Float*: NumCol: storage class: Private Disassembled Code: 4: OpFunction: Void main() 654: OpVariable: FloatVector4*: color: storage class: Function 657: OpVariable: FloatVector4*: param657: storage class: Function 658: OpVariable: FloatVector2*: param658: storage class: Function 5: lb5: OpStore: : const82 >> lDir0 OpStore: : const86 >> lDir1 OpStore: : const91 >> lCol0 OpStore: : const94 >> lCol1 659: OpLoad: FloatVector4: tmp659 << gl_FragCoord 660: OpVectorShuffle: FloatVector2: tmp660 << tmp659, tmp659, 0, 1 OpStore: : tmp660 >> param658 661: OpFunctionCall: Void: mainImage(vf4;vf2;(param657, param658) 662: OpLoad: FloatVector4: tmp662 << param657 OpStore: : tmp662 >> color 665: OpLoad: FloatVector4: tmp665 << color OpStore: : tmp665 >> finalColor OpReturn: 11: OpFunction: Float sdCross(vf3;(FloatVector3* p) 97: OpVariable: FloatVector3*: d: storage class: Function 12: lb12: 95: OpLoad: FloatVector3: tmp95 << p 96: OpExtInst(FAbs): FloatVector3: tmp96 << tmp95 OpStore: : tmp96 >> p 100: OpAccessChain: Float*: p[0] 101: OpLoad: Float: tmp101 << p[0] 103: OpAccessChain: Float*: p[1] 104: OpLoad: Float: tmp104 << p[1] 105: OpExtInst(FMax): Float: tmp105 << tmp101, tmp104 106: OpAccessChain: Float*: p[1] 107: OpLoad: Float: tmp107 << p[1] 109: OpAccessChain: Float*: p[2] 110: OpLoad: Float: tmp110 << p[2] 111: OpExtInst(FMax): Float: tmp111 << tmp107, tmp110 112: OpAccessChain: Float*: p[2] 113: OpLoad: Float: tmp113 << p[2] 114: OpAccessChain: Float*: p[0] 115: OpLoad: Float: tmp115 << p[0] 116: OpExtInst(FMax): Float: tmp116 << tmp113, tmp115 117: OpCompositeConstruct: FloatVector3: tmp117 << tmp105, tmp111, tmp116 OpStore: : tmp117 >> d 118: OpAccessChain: Float*: d[0] 119: OpLoad: Float: tmp119 << d[0] 120: OpAccessChain: Float*: d[1] 121: OpLoad: Float: tmp121 << d[1] 122: OpAccessChain: Float*: d[2] 123: OpLoad: Float: tmp123 << d[2] 124: OpExtInst(FMin): Float: tmp124 << tmp121, tmp123 125: OpExtInst(FMin): Float: tmp125 << tmp119, tmp124 127: OpFSub: Float: tmp127 << tmp125, const126 OpReturnValue: : << tmp127 14: OpFunction: Float sdCrossRep(vf3;(FloatVector3* p) 130: OpVariable: FloatVector3*: q: storage class: Function 139: OpVariable: FloatVector3*: param139: storage class: Function 15: lb15: 131: OpLoad: FloatVector3: tmp131 << p 132: OpCompositeConstruct: FloatVector3: tmp132 << const88, const88, const88 133: OpFAdd: FloatVector3: tmp133 << tmp131, tmp132 135: OpCompositeConstruct: FloatVector3: tmp135 << const134, const134, const134 136: OpFMod: FloatVector3: tmp136 << tmp133, tmp135 137: OpCompositeConstruct: FloatVector3: tmp137 << const88, const88, const88 138: OpFSub: FloatVector3: tmp138 << tmp136, tmp137 OpStore: : tmp138 >> q 140: OpLoad: FloatVector3: tmp140 << q OpStore: : tmp140 >> param139 141: OpFunctionCall: Float: sdCross(vf3;(param139) OpReturnValue: : << sdCross(vf3; 20: OpFunction: Float sdCrossRepScale(vf3;f1;(FloatVector3* p, Float* s) 147: OpVariable: FloatVector3*: param147: storage class: Function 21: lb21: 144: OpLoad: FloatVector3: tmp144 << p 145: OpLoad: Float: tmp145 << s 146: OpVectorTimesScalar: FloatVector3: tmp146 << tmp144, tmp145 OpStore: : tmp146 >> param147 148: OpFunctionCall: Float: sdCrossRep(vf3;(param147) 149: OpLoad: Float: tmp149 << s 150: OpFDiv: Float: tmp150 << sdCrossRep(vf3;, tmp149 OpReturnValue: : << tmp150 25: OpFunction: Float differenceSDF(f1;f1;(Float* distA, Float* distB) 26: lb26: 153: OpLoad: Float: tmp153 << distA 154: OpLoad: Float: tmp154 << distB 155: OpFNegate: Float: tmp155 << tmp154 156: OpExtInst(FMax): Float: tmp156 << tmp153, tmp155 OpReturnValue: : << tmp156 32: OpFunction: Float sdCylinder(vf3;vf2;(FloatVector3* p, FloatVector2* h) 159: OpVariable: FloatVector2*: d: storage class: Function 33: lb33: 160: OpLoad: FloatVector3: tmp160 << p 161: OpVectorShuffle: FloatVector2: tmp161 << tmp160, tmp160, 0, 2 162: OpExtInst(Length): Float: tmp162 << tmp161 163: OpAccessChain: Float*: p[1] 164: OpLoad: Float: tmp164 << p[1] 165: OpCompositeConstruct: FloatVector2: tmp165 << tmp162, tmp164 166: OpExtInst(FAbs): FloatVector2: tmp166 << tmp165 167: OpLoad: FloatVector2: tmp167 << h 168: OpFSub: FloatVector2: tmp168 << tmp166, tmp167 OpStore: : tmp168 >> d 169: OpAccessChain: Float*: d[0] 170: OpLoad: Float: tmp170 << d[0] 171: OpAccessChain: Float*: d[1] 172: OpLoad: Float: tmp172 << d[1] 173: OpExtInst(FMax): Float: tmp173 << tmp170, tmp172 175: OpExtInst(FMin): Float: tmp175 << tmp173, const174 176: OpLoad: FloatVector2: tmp176 << d 177: OpCompositeConstruct: FloatVector2: tmp177 << const174, const174 178: OpExtInst(FMax): FloatVector2: tmp178 << tmp176, tmp177 179: OpExtInst(Length): Float: tmp179 << tmp178 180: OpFAdd: Float: tmp180 << tmp175, tmp179 OpReturnValue: : << tmp180 37: OpFunction: FloatVector2 opU(vf2;vf2;(FloatVector2* d1, FloatVector2* d2) 191: OpVariable: FloatVector2*: resp: storage class: Function 38: lb38: 183: OpAccessChain: Float*: d1[0] 184: OpLoad: Float: tmp184 << d1[0] 185: OpAccessChain: Float*: d2[0] 186: OpLoad: Float: tmp186 << d2[0] 188: OpFOrdLessThan: Bool: tmp188 << tmp184, tmp186 OpSelectionMerge: (merge: lb190) OpBranchConditional: if(tmp188) then branch to lb189, else branch to lb193 189: lb189: 192: OpLoad: FloatVector2: tmp192 << d1 OpStore: : tmp192 >> resp OpBranch: to lb190 193: lb193: 194: OpLoad: FloatVector2: tmp194 << d2 OpStore: : tmp194 >> resp OpBranch: to lb190 190: lb190: 195: OpLoad: FloatVector2: tmp195 << resp OpReturnValue: : << tmp195 40: OpFunction: Float diso(vf3;(FloatVector3* p) 198: OpVariable: FloatVector2*: res: storage class: Function 205: OpVariable: Float*: sdcy1: storage class: Function 208: OpVariable: FloatVector3*: param208: storage class: Function 211: OpVariable: FloatVector2*: param211: storage class: Function 213: OpVariable: Float*: sdcy2: storage class: Function 217: OpVariable: FloatVector3*: param217: storage class: Function 220: OpVariable: FloatVector2*: param220: storage class: Function 222: OpVariable: Float*: dif1: storage class: Function 223: OpVariable: Float*: param223: storage class: Function 225: OpVariable: Float*: param225: storage class: Function 231: OpVariable: FloatVector2*: param231: storage class: Function 233: OpVariable: FloatVector2*: param233: storage class: Function 41: lb41: OpStore: : const200 >> res 201: OpAccessChain: Float*: p[2] 202: OpLoad: Float: tmp202 << p[2] 203: OpFMod: Float: tmp203 << tmp202, const134 204: OpAccessChain: Float*: p[2] OpStore: : tmp203 >> p[2] 209: OpLoad: FloatVector3: tmp209 << p 210: OpVectorShuffle: FloatVector3: tmp210 << tmp209, tmp209, 1, 2, 0 OpStore: : tmp210 >> param208 OpStore: : const207 >> param211 212: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param208, param211) OpStore: : sdCylinder(vf3;vf2; >> sdcy1 218: OpLoad: FloatVector3: tmp218 << p 219: OpVectorShuffle: FloatVector3: tmp219 << tmp218, tmp218, 1, 2, 0 OpStore: : tmp219 >> param217 OpStore: : const216 >> param220 221: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param217, param220) OpStore: : sdCylinder(vf3;vf2; >> sdcy2 224: OpLoad: Float: tmp224 << sdcy1 OpStore: : tmp224 >> param223 226: OpLoad: Float: tmp226 << sdcy2 OpStore: : tmp226 >> param225 227: OpFunctionCall: Float: differenceSDF(f1;f1;(param223, param225) OpStore: : differenceSDF(f1;f1; >> dif1 228: OpLoad: Float: tmp228 << dif1 230: OpCompositeConstruct: FloatVector2: tmp230 << tmp228, const229 232: OpLoad: FloatVector2: tmp232 << res OpStore: : tmp232 >> param231 OpStore: : tmp230 >> param233 234: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param231, param233) OpStore: : opU(vf2;vf2; >> res 235: OpAccessChain: Float*: res[0] 236: OpLoad: Float: tmp236 << res[0] OpReturnValue: : << tmp236 43: OpFunction: Float DE(vf3;(FloatVector3* p) 239: OpVariable: Float*: scale: storage class: Function 241: OpVariable: FloatVector2*: res: storage class: Function 244: OpVariable: Float*: dist: storage class: Function 246: OpVariable: FloatVector3*: param246: storage class: Function 249: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 260: OpVariable: FloatVector3*: param260: storage class: Function 262: OpVariable: Float*: param262: storage class: Function 286: OpVariable: FloatVector2*: param286: storage class: Function 288: OpVariable: FloatVector2*: param288: storage class: Function 294: OpVariable: FloatVector2*: param294: storage class: Function 296: OpVariable: FloatVector2*: param296: storage class: Function 44: lb44: OpStore: : const240 >> scale OpStore: : const243 >> res OpStore: : const245 >> dist 247: OpLoad: FloatVector3: tmp247 << p OpStore: : tmp247 >> param246 248: OpFunctionCall: Float: diso(vf3;(param246) OpStore: : diso(vf3; >> dist OpStore: : const250 >> i OpBranch: to lb251 251: lb251: OpLoopMerge: (merge: lb253, continue: lb254) OpBranch: to lb255 255: lb255: 256: OpLoad: Int: tmp256 << i Decorators: RelaxedPrecision 258: OpSLessThan: Bool: tmp258 << tmp256, const257 OpBranchConditional: if(tmp258) then branch to lb252, else branch to lb253 252: lb252: 259: OpLoad: Float: tmp259 << dist 261: OpLoad: FloatVector3: tmp261 << p OpStore: : tmp261 >> param260 263: OpLoad: Float: tmp263 << scale OpStore: : tmp263 >> param262 264: OpFunctionCall: Float: sdCrossRepScale(vf3;f1;(param260, param262) 265: OpFNegate: Float: tmp265 << sdCrossRepScale(vf3;f1; 266: OpExtInst(FMax): Float: tmp266 << tmp259, tmp265 OpStore: : tmp266 >> dist 268: OpLoad: Float: tmp268 << scale 269: OpFMul: Float: tmp269 << tmp268, const267 OpStore: : tmp269 >> scale OpBranch: to lb254 254: lb254: 270: OpLoad: Int: tmp270 << i Decorators: RelaxedPrecision 272: OpIAdd: Int: tmp272 << tmp270, const271 Decorators: RelaxedPrecision OpStore: : tmp272 >> i OpBranch: to lb251 253: lb253: 275: OpLoad: Float: tmp275 << iTime 276: OpExtInst(Floor): Float: tmp276 << tmp275 278: OpFMod: Float: tmp278 << tmp276, const277 280: OpFOrdGreaterThan: Bool: tmp280 << tmp278, const279 OpSelectionMerge: (merge: lb282) OpBranchConditional: if(tmp280) then branch to lb281, else branch to lb290 281: lb281: 283: OpLoad: Float: tmp283 << dist 285: OpCompositeConstruct: FloatVector2: tmp285 << tmp283, const284 287: OpLoad: FloatVector2: tmp287 << res OpStore: : tmp287 >> param286 OpStore: : tmp285 >> param288 289: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param286, param288) OpStore: : opU(vf2;vf2; >> res OpBranch: to lb282 290: lb290: 291: OpLoad: Float: tmp291 << dist 293: OpCompositeConstruct: FloatVector2: tmp293 << tmp291, const292 295: OpLoad: FloatVector2: tmp295 << res OpStore: : tmp295 >> param294 OpStore: : tmp293 >> param296 297: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param294, param296) OpStore: : opU(vf2;vf2; >> res OpBranch: to lb282 282: lb282: 300: OpAccessChain: Float*: res[1] 301: OpLoad: Float: tmp301 << res[1] OpStore: : tmp301 >> NumCol 302: OpAccessChain: Float*: res[0] 303: OpLoad: Float: tmp303 << res[0] OpReturnValue: : << tmp303 48: OpFunction: FloatVector2 march(vf3;vf3;(FloatVector3* ro, FloatVector3* rd) 306: OpVariable: Float*: t: storage class: Function 307: OpVariable: Float*: d: storage class: Function 309: OpVariable: Float*: it: storage class: Function 310: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 324: OpVariable: FloatVector3*: param324: storage class: Function 49: lb49: OpStore: : const174 >> t OpStore: : const308 >> d OpStore: : const174 >> it OpStore: : const250 >> i OpBranch: to lb311 311: lb311: OpLoopMerge: (merge: lb313, continue: lb314) OpBranch: to lb315 315: lb315: 316: OpLoad: Int: tmp316 << i Decorators: RelaxedPrecision 318: OpSLessThan: Bool: tmp318 << tmp316, const317 OpBranchConditional: if(tmp318) then branch to lb312, else branch to lb313 312: lb312: 319: OpLoad: FloatVector3: tmp319 << ro 320: OpLoad: Float: tmp320 << t 321: OpLoad: FloatVector3: tmp321 << rd 322: OpVectorTimesScalar: FloatVector3: tmp322 << tmp321, tmp320 323: OpFAdd: FloatVector3: tmp323 << tmp319, tmp322 OpStore: : tmp323 >> param324 325: OpFunctionCall: Float: DE(vf3;(param324) OpStore: : DE(vf3; >> d 326: OpLoad: Float: tmp326 << t 327: OpFAdd: Float: tmp327 << tmp326, DE(vf3; OpStore: : tmp327 >> t 328: OpLoad: Float: tmp328 << d 330: OpFOrdLessThan: Bool: tmp330 << tmp328, const329 331: OpLoad: Float: tmp331 << t 332: OpFOrdGreaterThan: Bool: tmp332 << tmp331, const308 333: OpLogicalOr: Bool: tmp333 << tmp330, tmp332 OpSelectionMerge: (merge: lb335) OpBranchConditional: if(tmp333) then branch to lb334, else branch to lb335 334: lb334: OpBranch: to lb313 335: lb335: 337: OpLoad: Float: tmp337 << it 338: OpFAdd: Float: tmp338 << tmp337, const88 OpStore: : tmp338 >> it OpBranch: to lb314 314: lb314: 339: OpLoad: Int: tmp339 << i Decorators: RelaxedPrecision 340: OpIAdd: Int: tmp340 << tmp339, const271 Decorators: RelaxedPrecision OpStore: : tmp340 >> i OpBranch: to lb311 313: lb313: 341: OpLoad: Float: tmp341 << t 342: OpLoad: Float: tmp342 << it 344: OpFDiv: Float: tmp344 << tmp342, const343 345: OpCompositeConstruct: FloatVector2: tmp345 << tmp341, tmp344 OpReturnValue: : << tmp345 54: OpFunction: Float getShadow(vf3;vf3;vf3;(FloatVector3* p, FloatVector3* n, FloatVector3* ld) 353: OpVariable: Float*: t: storage class: Function 354: OpVariable: Float*: d: storage class: Function 355: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 369: OpVariable: FloatVector3*: param369: storage class: Function 55: lb55: 349: OpLoad: FloatVector3: tmp349 << n 350: OpVectorTimesScalar: FloatVector3: tmp350 << tmp349, const348 351: OpLoad: FloatVector3: tmp351 << p 352: OpFAdd: FloatVector3: tmp352 << tmp351, tmp350 OpStore: : tmp352 >> p OpStore: : const174 >> t OpStore: : const308 >> d OpStore: : const250 >> i OpBranch: to lb356 356: lb356: OpLoopMerge: (merge: lb358, continue: lb359) OpBranch: to lb360 360: lb360: 361: OpLoad: Int: tmp361 << i Decorators: RelaxedPrecision 363: OpSLessThan: Bool: tmp363 << tmp361, const362 OpBranchConditional: if(tmp363) then branch to lb357, else branch to lb358 357: lb357: 364: OpLoad: FloatVector3: tmp364 << p 365: OpLoad: Float: tmp365 << t 366: OpLoad: FloatVector3: tmp366 << ld 367: OpVectorTimesScalar: FloatVector3: tmp367 << tmp366, tmp365 368: OpFAdd: FloatVector3: tmp368 << tmp364, tmp367 OpStore: : tmp368 >> param369 370: OpFunctionCall: Float: DE(vf3;(param369) OpStore: : DE(vf3; >> d 371: OpLoad: Float: tmp371 << t 372: OpFAdd: Float: tmp372 << tmp371, DE(vf3; OpStore: : tmp372 >> t 373: OpLoad: Float: tmp373 << d 374: OpFOrdLessThan: Bool: tmp374 << tmp373, const329 375: OpLoad: Float: tmp375 << t 376: OpFOrdGreaterThan: Bool: tmp376 << tmp375, const267 377: OpLogicalOr: Bool: tmp377 << tmp374, tmp376 OpSelectionMerge: (merge: lb379) OpBranchConditional: if(tmp377) then branch to lb378, else branch to lb379 378: lb378: OpBranch: to lb358 379: lb379: OpBranch: to lb359 359: lb359: 381: OpLoad: Int: tmp381 << i Decorators: RelaxedPrecision 382: OpIAdd: Int: tmp382 << tmp381, const271 Decorators: RelaxedPrecision OpStore: : tmp382 >> i OpBranch: to lb356 358: lb358: 383: OpLoad: Float: tmp383 << t 384: OpFOrdLessThanEqual: Bool: tmp384 << tmp383, const267 386: OpSelect: Float: tmp386 << tmp384, const385, const88 OpReturnValue: : << tmp386 58: OpFunction: FloatVector3 getNorm(vf3;(FloatVector3* p) 389: OpVariable: FloatVector2*: e: storage class: Function 395: OpVariable: FloatVector3*: param395: storage class: Function 401: OpVariable: FloatVector3*: param401: storage class: Function 408: OpVariable: FloatVector3*: param408: storage class: Function 414: OpVariable: FloatVector3*: param414: storage class: Function 421: OpVariable: FloatVector3*: param421: storage class: Function 427: OpVariable: FloatVector3*: param427: storage class: Function 59: lb59: OpStore: : const390 >> e 391: OpLoad: FloatVector3: tmp391 << p 392: OpLoad: FloatVector2: tmp392 << e 393: OpVectorShuffle: FloatVector3: tmp393 << tmp392, tmp392, 0, 1, 1 394: OpFAdd: FloatVector3: tmp394 << tmp391, tmp393 OpStore: : tmp394 >> param395 396: OpFunctionCall: Float: DE(vf3;(param395) 397: OpLoad: FloatVector3: tmp397 << p 398: OpLoad: FloatVector2: tmp398 << e 399: OpVectorShuffle: FloatVector3: tmp399 << tmp398, tmp398, 0, 1, 1 400: OpFSub: FloatVector3: tmp400 << tmp397, tmp399 OpStore: : tmp400 >> param401 402: OpFunctionCall: Float: DE(vf3;(param401) 403: OpFSub: Float: tmp403 << DE(vf3;, DE(vf3; 404: OpLoad: FloatVector3: tmp404 << p 405: OpLoad: FloatVector2: tmp405 << e 406: OpVectorShuffle: FloatVector3: tmp406 << tmp405, tmp405, 1, 0, 1 407: OpFAdd: FloatVector3: tmp407 << tmp404, tmp406 OpStore: : tmp407 >> param408 409: OpFunctionCall: Float: DE(vf3;(param408) 410: OpLoad: FloatVector3: tmp410 << p 411: OpLoad: FloatVector2: tmp411 << e 412: OpVectorShuffle: FloatVector3: tmp412 << tmp411, tmp411, 1, 0, 1 413: OpFSub: FloatVector3: tmp413 << tmp410, tmp412 OpStore: : tmp413 >> param414 415: OpFunctionCall: Float: DE(vf3;(param414) 416: OpFSub: Float: tmp416 << DE(vf3;, DE(vf3; 417: OpLoad: FloatVector3: tmp417 << p 418: OpLoad: FloatVector2: tmp418 << e 419: OpVectorShuffle: FloatVector3: tmp419 << tmp418, tmp418, 1, 1, 0 420: OpFAdd: FloatVector3: tmp420 << tmp417, tmp419 OpStore: : tmp420 >> param421 422: OpFunctionCall: Float: DE(vf3;(param421) 423: OpLoad: FloatVector3: tmp423 << p 424: OpLoad: FloatVector2: tmp424 << e 425: OpVectorShuffle: FloatVector3: tmp425 << tmp424, tmp424, 1, 1, 0 426: OpFSub: FloatVector3: tmp426 << tmp423, tmp425 OpStore: : tmp426 >> param427 428: OpFunctionCall: Float: DE(vf3;(param427) 429: OpFSub: Float: tmp429 << DE(vf3;, DE(vf3; 430: OpCompositeConstruct: FloatVector3: tmp430 << tmp403, tmp416, tmp429 431: OpExtInst(Normalize): FloatVector3: tmp431 << tmp430 OpReturnValue: : << tmp431 63: OpFunction: FloatVector3 light(vf3;vf3;(FloatVector3* p, FloatVector3* n) 434: OpVariable: FloatVector3*: col: storage class: Function 437: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 446: OpVariable: FloatVector3*: ld: storage class: Function 454: OpVariable: Float*: diff: storage class: Function 459: OpVariable: FloatVector3*: param459: storage class: Function 461: OpVariable: FloatVector3*: param461: storage class: Function 463: OpVariable: FloatVector3*: param463: storage class: Function 64: lb64: OpStore: : const436 >> col OpStore: : const250 >> i OpBranch: to lb438 438: lb438: OpLoopMerge: (merge: lb440, continue: lb441) OpBranch: to lb442 442: lb442: 443: OpLoad: Int: tmp443 << i Decorators: RelaxedPrecision 445: OpSLessThan: Bool: tmp445 << tmp443, const444 OpBranchConditional: if(tmp445) then branch to lb439, else branch to lb440 439: lb439: 447: OpLoad: Int: tmp447 << i Decorators: RelaxedPrecision 448: OpIEqual: Bool: tmp448 << tmp447, const250 449: OpLoad: FloatVector3: tmp449 << lDir0 450: OpLoad: FloatVector3: tmp450 << lDir1 452: OpCompositeConstruct: BoolVector3: tmp452 << tmp448, tmp448, tmp448 453: OpSelect: FloatVector3: tmp453 << tmp452, tmp449, tmp450 OpStore: : tmp453 >> ld 455: OpLoad: FloatVector3: tmp455 << n 456: OpLoad: FloatVector3: tmp456 << ld 457: OpDot: Float: tmp457 << tmp455, tmp456 458: OpExtInst(FMax): Float: tmp458 << tmp457, const174 OpStore: : tmp458 >> diff 460: OpLoad: FloatVector3: tmp460 << p OpStore: : tmp460 >> param459 462: OpLoad: FloatVector3: tmp462 << n OpStore: : tmp462 >> param461 464: OpLoad: FloatVector3: tmp464 << ld OpStore: : tmp464 >> param463 465: OpFunctionCall: Float: getShadow(vf3;vf3;vf3;(param459, param461, param463) 466: OpLoad: Float: tmp466 << diff 467: OpFMul: Float: tmp467 << tmp466, getShadow(vf3;vf3;vf3; OpStore: : tmp467 >> diff 468: OpLoad: Float: tmp468 << diff 469: OpLoad: Int: tmp469 << i Decorators: RelaxedPrecision 470: OpIEqual: Bool: tmp470 << tmp469, const250 471: OpLoad: FloatVector3: tmp471 << lCol0 472: OpLoad: FloatVector3: tmp472 << lCol1 473: OpCompositeConstruct: BoolVector3: tmp473 << tmp470, tmp470, tmp470 474: OpSelect: FloatVector3: tmp474 << tmp473, tmp471, tmp472 475: OpVectorTimesScalar: FloatVector3: tmp475 << tmp474, tmp468 476: OpLoad: FloatVector3: tmp476 << col 477: OpFAdd: FloatVector3: tmp477 << tmp476, tmp475 OpStore: : tmp477 >> col OpBranch: to lb441 441: lb441: 478: OpLoad: Int: tmp478 << i Decorators: RelaxedPrecision 479: OpIAdd: Int: tmp479 << tmp478, const271 Decorators: RelaxedPrecision OpStore: : tmp479 >> i OpBranch: to lb438 440: lb440: 480: OpLoad: FloatVector3: tmp480 << col 482: OpVectorTimesScalar: FloatVector3: tmp482 << tmp480, const481 OpReturnValue: : << tmp482 69: OpFunction: FloatVector3 getSphereColor(i1;(Int* i) 70: lb70: 485: OpLoad: Int: tmp485 << i Decorators: RelaxedPrecision 486: OpIEqual: Bool: tmp486 << tmp485, const250 OpSelectionMerge: (merge: lb488) OpBranchConditional: if(tmp486) then branch to lb487, else branch to lb488 487: lb487: OpReturnValue: : << const489 488: lb488: 491: OpLoad: Int: tmp491 << i Decorators: RelaxedPrecision 492: OpIEqual: Bool: tmp492 << tmp491, const271 OpSelectionMerge: (merge: lb494) OpBranchConditional: if(tmp492) then branch to lb493, else branch to lb494 493: lb493: OpReturnValue: : << const495 494: lb494: 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision 498: OpIEqual: Bool: tmp498 << tmp497, const444 OpSelectionMerge: (merge: lb500) OpBranchConditional: if(tmp498) then branch to lb499, else branch to lb500 499: lb499: OpReturnValue: : << const501 500: lb500: 503: OpLoad: Int: tmp503 << i Decorators: RelaxedPrecision 505: OpIEqual: Bool: tmp505 << tmp503, const504 OpSelectionMerge: (merge: lb507) OpBranchConditional: if(tmp505) then branch to lb506, else branch to lb507 506: lb506: OpReturnValue: : << const508 507: lb507: 510: OpLoad: Int: tmp510 << i Decorators: RelaxedPrecision 512: OpIEqual: Bool: tmp512 << tmp510, const511 OpSelectionMerge: (merge: lb514) OpBranchConditional: if(tmp512) then branch to lb513, else branch to lb514 513: lb513: OpReturnValue: : << const515 514: lb514: 517: OpLoad: Int: tmp517 << i Decorators: RelaxedPrecision 518: OpIEqual: Bool: tmp518 << tmp517, const257 OpSelectionMerge: (merge: lb520) OpBranchConditional: if(tmp518) then branch to lb519, else branch to lb520 519: lb519: OpReturnValue: : << const521 520: lb520: 523: OpLoad: Int: tmp523 << i Decorators: RelaxedPrecision 525: OpIEqual: Bool: tmp525 << tmp523, const524 OpSelectionMerge: (merge: lb527) OpBranchConditional: if(tmp525) then branch to lb526, else branch to lb527 526: lb526: OpBranch: to lb527 527: lb527: 528: OpLoad: Int: tmp528 << i Decorators: RelaxedPrecision 530: OpIEqual: Bool: tmp530 << tmp528, const529 OpSelectionMerge: (merge: lb532) OpBranchConditional: if(tmp530) then branch to lb531, else branch to lb532 531: lb531: OpReturnValue: : << const533 532: lb532: 535: OpLoad: Int: tmp535 << i Decorators: RelaxedPrecision 537: OpIEqual: Bool: tmp537 << tmp535, const536 OpSelectionMerge: (merge: lb539) OpBranchConditional: if(tmp537) then branch to lb538, else branch to lb539 538: lb538: OpReturnValue: : << const543 539: lb539: 545: OpLoad: Int: tmp545 << i Decorators: RelaxedPrecision 547: OpIEqual: Bool: tmp547 << tmp545, const546 OpSelectionMerge: (merge: lb549) OpBranchConditional: if(tmp547) then branch to lb548, else branch to lb549 548: lb548: OpReturnValue: : << const550 549: lb549: 552: OpLoad: Int: tmp552 << i Decorators: RelaxedPrecision 554: OpIEqual: Bool: tmp554 << tmp552, const553 OpSelectionMerge: (merge: lb556) OpBranchConditional: if(tmp554) then branch to lb555, else branch to lb556 555: lb555: OpReturnValue: : << const501 556: lb556: 558: OpLoad: Int: tmp558 << i Decorators: RelaxedPrecision 560: OpIEqual: Bool: tmp560 << tmp558, const559 OpSelectionMerge: (merge: lb562) OpBranchConditional: if(tmp560) then branch to lb561, else branch to lb562 561: lb561: OpReturnValue: : << const563 562: lb562: 565: OpUndef: FloatVector3: tmp565 << OpReturnValue: : << tmp565 76: OpFunction: Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) 566: OpVariable: Float*: time: storage class: Function 569: OpVariable: FloatVector2*: uv: storage class: Function 581: OpVariable: FloatVector3*: ro: storage class: Function 592: OpVariable: FloatVector3*: rd: storage class: Function 598: OpVariable: FloatVector2*: hit: storage class: Function 599: OpVariable: FloatVector3*: param599: storage class: Function 601: OpVariable: FloatVector3*: param601: storage class: Function 604: OpVariable: FloatVector3*: p: storage class: Function 611: OpVariable: FloatVector3*: nor: storage class: Function 612: OpVariable: FloatVector3*: param612: storage class: Function 615: OpVariable: FloatVector3*: col: storage class: Function 616: OpVariable: FloatVector3*: var616: storage class: Function 622: OpVariable: FloatVector3*: param622: storage class: Function 624: OpVariable: FloatVector3*: param624: storage class: Function 634: OpVariable: FloatVector3*: colobj: storage class: Function 637: OpVariable: Int*: param637: storage class: Function 77: lb77: 567: OpLoad: Float: tmp567 << iTime 568: OpFMul: Float: tmp568 << tmp567, const90 OpStore: : tmp568 >> time 570: OpLoad: FloatVector2: tmp570 << fragCoord 573: OpLoad: FloatVector3: tmp573 << iResolution 574: OpVectorShuffle: FloatVector2: tmp574 << tmp573, tmp573, 0, 1 575: OpVectorTimesScalar: FloatVector2: tmp575 << tmp574, const90 576: OpFSub: FloatVector2: tmp576 << tmp570, tmp575 577: OpAccessChain: Float*: iResolution[1] 578: OpLoad: Float: tmp578 << iResolution[1] 579: OpCompositeConstruct: FloatVector2: tmp579 << tmp578, tmp578 580: OpFDiv: FloatVector2: tmp580 << tmp576, tmp579 OpStore: : tmp580 >> uv 583: OpLoad: Float: tmp583 << iTime 584: OpExtInst(Sin): Float: tmp584 << tmp583 585: OpFMul: Float: tmp585 << const90, tmp584 586: OpFAdd: Float: tmp586 << const582, tmp585 588: OpLoad: Float: tmp588 << iTime 589: OpFMul: Float: tmp589 << tmp588, const90 590: OpFAdd: Float: tmp590 << const587, tmp589 591: OpCompositeConstruct: FloatVector3: tmp591 << const174, tmp586, tmp590 OpStore: : tmp591 >> ro 593: OpLoad: FloatVector2: tmp593 << uv 594: OpCompositeExtract: Float: tmp594 << tmp593, 0 595: OpCompositeExtract: Float: tmp595 << tmp593, 1 596: OpCompositeConstruct: FloatVector3: tmp596 << tmp594, tmp595, const88 597: OpExtInst(Normalize): FloatVector3: tmp597 << tmp596 OpStore: : tmp597 >> rd 600: OpLoad: FloatVector3: tmp600 << ro OpStore: : tmp600 >> param599 602: OpLoad: FloatVector3: tmp602 << rd OpStore: : tmp602 >> param601 603: OpFunctionCall: FloatVector2: march(vf3;vf3;(param599, param601) OpStore: : march(vf3;vf3; >> hit 605: OpLoad: FloatVector3: tmp605 << ro 606: OpAccessChain: Float*: hit[0] 607: OpLoad: Float: tmp607 << hit[0] 608: OpLoad: FloatVector3: tmp608 << rd 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp608, tmp607 610: OpFAdd: FloatVector3: tmp610 << tmp605, tmp609 OpStore: : tmp610 >> p 613: OpLoad: FloatVector3: tmp613 << p OpStore: : tmp613 >> param612 614: OpFunctionCall: FloatVector3: getNorm(vf3;(param612) OpStore: : getNorm(vf3; >> nor 617: OpAccessChain: Float*: hit[0] 618: OpLoad: Float: tmp618 << hit[0] 619: OpFOrdLessThan: Bool: tmp619 << tmp618, const308 OpSelectionMerge: (merge: lb621) OpBranchConditional: if(tmp619) then branch to lb620, else branch to lb627 620: lb620: 623: OpLoad: FloatVector3: tmp623 << p OpStore: : tmp623 >> param622 625: OpLoad: FloatVector3: tmp625 << nor OpStore: : tmp625 >> param624 626: OpFunctionCall: FloatVector3: light(vf3;vf3;(param622, param624) OpStore: : light(vf3;vf3; >> var616 OpBranch: to lb621 627: lb627: 628: OpLoad: FloatVector2: tmp628 << uv 629: OpExtInst(Length): Float: tmp629 << tmp628 630: OpFSub: Float: tmp630 << const88, tmp629 631: OpFMul: Float: tmp631 << const385, tmp630 632: OpCompositeConstruct: FloatVector3: tmp632 << tmp631, tmp631, tmp631 OpStore: : tmp632 >> var616 OpBranch: to lb621 621: lb621: 633: OpLoad: FloatVector3: tmp633 << var616 OpStore: : tmp633 >> col 635: OpLoad: Float: tmp635 << NumCol 636: OpConvertFToS: Int: tmp636 << tmp635 OpStore: : tmp636 >> param637 638: OpFunctionCall: FloatVector3: getSphereColor(i1;(param637) OpStore: : getSphereColor(i1; >> colobj 639: OpLoad: FloatVector3: tmp639 << colobj 640: OpLoad: FloatVector3: tmp640 << col 641: OpFMul: FloatVector3: tmp641 << tmp640, tmp639 OpStore: : tmp641 >> col 642: OpAccessChain: Float*: hit[1] 643: OpLoad: Float: tmp643 << hit[1] 644: OpExtInst(Pow): Float: tmp644 << tmp643, const267 645: OpLoad: FloatVector3: tmp645 << col 646: OpCompositeConstruct: FloatVector3: tmp646 << tmp644, tmp644, tmp644 647: OpFAdd: FloatVector3: tmp647 << tmp645, tmp646 OpStore: : tmp647 >> col 648: OpLoad: FloatVector3: tmp648 << col 649: OpExtInst(Sqrt): FloatVector3: tmp649 << tmp648 650: OpCompositeExtract: Float: tmp650 << tmp649, 0 651: OpCompositeExtract: Float: tmp651 << tmp649, 1 652: OpCompositeExtract: Float: tmp652 << tmp649, 2 653: OpCompositeConstruct: FloatVector4: tmp653 << tmp650, tmp651, tmp652, const88 OpStore: : tmp653 >> fragColor OpReturn: Performing hardware-independent optimization... Variable color Variable color is redundant. Removing both it and related Load/Store instructions. Variable param657 Variable param658 Removed 1 redundant local variables from function main Variable d Variable d is redundant. Removing both it and related Load/Store instructions. Removed 1 redundant local variables from function sdCross(vf3; Variable q Variable q is redundant. Removing both it and related Load/Store instructions. Variable param139 Removed 1 redundant local variables from function sdCrossRep(vf3; Variable param147 Variable d Variable d is redundant. Removing both it and related Load/Store instructions. Removed 1 redundant local variables from function sdCylinder(vf3;vf2; Variable resp Variable res Variable sdcy1 Variable sdcy1 is redundant. Removing both it and related Load/Store instructions. Variable param208 Variable param211 Variable sdcy2 Variable sdcy2 is redundant. Removing both it and related Load/Store instructions. Variable param217 Variable param220 Variable dif1 Variable dif1 is redundant. Removing both it and related Load/Store instructions. Variable param223 Variable param225 Variable param231 Variable param233 Removed 3 redundant local variables from function diso(vf3; Variable scale Variable res Variable dist Variable param246 Variable i Variable param260 Variable param262 Variable param286 Variable param288 Variable param294 Variable param296 Variable t Variable d Variable it Variable i Variable param324 Variable t Variable d Variable i Variable param369 Variable e Variable e is redundant. Removing both it and related Load/Store instructions. Variable param395 Variable param401 Variable param408 Variable param414 Variable param421 Variable param427 Removed 1 redundant local variables from function getNorm(vf3; Variable col Variable i Variable ld Variable ld is redundant. Removing both it and related Load/Store instructions. Variable diff Variable param459 Variable param461 Variable param463 Removed 1 redundant local variables from function light(vf3;vf3; Variable time Variable time is redundant. Removing both it and related Load/Store instructions. Variable uv Variable uv is redundant. Removing both it and related Load/Store instructions. Variable ro Variable ro is redundant. Removing both it and related Load/Store instructions. Variable rd Variable rd is redundant. Removing both it and related Load/Store instructions. Variable hit Variable hit is redundant. Removing both it and related Load/Store instructions. Variable param599 Variable param601 Variable p Variable p is redundant. Removing both it and related Load/Store instructions. Variable nor Variable nor is redundant. Removing both it and related Load/Store instructions. Variable param612 Variable col Variable var616 Variable param622 Variable param624 Variable colobj Variable colobj is redundant. Removing both it and related Load/Store instructions. Variable param637 Removed 8 redundant local variables from function mainImage(vf4;vf2; Optimization done. Optimized Disassembly: Module Info: OpSource: : ESSL ver 310 1: OpExtInstImport: : GLSL.std.450 OpMemoryModel: : addressing: Logical, memory: GLSL450 Capabilities: OpCapability: : Shader Inputs: 656: OpVariable: FloatVector4*: gl_FragCoord: storage class: Input Decorators: BuiltIn(FragCoord) Outputs: 664: OpVariable: FloatVector4*: finalColor: storage class: Output Uniform Constants: 274: OpVariable: Float*: iTime: storage class: UniformConstant 572: OpVariable: FloatVector3*: iResolution: storage class: UniformConstant 667: OpVariable: FloatVector4*: iMouse: storage class: UniformConstant 668: OpVariable: FloatVector4*: iDate: storage class: UniformConstant 669: OpVariable: Float*: iFrame: storage class: UniformConstant 673: OpVariable: FloatVector3[4]*: iChannelResolution: storage class: UniformConstant Textures: 677: OpVariable: SampledImage(Image(Float))*: iChannel0: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 678: OpVariable: SampledImage(Image(Float))*: iChannel1: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 679: OpVariable: SampledImage(Image(Float))*: iChannel2: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 680: OpVariable: SampledImage(Image(Float))*: iChannel3: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) Entry Points: 4: OpEntryPoint: : main, execution model: Fragment, Function: Void main(), OriginLowerLeft Constants: 80: OpConstant: Float const80 = 0.408248 81: OpConstant: Float const81 = 0.816497 82: OpConstantComposite: FloatVector3 const82 = {0.408248, 0.816497, 0.408248} 84: OpConstant: Float const84 = -0.408248 85: OpConstant: Float const85 = -0.816497 86: OpConstantComposite: FloatVector3 const86 = {-0.408248, 0.408248, -0.816497} 88: OpConstant: Float const88 = 1 89: OpConstant: Float const89 = 0.8 90: OpConstant: Float const90 = 0.5 91: OpConstantComposite: FloatVector3 const91 = {1, 0.8, 0.5} 93: OpConstant: Float const93 = 0.6 94: OpConstantComposite: FloatVector3 const94 = {0.6, 0.8, 1} 99: OpConstant: UInt const99 = 0 102: OpConstant: UInt const102 = 1 108: OpConstant: UInt const108 = 2 126: OpConstant: Float const126 = 0.333333 134: OpConstant: Float const134 = 2 174: OpConstant: Float const174 = 0 199: OpConstant: Float const199 = 9999 200: OpConstantComposite: FloatVector2 const200 = {9999, 0} 206: OpConstant: Float const206 = 6 207: OpConstantComposite: FloatVector2 const207 = {6, 6} 214: OpConstant: Float const214 = 1.9 215: OpConstant: Float const215 = 6.78 216: OpConstantComposite: FloatVector2 const216 = {1.9, 6.78} 229: OpConstant: Float const229 = 9 240: OpConstant: Float const240 = 0.35 242: OpConstant: Float const242 = 9999.9 243: OpConstantComposite: FloatVector2 const243 = {9999.9, 0} 245: OpConstant: Float const245 = -999 250: OpConstant: Int const250 = 0 257: OpConstant: Int const257 = 5 Decorators: RelaxedPrecision 267: OpConstant: Float const267 = 3 271: OpConstant: Int const271 = 1 277: OpConstant: Float const277 = 5 279: OpConstant: Float const279 = 0.4 284: OpConstant: Float const284 = 8 292: OpConstant: Float const292 = 7 308: OpConstant: Float const308 = 20 317: OpConstant: Int const317 = 100 Decorators: RelaxedPrecision 329: OpConstant: Float const329 = 0.001 343: OpConstant: Float const343 = 100 348: OpConstant: Float const348 = 0.002 362: OpConstant: Int const362 = 50 385: OpConstant: Float const385 = 0.1 390: OpConstantComposite: FloatVector2 const390 = {0.001, 0} 435: OpConstant: Float const435 = 0.01 436: OpConstantComposite: FloatVector3 const436 = {0.01, 0.01, 0.01} 444: OpConstant: Int const444 = 2 481: OpConstant: Float const481 = 0.7 489: OpConstantComposite: FloatVector3 const489 = {0, 0, 0} 495: OpConstantComposite: FloatVector3 const495 = {0, 0, 1} 501: OpConstantComposite: FloatVector3 const501 = {0, 1, 0} 504: OpConstant: Int const504 = 3 508: OpConstantComposite: FloatVector3 const508 = {0, 1, 1} 511: OpConstant: Int const511 = 4 515: OpConstantComposite: FloatVector3 const515 = {1, 0, 0} 521: OpConstantComposite: FloatVector3 const521 = {1, 0, 1} 524: OpConstant: Int const524 = 6 529: OpConstant: Int const529 = 7 533: OpConstantComposite: FloatVector3 const533 = {1, 1, 1} 536: OpConstant: Int const536 = 8 540: OpConstant: Float const540 = 0.425 541: OpConstant: Float const541 = 0.56 542: OpConstant: Float const542 = 0.9 543: OpConstantComposite: FloatVector3 const543 = {0.425, 0.56, 0.9} 546: OpConstant: Int const546 = 9 550: OpConstantComposite: FloatVector3 const550 = {0.5, 0.6, 0.6} 553: OpConstant: Int const553 = 10 559: OpConstant: Int const559 = 11 563: OpConstantComposite: FloatVector3 const563 = {0.5, 0.8, 0.9} 582: OpConstant: Float const582 = -1 587: OpConstant: Float const587 = -5 670: OpConstant: UInt const670 = 4 681: OpConstant: Int const681 = 64 Decorators: RelaxedPrecision 682: OpConstant: Float const682 = 0.0001 Private Global Variables: 79: OpVariable: FloatVector3*: lDir0: storage class: Private 83: OpVariable: FloatVector3*: lDir1: storage class: Private 87: OpVariable: FloatVector3*: lCol0: storage class: Private 92: OpVariable: FloatVector3*: lCol1: storage class: Private 299: OpVariable: Float*: NumCol: storage class: Private Disassembled Code: 4: OpFunction: Void main() 657: OpVariable: FloatVector4*: param657: storage class: Function 658: OpVariable: FloatVector2*: param658: storage class: Function 5: lb5: OpStore: : const82 >> lDir0 OpStore: : const86 >> lDir1 OpStore: : const91 >> lCol0 OpStore: : const94 >> lCol1 659: OpLoad: FloatVector4: tmp659 << gl_FragCoord 660: OpVectorShuffle: FloatVector2: tmp660 << tmp659, tmp659, 0, 1 OpStore: : tmp660 >> param658 661: OpFunctionCall: Void: mainImage(vf4;vf2;(param657, param658) 662: OpLoad: FloatVector4: tmp662 << param657 OpStore: : tmp662 >> finalColor OpReturn: 11: OpFunction: Float sdCross(vf3;(FloatVector3* p) 12: lb12: 95: OpLoad: FloatVector3: tmp95 << p 96: OpExtInst(FAbs): FloatVector3: tmp96 << tmp95 OpStore: : tmp96 >> p 100: OpAccessChain: Float*: p[0] 101: OpLoad: Float: tmp101 << p[0] 103: OpAccessChain: Float*: p[1] 104: OpLoad: Float: tmp104 << p[1] 105: OpExtInst(FMax): Float: tmp105 << tmp101, tmp104 106: OpAccessChain: Float*: p[1] 107: OpLoad: Float: tmp107 << p[1] 109: OpAccessChain: Float*: p[2] 110: OpLoad: Float: tmp110 << p[2] 111: OpExtInst(FMax): Float: tmp111 << tmp107, tmp110 112: OpAccessChain: Float*: p[2] 113: OpLoad: Float: tmp113 << p[2] 114: OpAccessChain: Float*: p[0] 115: OpLoad: Float: tmp115 << p[0] 116: OpExtInst(FMax): Float: tmp116 << tmp113, tmp115 117: OpCompositeConstruct: FloatVector3: tmp117 << tmp105, tmp111, tmp116 118: OpAccessChain: Float*: d[0] 119: OpCompositeExtract: Float: tmp119 << tmp117, 0 120: OpAccessChain: Float*: d[1] 121: OpCompositeExtract: Float: tmp121 << tmp117, 1 122: OpAccessChain: Float*: d[2] 123: OpCompositeExtract: Float: tmp123 << tmp117, 2 124: OpExtInst(FMin): Float: tmp124 << tmp121, tmp123 125: OpExtInst(FMin): Float: tmp125 << tmp119, tmp124 127: OpFSub: Float: tmp127 << tmp125, const126 OpReturnValue: : << tmp127 14: OpFunction: Float sdCrossRep(vf3;(FloatVector3* p) 139: OpVariable: FloatVector3*: param139: storage class: Function 15: lb15: 131: OpLoad: FloatVector3: tmp131 << p 132: OpCompositeConstruct: FloatVector3: tmp132 << const88, const88, const88 133: OpFAdd: FloatVector3: tmp133 << tmp131, tmp132 135: OpCompositeConstruct: FloatVector3: tmp135 << const134, const134, const134 136: OpFMod: FloatVector3: tmp136 << tmp133, tmp135 137: OpCompositeConstruct: FloatVector3: tmp137 << const88, const88, const88 138: OpFSub: FloatVector3: tmp138 << tmp136, tmp137 OpStore: : tmp138 >> param139 141: OpFunctionCall: Float: sdCross(vf3;(param139) OpReturnValue: : << sdCross(vf3; 20: OpFunction: Float sdCrossRepScale(vf3;f1;(FloatVector3* p, Float* s) 147: OpVariable: FloatVector3*: param147: storage class: Function 21: lb21: 144: OpLoad: FloatVector3: tmp144 << p 145: OpLoad: Float: tmp145 << s 146: OpVectorTimesScalar: FloatVector3: tmp146 << tmp144, tmp145 OpStore: : tmp146 >> param147 148: OpFunctionCall: Float: sdCrossRep(vf3;(param147) 149: OpLoad: Float: tmp149 << s 150: OpFDiv: Float: tmp150 << sdCrossRep(vf3;, tmp149 OpReturnValue: : << tmp150 25: OpFunction: Float differenceSDF(f1;f1;(Float* distA, Float* distB) 26: lb26: 153: OpLoad: Float: tmp153 << distA 154: OpLoad: Float: tmp154 << distB 155: OpFNegate: Float: tmp155 << tmp154 156: OpExtInst(FMax): Float: tmp156 << tmp153, tmp155 OpReturnValue: : << tmp156 32: OpFunction: Float sdCylinder(vf3;vf2;(FloatVector3* p, FloatVector2* h) 33: lb33: 160: OpLoad: FloatVector3: tmp160 << p 161: OpVectorShuffle: FloatVector2: tmp161 << tmp160, tmp160, 0, 2 162: OpExtInst(Length): Float: tmp162 << tmp161 163: OpAccessChain: Float*: p[1] 164: OpLoad: Float: tmp164 << p[1] 165: OpCompositeConstruct: FloatVector2: tmp165 << tmp162, tmp164 166: OpExtInst(FAbs): FloatVector2: tmp166 << tmp165 167: OpLoad: FloatVector2: tmp167 << h 168: OpFSub: FloatVector2: tmp168 << tmp166, tmp167 169: OpAccessChain: Float*: d[0] 170: OpCompositeExtract: Float: tmp170 << tmp168, 0 171: OpAccessChain: Float*: d[1] 172: OpCompositeExtract: Float: tmp172 << tmp168, 1 173: OpExtInst(FMax): Float: tmp173 << tmp170, tmp172 175: OpExtInst(FMin): Float: tmp175 << tmp173, const174 177: OpCompositeConstruct: FloatVector2: tmp177 << const174, const174 178: OpExtInst(FMax): FloatVector2: tmp178 << tmp168, tmp177 179: OpExtInst(Length): Float: tmp179 << tmp178 180: OpFAdd: Float: tmp180 << tmp175, tmp179 OpReturnValue: : << tmp180 37: OpFunction: FloatVector2 opU(vf2;vf2;(FloatVector2* d1, FloatVector2* d2) 191: OpVariable: FloatVector2*: resp: storage class: Function 38: lb38: 183: OpAccessChain: Float*: d1[0] 184: OpLoad: Float: tmp184 << d1[0] 185: OpAccessChain: Float*: d2[0] 186: OpLoad: Float: tmp186 << d2[0] 188: OpFOrdLessThan: Bool: tmp188 << tmp184, tmp186 OpSelectionMerge: (merge: lb190) OpBranchConditional: if(tmp188) then branch to lb189, else branch to lb193 189: lb189: 192: OpLoad: FloatVector2: tmp192 << d1 OpStore: : tmp192 >> resp OpBranch: to lb190 193: lb193: 194: OpLoad: FloatVector2: tmp194 << d2 OpStore: : tmp194 >> resp OpBranch: to lb190 190: lb190: 195: OpLoad: FloatVector2: tmp195 << resp OpReturnValue: : << tmp195 40: OpFunction: Float diso(vf3;(FloatVector3* p) 198: OpVariable: FloatVector2*: res: storage class: Function 208: OpVariable: FloatVector3*: param208: storage class: Function 211: OpVariable: FloatVector2*: param211: storage class: Function 217: OpVariable: FloatVector3*: param217: storage class: Function 220: OpVariable: FloatVector2*: param220: storage class: Function 223: OpVariable: Float*: param223: storage class: Function 225: OpVariable: Float*: param225: storage class: Function 231: OpVariable: FloatVector2*: param231: storage class: Function 233: OpVariable: FloatVector2*: param233: storage class: Function 41: lb41: OpStore: : const200 >> res 201: OpAccessChain: Float*: p[2] 202: OpLoad: Float: tmp202 << p[2] 203: OpFMod: Float: tmp203 << tmp202, const134 204: OpAccessChain: Float*: p[2] OpStore: : tmp203 >> p[2] 209: OpLoad: FloatVector3: tmp209 << p 210: OpVectorShuffle: FloatVector3: tmp210 << tmp209, tmp209, 1, 2, 0 OpStore: : tmp210 >> param208 OpStore: : const207 >> param211 212: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param208, param211) 218: OpLoad: FloatVector3: tmp218 << p 219: OpVectorShuffle: FloatVector3: tmp219 << tmp218, tmp218, 1, 2, 0 OpStore: : tmp219 >> param217 OpStore: : const216 >> param220 221: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param217, param220) OpStore: : sdCylinder(vf3;vf2; >> param223 OpStore: : sdCylinder(vf3;vf2; >> param225 227: OpFunctionCall: Float: differenceSDF(f1;f1;(param223, param225) 230: OpCompositeConstruct: FloatVector2: tmp230 << differenceSDF(f1;f1;, const229 232: OpLoad: FloatVector2: tmp232 << res OpStore: : tmp232 >> param231 OpStore: : tmp230 >> param233 234: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param231, param233) OpStore: : opU(vf2;vf2; >> res 235: OpAccessChain: Float*: res[0] 236: OpLoad: Float: tmp236 << res[0] OpReturnValue: : << tmp236 43: OpFunction: Float DE(vf3;(FloatVector3* p) 239: OpVariable: Float*: scale: storage class: Function 241: OpVariable: FloatVector2*: res: storage class: Function 244: OpVariable: Float*: dist: storage class: Function 246: OpVariable: FloatVector3*: param246: storage class: Function 249: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 260: OpVariable: FloatVector3*: param260: storage class: Function 262: OpVariable: Float*: param262: storage class: Function 286: OpVariable: FloatVector2*: param286: storage class: Function 288: OpVariable: FloatVector2*: param288: storage class: Function 294: OpVariable: FloatVector2*: param294: storage class: Function 296: OpVariable: FloatVector2*: param296: storage class: Function 44: lb44: OpStore: : const240 >> scale OpStore: : const243 >> res OpStore: : const245 >> dist 247: OpLoad: FloatVector3: tmp247 << p OpStore: : tmp247 >> param246 248: OpFunctionCall: Float: diso(vf3;(param246) OpStore: : diso(vf3; >> dist OpStore: : const250 >> i OpBranch: to lb251 251: lb251: OpLoopMerge: (merge: lb253, continue: lb254) OpBranch: to lb255 255: lb255: 256: OpLoad: Int: tmp256 << i Decorators: RelaxedPrecision 258: OpSLessThan: Bool: tmp258 << tmp256, const257 OpBranchConditional: if(tmp258) then branch to lb252, else branch to lb253 252: lb252: 259: OpLoad: Float: tmp259 << dist 261: OpLoad: FloatVector3: tmp261 << p OpStore: : tmp261 >> param260 263: OpLoad: Float: tmp263 << scale OpStore: : tmp263 >> param262 264: OpFunctionCall: Float: sdCrossRepScale(vf3;f1;(param260, param262) 265: OpFNegate: Float: tmp265 << sdCrossRepScale(vf3;f1; 266: OpExtInst(FMax): Float: tmp266 << tmp259, tmp265 OpStore: : tmp266 >> dist 268: OpLoad: Float: tmp268 << scale 269: OpFMul: Float: tmp269 << tmp268, const267 OpStore: : tmp269 >> scale OpBranch: to lb254 254: lb254: 270: OpLoad: Int: tmp270 << i Decorators: RelaxedPrecision 272: OpIAdd: Int: tmp272 << tmp270, const271 Decorators: RelaxedPrecision OpStore: : tmp272 >> i OpBranch: to lb251 253: lb253: 275: OpLoad: Float: tmp275 << iTime 276: OpExtInst(Floor): Float: tmp276 << tmp275 278: OpFMod: Float: tmp278 << tmp276, const277 280: OpFOrdGreaterThan: Bool: tmp280 << tmp278, const279 OpSelectionMerge: (merge: lb282) OpBranchConditional: if(tmp280) then branch to lb281, else branch to lb290 281: lb281: 283: OpLoad: Float: tmp283 << dist 285: OpCompositeConstruct: FloatVector2: tmp285 << tmp283, const284 287: OpLoad: FloatVector2: tmp287 << res OpStore: : tmp287 >> param286 OpStore: : tmp285 >> param288 289: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param286, param288) OpStore: : opU(vf2;vf2; >> res OpBranch: to lb282 290: lb290: 291: OpLoad: Float: tmp291 << dist 293: OpCompositeConstruct: FloatVector2: tmp293 << tmp291, const292 295: OpLoad: FloatVector2: tmp295 << res OpStore: : tmp295 >> param294 OpStore: : tmp293 >> param296 297: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param294, param296) OpStore: : opU(vf2;vf2; >> res OpBranch: to lb282 282: lb282: 300: OpAccessChain: Float*: res[1] 301: OpLoad: Float: tmp301 << res[1] OpStore: : tmp301 >> NumCol 302: OpAccessChain: Float*: res[0] 303: OpLoad: Float: tmp303 << res[0] OpReturnValue: : << tmp303 48: OpFunction: FloatVector2 march(vf3;vf3;(FloatVector3* ro, FloatVector3* rd) 306: OpVariable: Float*: t: storage class: Function 307: OpVariable: Float*: d: storage class: Function 309: OpVariable: Float*: it: storage class: Function 310: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 324: OpVariable: FloatVector3*: param324: storage class: Function 49: lb49: OpStore: : const174 >> t OpStore: : const308 >> d OpStore: : const174 >> it OpStore: : const250 >> i OpBranch: to lb311 311: lb311: OpLoopMerge: (merge: lb313, continue: lb314) OpBranch: to lb315 315: lb315: 316: OpLoad: Int: tmp316 << i Decorators: RelaxedPrecision 318: OpSLessThan: Bool: tmp318 << tmp316, const317 OpBranchConditional: if(tmp318) then branch to lb312, else branch to lb313 312: lb312: 319: OpLoad: FloatVector3: tmp319 << ro 320: OpLoad: Float: tmp320 << t 321: OpLoad: FloatVector3: tmp321 << rd 322: OpVectorTimesScalar: FloatVector3: tmp322 << tmp321, tmp320 323: OpFAdd: FloatVector3: tmp323 << tmp319, tmp322 OpStore: : tmp323 >> param324 325: OpFunctionCall: Float: DE(vf3;(param324) OpStore: : DE(vf3; >> d 326: OpLoad: Float: tmp326 << t 327: OpFAdd: Float: tmp327 << tmp326, DE(vf3; OpStore: : tmp327 >> t 328: OpLoad: Float: tmp328 << d 330: OpFOrdLessThan: Bool: tmp330 << tmp328, const329 331: OpLoad: Float: tmp331 << t 332: OpFOrdGreaterThan: Bool: tmp332 << tmp331, const308 333: OpLogicalOr: Bool: tmp333 << tmp330, tmp332 OpSelectionMerge: (merge: lb335) OpBranchConditional: if(tmp333) then branch to lb334, else branch to lb335 334: lb334: OpBranch: to lb313 335: lb335: 337: OpLoad: Float: tmp337 << it 338: OpFAdd: Float: tmp338 << tmp337, const88 OpStore: : tmp338 >> it OpBranch: to lb314 314: lb314: 339: OpLoad: Int: tmp339 << i Decorators: RelaxedPrecision 340: OpIAdd: Int: tmp340 << tmp339, const271 Decorators: RelaxedPrecision OpStore: : tmp340 >> i OpBranch: to lb311 313: lb313: 341: OpLoad: Float: tmp341 << t 342: OpLoad: Float: tmp342 << it 344: OpFDiv: Float: tmp344 << tmp342, const343 345: OpCompositeConstruct: FloatVector2: tmp345 << tmp341, tmp344 OpReturnValue: : << tmp345 54: OpFunction: Float getShadow(vf3;vf3;vf3;(FloatVector3* p, FloatVector3* n, FloatVector3* ld) 353: OpVariable: Float*: t: storage class: Function 354: OpVariable: Float*: d: storage class: Function 355: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 369: OpVariable: FloatVector3*: param369: storage class: Function 55: lb55: 349: OpLoad: FloatVector3: tmp349 << n 350: OpVectorTimesScalar: FloatVector3: tmp350 << tmp349, const348 351: OpLoad: FloatVector3: tmp351 << p 352: OpFAdd: FloatVector3: tmp352 << tmp351, tmp350 OpStore: : tmp352 >> p OpStore: : const174 >> t OpStore: : const308 >> d OpStore: : const250 >> i OpBranch: to lb356 356: lb356: OpLoopMerge: (merge: lb358, continue: lb359) OpBranch: to lb360 360: lb360: 361: OpLoad: Int: tmp361 << i Decorators: RelaxedPrecision 363: OpSLessThan: Bool: tmp363 << tmp361, const362 OpBranchConditional: if(tmp363) then branch to lb357, else branch to lb358 357: lb357: 364: OpLoad: FloatVector3: tmp364 << p 365: OpLoad: Float: tmp365 << t 366: OpLoad: FloatVector3: tmp366 << ld 367: OpVectorTimesScalar: FloatVector3: tmp367 << tmp366, tmp365 368: OpFAdd: FloatVector3: tmp368 << tmp364, tmp367 OpStore: : tmp368 >> param369 370: OpFunctionCall: Float: DE(vf3;(param369) OpStore: : DE(vf3; >> d 371: OpLoad: Float: tmp371 << t 372: OpFAdd: Float: tmp372 << tmp371, DE(vf3; OpStore: : tmp372 >> t 373: OpLoad: Float: tmp373 << d 374: OpFOrdLessThan: Bool: tmp374 << tmp373, const329 375: OpLoad: Float: tmp375 << t 376: OpFOrdGreaterThan: Bool: tmp376 << tmp375, const267 377: OpLogicalOr: Bool: tmp377 << tmp374, tmp376 OpSelectionMerge: (merge: lb379) OpBranchConditional: if(tmp377) then branch to lb378, else branch to lb379 378: lb378: OpBranch: to lb358 379: lb379: OpBranch: to lb359 359: lb359: 381: OpLoad: Int: tmp381 << i Decorators: RelaxedPrecision 382: OpIAdd: Int: tmp382 << tmp381, const271 Decorators: RelaxedPrecision OpStore: : tmp382 >> i OpBranch: to lb356 358: lb358: 383: OpLoad: Float: tmp383 << t 384: OpFOrdLessThanEqual: Bool: tmp384 << tmp383, const267 386: OpSelect: Float: tmp386 << tmp384, const385, const88 OpReturnValue: : << tmp386 58: OpFunction: FloatVector3 getNorm(vf3;(FloatVector3* p) 395: OpVariable: FloatVector3*: param395: storage class: Function 401: OpVariable: FloatVector3*: param401: storage class: Function 408: OpVariable: FloatVector3*: param408: storage class: Function 414: OpVariable: FloatVector3*: param414: storage class: Function 421: OpVariable: FloatVector3*: param421: storage class: Function 427: OpVariable: FloatVector3*: param427: storage class: Function 59: lb59: 391: OpLoad: FloatVector3: tmp391 << p 393: OpVectorShuffle: FloatVector3: tmp393 << const390, const390, 0, 1, 1 394: OpFAdd: FloatVector3: tmp394 << tmp391, tmp393 OpStore: : tmp394 >> param395 396: OpFunctionCall: Float: DE(vf3;(param395) 397: OpLoad: FloatVector3: tmp397 << p 399: OpVectorShuffle: FloatVector3: tmp399 << const390, const390, 0, 1, 1 400: OpFSub: FloatVector3: tmp400 << tmp397, tmp399 OpStore: : tmp400 >> param401 402: OpFunctionCall: Float: DE(vf3;(param401) 403: OpFSub: Float: tmp403 << DE(vf3;, DE(vf3; 404: OpLoad: FloatVector3: tmp404 << p 406: OpVectorShuffle: FloatVector3: tmp406 << const390, const390, 1, 0, 1 407: OpFAdd: FloatVector3: tmp407 << tmp404, tmp406 OpStore: : tmp407 >> param408 409: OpFunctionCall: Float: DE(vf3;(param408) 410: OpLoad: FloatVector3: tmp410 << p 412: OpVectorShuffle: FloatVector3: tmp412 << const390, const390, 1, 0, 1 413: OpFSub: FloatVector3: tmp413 << tmp410, tmp412 OpStore: : tmp413 >> param414 415: OpFunctionCall: Float: DE(vf3;(param414) 416: OpFSub: Float: tmp416 << DE(vf3;, DE(vf3; 417: OpLoad: FloatVector3: tmp417 << p 419: OpVectorShuffle: FloatVector3: tmp419 << const390, const390, 1, 1, 0 420: OpFAdd: FloatVector3: tmp420 << tmp417, tmp419 OpStore: : tmp420 >> param421 422: OpFunctionCall: Float: DE(vf3;(param421) 423: OpLoad: FloatVector3: tmp423 << p 425: OpVectorShuffle: FloatVector3: tmp425 << const390, const390, 1, 1, 0 426: OpFSub: FloatVector3: tmp426 << tmp423, tmp425 OpStore: : tmp426 >> param427 428: OpFunctionCall: Float: DE(vf3;(param427) 429: OpFSub: Float: tmp429 << DE(vf3;, DE(vf3; 430: OpCompositeConstruct: FloatVector3: tmp430 << tmp403, tmp416, tmp429 431: OpExtInst(Normalize): FloatVector3: tmp431 << tmp430 OpReturnValue: : << tmp431 63: OpFunction: FloatVector3 light(vf3;vf3;(FloatVector3* p, FloatVector3* n) 434: OpVariable: FloatVector3*: col: storage class: Function 437: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 454: OpVariable: Float*: diff: storage class: Function 459: OpVariable: FloatVector3*: param459: storage class: Function 461: OpVariable: FloatVector3*: param461: storage class: Function 463: OpVariable: FloatVector3*: param463: storage class: Function 64: lb64: OpStore: : const436 >> col OpStore: : const250 >> i OpBranch: to lb438 438: lb438: OpLoopMerge: (merge: lb440, continue: lb441) OpBranch: to lb442 442: lb442: 443: OpLoad: Int: tmp443 << i Decorators: RelaxedPrecision 445: OpSLessThan: Bool: tmp445 << tmp443, const444 OpBranchConditional: if(tmp445) then branch to lb439, else branch to lb440 439: lb439: 447: OpLoad: Int: tmp447 << i Decorators: RelaxedPrecision 448: OpIEqual: Bool: tmp448 << tmp447, const250 449: OpLoad: FloatVector3: tmp449 << lDir0 450: OpLoad: FloatVector3: tmp450 << lDir1 452: OpCompositeConstruct: BoolVector3: tmp452 << tmp448, tmp448, tmp448 453: OpSelect: FloatVector3: tmp453 << tmp452, tmp449, tmp450 455: OpLoad: FloatVector3: tmp455 << n 457: OpDot: Float: tmp457 << tmp455, tmp453 458: OpExtInst(FMax): Float: tmp458 << tmp457, const174 OpStore: : tmp458 >> diff 460: OpLoad: FloatVector3: tmp460 << p OpStore: : tmp460 >> param459 462: OpLoad: FloatVector3: tmp462 << n OpStore: : tmp462 >> param461 OpStore: : tmp453 >> param463 465: OpFunctionCall: Float: getShadow(vf3;vf3;vf3;(param459, param461, param463) 466: OpLoad: Float: tmp466 << diff 467: OpFMul: Float: tmp467 << tmp466, getShadow(vf3;vf3;vf3; OpStore: : tmp467 >> diff 468: OpLoad: Float: tmp468 << diff 469: OpLoad: Int: tmp469 << i Decorators: RelaxedPrecision 470: OpIEqual: Bool: tmp470 << tmp469, const250 471: OpLoad: FloatVector3: tmp471 << lCol0 472: OpLoad: FloatVector3: tmp472 << lCol1 473: OpCompositeConstruct: BoolVector3: tmp473 << tmp470, tmp470, tmp470 474: OpSelect: FloatVector3: tmp474 << tmp473, tmp471, tmp472 475: OpVectorTimesScalar: FloatVector3: tmp475 << tmp474, tmp468 476: OpLoad: FloatVector3: tmp476 << col 477: OpFAdd: FloatVector3: tmp477 << tmp476, tmp475 OpStore: : tmp477 >> col OpBranch: to lb441 441: lb441: 478: OpLoad: Int: tmp478 << i Decorators: RelaxedPrecision 479: OpIAdd: Int: tmp479 << tmp478, const271 Decorators: RelaxedPrecision OpStore: : tmp479 >> i OpBranch: to lb438 440: lb440: 480: OpLoad: FloatVector3: tmp480 << col 482: OpVectorTimesScalar: FloatVector3: tmp482 << tmp480, const481 OpReturnValue: : << tmp482 69: OpFunction: FloatVector3 getSphereColor(i1;(Int* i) 70: lb70: 485: OpLoad: Int: tmp485 << i Decorators: RelaxedPrecision 486: OpIEqual: Bool: tmp486 << tmp485, const250 OpSelectionMerge: (merge: lb488) OpBranchConditional: if(tmp486) then branch to lb487, else branch to lb488 487: lb487: OpReturnValue: : << const489 488: lb488: 491: OpLoad: Int: tmp491 << i Decorators: RelaxedPrecision 492: OpIEqual: Bool: tmp492 << tmp491, const271 OpSelectionMerge: (merge: lb494) OpBranchConditional: if(tmp492) then branch to lb493, else branch to lb494 493: lb493: OpReturnValue: : << const495 494: lb494: 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision 498: OpIEqual: Bool: tmp498 << tmp497, const444 OpSelectionMerge: (merge: lb500) OpBranchConditional: if(tmp498) then branch to lb499, else branch to lb500 499: lb499: OpReturnValue: : << const501 500: lb500: 503: OpLoad: Int: tmp503 << i Decorators: RelaxedPrecision 505: OpIEqual: Bool: tmp505 << tmp503, const504 OpSelectionMerge: (merge: lb507) OpBranchConditional: if(tmp505) then branch to lb506, else branch to lb507 506: lb506: OpReturnValue: : << const508 507: lb507: 510: OpLoad: Int: tmp510 << i Decorators: RelaxedPrecision 512: OpIEqual: Bool: tmp512 << tmp510, const511 OpSelectionMerge: (merge: lb514) OpBranchConditional: if(tmp512) then branch to lb513, else branch to lb514 513: lb513: OpReturnValue: : << const515 514: lb514: 517: OpLoad: Int: tmp517 << i Decorators: RelaxedPrecision 518: OpIEqual: Bool: tmp518 << tmp517, const257 OpSelectionMerge: (merge: lb520) OpBranchConditional: if(tmp518) then branch to lb519, else branch to lb520 519: lb519: OpReturnValue: : << const521 520: lb520: 523: OpLoad: Int: tmp523 << i Decorators: RelaxedPrecision 525: OpIEqual: Bool: tmp525 << tmp523, const524 OpSelectionMerge: (merge: lb527) OpBranchConditional: if(tmp525) then branch to lb526, else branch to lb527 526: lb526: OpBranch: to lb527 527: lb527: 528: OpLoad: Int: tmp528 << i Decorators: RelaxedPrecision 530: OpIEqual: Bool: tmp530 << tmp528, const529 OpSelectionMerge: (merge: lb532) OpBranchConditional: if(tmp530) then branch to lb531, else branch to lb532 531: lb531: OpReturnValue: : << const533 532: lb532: 535: OpLoad: Int: tmp535 << i Decorators: RelaxedPrecision 537: OpIEqual: Bool: tmp537 << tmp535, const536 OpSelectionMerge: (merge: lb539) OpBranchConditional: if(tmp537) then branch to lb538, else branch to lb539 538: lb538: OpReturnValue: : << const543 539: lb539: 545: OpLoad: Int: tmp545 << i Decorators: RelaxedPrecision 547: OpIEqual: Bool: tmp547 << tmp545, const546 OpSelectionMerge: (merge: lb549) OpBranchConditional: if(tmp547) then branch to lb548, else branch to lb549 548: lb548: OpReturnValue: : << const550 549: lb549: 552: OpLoad: Int: tmp552 << i Decorators: RelaxedPrecision 554: OpIEqual: Bool: tmp554 << tmp552, const553 OpSelectionMerge: (merge: lb556) OpBranchConditional: if(tmp554) then branch to lb555, else branch to lb556 555: lb555: OpReturnValue: : << const501 556: lb556: 558: OpLoad: Int: tmp558 << i Decorators: RelaxedPrecision 560: OpIEqual: Bool: tmp560 << tmp558, const559 OpSelectionMerge: (merge: lb562) OpBranchConditional: if(tmp560) then branch to lb561, else branch to lb562 561: lb561: OpReturnValue: : << const563 562: lb562: 565: OpUndef: FloatVector3: tmp565 << OpReturnValue: : << tmp565 76: OpFunction: Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) 599: OpVariable: FloatVector3*: param599: storage class: Function 601: OpVariable: FloatVector3*: param601: storage class: Function 612: OpVariable: FloatVector3*: param612: storage class: Function 615: OpVariable: FloatVector3*: col: storage class: Function 616: OpVariable: FloatVector3*: var616: storage class: Function 622: OpVariable: FloatVector3*: param622: storage class: Function 624: OpVariable: FloatVector3*: param624: storage class: Function 637: OpVariable: Int*: param637: storage class: Function 77: lb77: 567: OpLoad: Float: tmp567 << iTime 568: OpFMul: Float: tmp568 << tmp567, const90 570: OpLoad: FloatVector2: tmp570 << fragCoord 573: OpLoad: FloatVector3: tmp573 << iResolution 574: OpVectorShuffle: FloatVector2: tmp574 << tmp573, tmp573, 0, 1 575: OpVectorTimesScalar: FloatVector2: tmp575 << tmp574, const90 576: OpFSub: FloatVector2: tmp576 << tmp570, tmp575 577: OpAccessChain: Float*: iResolution[1] 578: OpLoad: Float: tmp578 << iResolution[1] 579: OpCompositeConstruct: FloatVector2: tmp579 << tmp578, tmp578 580: OpFDiv: FloatVector2: tmp580 << tmp576, tmp579 583: OpLoad: Float: tmp583 << iTime 584: OpExtInst(Sin): Float: tmp584 << tmp583 585: OpFMul: Float: tmp585 << const90, tmp584 586: OpFAdd: Float: tmp586 << const582, tmp585 588: OpLoad: Float: tmp588 << iTime 589: OpFMul: Float: tmp589 << tmp588, const90 590: OpFAdd: Float: tmp590 << const587, tmp589 591: OpCompositeConstruct: FloatVector3: tmp591 << const174, tmp586, tmp590 594: OpCompositeExtract: Float: tmp594 << tmp580, 0 595: OpCompositeExtract: Float: tmp595 << tmp580, 1 596: OpCompositeConstruct: FloatVector3: tmp596 << tmp594, tmp595, const88 597: OpExtInst(Normalize): FloatVector3: tmp597 << tmp596 OpStore: : tmp591 >> param599 OpStore: : tmp597 >> param601 603: OpFunctionCall: FloatVector2: march(vf3;vf3;(param599, param601) 606: OpAccessChain: Float*: hit[0] 607: OpCompositeExtract: Float: tmp607 << march(vf3;vf3;, 0 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp597, tmp607 610: OpFAdd: FloatVector3: tmp610 << tmp591, tmp609 OpStore: : tmp610 >> param612 614: OpFunctionCall: FloatVector3: getNorm(vf3;(param612) 617: OpAccessChain: Float*: hit[0] 618: OpCompositeExtract: Float: tmp618 << march(vf3;vf3;, 0 619: OpFOrdLessThan: Bool: tmp619 << tmp618, const308 OpSelectionMerge: (merge: lb621) OpBranchConditional: if(tmp619) then branch to lb620, else branch to lb627 620: lb620: OpStore: : tmp610 >> param622 OpStore: : getNorm(vf3; >> param624 626: OpFunctionCall: FloatVector3: light(vf3;vf3;(param622, param624) OpStore: : light(vf3;vf3; >> var616 OpBranch: to lb621 627: lb627: 629: OpExtInst(Length): Float: tmp629 << tmp580 630: OpFSub: Float: tmp630 << const88, tmp629 631: OpFMul: Float: tmp631 << const385, tmp630 632: OpCompositeConstruct: FloatVector3: tmp632 << tmp631, tmp631, tmp631 OpStore: : tmp632 >> var616 OpBranch: to lb621 621: lb621: 633: OpLoad: FloatVector3: tmp633 << var616 OpStore: : tmp633 >> col 635: OpLoad: Float: tmp635 << NumCol 636: OpConvertFToS: Int: tmp636 << tmp635 OpStore: : tmp636 >> param637 638: OpFunctionCall: FloatVector3: getSphereColor(i1;(param637) 640: OpLoad: FloatVector3: tmp640 << col 641: OpFMul: FloatVector3: tmp641 << tmp640, getSphereColor(i1; OpStore: : tmp641 >> col 642: OpAccessChain: Float*: hit[1] 643: OpCompositeExtract: Float: tmp643 << march(vf3;vf3;, 1 644: OpExtInst(Pow): Float: tmp644 << tmp643, const267 645: OpLoad: FloatVector3: tmp645 << col 646: OpCompositeConstruct: FloatVector3: tmp646 << tmp644, tmp644, tmp644 647: OpFAdd: FloatVector3: tmp647 << tmp645, tmp646 OpStore: : tmp647 >> col 648: OpLoad: FloatVector3: tmp648 << col 649: OpExtInst(Sqrt): FloatVector3: tmp649 << tmp648 650: OpCompositeExtract: Float: tmp650 << tmp649, 0 651: OpCompositeExtract: Float: tmp651 << tmp649, 1 652: OpCompositeExtract: Float: tmp652 << tmp649, 2 653: OpCompositeConstruct: FloatVector4: tmp653 << tmp650, tmp651, tmp652, const88 OpStore: : tmp653 >> fragColor OpReturn: Generating the compiled code... Intermediate disassembly (pre optimization): Program Type: Fragment Special Input Variables: offset: unset, size: 16, FloatVector4 gl_FragCoord BuiltIn(FragCoord) Textures: offset: 0, size: 4, Float iChannel0 offset: 1, size: 4, Float iChannel1 offset: 2, size: 4, Float iChannel2 offset: 3, size: 4, Float iChannel3 Output Variables: offset: 0, size: 16, FloatVector4 finalColor Uniform Constants: offset: 0, size: 4, Float iTime offset: 4, size: 12, FloatVector3 iResolution offset: 16, size: 16, FloatVector4 iMouse offset: 32, size: 16, FloatVector4 iDate offset: 48, size: 4, Float iFrame offset: 52, size: 48, FloatVector3 iChannelResolution[4] Private Global Variables: offset: unset, size: 12, FloatVector3 lDir0 offset: unset, size: 12, FloatVector3 lDir1 offset: unset, size: 12, FloatVector3 lCol0 offset: unset, size: 12, FloatVector3 lCol1 offset: unset, size: 4, Float NumCol Constants: Float const80: 0.408248 Float const81: 0.816497 FloatVector3 const82: {0.408248, 0.816497, 0.408248} Float const84: -0.408248 Float const85: -0.816497 FloatVector3 const86: {-0.408248, 0.408248, -0.816497} Float const88: 1 Float const89: 0.8 Float const90: 0.5 FloatVector3 const91: {1, 0.8, 0.5} Float const93: 0.6 FloatVector3 const94: {0.6, 0.8, 1} UInt32 const99: 0 UInt32 const102: 1 UInt32 const108: 2 Float const126: 0.333333 Float const134: 2 Float const174: 0 Float const199: 9999 FloatVector2 const200: {9999, 0} Float const206: 6 FloatVector2 const207: {6, 6} Float const214: 1.9 Float const215: 6.78 FloatVector2 const216: {1.9, 6.78} Float const229: 9 Float const240: 0.35 Float const242: 9999.9 FloatVector2 const243: {9999.9, 0} Float const245: -999 Int32 const250: 0 Int32 const257: 5 Float const267: 3 Int32 const271: 1 Float const277: 5 Float const279: 0.4 Float const284: 8 Float const292: 7 Float const308: 20 Int32 const317: 100 Float const329: 0.001 Float const343: 100 Float const348: 0.002 Int32 const362: 50 Float const385: 0.1 FloatVector2 const390: {0.001, 0} Float const435: 0.01 FloatVector3 const436: {0.01, 0.01, 0.01} Int32 const444: 2 Float const481: 0.7 FloatVector3 const489: {0, 0, 0} FloatVector3 const495: {0, 0, 1} FloatVector3 const501: {0, 1, 0} Int32 const504: 3 FloatVector3 const508: {0, 1, 1} Int32 const511: 4 FloatVector3 const515: {1, 0, 0} FloatVector3 const521: {1, 0, 1} Int32 const524: 6 Int32 const529: 7 FloatVector3 const533: {1, 1, 1} Int32 const536: 8 Float const540: 0.425 Float const541: 0.56 Float const542: 0.9 FloatVector3 const543: {0.425, 0.56, 0.9} Int32 const546: 9 FloatVector3 const550: {0.5, 0.6, 0.6} Int32 const553: 10 Int32 const559: 11 FloatVector3 const563: {0.5, 0.8, 0.9} Float const582: -1 Float const587: -5 UInt32 const670: 4 Int32 const681: 64 Float const682: 0.0001 Function Local Variables: offset: unset, size: 16, FloatVector4 main.param657 offset: unset, size: 8, FloatVector2 main.param658 offset: unset, size: 16, FloatVector4 main.fragColor offset: unset, size: 8, FloatVector2 main.fragCoord offset: unset, size: 12, FloatVector3 main.p offset: unset, size: 12, FloatVector3 sdCross(vf3;.p offset: unset, size: 12, FloatVector3 sdCrossRep(vf3;.param139 offset: unset, size: 12, FloatVector3 sdCrossRep(vf3;.p offset: unset, size: 4, Float sdCrossRep(vf3;.s offset: unset, size: 12, FloatVector3 sdCrossRepScale(vf3;f1;.param147 offset: unset, size: 4, Float sdCrossRepScale(vf3;f1;.distA offset: unset, size: 4, Float sdCrossRepScale(vf3;f1;.distB offset: unset, size: 12, FloatVector3 differenceSDF(f1;f1;.p offset: unset, size: 8, FloatVector2 differenceSDF(f1;f1;.h offset: unset, size: 8, FloatVector2 sdCylinder(vf3;vf2;.d1 offset: unset, size: 8, FloatVector2 sdCylinder(vf3;vf2;.d2 offset: unset, size: 8, FloatVector2 opU(vf2;vf2;.resp offset: unset, size: 12, FloatVector3 opU(vf2;vf2;.p offset: unset, size: 8, FloatVector2 diso(vf3;.res offset: unset, size: 12, FloatVector3 diso(vf3;.param208 offset: unset, size: 8, FloatVector2 diso(vf3;.param211 offset: unset, size: 12, FloatVector3 diso(vf3;.param217 offset: unset, size: 8, FloatVector2 diso(vf3;.param220 offset: unset, size: 4, Float diso(vf3;.param223 offset: unset, size: 4, Float diso(vf3;.param225 offset: unset, size: 8, FloatVector2 diso(vf3;.param231 offset: unset, size: 8, FloatVector2 diso(vf3;.param233 offset: unset, size: 12, FloatVector3 diso(vf3;.p offset: unset, size: 4, Float DE(vf3;.scale offset: unset, size: 8, FloatVector2 DE(vf3;.res offset: unset, size: 4, Float DE(vf3;.dist offset: unset, size: 12, FloatVector3 DE(vf3;.param246 offset: unset, size: 4, Int32 DE(vf3;.i offset: unset, size: 12, FloatVector3 DE(vf3;.param260 offset: unset, size: 4, Float DE(vf3;.param262 offset: unset, size: 8, FloatVector2 DE(vf3;.param286 offset: unset, size: 8, FloatVector2 DE(vf3;.param288 offset: unset, size: 8, FloatVector2 DE(vf3;.param294 offset: unset, size: 8, FloatVector2 DE(vf3;.param296 offset: unset, size: 12, FloatVector3 DE(vf3;.ro offset: unset, size: 12, FloatVector3 DE(vf3;.rd offset: unset, size: 4, Float march(vf3;vf3;.t offset: unset, size: 4, Float march(vf3;vf3;.d offset: unset, size: 4, Float march(vf3;vf3;.it offset: unset, size: 4, Int32 march(vf3;vf3;.i offset: unset, size: 12, FloatVector3 march(vf3;vf3;.param324 offset: unset, size: 12, FloatVector3 march(vf3;vf3;.p offset: unset, size: 12, FloatVector3 march(vf3;vf3;.n offset: unset, size: 12, FloatVector3 march(vf3;vf3;.ld offset: unset, size: 4, Float getShadow(vf3;vf3;vf3;.t offset: unset, size: 4, Float getShadow(vf3;vf3;vf3;.d offset: unset, size: 4, Int32 getShadow(vf3;vf3;vf3;.i offset: unset, size: 12, FloatVector3 getShadow(vf3;vf3;vf3;.param369 offset: unset, size: 12, FloatVector3 getShadow(vf3;vf3;vf3;.p offset: unset, size: 12, FloatVector3 getNorm(vf3;.param395 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param401 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param408 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param414 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param421 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param427 offset: unset, size: 12, FloatVector3 getNorm(vf3;.p offset: unset, size: 12, FloatVector3 getNorm(vf3;.n offset: unset, size: 12, FloatVector3 light(vf3;vf3;.col offset: unset, size: 4, Int32 light(vf3;vf3;.i offset: unset, size: 4, Float light(vf3;vf3;.diff offset: unset, size: 12, FloatVector3 light(vf3;vf3;.param459 offset: unset, size: 12, FloatVector3 light(vf3;vf3;.param461 offset: unset, size: 12, FloatVector3 light(vf3;vf3;.param463 offset: unset, size: 4, Int32 light(vf3;vf3;.i offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param599 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param601 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param612 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.col offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.var616 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param622 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param624 offset: unset, size: 4, Int32 mainImage(vf4;vf2;.param637 Instructions: V_SUB_F32 vDst(VGPR14) src0(SGPR2) src1(VGPR14) // VOP2 # Void main() Function: Void main() # lb5 Label: lb5 # OpStore: : const82 >> lDir0 V_MOV_B32 vDst(VGPR27) src0(LITERAL_CONST) const: 0x3ed105ec V_MOV_B32 vDst(VGPR28) src0(LITERAL_CONST) const: 0x3f5105ec V_MOV_B32 vDst(VGPR29) src0(LITERAL_CONST) const: 0x3ed105ec V_MOV_B32 vDst(VGPR24) src0(VGPR27) V_MOV_B32 vDst(VGPR25) src0(VGPR28) V_MOV_B32 vDst(VGPR26) src0(VGPR29) # OpStore: : const86 >> lDir1 V_MOV_B32 vDst(VGPR33) src0(LITERAL_CONST) const: 0xbed105ec V_MOV_B32 vDst(VGPR34) src0(LITERAL_CONST) const: 0x3ed105ec V_MOV_B32 vDst(VGPR35) src0(LITERAL_CONST) const: 0xbf5105ec V_MOV_B32 vDst(VGPR30) src0(VGPR33) V_MOV_B32 vDst(VGPR31) src0(VGPR34) V_MOV_B32 vDst(VGPR32) src0(VGPR35) # OpStore: : const91 >> lCol0 V_MOV_B32 vDst(VGPR39) src0(1_0_F) V_MOV_B32 vDst(VGPR40) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR41) src0(0_5_F) V_MOV_B32 vDst(VGPR36) src0(VGPR39) V_MOV_B32 vDst(VGPR37) src0(VGPR40) V_MOV_B32 vDst(VGPR38) src0(VGPR41) # OpStore: : const94 >> lCol1 V_MOV_B32 vDst(VGPR45) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR46) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR47) src0(1_0_F) V_MOV_B32 vDst(VGPR42) src0(VGPR45) V_MOV_B32 vDst(VGPR43) src0(VGPR46) V_MOV_B32 vDst(VGPR44) src0(VGPR47) # 659: OpLoad: FloatVector4: tmp659 << gl_FragCoord V_MOV_B32 vDst(VGPR48) src0(VGPR13) V_MOV_B32 vDst(VGPR49) src0(VGPR14) V_MOV_B32 vDst(VGPR50) src0(VGPR15) V_MOV_B32 vDst(VGPR51) src0(VGPR16) # 660: OpVectorShuffle: FloatVector2: tmp660 << tmp659, tmp659, 0, 1 V_MOV_B32 vDst(VGPR52) src0(VGPR48) V_MOV_B32 vDst(VGPR53) src0(VGPR49) # OpStore: : tmp660 >> param658 V_MOV_B32 vDst(VGPR22) src0(VGPR52) V_MOV_B32 vDst(VGPR23) src0(VGPR53) # 661: OpFunctionCall: Void: mainImage(vf4;vf2;(param657, param658) S_ADD_U32 sDst(SGPR12) src0(LITERAL_CONST) src1(0) const: 0x12 # VGPR[18:21] S_ADD_U32 sDst(SGPR13) src0(LITERAL_CONST) src1(0) const: 0x16 # VGPR[22:23] S_MOV_B64 sDst(SGPR14) src0(EXEC) # Indirect branch to mainImage(vf4;vf2;: ??? S_GETPC_B64 sDst(SGPR10) src0(SGPR10) S_ADD_U32 sDst(SGPR10) src0(SGPR10) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR11) src0(SGPR11) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR10) src0(SGPR10) S_MOV_B64 sDst(EXEC) src0(SGPR14) # .lbl0 # 662: OpLoad: FloatVector4: tmp662 << param657 # OpStore: : tmp662 >> finalColor V_MOV_B32 vDst(VGPR54) src0(VGPR18) V_MOV_B32 vDst(VGPR55) src0(VGPR19) V_MOV_B32 vDst(VGPR56) src0(VGPR20) V_MOV_B32 vDst(VGPR57) src0(VGPR21) # OpReturn: S_ENDPGM 0 # Float sdCross(vf3;(FloatVector3* p) Function: Float sdCross(vf3;() S_MOV_B64 sDst(SGPR20) src0(EXEC) # lb12 Label: lb12 # 95: OpLoad: FloatVector3: tmp95 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR58) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR59) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR60) src0(VGPR2) # 96: OpExtInst(FAbs): FloatVector3: tmp96 << tmp95 V_ADD_F32 vDst(VGPR61) src0(VGPR58) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR62) src0(VGPR59) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR63) src0(VGPR60) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp96 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR61) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR62) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR63) # 100: OpAccessChain: Float*: p[0] # 101: OpLoad: Float: tmp101 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR64) src0(VGPR0) # 103: OpAccessChain: Float*: p[1] # 104: OpLoad: Float: tmp104 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR65) src0(VGPR1) # 105: OpExtInst(FMax): Float: tmp105 << tmp101, tmp104 V_MAX_F32 vDst(VGPR66) src0(VGPR64) src1(VGPR65) // VOP2 # 106: OpAccessChain: Float*: p[1] # 107: OpLoad: Float: tmp107 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR67) src0(VGPR1) # 109: OpAccessChain: Float*: p[2] # 110: OpLoad: Float: tmp110 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR68) src0(VGPR2) # 111: OpExtInst(FMax): Float: tmp111 << tmp107, tmp110 V_MAX_F32 vDst(VGPR69) src0(VGPR67) src1(VGPR68) // VOP2 # 112: OpAccessChain: Float*: p[2] # 113: OpLoad: Float: tmp113 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR70) src0(VGPR2) # 114: OpAccessChain: Float*: p[0] # 115: OpLoad: Float: tmp115 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR71) src0(VGPR0) # 116: OpExtInst(FMax): Float: tmp116 << tmp113, tmp115 V_MAX_F32 vDst(VGPR72) src0(VGPR70) src1(VGPR71) // VOP2 # 117: OpCompositeConstruct: FloatVector3: tmp117 << tmp105, tmp111, tmp116 V_MOV_B32 vDst(VGPR73) src0(VGPR66) V_MOV_B32 vDst(VGPR74) src0(VGPR69) V_MOV_B32 vDst(VGPR75) src0(VGPR72) # 118: OpAccessChain: Float*: d[0] # 119: OpCompositeExtract: Float: tmp119 << tmp117, 0 V_MOV_B32 vDst(VGPR76) src0(VGPR73) # 120: OpAccessChain: Float*: d[1] # 121: OpCompositeExtract: Float: tmp121 << tmp117, 1 V_MOV_B32 vDst(VGPR77) src0(VGPR74) # 122: OpAccessChain: Float*: d[2] # 123: OpCompositeExtract: Float: tmp123 << tmp117, 2 V_MOV_B32 vDst(VGPR78) src0(VGPR75) # 124: OpExtInst(FMin): Float: tmp124 << tmp121, tmp123 V_MIN_F32 vDst(VGPR79) src0(VGPR77) src1(VGPR78) // VOP2 # 125: OpExtInst(FMin): Float: tmp125 << tmp119, tmp124 V_MIN_F32 vDst(VGPR80) src0(VGPR76) src1(VGPR79) // VOP2 # 127: OpFSub: Float: tmp127 << tmp125, const126 V_MOV_B32 vDst(VGPR81) src0(LITERAL_CONST) const: 0x3eaaaaab V_SUB_F32 vDst(VGPR82) src0(VGPR80) src1(VGPR81) // VOP2 # OpReturnValue: : << tmp127 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR82) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # Float sdCrossRep(vf3;(FloatVector3* p) Function: Float sdCrossRep(vf3;() S_MOV_B64 sDst(SGPR26) src0(EXEC) # lb15 Label: lb15 # 131: OpLoad: FloatVector3: tmp131 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR86) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR87) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR88) src0(VGPR2) # 132: OpCompositeConstruct: FloatVector3: tmp132 << const88, const88, const88 V_MOV_B32 vDst(VGPR89) src0(1_0_F) V_MOV_B32 vDst(VGPR90) src0(1_0_F) V_MOV_B32 vDst(VGPR91) src0(1_0_F) # 133: OpFAdd: FloatVector3: tmp133 << tmp131, tmp132 V_ADD_F32 vDst(VGPR92) src0(VGPR86) src1(VGPR89) // VOP2 V_ADD_F32 vDst(VGPR93) src0(VGPR87) src1(VGPR90) // VOP2 V_ADD_F32 vDst(VGPR94) src0(VGPR88) src1(VGPR91) // VOP2 # 135: OpCompositeConstruct: FloatVector3: tmp135 << const134, const134, const134 V_MOV_B32 vDst(VGPR95) src0(2_0_F) V_MOV_B32 vDst(VGPR96) src0(2_0_F) V_MOV_B32 vDst(VGPR97) src0(2_0_F) # 136: OpFMod: FloatVector3: tmp136 << tmp133, tmp135 V_RCP_F32 vDst(VGPR98) src0(VGPR95) V_MUL_F32 vDst(VGPR98) src0(VGPR92) src1(VGPR98) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR98) src0(VGPR98) src1(VGPR95) src2(VGPR92) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR98) src0(VGPR98) V_RCP_F32 vDst(VGPR99) src0(VGPR96) V_MUL_F32 vDst(VGPR99) src0(VGPR93) src1(VGPR99) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR99) src0(VGPR99) src1(VGPR96) src2(VGPR93) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR99) src0(VGPR99) V_RCP_F32 vDst(VGPR100) src0(VGPR97) V_MUL_F32 vDst(VGPR100) src0(VGPR94) src1(VGPR100) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR100) src0(VGPR100) src1(VGPR97) src2(VGPR94) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR100) src0(VGPR100) V_MAD_F32 vDst(VGPR98) src0(VGPR95) src1(VGPR98) src2(VGPR92) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR99) src0(VGPR96) src1(VGPR99) src2(VGPR93) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR100) src0(VGPR97) src1(VGPR100) src2(VGPR94) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 137: OpCompositeConstruct: FloatVector3: tmp137 << const88, const88, const88 V_MOV_B32 vDst(VGPR101) src0(1_0_F) V_MOV_B32 vDst(VGPR102) src0(1_0_F) V_MOV_B32 vDst(VGPR103) src0(1_0_F) # 138: OpFSub: FloatVector3: tmp138 << tmp136, tmp137 V_SUB_F32 vDst(VGPR104) src0(VGPR98) src1(VGPR101) // VOP2 V_SUB_F32 vDst(VGPR105) src0(VGPR99) src1(VGPR102) // VOP2 V_SUB_F32 vDst(VGPR106) src0(VGPR100) src1(VGPR103) // VOP2 # OpStore: : tmp138 >> param139 V_MOV_B32 vDst(VGPR83) src0(VGPR104) V_MOV_B32 vDst(VGPR84) src0(VGPR105) V_MOV_B32 vDst(VGPR85) src0(VGPR106) # 141: OpFunctionCall: Float: sdCross(vf3;(param139) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x53 # VGPR[83:85] S_MOV_B64 sDst(SGPR28) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x6b # VGPR107 # Indirect branch to sdCross(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR28) # .lbl1 # OpReturnValue: : << sdCross(vf3; S_MOV_B32 sDst(M0) src0(SGPR24) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR107) S_SETPC_B64 sDst(SGPR22) src0(SGPR22) # Float sdCrossRepScale(vf3;f1;(FloatVector3* p, Float* s) Function: Float sdCrossRepScale(vf3;f1;(, Float sdCrossRep(vf3;.s) S_MOV_B64 sDst(SGPR36) src0(EXEC) # lb21 Label: lb21 # 144: OpLoad: FloatVector3: tmp144 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR33) const: 0x0 V_MOVRELS_B32 vDst(VGPR111) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR112) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR113) src0(VGPR2) # 145: OpLoad: Float: tmp145 << s S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR34) const: 0x0 V_MOVRELS_B32 vDst(VGPR114) src0(VGPR0) # 146: OpVectorTimesScalar: FloatVector3: tmp146 << tmp144, tmp145 V_MUL_F32 vDst(VGPR115) src0(VGPR114) src1(VGPR111) // VOP2 V_MUL_F32 vDst(VGPR116) src0(VGPR114) src1(VGPR112) // VOP2 V_MUL_F32 vDst(VGPR117) src0(VGPR114) src1(VGPR113) // VOP2 # OpStore: : tmp146 >> param147 V_MOV_B32 vDst(VGPR108) src0(VGPR115) V_MOV_B32 vDst(VGPR109) src0(VGPR116) V_MOV_B32 vDst(VGPR110) src0(VGPR117) # 148: OpFunctionCall: Float: sdCrossRep(vf3;(param147) S_ADD_U32 sDst(SGPR25) src0(LITERAL_CONST) src1(0) const: 0x6c # VGPR[108:110] S_MOV_B64 sDst(SGPR38) src0(EXEC) S_MOV_B32 sDst(SGPR24) src0(LITERAL_CONST) const: 0x76 # VGPR118 # Indirect branch to sdCrossRep(vf3;: ??? S_GETPC_B64 sDst(SGPR22) src0(SGPR22) S_ADD_U32 sDst(SGPR22) src0(SGPR22) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR23) src0(SGPR23) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR22) src0(SGPR22) S_MOV_B64 sDst(EXEC) src0(SGPR38) # .lbl2 # 149: OpLoad: Float: tmp149 << s S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR34) const: 0x0 V_MOVRELS_B32 vDst(VGPR119) src0(VGPR0) # 150: OpFDiv: Float: tmp150 << sdCrossRep(vf3;, tmp149 V_RCP_F32 vDst(VGPR120) src0(VGPR119) V_MUL_F32 vDst(VGPR120) src0(VGPR118) src1(VGPR120) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR120) src0(VGPR120) src1(VGPR119) src2(VGPR118) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp150 S_MOV_B32 sDst(M0) src0(SGPR32) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR120) S_SETPC_B64 sDst(SGPR30) src0(SGPR30) # Float differenceSDF(f1;f1;(Float* distA, Float* distB) Function: Float differenceSDF(f1;f1;(, Float sdCrossRepScale(vf3;f1;.distB) S_MOV_B64 sDst(SGPR46) src0(EXEC) # lb26 Label: lb26 # 153: OpLoad: Float: tmp153 << distA S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR43) const: 0x0 V_MOVRELS_B32 vDst(VGPR121) src0(VGPR0) # 154: OpLoad: Float: tmp154 << distB S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR44) const: 0x0 V_MOVRELS_B32 vDst(VGPR122) src0(VGPR0) # 155: OpFNegate: Float: tmp155 << tmp154 V_MUL_F32 vDst(VGPR123) src0(M1_0_F) src1(VGPR122) // VOP2 # 156: OpExtInst(FMax): Float: tmp156 << tmp153, tmp155 V_MAX_F32 vDst(VGPR124) src0(VGPR121) src1(VGPR123) // VOP2 # OpReturnValue: : << tmp156 S_MOV_B32 sDst(M0) src0(SGPR42) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR124) S_SETPC_B64 sDst(SGPR40) src0(SGPR40) # Float sdCylinder(vf3;vf2;(FloatVector3* p, FloatVector2* h) Function: Float sdCylinder(vf3;vf2;(, FloatVector2 differenceSDF(f1;f1;.h) S_MOV_B64 sDst(SGPR54) src0(EXEC) # lb33 Label: lb33 # 160: OpLoad: FloatVector3: tmp160 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR51) const: 0x0 V_MOVRELS_B32 vDst(VGPR125) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR126) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR127) src0(VGPR2) # 161: OpVectorShuffle: FloatVector2: tmp161 << tmp160, tmp160, 0, 2 V_MOV_B32 vDst(VGPR128) src0(VGPR125) V_MOV_B32 vDst(VGPR129) src0(VGPR127) # 162: OpExtInst(Length): Float: tmp162 << tmp161 V_MUL_F32 vDst(VGPR130) src0(VGPR128) src1(VGPR128) // VOP2 V_MAC_F32 vDst(VGPR130) src0(VGPR129) src1(VGPR129) // VOP2 V_SQRT_F32 vDst(VGPR130) src0(VGPR130) # 163: OpAccessChain: Float*: p[1] # 164: OpLoad: Float: tmp164 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR51) const: 0x0 V_MOVRELS_B32 vDst(VGPR131) src0(VGPR1) # 165: OpCompositeConstruct: FloatVector2: tmp165 << tmp162, tmp164 V_MOV_B32 vDst(VGPR132) src0(VGPR130) V_MOV_B32 vDst(VGPR133) src0(VGPR131) # 166: OpExtInst(FAbs): FloatVector2: tmp166 << tmp165 V_ADD_F32 vDst(VGPR134) src0(VGPR132) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR135) src0(VGPR133) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 167: OpLoad: FloatVector2: tmp167 << h S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR52) const: 0x0 V_MOVRELS_B32 vDst(VGPR136) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR137) src0(VGPR1) # 168: OpFSub: FloatVector2: tmp168 << tmp166, tmp167 V_SUB_F32 vDst(VGPR138) src0(VGPR134) src1(VGPR136) // VOP2 V_SUB_F32 vDst(VGPR139) src0(VGPR135) src1(VGPR137) // VOP2 # 169: OpAccessChain: Float*: d[0] # 170: OpCompositeExtract: Float: tmp170 << tmp168, 0 V_MOV_B32 vDst(VGPR140) src0(VGPR138) # 171: OpAccessChain: Float*: d[1] # 172: OpCompositeExtract: Float: tmp172 << tmp168, 1 V_MOV_B32 vDst(VGPR141) src0(VGPR139) # 173: OpExtInst(FMax): Float: tmp173 << tmp170, tmp172 V_MAX_F32 vDst(VGPR142) src0(VGPR140) src1(VGPR141) // VOP2 # 175: OpExtInst(FMin): Float: tmp175 << tmp173, const174 V_MOV_B32 vDst(VGPR143) src0(LITERAL_CONST) const: 0x00000000 V_MIN_F32 vDst(VGPR144) src0(VGPR142) src1(VGPR143) // VOP2 # 177: OpCompositeConstruct: FloatVector2: tmp177 << const174, const174 V_MOV_B32 vDst(VGPR147) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR145) src0(VGPR147) V_MOV_B32 vDst(VGPR148) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR146) src0(VGPR148) # 178: OpExtInst(FMax): FloatVector2: tmp178 << tmp168, tmp177 V_MAX_F32 vDst(VGPR149) src0(VGPR138) src1(VGPR145) // VOP2 V_MAX_F32 vDst(VGPR150) src0(VGPR139) src1(VGPR146) // VOP2 # 179: OpExtInst(Length): Float: tmp179 << tmp178 V_MUL_F32 vDst(VGPR151) src0(VGPR149) src1(VGPR149) // VOP2 V_MAC_F32 vDst(VGPR151) src0(VGPR150) src1(VGPR150) // VOP2 V_SQRT_F32 vDst(VGPR151) src0(VGPR151) # 180: OpFAdd: Float: tmp180 << tmp175, tmp179 V_ADD_F32 vDst(VGPR152) src0(VGPR144) src1(VGPR151) // VOP2 # OpReturnValue: : << tmp180 S_MOV_B32 sDst(M0) src0(SGPR50) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR152) S_SETPC_B64 sDst(SGPR48) src0(SGPR48) # FloatVector2 opU(vf2;vf2;(FloatVector2* d1, FloatVector2* d2) Function: FloatVector2 opU(vf2;vf2;(, FloatVector2 sdCylinder(vf3;vf2;.d2) S_MOV_B64 sDst(SGPR62) src0(EXEC) # lb38 Label: lb38 # 183: OpAccessChain: Float*: d1[0] # 184: OpLoad: Float: tmp184 << d1[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR59) const: 0x0 V_MOVRELS_B32 vDst(VGPR155) src0(VGPR0) # 185: OpAccessChain: Float*: d2[0] # 186: OpLoad: Float: tmp186 << d2[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR60) const: 0x0 V_MOVRELS_B32 vDst(VGPR156) src0(VGPR0) # 188: OpFOrdLessThan: Bool: tmp188 << tmp184, tmp186 V_CMP_LT_F32 dst(SGPR64) src0(VGPR155) src1(VGPR156) // VOP3a # OpSelectionMerge: (merge: lb190) # CF Block: Merge: lb190 S_MOV_B64 sDst(SGPR66) src0(EXEC) # OpBranchConditional: if(tmp188) then branch to lb189, else branch to lb193 # CF Block: Cond Branch: true: lb189, false: lb193 S_AND_B64 sDst(EXEC) src0(SGPR64) src1(EXEC) S_CBRANCH_EXECZ ??? lb193 S_BRANCH ??? lb189 # lb189 Label: lb189 # 192: OpLoad: FloatVector2: tmp192 << d1 S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR59) const: 0x0 V_MOVRELS_B32 vDst(VGPR157) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR158) src0(VGPR1) # OpStore: : tmp192 >> resp V_MOV_B32 vDst(VGPR153) src0(VGPR157) V_MOV_B32 vDst(VGPR154) src0(VGPR158) # OpBranch: to lb190 S_BRANCH ??? lb190 # lb193 Label: lb193 # 194: OpLoad: FloatVector2: tmp194 << d2 S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR60) const: 0x0 V_MOVRELS_B32 vDst(VGPR159) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR160) src0(VGPR1) # OpStore: : tmp194 >> resp V_MOV_B32 vDst(VGPR153) src0(VGPR159) V_MOV_B32 vDst(VGPR154) src0(VGPR160) # OpBranch: to lb190 S_BRANCH ??? lb190 # lb190 Label: lb190 # 195: OpLoad: FloatVector2: tmp195 << resp # OpReturnValue: : << tmp195 S_MOV_B32 sDst(M0) src0(SGPR58) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR153) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR154) S_SETPC_B64 sDst(SGPR56) src0(SGPR56) # Float diso(vf3;(FloatVector3* p) Function: Float diso(vf3;() S_MOV_B64 sDst(SGPR72) src0(EXEC) # lb41 Label: lb41 # OpStore: : const200 >> res V_MOV_B32 vDst(VGPR179) src0(LITERAL_CONST) const: 0x461c3c00 V_MOV_B32 vDst(VGPR180) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR161) src0(VGPR179) V_MOV_B32 vDst(VGPR162) src0(VGPR180) # 201: OpAccessChain: Float*: p[2] # 202: OpLoad: Float: tmp202 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR181) src0(VGPR2) # 203: OpFMod: Float: tmp203 << tmp202, const134 V_MOV_B32 vDst(VGPR182) src0(2_0_F) V_RCP_F32 vDst(VGPR183) src0(VGPR182) V_MUL_F32 vDst(VGPR183) src0(VGPR181) src1(VGPR183) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR183) src0(VGPR183) src1(VGPR182) src2(VGPR181) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR183) src0(VGPR183) V_MAD_F32 vDst(VGPR183) src0(VGPR182) src1(VGPR183) src2(VGPR181) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 204: OpAccessChain: Float*: p[2] # OpStore: : tmp203 >> p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELD_B32 vDst(VGPR2) src0(VGPR183) # 209: OpLoad: FloatVector3: tmp209 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR184) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR185) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR186) src0(VGPR2) # 210: OpVectorShuffle: FloatVector3: tmp210 << tmp209, tmp209, 1, 2, 0 V_MOV_B32 vDst(VGPR187) src0(VGPR185) V_MOV_B32 vDst(VGPR188) src0(VGPR186) V_MOV_B32 vDst(VGPR189) src0(VGPR184) # OpStore: : tmp210 >> param208 V_MOV_B32 vDst(VGPR163) src0(VGPR187) V_MOV_B32 vDst(VGPR164) src0(VGPR188) V_MOV_B32 vDst(VGPR165) src0(VGPR189) # OpStore: : const207 >> param211 V_MOV_B32 vDst(VGPR190) src0(LITERAL_CONST) const: 0x40c00000 V_MOV_B32 vDst(VGPR191) src0(LITERAL_CONST) const: 0x40c00000 V_MOV_B32 vDst(VGPR166) src0(VGPR190) V_MOV_B32 vDst(VGPR167) src0(VGPR191) # 212: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param208, param211) S_ADD_U32 sDst(SGPR51) src0(LITERAL_CONST) src1(0) const: 0xa3 # VGPR[163:165] S_ADD_U32 sDst(SGPR52) src0(LITERAL_CONST) src1(0) const: 0xa6 # VGPR[166:167] S_MOV_B64 sDst(SGPR74) src0(EXEC) S_MOV_B32 sDst(SGPR50) src0(LITERAL_CONST) const: 0xc0 # VGPR192 # Indirect branch to sdCylinder(vf3;vf2;: ??? S_GETPC_B64 sDst(SGPR48) src0(SGPR48) S_ADD_U32 sDst(SGPR48) src0(SGPR48) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR49) src0(SGPR49) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR48) src0(SGPR48) S_MOV_B64 sDst(EXEC) src0(SGPR74) # .lbl3 # 218: OpLoad: FloatVector3: tmp218 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR193) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR194) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR195) src0(VGPR2) # 219: OpVectorShuffle: FloatVector3: tmp219 << tmp218, tmp218, 1, 2, 0 V_MOV_B32 vDst(VGPR196) src0(VGPR194) V_MOV_B32 vDst(VGPR197) src0(VGPR195) V_MOV_B32 vDst(VGPR198) src0(VGPR193) # OpStore: : tmp219 >> param217 V_MOV_B32 vDst(VGPR168) src0(VGPR196) V_MOV_B32 vDst(VGPR169) src0(VGPR197) V_MOV_B32 vDst(VGPR170) src0(VGPR198) # OpStore: : const216 >> param220 V_MOV_B32 vDst(VGPR199) src0(LITERAL_CONST) const: 0x3ff33333 V_MOV_B32 vDst(VGPR200) src0(LITERAL_CONST) const: 0x40d8f5c3 V_MOV_B32 vDst(VGPR171) src0(VGPR199) V_MOV_B32 vDst(VGPR172) src0(VGPR200) # 221: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param217, param220) S_ADD_U32 sDst(SGPR51) src0(LITERAL_CONST) src1(0) const: 0xa8 # VGPR[168:170] S_ADD_U32 sDst(SGPR52) src0(LITERAL_CONST) src1(0) const: 0xab # VGPR[171:172] S_MOV_B64 sDst(SGPR76) src0(EXEC) S_MOV_B32 sDst(SGPR50) src0(LITERAL_CONST) const: 0xc9 # VGPR201 # Indirect branch to sdCylinder(vf3;vf2;: ??? S_GETPC_B64 sDst(SGPR48) src0(SGPR48) S_ADD_U32 sDst(SGPR48) src0(SGPR48) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR49) src0(SGPR49) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR48) src0(SGPR48) S_MOV_B64 sDst(EXEC) src0(SGPR76) # .lbl4 # OpStore: : sdCylinder(vf3;vf2; >> param223 V_MOV_B32 vDst(VGPR173) src0(VGPR192) # OpStore: : sdCylinder(vf3;vf2; >> param225 V_MOV_B32 vDst(VGPR174) src0(VGPR201) # 227: OpFunctionCall: Float: differenceSDF(f1;f1;(param223, param225) S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0xad # VGPR173 S_ADD_U32 sDst(SGPR44) src0(LITERAL_CONST) src1(0) const: 0xae # VGPR174 S_MOV_B64 sDst(SGPR78) src0(EXEC) S_MOV_B32 sDst(SGPR42) src0(LITERAL_CONST) const: 0xca # VGPR202 # Indirect branch to differenceSDF(f1;f1;: ??? S_GETPC_B64 sDst(SGPR40) src0(SGPR40) S_ADD_U32 sDst(SGPR40) src0(SGPR40) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR41) src0(SGPR41) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR40) src0(SGPR40) S_MOV_B64 sDst(EXEC) src0(SGPR78) # .lbl5 # 230: OpCompositeConstruct: FloatVector2: tmp230 << differenceSDF(f1;f1;, const229 V_MOV_B32 vDst(VGPR203) src0(VGPR202) V_MOV_B32 vDst(VGPR205) src0(LITERAL_CONST) const: 0x41100000 V_MOV_B32 vDst(VGPR204) src0(VGPR205) # 232: OpLoad: FloatVector2: tmp232 << res # OpStore: : tmp232 >> param231 V_MOV_B32 vDst(VGPR175) src0(VGPR161) V_MOV_B32 vDst(VGPR176) src0(VGPR162) # OpStore: : tmp230 >> param233 V_MOV_B32 vDst(VGPR177) src0(VGPR203) V_MOV_B32 vDst(VGPR178) src0(VGPR204) # 234: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param231, param233) S_ADD_U32 sDst(SGPR59) src0(LITERAL_CONST) src1(0) const: 0xaf # VGPR[175:176] S_ADD_U32 sDst(SGPR60) src0(LITERAL_CONST) src1(0) const: 0xb1 # VGPR[177:178] S_MOV_B64 sDst(SGPR80) src0(EXEC) S_MOV_B32 sDst(SGPR58) src0(LITERAL_CONST) const: 0xce # VGPR[206:207] # Indirect branch to opU(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_ADD_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR80) # .lbl6 # OpStore: : opU(vf2;vf2; >> res V_MOV_B32 vDst(VGPR161) src0(VGPR206) V_MOV_B32 vDst(VGPR162) src0(VGPR207) # 235: OpAccessChain: Float*: res[0] # 236: OpLoad: Float: tmp236 << res[0] V_MOV_B32 vDst(VGPR208) src0(VGPR161) # OpReturnValue: : << tmp236 S_MOV_B32 sDst(M0) src0(SGPR70) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR208) S_SETPC_B64 sDst(SGPR68) src0(SGPR68) # Float DE(vf3;(FloatVector3* p) Function: Float DE(vf3;() S_MOV_B64 sDst(SGPR86) src0(EXEC) # lb44 Label: lb44 # OpStore: : const240 >> scale V_MOV_B32 vDst(VGPR229) src0(LITERAL_CONST) const: 0x3eb33333 V_MOV_B32 vDst(VGPR209) src0(VGPR229) # OpStore: : const243 >> res V_MOV_B32 vDst(VGPR230) src0(LITERAL_CONST) const: 0x461c3f9a V_MOV_B32 vDst(VGPR231) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR210) src0(VGPR230) V_MOV_B32 vDst(VGPR211) src0(VGPR231) # OpStore: : const245 >> dist V_MOV_B32 vDst(VGPR232) src0(LITERAL_CONST) const: 0xc479c000 V_MOV_B32 vDst(VGPR212) src0(VGPR232) # 247: OpLoad: FloatVector3: tmp247 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR233) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR234) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR235) src0(VGPR2) # OpStore: : tmp247 >> param246 V_MOV_B32 vDst(VGPR213) src0(VGPR233) V_MOV_B32 vDst(VGPR214) src0(VGPR234) V_MOV_B32 vDst(VGPR215) src0(VGPR235) # 248: OpFunctionCall: Float: diso(vf3;(param246) S_ADD_U32 sDst(SGPR71) src0(LITERAL_CONST) src1(0) const: 0xd5 # VGPR[213:215] S_MOV_B64 sDst(SGPR88) src0(EXEC) S_MOV_B32 sDst(SGPR70) src0(LITERAL_CONST) const: 0xec # VGPR236 # Indirect branch to diso(vf3;: ??? S_GETPC_B64 sDst(SGPR68) src0(SGPR68) S_ADD_U32 sDst(SGPR68) src0(SGPR68) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR69) src0(SGPR69) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR68) src0(SGPR68) S_MOV_B64 sDst(EXEC) src0(SGPR88) # .lbl7 # OpStore: : diso(vf3; >> dist V_MOV_B32 vDst(VGPR212) src0(VGPR236) # OpStore: : const250 >> i V_MOV_B32 vDst(VGPR216) src0(0) # OpBranch: to lb251 S_BRANCH ??? lb251 # lb251 Label: lb251 # OpLoopMerge: (merge: lb253, continue: lb254) # CF Block: Merge: lb253, Continue: lb254 S_MOV_B64 sDst(SGPR90) src0(EXEC) S_MOV_B64 sDst(SGPR92) src0(EXEC) S_MOV_B64 sDst(SGPR94) src0(EXEC) Label: lb251Loop # OpBranch: to lb255 S_BRANCH ??? lb255 # lb255 Label: lb255 # 256: OpLoad: Int: tmp256 << i Decorators: RelaxedPrecision # 258: OpSLessThan: Bool: tmp258 << tmp256, const257 V_MOV_B32 vDst(VGPR237) src0(5_INT) V_CMP_LT_I32 dst(SGPR96) src0(VGPR216) src1(VGPR237) // VOP3a # OpBranchConditional: if(tmp258) then branch to lb252, else branch to lb253 # CF Block: Cond Branch: true: lb252, false: lb253 S_AND_B64 sDst(EXEC) src0(SGPR96) src1(EXEC) S_CBRANCH_EXECZ ??? lb253 S_BRANCH ??? lb252 # lb252 Label: lb252 # 259: OpLoad: Float: tmp259 << dist # 261: OpLoad: FloatVector3: tmp261 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR238) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR239) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR240) src0(VGPR2) # OpStore: : tmp261 >> param260 V_MOV_B32 vDst(VGPR217) src0(VGPR238) V_MOV_B32 vDst(VGPR218) src0(VGPR239) V_MOV_B32 vDst(VGPR219) src0(VGPR240) # 263: OpLoad: Float: tmp263 << scale # OpStore: : tmp263 >> param262 V_MOV_B32 vDst(VGPR220) src0(VGPR209) # 264: OpFunctionCall: Float: sdCrossRepScale(vf3;f1;(param260, param262) S_ADD_U32 sDst(SGPR33) src0(LITERAL_CONST) src1(0) const: 0xd9 # VGPR[217:219] S_ADD_U32 sDst(SGPR34) src0(LITERAL_CONST) src1(0) const: 0xdc # VGPR220 S_MOV_B64 sDst(SGPR98) src0(EXEC) S_MOV_B32 sDst(SGPR32) src0(LITERAL_CONST) const: 0xf1 # VGPR241 # Indirect branch to sdCrossRepScale(vf3;f1;: ??? S_GETPC_B64 sDst(SGPR30) src0(SGPR30) S_ADD_U32 sDst(SGPR30) src0(SGPR30) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR31) src0(SGPR31) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR30) src0(SGPR30) S_MOV_B64 sDst(EXEC) src0(SGPR98) # .lbl8 # 265: OpFNegate: Float: tmp265 << sdCrossRepScale(vf3;f1; V_MUL_F32 vDst(VGPR242) src0(M1_0_F) src1(VGPR241) // VOP2 # 266: OpExtInst(FMax): Float: tmp266 << tmp259, tmp265 V_MAX_F32 vDst(VGPR243) src0(VGPR212) src1(VGPR242) // VOP2 # OpStore: : tmp266 >> dist V_MOV_B32 vDst(VGPR212) src0(VGPR243) # 268: OpLoad: Float: tmp268 << scale # 269: OpFMul: Float: tmp269 << tmp268, const267 V_MOV_B32 vDst(VGPR244) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR245) src0(VGPR209) src1(VGPR244) // VOP2 # OpStore: : tmp269 >> scale V_MOV_B32 vDst(VGPR209) src0(VGPR245) # OpBranch: to lb254 S_BRANCH ??? lb254 # lb254 Label: lb254 # 270: OpLoad: Int: tmp270 << i Decorators: RelaxedPrecision # 272: OpIAdd: Int: tmp272 << tmp270, const271 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR246) src0(1_INT) V_ADD_I32 vDst(VGPR247) src0(VGPR216) src1(VGPR246) // VOP2 # OpStore: : tmp272 >> i V_MOV_B32 vDst(VGPR216) src0(VGPR247) # OpBranch: to lb251 S_BRANCH ??? lb251 # lb253 Label: lb253 # 275: OpLoad: Float: tmp275 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR100) S_WAITCNT 0 # 276: OpExtInst(Floor): Float: tmp276 << tmp275 V_FLOOR_F32 vDst(VGPR248) src0(SGPR100) # 278: OpFMod: Float: tmp278 << tmp276, const277 V_MOV_B32 vDst(VGPR249) src0(LITERAL_CONST) const: 0x40a00000 V_RCP_F32 vDst(VGPR250) src0(VGPR249) V_MUL_F32 vDst(VGPR250) src0(VGPR248) src1(VGPR250) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR250) src0(VGPR250) src1(VGPR249) src2(VGPR248) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR250) src0(VGPR250) V_MAD_F32 vDst(VGPR250) src0(VGPR249) src1(VGPR250) src2(VGPR248) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 280: OpFOrdGreaterThan: Bool: tmp280 << tmp278, const279 V_MOV_B32 vDst(VGPR251) src0(LITERAL_CONST) const: 0x3ecccccd V_CMP_GT_F32 dst(SGPR102) src0(VGPR250) src1(VGPR251) // VOP3a # OpSelectionMerge: (merge: lb282) # CF Block: Merge: lb282 S_MOV_B64 sDst(SGPR104) src0(EXEC) # OpBranchConditional: if(tmp280) then branch to lb281, else branch to lb290 # CF Block: Cond Branch: true: lb281, false: lb290 S_AND_B64 sDst(EXEC) src0(SGPR102) src1(EXEC) S_CBRANCH_EXECZ ??? lb290 S_BRANCH ??? lb281 # lb281 Label: lb281 # 283: OpLoad: Float: tmp283 << dist # 285: OpCompositeConstruct: FloatVector2: tmp285 << tmp283, const284 V_MOV_B32 vDst(VGPR252) src0(VGPR212) V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x41000000 V_MOV_B32 vDst(VGPR253) src0(VGPR254) # 287: OpLoad: FloatVector2: tmp287 << res # OpStore: : tmp287 >> param286 V_MOV_B32 vDst(VGPR221) src0(VGPR210) V_MOV_B32 vDst(VGPR222) src0(VGPR211) # OpStore: : tmp285 >> param288 V_MOV_B32 vDst(VGPR223) src0(VGPR252) V_MOV_B32 vDst(VGPR224) src0(VGPR253) # 289: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param286, param288) S_ADD_U32 sDst(SGPR59) src0(LITERAL_CONST) src1(0) const: 0xdd # VGPR[221:222] S_ADD_U32 sDst(SGPR60) src0(LITERAL_CONST) src1(0) const: 0xdf # VGPR[223:224] S_MOV_B64 sDst(SGPR106) src0(EXEC) S_MOV_B32 sDst(SGPR58) src0(LITERAL_CONST) const: 0xff # VGPR[255:256] # Indirect branch to opU(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_ADD_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR106) # .lbl9 # OpStore: : opU(vf2;vf2; >> res V_MOV_B32 vDst(VGPR210) src0(VGPR255) V_MOV_B32 vDst(VGPR211) src0(VGPR256) # OpBranch: to lb282 S_BRANCH ??? lb282 # lb290 Label: lb290 # 291: OpLoad: Float: tmp291 << dist # 293: OpCompositeConstruct: FloatVector2: tmp293 << tmp291, const292 V_MOV_B32 vDst(VGPR257) src0(VGPR212) V_MOV_B32 vDst(VGPR259) src0(LITERAL_CONST) const: 0x40e00000 V_MOV_B32 vDst(VGPR258) src0(VGPR259) # 295: OpLoad: FloatVector2: tmp295 << res # OpStore: : tmp295 >> param294 V_MOV_B32 vDst(VGPR225) src0(VGPR210) V_MOV_B32 vDst(VGPR226) src0(VGPR211) # OpStore: : tmp293 >> param296 V_MOV_B32 vDst(VGPR227) src0(VGPR257) V_MOV_B32 vDst(VGPR228) src0(VGPR258) # 297: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param294, param296) S_ADD_U32 sDst(SGPR59) src0(LITERAL_CONST) src1(0) const: 0xe1 # VGPR[225:226] S_ADD_U32 sDst(SGPR60) src0(LITERAL_CONST) src1(0) const: 0xe3 # VGPR[227:228] S_MOV_B64 sDst(SGPR108) src0(EXEC) S_MOV_B32 sDst(SGPR58) src0(LITERAL_CONST) const: 0x104 # VGPR[260:261] # Indirect branch to opU(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_ADD_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR108) # .lbl10 # OpStore: : opU(vf2;vf2; >> res V_MOV_B32 vDst(VGPR210) src0(VGPR260) V_MOV_B32 vDst(VGPR211) src0(VGPR261) # OpBranch: to lb282 S_BRANCH ??? lb282 # lb282 Label: lb282 # 300: OpAccessChain: Float*: res[1] # 301: OpLoad: Float: tmp301 << res[1] V_MOV_B32 vDst(VGPR262) src0(VGPR211) # OpStore: : tmp301 >> NumCol V_MOV_B32 vDst(VGPR263) src0(VGPR262) # 302: OpAccessChain: Float*: res[0] # 303: OpLoad: Float: tmp303 << res[0] V_MOV_B32 vDst(VGPR264) src0(VGPR210) # OpReturnValue: : << tmp303 S_MOV_B32 sDst(M0) src0(SGPR84) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR264) S_SETPC_B64 sDst(SGPR82) src0(SGPR82) # FloatVector2 march(vf3;vf3;(FloatVector3* ro, FloatVector3* rd) Function: FloatVector2 march(vf3;vf3;(, FloatVector3 DE(vf3;.rd) S_MOV_B64 sDst(SGPR116) src0(EXEC) # lb49 Label: lb49 # OpStore: : const174 >> t V_MOV_B32 vDst(VGPR272) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR265) src0(VGPR272) # OpStore: : const308 >> d V_MOV_B32 vDst(VGPR273) src0(LITERAL_CONST) const: 0x41a00000 V_MOV_B32 vDst(VGPR266) src0(VGPR273) # OpStore: : const174 >> it V_MOV_B32 vDst(VGPR274) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR267) src0(VGPR274) # OpStore: : const250 >> i V_MOV_B32 vDst(VGPR268) src0(0) # OpBranch: to lb311 S_BRANCH ??? lb311 # lb311 Label: lb311 # OpLoopMerge: (merge: lb313, continue: lb314) # CF Block: Merge: lb313, Continue: lb314 S_MOV_B64 sDst(SGPR118) src0(EXEC) S_MOV_B64 sDst(SGPR120) src0(EXEC) S_MOV_B64 sDst(SGPR122) src0(EXEC) Label: lb311Loop # OpBranch: to lb315 S_BRANCH ??? lb315 # lb315 Label: lb315 # 316: OpLoad: Int: tmp316 << i Decorators: RelaxedPrecision # 318: OpSLessThan: Bool: tmp318 << tmp316, const317 V_MOV_B32 vDst(VGPR275) src0(LITERAL_CONST) const: 0x00000064 V_CMP_LT_I32 dst(SGPR124) src0(VGPR268) src1(VGPR275) // VOP3a # OpBranchConditional: if(tmp318) then branch to lb312, else branch to lb313 # CF Block: Cond Branch: true: lb312, false: lb313 S_AND_B64 sDst(EXEC) src0(SGPR124) src1(EXEC) S_CBRANCH_EXECZ ??? lb313 S_BRANCH ??? lb312 # lb312 Label: lb312 # 319: OpLoad: FloatVector3: tmp319 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR113) const: 0x0 V_MOVRELS_B32 vDst(VGPR276) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR277) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR278) src0(VGPR2) # 320: OpLoad: Float: tmp320 << t # 321: OpLoad: FloatVector3: tmp321 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR114) const: 0x0 V_MOVRELS_B32 vDst(VGPR279) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR280) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR281) src0(VGPR2) # 322: OpVectorTimesScalar: FloatVector3: tmp322 << tmp321, tmp320 V_MUL_F32 vDst(VGPR282) src0(VGPR265) src1(VGPR279) // VOP2 V_MUL_F32 vDst(VGPR283) src0(VGPR265) src1(VGPR280) // VOP2 V_MUL_F32 vDst(VGPR284) src0(VGPR265) src1(VGPR281) // VOP2 # 323: OpFAdd: FloatVector3: tmp323 << tmp319, tmp322 V_ADD_F32 vDst(VGPR285) src0(VGPR276) src1(VGPR282) // VOP2 V_ADD_F32 vDst(VGPR286) src0(VGPR277) src1(VGPR283) // VOP2 V_ADD_F32 vDst(VGPR287) src0(VGPR278) src1(VGPR284) // VOP2 # OpStore: : tmp323 >> param324 V_MOV_B32 vDst(VGPR269) src0(VGPR285) V_MOV_B32 vDst(VGPR270) src0(VGPR286) V_MOV_B32 vDst(VGPR271) src0(VGPR287) # 325: OpFunctionCall: Float: DE(vf3;(param324) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x10d # VGPR[269:271] S_MOV_B64 sDst(SGPR126) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x120 # VGPR288 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR126) # .lbl11 # OpStore: : DE(vf3; >> d V_MOV_B32 vDst(VGPR266) src0(VGPR288) # 326: OpLoad: Float: tmp326 << t # 327: OpFAdd: Float: tmp327 << tmp326, DE(vf3; V_ADD_F32 vDst(VGPR289) src0(VGPR265) src1(VGPR288) // VOP2 # OpStore: : tmp327 >> t V_MOV_B32 vDst(VGPR265) src0(VGPR289) # 328: OpLoad: Float: tmp328 << d # 330: OpFOrdLessThan: Bool: tmp330 << tmp328, const329 V_MOV_B32 vDst(VGPR290) src0(LITERAL_CONST) const: 0x3a83126f V_CMP_LT_F32 dst(SGPR128) src0(VGPR266) src1(VGPR290) // VOP3a # 331: OpLoad: Float: tmp331 << t # 332: OpFOrdGreaterThan: Bool: tmp332 << tmp331, const308 V_MOV_B32 vDst(VGPR291) src0(LITERAL_CONST) const: 0x41a00000 V_CMP_GT_F32 dst(SGPR130) src0(VGPR265) src1(VGPR291) // VOP3a # 333: OpLogicalOr: Bool: tmp333 << tmp330, tmp332 S_OR_B64 sDst(SGPR132) src0(SGPR128) src1(SGPR130) # OpSelectionMerge: (merge: lb335) # CF Block: Merge: lb335 S_MOV_B64 sDst(SGPR134) src0(EXEC) # OpBranchConditional: if(tmp333) then branch to lb334, else branch to lb335 # CF Block: Cond Branch: true: lb334, false: lb335 S_AND_B64 sDst(EXEC) src0(SGPR132) src1(EXEC) S_CBRANCH_EXECZ ??? lb335 S_BRANCH ??? lb334 # lb334 Label: lb334 # OpBranch: to lb313 S_BRANCH ??? lb313 # lb335 Label: lb335 # 337: OpLoad: Float: tmp337 << it # 338: OpFAdd: Float: tmp338 << tmp337, const88 V_MOV_B32 vDst(VGPR292) src0(1_0_F) V_ADD_F32 vDst(VGPR293) src0(VGPR267) src1(VGPR292) // VOP2 # OpStore: : tmp338 >> it V_MOV_B32 vDst(VGPR267) src0(VGPR293) # OpBranch: to lb314 S_BRANCH ??? lb314 # lb314 Label: lb314 # 339: OpLoad: Int: tmp339 << i Decorators: RelaxedPrecision # 340: OpIAdd: Int: tmp340 << tmp339, const271 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR294) src0(1_INT) V_ADD_I32 vDst(VGPR295) src0(VGPR268) src1(VGPR294) // VOP2 # OpStore: : tmp340 >> i V_MOV_B32 vDst(VGPR268) src0(VGPR295) # OpBranch: to lb311 S_BRANCH ??? lb311 # lb313 Label: lb313 # 341: OpLoad: Float: tmp341 << t # 342: OpLoad: Float: tmp342 << it # 344: OpFDiv: Float: tmp344 << tmp342, const343 V_MOV_B32 vDst(VGPR296) src0(LITERAL_CONST) const: 0x42c80000 V_RCP_F32 vDst(VGPR297) src0(VGPR296) V_MUL_F32 vDst(VGPR297) src0(VGPR267) src1(VGPR297) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR297) src0(VGPR297) src1(VGPR296) src2(VGPR267) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 345: OpCompositeConstruct: FloatVector2: tmp345 << tmp341, tmp344 V_MOV_B32 vDst(VGPR298) src0(VGPR265) V_MOV_B32 vDst(VGPR299) src0(VGPR297) # OpReturnValue: : << tmp345 S_MOV_B32 sDst(M0) src0(SGPR112) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR298) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR299) S_SETPC_B64 sDst(SGPR110) src0(SGPR110) # Float getShadow(vf3;vf3;vf3;(FloatVector3* p, FloatVector3* n, FloatVector3* ld) Function: Float getShadow(vf3;vf3;vf3;(, FloatVector3 march(vf3;vf3;.n, FloatVector3 march(vf3;vf3;.ld) S_MOV_B64 sDst(SGPR142) src0(EXEC) # lb55 Label: lb55 # 349: OpLoad: FloatVector3: tmp349 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR140) const: 0x0 V_MOVRELS_B32 vDst(VGPR306) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR307) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR308) src0(VGPR2) # 350: OpVectorTimesScalar: FloatVector3: tmp350 << tmp349, const348 V_MOV_B32 vDst(VGPR312) src0(LITERAL_CONST) const: 0x3b03126f V_MUL_F32 vDst(VGPR309) src0(VGPR312) src1(VGPR306) // VOP2 V_MUL_F32 vDst(VGPR310) src0(VGPR312) src1(VGPR307) // VOP2 V_MUL_F32 vDst(VGPR311) src0(VGPR312) src1(VGPR308) // VOP2 # 351: OpLoad: FloatVector3: tmp351 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR139) const: 0x0 V_MOVRELS_B32 vDst(VGPR313) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR314) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR315) src0(VGPR2) # 352: OpFAdd: FloatVector3: tmp352 << tmp351, tmp350 V_ADD_F32 vDst(VGPR316) src0(VGPR313) src1(VGPR309) // VOP2 V_ADD_F32 vDst(VGPR317) src0(VGPR314) src1(VGPR310) // VOP2 V_ADD_F32 vDst(VGPR318) src0(VGPR315) src1(VGPR311) // VOP2 # OpStore: : tmp352 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR139) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR316) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR317) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR318) # OpStore: : const174 >> t V_MOV_B32 vDst(VGPR319) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR300) src0(VGPR319) # OpStore: : const308 >> d V_MOV_B32 vDst(VGPR320) src0(LITERAL_CONST) const: 0x41a00000 V_MOV_B32 vDst(VGPR301) src0(VGPR320) # OpStore: : const250 >> i V_MOV_B32 vDst(VGPR302) src0(0) # OpBranch: to lb356 S_BRANCH ??? lb356 # lb356 Label: lb356 # OpLoopMerge: (merge: lb358, continue: lb359) # CF Block: Merge: lb358, Continue: lb359 S_MOV_B64 sDst(SGPR144) src0(EXEC) S_MOV_B64 sDst(SGPR146) src0(EXEC) S_MOV_B64 sDst(SGPR148) src0(EXEC) Label: lb356Loop # OpBranch: to lb360 S_BRANCH ??? lb360 # lb360 Label: lb360 # 361: OpLoad: Int: tmp361 << i Decorators: RelaxedPrecision # 363: OpSLessThan: Bool: tmp363 << tmp361, const362 V_MOV_B32 vDst(VGPR321) src0(50_INT) V_CMP_LT_I32 dst(SGPR150) src0(VGPR302) src1(VGPR321) // VOP3a # OpBranchConditional: if(tmp363) then branch to lb357, else branch to lb358 # CF Block: Cond Branch: true: lb357, false: lb358 S_AND_B64 sDst(EXEC) src0(SGPR150) src1(EXEC) S_CBRANCH_EXECZ ??? lb358 S_BRANCH ??? lb357 # lb357 Label: lb357 # 364: OpLoad: FloatVector3: tmp364 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR139) const: 0x0 V_MOVRELS_B32 vDst(VGPR322) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR323) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR324) src0(VGPR2) # 365: OpLoad: Float: tmp365 << t # 366: OpLoad: FloatVector3: tmp366 << ld S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR141) const: 0x0 V_MOVRELS_B32 vDst(VGPR325) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR326) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR327) src0(VGPR2) # 367: OpVectorTimesScalar: FloatVector3: tmp367 << tmp366, tmp365 V_MUL_F32 vDst(VGPR328) src0(VGPR300) src1(VGPR325) // VOP2 V_MUL_F32 vDst(VGPR329) src0(VGPR300) src1(VGPR326) // VOP2 V_MUL_F32 vDst(VGPR330) src0(VGPR300) src1(VGPR327) // VOP2 # 368: OpFAdd: FloatVector3: tmp368 << tmp364, tmp367 V_ADD_F32 vDst(VGPR331) src0(VGPR322) src1(VGPR328) // VOP2 V_ADD_F32 vDst(VGPR332) src0(VGPR323) src1(VGPR329) // VOP2 V_ADD_F32 vDst(VGPR333) src0(VGPR324) src1(VGPR330) // VOP2 # OpStore: : tmp368 >> param369 V_MOV_B32 vDst(VGPR303) src0(VGPR331) V_MOV_B32 vDst(VGPR304) src0(VGPR332) V_MOV_B32 vDst(VGPR305) src0(VGPR333) # 370: OpFunctionCall: Float: DE(vf3;(param369) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x12f # VGPR[303:305] S_MOV_B64 sDst(SGPR152) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x14e # VGPR334 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR152) # .lbl12 # OpStore: : DE(vf3; >> d V_MOV_B32 vDst(VGPR301) src0(VGPR334) # 371: OpLoad: Float: tmp371 << t # 372: OpFAdd: Float: tmp372 << tmp371, DE(vf3; V_ADD_F32 vDst(VGPR335) src0(VGPR300) src1(VGPR334) // VOP2 # OpStore: : tmp372 >> t V_MOV_B32 vDst(VGPR300) src0(VGPR335) # 373: OpLoad: Float: tmp373 << d # 374: OpFOrdLessThan: Bool: tmp374 << tmp373, const329 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x3a83126f V_CMP_LT_F32 dst(SGPR154) src0(VGPR301) src1(VGPR336) // VOP3a # 375: OpLoad: Float: tmp375 << t # 376: OpFOrdGreaterThan: Bool: tmp376 << tmp375, const267 V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x40400000 V_CMP_GT_F32 dst(SGPR156) src0(VGPR300) src1(VGPR337) // VOP3a # 377: OpLogicalOr: Bool: tmp377 << tmp374, tmp376 S_OR_B64 sDst(SGPR158) src0(SGPR154) src1(SGPR156) # OpSelectionMerge: (merge: lb379) # CF Block: Merge: lb379 S_MOV_B64 sDst(SGPR160) src0(EXEC) # OpBranchConditional: if(tmp377) then branch to lb378, else branch to lb379 # CF Block: Cond Branch: true: lb378, false: lb379 S_AND_B64 sDst(EXEC) src0(SGPR158) src1(EXEC) S_CBRANCH_EXECZ ??? lb379 S_BRANCH ??? lb378 # lb378 Label: lb378 # OpBranch: to lb358 S_BRANCH ??? lb358 # lb379 Label: lb379 # OpBranch: to lb359 S_BRANCH ??? lb359 # lb359 Label: lb359 # 381: OpLoad: Int: tmp381 << i Decorators: RelaxedPrecision # 382: OpIAdd: Int: tmp382 << tmp381, const271 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR338) src0(1_INT) V_ADD_I32 vDst(VGPR339) src0(VGPR302) src1(VGPR338) // VOP2 # OpStore: : tmp382 >> i V_MOV_B32 vDst(VGPR302) src0(VGPR339) # OpBranch: to lb356 S_BRANCH ??? lb356 # lb358 Label: lb358 # 383: OpLoad: Float: tmp383 << t # 384: OpFOrdLessThanEqual: Bool: tmp384 << tmp383, const267 V_MOV_B32 vDst(VGPR340) src0(LITERAL_CONST) const: 0x40400000 V_CMP_LE_F32 dst(SGPR162) src0(VGPR300) src1(VGPR340) // VOP3a # 386: OpSelect: Float: tmp386 << tmp384, const385, const88 # CF Block: Merge: .lbl14 S_MOV_B64 sDst(SGPR164) src0(EXEC) # CF Block: Cond Branch: true: .lbl15, false: .lbl13 S_AND_B64 sDst(EXEC) src0(SGPR162) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl13 S_BRANCH ??? .lbl15 Label: .lbl15 V_MOV_B32 vDst(VGPR342) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR341) src0(VGPR342) S_BRANCH ??? .lbl14 Label: .lbl13 V_MOV_B32 vDst(VGPR341) src0(1_0_F) S_BRANCH ??? .lbl14 Label: .lbl14 # OpReturnValue: : << tmp386 S_MOV_B32 sDst(M0) src0(SGPR138) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR341) S_SETPC_B64 sDst(SGPR136) src0(SGPR136) # FloatVector3 getNorm(vf3;(FloatVector3* p) Function: FloatVector3 getNorm(vf3;() S_MOV_B64 sDst(SGPR170) src0(EXEC) # lb59 Label: lb59 # 391: OpLoad: FloatVector3: tmp391 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR361) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR362) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR363) src0(VGPR2) # 393: OpVectorShuffle: FloatVector3: tmp393 << const390, const390, 0, 1, 1 V_MOV_B32 vDst(VGPR364) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR365) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR366) src0(VGPR364) V_MOV_B32 vDst(VGPR367) src0(VGPR365) V_MOV_B32 vDst(VGPR368) src0(VGPR365) # 394: OpFAdd: FloatVector3: tmp394 << tmp391, tmp393 V_ADD_F32 vDst(VGPR369) src0(VGPR361) src1(VGPR366) // VOP2 V_ADD_F32 vDst(VGPR370) src0(VGPR362) src1(VGPR367) // VOP2 V_ADD_F32 vDst(VGPR371) src0(VGPR363) src1(VGPR368) // VOP2 # OpStore: : tmp394 >> param395 V_MOV_B32 vDst(VGPR343) src0(VGPR369) V_MOV_B32 vDst(VGPR344) src0(VGPR370) V_MOV_B32 vDst(VGPR345) src0(VGPR371) # 396: OpFunctionCall: Float: DE(vf3;(param395) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x157 # VGPR[343:345] S_MOV_B64 sDst(SGPR172) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x174 # VGPR372 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR172) # .lbl16 # 397: OpLoad: FloatVector3: tmp397 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR373) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR374) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR375) src0(VGPR2) # 399: OpVectorShuffle: FloatVector3: tmp399 << const390, const390, 0, 1, 1 V_MOV_B32 vDst(VGPR376) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR377) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR378) src0(VGPR376) V_MOV_B32 vDst(VGPR379) src0(VGPR377) V_MOV_B32 vDst(VGPR380) src0(VGPR377) # 400: OpFSub: FloatVector3: tmp400 << tmp397, tmp399 V_SUB_F32 vDst(VGPR381) src0(VGPR373) src1(VGPR378) // VOP2 V_SUB_F32 vDst(VGPR382) src0(VGPR374) src1(VGPR379) // VOP2 V_SUB_F32 vDst(VGPR383) src0(VGPR375) src1(VGPR380) // VOP2 # OpStore: : tmp400 >> param401 V_MOV_B32 vDst(VGPR346) src0(VGPR381) V_MOV_B32 vDst(VGPR347) src0(VGPR382) V_MOV_B32 vDst(VGPR348) src0(VGPR383) # 402: OpFunctionCall: Float: DE(vf3;(param401) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x15a # VGPR[346:348] S_MOV_B64 sDst(SGPR174) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x180 # VGPR384 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR174) # .lbl17 # 403: OpFSub: Float: tmp403 << DE(vf3;, DE(vf3; V_SUB_F32 vDst(VGPR385) src0(VGPR372) src1(VGPR384) // VOP2 # 404: OpLoad: FloatVector3: tmp404 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR386) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR387) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR388) src0(VGPR2) # 406: OpVectorShuffle: FloatVector3: tmp406 << const390, const390, 1, 0, 1 V_MOV_B32 vDst(VGPR389) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR390) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR391) src0(VGPR390) V_MOV_B32 vDst(VGPR392) src0(VGPR389) V_MOV_B32 vDst(VGPR393) src0(VGPR390) # 407: OpFAdd: FloatVector3: tmp407 << tmp404, tmp406 V_ADD_F32 vDst(VGPR394) src0(VGPR386) src1(VGPR391) // VOP2 V_ADD_F32 vDst(VGPR395) src0(VGPR387) src1(VGPR392) // VOP2 V_ADD_F32 vDst(VGPR396) src0(VGPR388) src1(VGPR393) // VOP2 # OpStore: : tmp407 >> param408 V_MOV_B32 vDst(VGPR349) src0(VGPR394) V_MOV_B32 vDst(VGPR350) src0(VGPR395) V_MOV_B32 vDst(VGPR351) src0(VGPR396) # 409: OpFunctionCall: Float: DE(vf3;(param408) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x15d # VGPR[349:351] S_MOV_B64 sDst(SGPR176) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x18d # VGPR397 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR176) # .lbl18 # 410: OpLoad: FloatVector3: tmp410 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR398) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR399) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR400) src0(VGPR2) # 412: OpVectorShuffle: FloatVector3: tmp412 << const390, const390, 1, 0, 1 V_MOV_B32 vDst(VGPR401) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR402) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR403) src0(VGPR402) V_MOV_B32 vDst(VGPR404) src0(VGPR401) V_MOV_B32 vDst(VGPR405) src0(VGPR402) # 413: OpFSub: FloatVector3: tmp413 << tmp410, tmp412 V_SUB_F32 vDst(VGPR406) src0(VGPR398) src1(VGPR403) // VOP2 V_SUB_F32 vDst(VGPR407) src0(VGPR399) src1(VGPR404) // VOP2 V_SUB_F32 vDst(VGPR408) src0(VGPR400) src1(VGPR405) // VOP2 # OpStore: : tmp413 >> param414 V_MOV_B32 vDst(VGPR352) src0(VGPR406) V_MOV_B32 vDst(VGPR353) src0(VGPR407) V_MOV_B32 vDst(VGPR354) src0(VGPR408) # 415: OpFunctionCall: Float: DE(vf3;(param414) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x160 # VGPR[352:354] S_MOV_B64 sDst(SGPR178) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x199 # VGPR409 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR178) # .lbl19 # 416: OpFSub: Float: tmp416 << DE(vf3;, DE(vf3; V_SUB_F32 vDst(VGPR410) src0(VGPR397) src1(VGPR409) // VOP2 # 417: OpLoad: FloatVector3: tmp417 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR411) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR412) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR413) src0(VGPR2) # 419: OpVectorShuffle: FloatVector3: tmp419 << const390, const390, 1, 1, 0 V_MOV_B32 vDst(VGPR414) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR415) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR416) src0(VGPR415) V_MOV_B32 vDst(VGPR417) src0(VGPR415) V_MOV_B32 vDst(VGPR418) src0(VGPR414) # 420: OpFAdd: FloatVector3: tmp420 << tmp417, tmp419 V_ADD_F32 vDst(VGPR419) src0(VGPR411) src1(VGPR416) // VOP2 V_ADD_F32 vDst(VGPR420) src0(VGPR412) src1(VGPR417) // VOP2 V_ADD_F32 vDst(VGPR421) src0(VGPR413) src1(VGPR418) // VOP2 # OpStore: : tmp420 >> param421 V_MOV_B32 vDst(VGPR355) src0(VGPR419) V_MOV_B32 vDst(VGPR356) src0(VGPR420) V_MOV_B32 vDst(VGPR357) src0(VGPR421) # 422: OpFunctionCall: Float: DE(vf3;(param421) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x163 # VGPR[355:357] S_MOV_B64 sDst(SGPR180) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x1a6 # VGPR422 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR180) # .lbl20 # 423: OpLoad: FloatVector3: tmp423 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR423) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR424) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR425) src0(VGPR2) # 425: OpVectorShuffle: FloatVector3: tmp425 << const390, const390, 1, 1, 0 V_MOV_B32 vDst(VGPR426) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR427) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR428) src0(VGPR427) V_MOV_B32 vDst(VGPR429) src0(VGPR427) V_MOV_B32 vDst(VGPR430) src0(VGPR426) # 426: OpFSub: FloatVector3: tmp426 << tmp423, tmp425 V_SUB_F32 vDst(VGPR431) src0(VGPR423) src1(VGPR428) // VOP2 V_SUB_F32 vDst(VGPR432) src0(VGPR424) src1(VGPR429) // VOP2 V_SUB_F32 vDst(VGPR433) src0(VGPR425) src1(VGPR430) // VOP2 # OpStore: : tmp426 >> param427 V_MOV_B32 vDst(VGPR358) src0(VGPR431) V_MOV_B32 vDst(VGPR359) src0(VGPR432) V_MOV_B32 vDst(VGPR360) src0(VGPR433) # 428: OpFunctionCall: Float: DE(vf3;(param427) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x166 # VGPR[358:360] S_MOV_B64 sDst(SGPR182) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x1b2 # VGPR434 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR182) # .lbl21 # 429: OpFSub: Float: tmp429 << DE(vf3;, DE(vf3; V_SUB_F32 vDst(VGPR435) src0(VGPR422) src1(VGPR434) // VOP2 # 430: OpCompositeConstruct: FloatVector3: tmp430 << tmp403, tmp416, tmp429 V_MOV_B32 vDst(VGPR436) src0(VGPR385) V_MOV_B32 vDst(VGPR437) src0(VGPR410) V_MOV_B32 vDst(VGPR438) src0(VGPR435) # 431: OpExtInst(Normalize): FloatVector3: tmp431 << tmp430 V_MUL_F32 vDst(VGPR439) src0(VGPR436) src1(VGPR436) // VOP2 V_MAC_F32 vDst(VGPR439) src0(VGPR437) src1(VGPR437) // VOP2 V_MAC_F32 vDst(VGPR439) src0(VGPR438) src1(VGPR438) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR439) src0(VGPR439) V_MUL_F32 vDst(VGPR440) src0(VGPR436) src1(VGPR439) // VOP2 V_MUL_F32 vDst(VGPR441) src0(VGPR437) src1(VGPR439) // VOP2 V_MUL_F32 vDst(VGPR442) src0(VGPR438) src1(VGPR439) // VOP2 # OpReturnValue: : << tmp431 S_MOV_B32 sDst(M0) src0(SGPR168) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR440) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR441) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR442) S_SETPC_B64 sDst(SGPR166) src0(SGPR166) # FloatVector3 light(vf3;vf3;(FloatVector3* p, FloatVector3* n) Function: FloatVector3 light(vf3;vf3;(, FloatVector3 getNorm(vf3;.n) S_MOV_B64 sDst(SGPR190) src0(EXEC) # lb64 Label: lb64 # OpStore: : const436 >> col V_MOV_B32 vDst(VGPR457) src0(LITERAL_CONST) const: 0x3c23d70a V_MOV_B32 vDst(VGPR458) src0(LITERAL_CONST) const: 0x3c23d70a V_MOV_B32 vDst(VGPR459) src0(LITERAL_CONST) const: 0x3c23d70a V_MOV_B32 vDst(VGPR443) src0(VGPR457) V_MOV_B32 vDst(VGPR444) src0(VGPR458) V_MOV_B32 vDst(VGPR445) src0(VGPR459) # OpStore: : const250 >> i V_MOV_B32 vDst(VGPR446) src0(0) # OpBranch: to lb438 S_BRANCH ??? lb438 # lb438 Label: lb438 # OpLoopMerge: (merge: lb440, continue: lb441) # CF Block: Merge: lb440, Continue: lb441 S_MOV_B64 sDst(SGPR192) src0(EXEC) S_MOV_B64 sDst(SGPR194) src0(EXEC) S_MOV_B64 sDst(SGPR196) src0(EXEC) Label: lb438Loop # OpBranch: to lb442 S_BRANCH ??? lb442 # lb442 Label: lb442 # 443: OpLoad: Int: tmp443 << i Decorators: RelaxedPrecision # 445: OpSLessThan: Bool: tmp445 << tmp443, const444 V_MOV_B32 vDst(VGPR460) src0(2_INT) V_CMP_LT_I32 dst(SGPR198) src0(VGPR446) src1(VGPR460) // VOP3a # OpBranchConditional: if(tmp445) then branch to lb439, else branch to lb440 # CF Block: Cond Branch: true: lb439, false: lb440 S_AND_B64 sDst(EXEC) src0(SGPR198) src1(EXEC) S_CBRANCH_EXECZ ??? lb440 S_BRANCH ??? lb439 # lb439 Label: lb439 # 447: OpLoad: Int: tmp447 << i Decorators: RelaxedPrecision # 448: OpIEqual: Bool: tmp448 << tmp447, const250 V_MOV_B32 vDst(VGPR461) src0(0) V_CMP_EQ_I32 dst(SGPR200) src0(VGPR446) src1(VGPR461) // VOP3a # 449: OpLoad: FloatVector3: tmp449 << lDir0 # 450: OpLoad: FloatVector3: tmp450 << lDir1 # 452: OpCompositeConstruct: BoolVector3: tmp452 << tmp448, tmp448, tmp448 S_MOV_B64 sDst(SGPR202) src0(SGPR200) S_MOV_B64 sDst(SGPR204) src0(SGPR200) S_MOV_B64 sDst(SGPR206) src0(SGPR200) # 453: OpSelect: FloatVector3: tmp453 << tmp452, tmp449, tmp450 S_OR_B64 sDst(SGPR208) src0(SGPR202) src1(SGPR204) S_OR_B64 sDst(SGPR208) src0(SGPR206) src1(SGPR208) # CF Block: Merge: .lbl23 S_MOV_B64 sDst(SGPR210) src0(EXEC) # CF Block: Cond Branch: true: .lbl24, false: .lbl22 S_AND_B64 sDst(EXEC) src0(SGPR208) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl22 S_BRANCH ??? .lbl24 Label: .lbl24 V_MOV_B32 vDst(VGPR462) src0(VGPR24) V_MOV_B32 vDst(VGPR463) src0(VGPR25) V_MOV_B32 vDst(VGPR464) src0(VGPR26) S_BRANCH ??? .lbl23 Label: .lbl22 V_MOV_B32 vDst(VGPR462) src0(VGPR30) V_MOV_B32 vDst(VGPR463) src0(VGPR31) V_MOV_B32 vDst(VGPR464) src0(VGPR32) S_BRANCH ??? .lbl23 Label: .lbl23 # 455: OpLoad: FloatVector3: tmp455 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR188) const: 0x0 V_MOVRELS_B32 vDst(VGPR465) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR466) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR467) src0(VGPR2) # 457: OpDot: Float: tmp457 << tmp455, tmp453 V_MUL_F32 vDst(VGPR468) src0(VGPR465) src1(VGPR462) // VOP2 V_MAC_F32 vDst(VGPR468) src0(VGPR466) src1(VGPR463) // VOP2 V_MAC_F32 vDst(VGPR468) src0(VGPR467) src1(VGPR464) // VOP2 # 458: OpExtInst(FMax): Float: tmp458 << tmp457, const174 V_MOV_B32 vDst(VGPR469) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR470) src0(VGPR468) src1(VGPR469) // VOP2 # OpStore: : tmp458 >> diff V_MOV_B32 vDst(VGPR447) src0(VGPR470) # 460: OpLoad: FloatVector3: tmp460 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR187) const: 0x0 V_MOVRELS_B32 vDst(VGPR471) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR472) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR473) src0(VGPR2) # OpStore: : tmp460 >> param459 V_MOV_B32 vDst(VGPR448) src0(VGPR471) V_MOV_B32 vDst(VGPR449) src0(VGPR472) V_MOV_B32 vDst(VGPR450) src0(VGPR473) # 462: OpLoad: FloatVector3: tmp462 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR188) const: 0x0 V_MOVRELS_B32 vDst(VGPR474) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR475) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR476) src0(VGPR2) # OpStore: : tmp462 >> param461 V_MOV_B32 vDst(VGPR451) src0(VGPR474) V_MOV_B32 vDst(VGPR452) src0(VGPR475) V_MOV_B32 vDst(VGPR453) src0(VGPR476) # OpStore: : tmp453 >> param463 V_MOV_B32 vDst(VGPR454) src0(VGPR462) V_MOV_B32 vDst(VGPR455) src0(VGPR463) V_MOV_B32 vDst(VGPR456) src0(VGPR464) # 465: OpFunctionCall: Float: getShadow(vf3;vf3;vf3;(param459, param461, param463) S_ADD_U32 sDst(SGPR139) src0(LITERAL_CONST) src1(0) const: 0x1c0 # VGPR[448:450] S_ADD_U32 sDst(SGPR140) src0(LITERAL_CONST) src1(0) const: 0x1c3 # VGPR[451:453] S_ADD_U32 sDst(SGPR141) src0(LITERAL_CONST) src1(0) const: 0x1c6 # VGPR[454:456] S_MOV_B64 sDst(SGPR212) src0(EXEC) S_MOV_B32 sDst(SGPR138) src0(LITERAL_CONST) const: 0x1dd # VGPR477 # Indirect branch to getShadow(vf3;vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR136) src0(SGPR136) S_ADD_U32 sDst(SGPR136) src0(SGPR136) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR137) src0(SGPR137) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR136) src0(SGPR136) S_MOV_B64 sDst(EXEC) src0(SGPR212) # .lbl25 # 466: OpLoad: Float: tmp466 << diff # 467: OpFMul: Float: tmp467 << tmp466, getShadow(vf3;vf3;vf3; V_MUL_F32 vDst(VGPR478) src0(VGPR447) src1(VGPR477) // VOP2 # OpStore: : tmp467 >> diff V_MOV_B32 vDst(VGPR447) src0(VGPR478) # 468: OpLoad: Float: tmp468 << diff # 469: OpLoad: Int: tmp469 << i Decorators: RelaxedPrecision # 470: OpIEqual: Bool: tmp470 << tmp469, const250 V_MOV_B32 vDst(VGPR479) src0(0) V_CMP_EQ_I32 dst(SGPR214) src0(VGPR446) src1(VGPR479) // VOP3a # 471: OpLoad: FloatVector3: tmp471 << lCol0 # 472: OpLoad: FloatVector3: tmp472 << lCol1 # 473: OpCompositeConstruct: BoolVector3: tmp473 << tmp470, tmp470, tmp470 S_MOV_B64 sDst(SGPR216) src0(SGPR214) S_MOV_B64 sDst(SGPR218) src0(SGPR214) S_MOV_B64 sDst(SGPR220) src0(SGPR214) # 474: OpSelect: FloatVector3: tmp474 << tmp473, tmp471, tmp472 S_OR_B64 sDst(SGPR222) src0(SGPR216) src1(SGPR218) S_OR_B64 sDst(SGPR222) src0(SGPR220) src1(SGPR222) # CF Block: Merge: .lbl27 S_MOV_B64 sDst(SGPR224) src0(EXEC) # CF Block: Cond Branch: true: .lbl28, false: .lbl26 S_AND_B64 sDst(EXEC) src0(SGPR222) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl26 S_BRANCH ??? .lbl28 Label: .lbl28 V_MOV_B32 vDst(VGPR480) src0(VGPR36) V_MOV_B32 vDst(VGPR481) src0(VGPR37) V_MOV_B32 vDst(VGPR482) src0(VGPR38) S_BRANCH ??? .lbl27 Label: .lbl26 V_MOV_B32 vDst(VGPR480) src0(VGPR42) V_MOV_B32 vDst(VGPR481) src0(VGPR43) V_MOV_B32 vDst(VGPR482) src0(VGPR44) S_BRANCH ??? .lbl27 Label: .lbl27 # 475: OpVectorTimesScalar: FloatVector3: tmp475 << tmp474, tmp468 V_MUL_F32 vDst(VGPR483) src0(VGPR447) src1(VGPR480) // VOP2 V_MUL_F32 vDst(VGPR484) src0(VGPR447) src1(VGPR481) // VOP2 V_MUL_F32 vDst(VGPR485) src0(VGPR447) src1(VGPR482) // VOP2 # 476: OpLoad: FloatVector3: tmp476 << col # 477: OpFAdd: FloatVector3: tmp477 << tmp476, tmp475 V_ADD_F32 vDst(VGPR486) src0(VGPR443) src1(VGPR483) // VOP2 V_ADD_F32 vDst(VGPR487) src0(VGPR444) src1(VGPR484) // VOP2 V_ADD_F32 vDst(VGPR488) src0(VGPR445) src1(VGPR485) // VOP2 # OpStore: : tmp477 >> col V_MOV_B32 vDst(VGPR443) src0(VGPR486) V_MOV_B32 vDst(VGPR444) src0(VGPR487) V_MOV_B32 vDst(VGPR445) src0(VGPR488) # OpBranch: to lb441 S_BRANCH ??? lb441 # lb441 Label: lb441 # 478: OpLoad: Int: tmp478 << i Decorators: RelaxedPrecision # 479: OpIAdd: Int: tmp479 << tmp478, const271 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR489) src0(1_INT) V_ADD_I32 vDst(VGPR490) src0(VGPR446) src1(VGPR489) // VOP2 # OpStore: : tmp479 >> i V_MOV_B32 vDst(VGPR446) src0(VGPR490) # OpBranch: to lb438 S_BRANCH ??? lb438 # lb440 Label: lb440 # 480: OpLoad: FloatVector3: tmp480 << col # 482: OpVectorTimesScalar: FloatVector3: tmp482 << tmp480, const481 V_MOV_B32 vDst(VGPR494) src0(LITERAL_CONST) const: 0x3f333333 V_MUL_F32 vDst(VGPR491) src0(VGPR494) src1(VGPR443) // VOP2 V_MUL_F32 vDst(VGPR492) src0(VGPR494) src1(VGPR444) // VOP2 V_MUL_F32 vDst(VGPR493) src0(VGPR494) src1(VGPR445) // VOP2 # OpReturnValue: : << tmp482 S_MOV_B32 sDst(M0) src0(SGPR186) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR491) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR492) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR493) S_SETPC_B64 sDst(SGPR184) src0(SGPR184) # FloatVector3 getSphereColor(i1;(Int* i) Function: FloatVector3 getSphereColor(i1;() S_MOV_B64 sDst(SGPR230) src0(EXEC) # lb70 Label: lb70 # 485: OpLoad: Int: tmp485 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR495) src0(VGPR0) # 486: OpIEqual: Bool: tmp486 << tmp485, const250 V_MOV_B32 vDst(VGPR496) src0(0) V_CMP_EQ_I32 dst(SGPR232) src0(VGPR495) src1(VGPR496) // VOP3a # OpSelectionMerge: (merge: lb488) # CF Block: Merge: lb488 S_MOV_B64 sDst(SGPR234) src0(EXEC) # OpBranchConditional: if(tmp486) then branch to lb487, else branch to lb488 # CF Block: Cond Branch: true: lb487, false: lb488 S_AND_B64 sDst(EXEC) src0(SGPR232) src1(EXEC) S_CBRANCH_EXECZ ??? lb488 S_BRANCH ??? lb487 # lb487 Label: lb487 # OpReturnValue: : << const489 V_MOV_B32 vDst(VGPR497) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR498) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR499) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR497) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR498) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR499) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb488 Label: lb488 # 491: OpLoad: Int: tmp491 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR500) src0(VGPR0) # 492: OpIEqual: Bool: tmp492 << tmp491, const271 V_MOV_B32 vDst(VGPR501) src0(1_INT) V_CMP_EQ_I32 dst(SGPR236) src0(VGPR500) src1(VGPR501) // VOP3a # OpSelectionMerge: (merge: lb494) # CF Block: Merge: lb494 S_MOV_B64 sDst(SGPR238) src0(EXEC) # OpBranchConditional: if(tmp492) then branch to lb493, else branch to lb494 # CF Block: Cond Branch: true: lb493, false: lb494 S_AND_B64 sDst(EXEC) src0(SGPR236) src1(EXEC) S_CBRANCH_EXECZ ??? lb494 S_BRANCH ??? lb493 # lb493 Label: lb493 # OpReturnValue: : << const495 V_MOV_B32 vDst(VGPR502) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR503) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR504) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR502) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR503) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR504) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb494 Label: lb494 # 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR505) src0(VGPR0) # 498: OpIEqual: Bool: tmp498 << tmp497, const444 V_MOV_B32 vDst(VGPR506) src0(2_INT) V_CMP_EQ_I32 dst(SGPR240) src0(VGPR505) src1(VGPR506) // VOP3a # OpSelectionMerge: (merge: lb500) # CF Block: Merge: lb500 S_MOV_B64 sDst(SGPR242) src0(EXEC) # OpBranchConditional: if(tmp498) then branch to lb499, else branch to lb500 # CF Block: Cond Branch: true: lb499, false: lb500 S_AND_B64 sDst(EXEC) src0(SGPR240) src1(EXEC) S_CBRANCH_EXECZ ??? lb500 S_BRANCH ??? lb499 # lb499 Label: lb499 # OpReturnValue: : << const501 V_MOV_B32 vDst(VGPR507) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR508) src0(1_0_F) V_MOV_B32 vDst(VGPR509) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR507) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR508) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR509) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb500 Label: lb500 # 503: OpLoad: Int: tmp503 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR510) src0(VGPR0) # 505: OpIEqual: Bool: tmp505 << tmp503, const504 V_MOV_B32 vDst(VGPR511) src0(3_INT) V_CMP_EQ_I32 dst(SGPR244) src0(VGPR510) src1(VGPR511) // VOP3a # OpSelectionMerge: (merge: lb507) # CF Block: Merge: lb507 S_MOV_B64 sDst(SGPR246) src0(EXEC) # OpBranchConditional: if(tmp505) then branch to lb506, else branch to lb507 # CF Block: Cond Branch: true: lb506, false: lb507 S_AND_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_CBRANCH_EXECZ ??? lb507 S_BRANCH ??? lb506 # lb506 Label: lb506 # OpReturnValue: : << const508 V_MOV_B32 vDst(VGPR512) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR513) src0(1_0_F) V_MOV_B32 vDst(VGPR514) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR512) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR513) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR514) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb507 Label: lb507 # 510: OpLoad: Int: tmp510 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR515) src0(VGPR0) # 512: OpIEqual: Bool: tmp512 << tmp510, const511 V_MOV_B32 vDst(VGPR516) src0(4_INT) V_CMP_EQ_I32 dst(SGPR248) src0(VGPR515) src1(VGPR516) // VOP3a # OpSelectionMerge: (merge: lb514) # CF Block: Merge: lb514 S_MOV_B64 sDst(SGPR250) src0(EXEC) # OpBranchConditional: if(tmp512) then branch to lb513, else branch to lb514 # CF Block: Cond Branch: true: lb513, false: lb514 S_AND_B64 sDst(EXEC) src0(SGPR248) src1(EXEC) S_CBRANCH_EXECZ ??? lb514 S_BRANCH ??? lb513 # lb513 Label: lb513 # OpReturnValue: : << const515 V_MOV_B32 vDst(VGPR517) src0(1_0_F) V_MOV_B32 vDst(VGPR518) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR519) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR517) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR518) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR519) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb514 Label: lb514 # 517: OpLoad: Int: tmp517 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR520) src0(VGPR0) # 518: OpIEqual: Bool: tmp518 << tmp517, const257 V_MOV_B32 vDst(VGPR521) src0(5_INT) V_CMP_EQ_I32 dst(SGPR252) src0(VGPR520) src1(VGPR521) // VOP3a # OpSelectionMerge: (merge: lb520) # CF Block: Merge: lb520 S_MOV_B64 sDst(SGPR254) src0(EXEC) # OpBranchConditional: if(tmp518) then branch to lb519, else branch to lb520 # CF Block: Cond Branch: true: lb519, false: lb520 S_AND_B64 sDst(EXEC) src0(SGPR252) src1(EXEC) S_CBRANCH_EXECZ ??? lb520 S_BRANCH ??? lb519 # lb519 Label: lb519 # OpReturnValue: : << const521 V_MOV_B32 vDst(VGPR522) src0(1_0_F) V_MOV_B32 vDst(VGPR523) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR524) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR522) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR523) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR524) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb520 Label: lb520 # 523: OpLoad: Int: tmp523 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR525) src0(VGPR0) # 525: OpIEqual: Bool: tmp525 << tmp523, const524 V_MOV_B32 vDst(VGPR526) src0(6_INT) V_CMP_EQ_I32 dst(SGPR256) src0(VGPR525) src1(VGPR526) // VOP3a # OpSelectionMerge: (merge: lb527) # CF Block: Merge: lb527 S_MOV_B64 sDst(SGPR258) src0(EXEC) # OpBranchConditional: if(tmp525) then branch to lb526, else branch to lb527 # CF Block: Cond Branch: true: lb526, false: lb527 S_AND_B64 sDst(EXEC) src0(SGPR256) src1(EXEC) S_CBRANCH_EXECZ ??? lb527 S_BRANCH ??? lb526 # lb526 Label: lb526 # OpBranch: to lb527 S_BRANCH ??? lb527 # lb527 Label: lb527 # 528: OpLoad: Int: tmp528 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR527) src0(VGPR0) # 530: OpIEqual: Bool: tmp530 << tmp528, const529 V_MOV_B32 vDst(VGPR528) src0(7_INT) V_CMP_EQ_I32 dst(SGPR260) src0(VGPR527) src1(VGPR528) // VOP3a # OpSelectionMerge: (merge: lb532) # CF Block: Merge: lb532 S_MOV_B64 sDst(SGPR262) src0(EXEC) # OpBranchConditional: if(tmp530) then branch to lb531, else branch to lb532 # CF Block: Cond Branch: true: lb531, false: lb532 S_AND_B64 sDst(EXEC) src0(SGPR260) src1(EXEC) S_CBRANCH_EXECZ ??? lb532 S_BRANCH ??? lb531 # lb531 Label: lb531 # OpReturnValue: : << const533 V_MOV_B32 vDst(VGPR529) src0(1_0_F) V_MOV_B32 vDst(VGPR530) src0(1_0_F) V_MOV_B32 vDst(VGPR531) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR529) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR530) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR531) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb532 Label: lb532 # 535: OpLoad: Int: tmp535 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR532) src0(VGPR0) # 537: OpIEqual: Bool: tmp537 << tmp535, const536 V_MOV_B32 vDst(VGPR533) src0(8_INT) V_CMP_EQ_I32 dst(SGPR264) src0(VGPR532) src1(VGPR533) // VOP3a # OpSelectionMerge: (merge: lb539) # CF Block: Merge: lb539 S_MOV_B64 sDst(SGPR266) src0(EXEC) # OpBranchConditional: if(tmp537) then branch to lb538, else branch to lb539 # CF Block: Cond Branch: true: lb538, false: lb539 S_AND_B64 sDst(EXEC) src0(SGPR264) src1(EXEC) S_CBRANCH_EXECZ ??? lb539 S_BRANCH ??? lb538 # lb538 Label: lb538 # OpReturnValue: : << const543 V_MOV_B32 vDst(VGPR534) src0(LITERAL_CONST) const: 0x3ed9999a V_MOV_B32 vDst(VGPR535) src0(LITERAL_CONST) const: 0x3f0f5c29 V_MOV_B32 vDst(VGPR536) src0(LITERAL_CONST) const: 0x3f666666 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR534) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR535) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR536) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb539 Label: lb539 # 545: OpLoad: Int: tmp545 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR537) src0(VGPR0) # 547: OpIEqual: Bool: tmp547 << tmp545, const546 V_MOV_B32 vDst(VGPR538) src0(9_INT) V_CMP_EQ_I32 dst(SGPR268) src0(VGPR537) src1(VGPR538) // VOP3a # OpSelectionMerge: (merge: lb549) # CF Block: Merge: lb549 S_MOV_B64 sDst(SGPR270) src0(EXEC) # OpBranchConditional: if(tmp547) then branch to lb548, else branch to lb549 # CF Block: Cond Branch: true: lb548, false: lb549 S_AND_B64 sDst(EXEC) src0(SGPR268) src1(EXEC) S_CBRANCH_EXECZ ??? lb549 S_BRANCH ??? lb548 # lb548 Label: lb548 # OpReturnValue: : << const550 V_MOV_B32 vDst(VGPR539) src0(0_5_F) V_MOV_B32 vDst(VGPR540) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR541) src0(LITERAL_CONST) const: 0x3f19999a S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR539) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR540) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR541) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb549 Label: lb549 # 552: OpLoad: Int: tmp552 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR542) src0(VGPR0) # 554: OpIEqual: Bool: tmp554 << tmp552, const553 V_MOV_B32 vDst(VGPR543) src0(10_INT) V_CMP_EQ_I32 dst(SGPR272) src0(VGPR542) src1(VGPR543) // VOP3a # OpSelectionMerge: (merge: lb556) # CF Block: Merge: lb556 S_MOV_B64 sDst(SGPR274) src0(EXEC) # OpBranchConditional: if(tmp554) then branch to lb555, else branch to lb556 # CF Block: Cond Branch: true: lb555, false: lb556 S_AND_B64 sDst(EXEC) src0(SGPR272) src1(EXEC) S_CBRANCH_EXECZ ??? lb556 S_BRANCH ??? lb555 # lb555 Label: lb555 # OpReturnValue: : << const501 V_MOV_B32 vDst(VGPR544) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR545) src0(1_0_F) V_MOV_B32 vDst(VGPR546) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR544) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR545) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR546) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb556 Label: lb556 # 558: OpLoad: Int: tmp558 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR547) src0(VGPR0) # 560: OpIEqual: Bool: tmp560 << tmp558, const559 V_MOV_B32 vDst(VGPR548) src0(11_INT) V_CMP_EQ_I32 dst(SGPR276) src0(VGPR547) src1(VGPR548) // VOP3a # OpSelectionMerge: (merge: lb562) # CF Block: Merge: lb562 S_MOV_B64 sDst(SGPR278) src0(EXEC) # OpBranchConditional: if(tmp560) then branch to lb561, else branch to lb562 # CF Block: Cond Branch: true: lb561, false: lb562 S_AND_B64 sDst(EXEC) src0(SGPR276) src1(EXEC) S_CBRANCH_EXECZ ??? lb562 S_BRANCH ??? lb561 # lb561 Label: lb561 # OpReturnValue: : << const563 V_MOV_B32 vDst(VGPR549) src0(0_5_F) V_MOV_B32 vDst(VGPR550) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR551) src0(LITERAL_CONST) const: 0x3f666666 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR549) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR550) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR551) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # lb562 Label: lb562 # 565: OpUndef: FloatVector3: tmp565 << # OpReturnValue: : << tmp565 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR280) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR281) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR282) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) Function: Void mainImage(vf4;vf2;(, FloatVector2 main.fragCoord) S_MOV_B64 sDst(SGPR284) src0(EXEC) # lb77 Label: lb77 # 567: OpLoad: Float: tmp567 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR286) S_WAITCNT 0 # 568: OpFMul: Float: tmp568 << tmp567, const90 V_MOV_B32 vDst(VGPR574) src0(0_5_F) V_MUL_F32 vDst(VGPR575) src0(SGPR286) src1(VGPR574) // VOP2 # 570: OpLoad: FloatVector2: tmp570 << fragCoord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR13) const: 0x0 V_MOVRELS_B32 vDst(VGPR576) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR577) src0(VGPR1) # 573: OpLoad: FloatVector3: tmp573 << iResolution S_LOAD_DWORDX2_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR[288:289]) S_WAITCNT 0 S_LOAD_DWORD_IMM offset(12) sBase(SGPR[0:1]) sDst(SGPR290) S_WAITCNT 0 # 574: OpVectorShuffle: FloatVector2: tmp574 << tmp573, tmp573, 0, 1 V_MOV_B32 vDst(VGPR578) src0(SGPR288) V_MOV_B32 vDst(VGPR579) src0(SGPR289) # 575: OpVectorTimesScalar: FloatVector2: tmp575 << tmp574, const90 V_MOV_B32 vDst(VGPR582) src0(0_5_F) V_MUL_F32 vDst(VGPR580) src0(VGPR582) src1(VGPR578) // VOP2 V_MUL_F32 vDst(VGPR581) src0(VGPR582) src1(VGPR579) // VOP2 # 576: OpFSub: FloatVector2: tmp576 << tmp570, tmp575 V_SUB_F32 vDst(VGPR583) src0(VGPR576) src1(VGPR580) // VOP2 V_SUB_F32 vDst(VGPR584) src0(VGPR577) src1(VGPR581) // VOP2 # 577: OpAccessChain: Float*: iResolution[1] # 578: OpLoad: Float: tmp578 << iResolution[1] S_LOAD_DWORD_IMM offset(8) sBase(SGPR[0:1]) sDst(SGPR291) S_WAITCNT 0 # 579: OpCompositeConstruct: FloatVector2: tmp579 << tmp578, tmp578 V_MOV_B32 vDst(VGPR585) src0(SGPR291) V_MOV_B32 vDst(VGPR586) src0(SGPR291) # 580: OpFDiv: FloatVector2: tmp580 << tmp576, tmp579 V_RCP_F32 vDst(VGPR587) src0(VGPR585) V_RCP_F32 vDst(VGPR588) src0(VGPR586) V_MUL_F32 vDst(VGPR587) src0(VGPR583) src1(VGPR587) // VOP2 V_MUL_F32 vDst(VGPR588) src0(VGPR584) src1(VGPR588) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR587) src0(VGPR587) src1(VGPR585) src2(VGPR583) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR588) src0(VGPR588) src1(VGPR586) src2(VGPR584) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 583: OpLoad: Float: tmp583 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR292) S_WAITCNT 0 # 584: OpExtInst(Sin): Float: tmp584 << tmp583 V_MOV_B32 vDst(VGPR659) src0(LITERAL_CONST) const: 0x3e22f983 V_MUL_F32 vDst(VGPR589) src0(VGPR659) src1(SGPR292) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FRACT_F32 vDst(VGPR589) src0(VGPR589) V_SIN_F32 vDst(VGPR589) src0(VGPR589) # 585: OpFMul: Float: tmp585 << const90, tmp584 V_MUL_F32 vDst(VGPR590) src0(0_5_F) src1(VGPR589) // VOP2 # 586: OpFAdd: Float: tmp586 << const582, tmp585 V_ADD_F32 vDst(VGPR591) src0(M1_0_F) src1(VGPR590) // VOP2 # 588: OpLoad: Float: tmp588 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR293) S_WAITCNT 0 # 589: OpFMul: Float: tmp589 << tmp588, const90 V_MOV_B32 vDst(VGPR592) src0(0_5_F) V_MUL_F32 vDst(VGPR593) src0(SGPR293) src1(VGPR592) // VOP2 # 590: OpFAdd: Float: tmp590 << const587, tmp589 V_MOV_B32 vDst(VGPR594) src0(LITERAL_CONST) const: 0xc0a00000 V_ADD_F32 vDst(VGPR595) src0(VGPR594) src1(VGPR593) // VOP2 # 591: OpCompositeConstruct: FloatVector3: tmp591 << const174, tmp586, tmp590 V_MOV_B32 vDst(VGPR599) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR596) src0(VGPR599) V_MOV_B32 vDst(VGPR597) src0(VGPR591) V_MOV_B32 vDst(VGPR598) src0(VGPR595) # 594: OpCompositeExtract: Float: tmp594 << tmp580, 0 V_MOV_B32 vDst(VGPR600) src0(VGPR587) # 595: OpCompositeExtract: Float: tmp595 << tmp580, 1 V_MOV_B32 vDst(VGPR601) src0(VGPR588) # 596: OpCompositeConstruct: FloatVector3: tmp596 << tmp594, tmp595, const88 V_MOV_B32 vDst(VGPR602) src0(VGPR600) V_MOV_B32 vDst(VGPR603) src0(VGPR601) V_MOV_B32 vDst(VGPR604) src0(1_0_F) # 597: OpExtInst(Normalize): FloatVector3: tmp597 << tmp596 V_MUL_F32 vDst(VGPR605) src0(VGPR602) src1(VGPR602) // VOP2 V_MAC_F32 vDst(VGPR605) src0(VGPR603) src1(VGPR603) // VOP2 V_MAC_F32 vDst(VGPR605) src0(VGPR604) src1(VGPR604) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR605) src0(VGPR605) V_MUL_F32 vDst(VGPR606) src0(VGPR602) src1(VGPR605) // VOP2 V_MUL_F32 vDst(VGPR607) src0(VGPR603) src1(VGPR605) // VOP2 V_MUL_F32 vDst(VGPR608) src0(VGPR604) src1(VGPR605) // VOP2 # OpStore: : tmp591 >> param599 V_MOV_B32 vDst(VGPR552) src0(VGPR596) V_MOV_B32 vDst(VGPR553) src0(VGPR597) V_MOV_B32 vDst(VGPR554) src0(VGPR598) # OpStore: : tmp597 >> param601 V_MOV_B32 vDst(VGPR555) src0(VGPR606) V_MOV_B32 vDst(VGPR556) src0(VGPR607) V_MOV_B32 vDst(VGPR557) src0(VGPR608) # 603: OpFunctionCall: FloatVector2: march(vf3;vf3;(param599, param601) S_ADD_U32 sDst(SGPR113) src0(LITERAL_CONST) src1(0) const: 0x228 # VGPR[552:554] S_ADD_U32 sDst(SGPR114) src0(LITERAL_CONST) src1(0) const: 0x22b # VGPR[555:557] S_MOV_B64 sDst(SGPR294) src0(EXEC) S_MOV_B32 sDst(SGPR112) src0(LITERAL_CONST) const: 0x261 # VGPR[609:610] # Indirect branch to march(vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR110) src0(SGPR110) S_ADD_U32 sDst(SGPR110) src0(SGPR110) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR111) src0(SGPR111) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR110) src0(SGPR110) S_MOV_B64 sDst(EXEC) src0(SGPR294) # .lbl29 # 606: OpAccessChain: Float*: hit[0] # 607: OpCompositeExtract: Float: tmp607 << march(vf3;vf3;, 0 V_MOV_B32 vDst(VGPR611) src0(VGPR609) # 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp597, tmp607 V_MUL_F32 vDst(VGPR612) src0(VGPR611) src1(VGPR606) // VOP2 V_MUL_F32 vDst(VGPR613) src0(VGPR611) src1(VGPR607) // VOP2 V_MUL_F32 vDst(VGPR614) src0(VGPR611) src1(VGPR608) // VOP2 # 610: OpFAdd: FloatVector3: tmp610 << tmp591, tmp609 V_ADD_F32 vDst(VGPR615) src0(VGPR596) src1(VGPR612) // VOP2 V_ADD_F32 vDst(VGPR616) src0(VGPR597) src1(VGPR613) // VOP2 V_ADD_F32 vDst(VGPR617) src0(VGPR598) src1(VGPR614) // VOP2 # OpStore: : tmp610 >> param612 V_MOV_B32 vDst(VGPR558) src0(VGPR615) V_MOV_B32 vDst(VGPR559) src0(VGPR616) V_MOV_B32 vDst(VGPR560) src0(VGPR617) # 614: OpFunctionCall: FloatVector3: getNorm(vf3;(param612) S_ADD_U32 sDst(SGPR169) src0(LITERAL_CONST) src1(0) const: 0x22e # VGPR[558:560] S_MOV_B64 sDst(SGPR296) src0(EXEC) S_MOV_B32 sDst(SGPR168) src0(LITERAL_CONST) const: 0x26a # VGPR[618:620] # Indirect branch to getNorm(vf3;: ??? S_GETPC_B64 sDst(SGPR166) src0(SGPR166) S_ADD_U32 sDst(SGPR166) src0(SGPR166) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR167) src0(SGPR167) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR166) src0(SGPR166) S_MOV_B64 sDst(EXEC) src0(SGPR296) # .lbl30 # 617: OpAccessChain: Float*: hit[0] # 618: OpCompositeExtract: Float: tmp618 << march(vf3;vf3;, 0 V_MOV_B32 vDst(VGPR621) src0(VGPR609) # 619: OpFOrdLessThan: Bool: tmp619 << tmp618, const308 V_MOV_B32 vDst(VGPR622) src0(LITERAL_CONST) const: 0x41a00000 V_CMP_LT_F32 dst(SGPR298) src0(VGPR621) src1(VGPR622) // VOP3a # OpSelectionMerge: (merge: lb621) # CF Block: Merge: lb621 S_MOV_B64 sDst(SGPR300) src0(EXEC) # OpBranchConditional: if(tmp619) then branch to lb620, else branch to lb627 # CF Block: Cond Branch: true: lb620, false: lb627 S_AND_B64 sDst(EXEC) src0(SGPR298) src1(EXEC) S_CBRANCH_EXECZ ??? lb627 S_BRANCH ??? lb620 # lb620 Label: lb620 # OpStore: : tmp610 >> param622 V_MOV_B32 vDst(VGPR567) src0(VGPR615) V_MOV_B32 vDst(VGPR568) src0(VGPR616) V_MOV_B32 vDst(VGPR569) src0(VGPR617) # OpStore: : getNorm(vf3; >> param624 V_MOV_B32 vDst(VGPR570) src0(VGPR618) V_MOV_B32 vDst(VGPR571) src0(VGPR619) V_MOV_B32 vDst(VGPR572) src0(VGPR620) # 626: OpFunctionCall: FloatVector3: light(vf3;vf3;(param622, param624) S_ADD_U32 sDst(SGPR187) src0(LITERAL_CONST) src1(0) const: 0x237 # VGPR[567:569] S_ADD_U32 sDst(SGPR188) src0(LITERAL_CONST) src1(0) const: 0x23a # VGPR[570:572] S_MOV_B64 sDst(SGPR302) src0(EXEC) S_MOV_B32 sDst(SGPR186) src0(LITERAL_CONST) const: 0x26f # VGPR[623:625] # Indirect branch to light(vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR184) src0(SGPR184) S_ADD_U32 sDst(SGPR184) src0(SGPR184) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR185) src0(SGPR185) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR184) src0(SGPR184) S_MOV_B64 sDst(EXEC) src0(SGPR302) # .lbl31 # OpStore: : light(vf3;vf3; >> var616 V_MOV_B32 vDst(VGPR564) src0(VGPR623) V_MOV_B32 vDst(VGPR565) src0(VGPR624) V_MOV_B32 vDst(VGPR566) src0(VGPR625) # OpBranch: to lb621 S_BRANCH ??? lb621 # lb627 Label: lb627 # 629: OpExtInst(Length): Float: tmp629 << tmp580 V_MUL_F32 vDst(VGPR626) src0(VGPR587) src1(VGPR587) // VOP2 V_MAC_F32 vDst(VGPR626) src0(VGPR588) src1(VGPR588) // VOP2 V_SQRT_F32 vDst(VGPR626) src0(VGPR626) # 630: OpFSub: Float: tmp630 << const88, tmp629 V_SUB_F32 vDst(VGPR627) src0(1_0_F) src1(VGPR626) // VOP2 # 631: OpFMul: Float: tmp631 << const385, tmp630 V_MOV_B32 vDst(VGPR628) src0(LITERAL_CONST) const: 0x3dcccccd V_MUL_F32 vDst(VGPR629) src0(VGPR628) src1(VGPR627) // VOP2 # 632: OpCompositeConstruct: FloatVector3: tmp632 << tmp631, tmp631, tmp631 V_MOV_B32 vDst(VGPR630) src0(VGPR629) V_MOV_B32 vDst(VGPR631) src0(VGPR629) V_MOV_B32 vDst(VGPR632) src0(VGPR629) # OpStore: : tmp632 >> var616 V_MOV_B32 vDst(VGPR564) src0(VGPR630) V_MOV_B32 vDst(VGPR565) src0(VGPR631) V_MOV_B32 vDst(VGPR566) src0(VGPR632) # OpBranch: to lb621 S_BRANCH ??? lb621 # lb621 Label: lb621 # 633: OpLoad: FloatVector3: tmp633 << var616 # OpStore: : tmp633 >> col V_MOV_B32 vDst(VGPR561) src0(VGPR564) V_MOV_B32 vDst(VGPR562) src0(VGPR565) V_MOV_B32 vDst(VGPR563) src0(VGPR566) # 635: OpLoad: Float: tmp635 << NumCol # 636: OpConvertFToS: Int: tmp636 << tmp635 V_CVT_I32_F32 vDst(VGPR633) src0(VGPR263) # OpStore: : tmp636 >> param637 V_MOV_B32 vDst(VGPR573) src0(VGPR633) # 638: OpFunctionCall: FloatVector3: getSphereColor(i1;(param637) S_ADD_U32 sDst(SGPR229) src0(LITERAL_CONST) src1(0) const: 0x23d # VGPR573 S_MOV_B64 sDst(SGPR304) src0(EXEC) S_MOV_B32 sDst(SGPR228) src0(LITERAL_CONST) const: 0x27a # VGPR[634:636] # Indirect branch to getSphereColor(i1;: ??? S_GETPC_B64 sDst(SGPR226) src0(SGPR226) S_ADD_U32 sDst(SGPR226) src0(SGPR226) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR227) src0(SGPR227) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR226) src0(SGPR226) S_MOV_B64 sDst(EXEC) src0(SGPR304) # .lbl32 # 640: OpLoad: FloatVector3: tmp640 << col # 641: OpFMul: FloatVector3: tmp641 << tmp640, getSphereColor(i1; V_MUL_F32 vDst(VGPR637) src0(VGPR561) src1(VGPR634) // VOP2 V_MUL_F32 vDst(VGPR638) src0(VGPR562) src1(VGPR635) // VOP2 V_MUL_F32 vDst(VGPR639) src0(VGPR563) src1(VGPR636) // VOP2 # OpStore: : tmp641 >> col V_MOV_B32 vDst(VGPR561) src0(VGPR637) V_MOV_B32 vDst(VGPR562) src0(VGPR638) V_MOV_B32 vDst(VGPR563) src0(VGPR639) # 642: OpAccessChain: Float*: hit[1] # 643: OpCompositeExtract: Float: tmp643 << march(vf3;vf3;, 1 V_MOV_B32 vDst(VGPR640) src0(VGPR610) # 644: OpExtInst(Pow): Float: tmp644 << tmp643, const267 V_MOV_B32 vDst(VGPR641) src0(LITERAL_CONST) const: 0x40400000 V_LOG_F32 vDst(VGPR642) src0(VGPR640) V_MUL_F32 vDst(VGPR642) src0(VGPR641) src1(VGPR642) // VOP2 V_EXP_F32 vDst(VGPR642) src0(VGPR642) # 645: OpLoad: FloatVector3: tmp645 << col # 646: OpCompositeConstruct: FloatVector3: tmp646 << tmp644, tmp644, tmp644 V_MOV_B32 vDst(VGPR643) src0(VGPR642) V_MOV_B32 vDst(VGPR644) src0(VGPR642) V_MOV_B32 vDst(VGPR645) src0(VGPR642) # 647: OpFAdd: FloatVector3: tmp647 << tmp645, tmp646 V_ADD_F32 vDst(VGPR646) src0(VGPR561) src1(VGPR643) // VOP2 V_ADD_F32 vDst(VGPR647) src0(VGPR562) src1(VGPR644) // VOP2 V_ADD_F32 vDst(VGPR648) src0(VGPR563) src1(VGPR645) // VOP2 # OpStore: : tmp647 >> col V_MOV_B32 vDst(VGPR561) src0(VGPR646) V_MOV_B32 vDst(VGPR562) src0(VGPR647) V_MOV_B32 vDst(VGPR563) src0(VGPR648) # 648: OpLoad: FloatVector3: tmp648 << col # 649: OpExtInst(Sqrt): FloatVector3: tmp649 << tmp648 V_SQRT_F32 vDst(VGPR649) src0(VGPR561) V_SQRT_F32 vDst(VGPR650) src0(VGPR562) V_SQRT_F32 vDst(VGPR651) src0(VGPR563) # 650: OpCompositeExtract: Float: tmp650 << tmp649, 0 V_MOV_B32 vDst(VGPR652) src0(VGPR649) # 651: OpCompositeExtract: Float: tmp651 << tmp649, 1 V_MOV_B32 vDst(VGPR653) src0(VGPR650) # 652: OpCompositeExtract: Float: tmp652 << tmp649, 2 V_MOV_B32 vDst(VGPR654) src0(VGPR651) # 653: OpCompositeConstruct: FloatVector4: tmp653 << tmp650, tmp651, tmp652, const88 V_MOV_B32 vDst(VGPR655) src0(VGPR652) V_MOV_B32 vDst(VGPR656) src0(VGPR653) V_MOV_B32 vDst(VGPR657) src0(VGPR654) V_MOV_B32 vDst(VGPR658) src0(1_0_F) # OpStore: : tmp653 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR655) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR656) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR657) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR658) # OpReturn: S_SETPC_B64 sDst(SGPR10) src0(SGPR10) Performing GPU-specific optimization... Pre register allocation control-flow processing... Intermediate disassembly (pre register allocation): Program Type: Fragment Special Input Variables: offset: unset, size: 16, FloatVector4 gl_FragCoord BuiltIn(FragCoord) Textures: offset: 0, size: 4, Float iChannel0 offset: 1, size: 4, Float iChannel1 offset: 2, size: 4, Float iChannel2 offset: 3, size: 4, Float iChannel3 Output Variables: offset: 0, size: 16, FloatVector4 finalColor Uniform Constants: offset: 0, size: 4, Float iTime offset: 4, size: 12, FloatVector3 iResolution offset: 16, size: 16, FloatVector4 iMouse offset: 32, size: 16, FloatVector4 iDate offset: 48, size: 4, Float iFrame offset: 52, size: 48, FloatVector3 iChannelResolution[4] Private Global Variables: offset: unset, size: 12, FloatVector3 lDir0 offset: unset, size: 12, FloatVector3 lDir1 offset: unset, size: 12, FloatVector3 lCol0 offset: unset, size: 12, FloatVector3 lCol1 offset: unset, size: 4, Float NumCol Constants: Float const80: 0.408248 Float const81: 0.816497 FloatVector3 const82: {0.408248, 0.816497, 0.408248} Float const84: -0.408248 Float const85: -0.816497 FloatVector3 const86: {-0.408248, 0.408248, -0.816497} Float const88: 1 Float const89: 0.8 Float const90: 0.5 FloatVector3 const91: {1, 0.8, 0.5} Float const93: 0.6 FloatVector3 const94: {0.6, 0.8, 1} UInt32 const99: 0 UInt32 const102: 1 UInt32 const108: 2 Float const126: 0.333333 Float const134: 2 Float const174: 0 Float const199: 9999 FloatVector2 const200: {9999, 0} Float const206: 6 FloatVector2 const207: {6, 6} Float const214: 1.9 Float const215: 6.78 FloatVector2 const216: {1.9, 6.78} Float const229: 9 Float const240: 0.35 Float const242: 9999.9 FloatVector2 const243: {9999.9, 0} Float const245: -999 Int32 const250: 0 Int32 const257: 5 Float const267: 3 Int32 const271: 1 Float const277: 5 Float const279: 0.4 Float const284: 8 Float const292: 7 Float const308: 20 Int32 const317: 100 Float const329: 0.001 Float const343: 100 Float const348: 0.002 Int32 const362: 50 Float const385: 0.1 FloatVector2 const390: {0.001, 0} Float const435: 0.01 FloatVector3 const436: {0.01, 0.01, 0.01} Int32 const444: 2 Float const481: 0.7 FloatVector3 const489: {0, 0, 0} FloatVector3 const495: {0, 0, 1} FloatVector3 const501: {0, 1, 0} Int32 const504: 3 FloatVector3 const508: {0, 1, 1} Int32 const511: 4 FloatVector3 const515: {1, 0, 0} FloatVector3 const521: {1, 0, 1} Int32 const524: 6 Int32 const529: 7 FloatVector3 const533: {1, 1, 1} Int32 const536: 8 Float const540: 0.425 Float const541: 0.56 Float const542: 0.9 FloatVector3 const543: {0.425, 0.56, 0.9} Int32 const546: 9 FloatVector3 const550: {0.5, 0.6, 0.6} Int32 const553: 10 Int32 const559: 11 FloatVector3 const563: {0.5, 0.8, 0.9} Float const582: -1 Float const587: -5 UInt32 const670: 4 Int32 const681: 64 Float const682: 0.0001 Function Local Variables: offset: unset, size: 16, FloatVector4 main.param657 offset: unset, size: 8, FloatVector2 main.param658 offset: unset, size: 16, FloatVector4 main.fragColor offset: unset, size: 8, FloatVector2 main.fragCoord offset: unset, size: 12, FloatVector3 main.p offset: unset, size: 12, FloatVector3 sdCross(vf3;.p offset: unset, size: 12, FloatVector3 sdCrossRep(vf3;.param139 offset: unset, size: 12, FloatVector3 sdCrossRep(vf3;.p offset: unset, size: 4, Float sdCrossRep(vf3;.s offset: unset, size: 12, FloatVector3 sdCrossRepScale(vf3;f1;.param147 offset: unset, size: 4, Float sdCrossRepScale(vf3;f1;.distA offset: unset, size: 4, Float sdCrossRepScale(vf3;f1;.distB offset: unset, size: 12, FloatVector3 differenceSDF(f1;f1;.p offset: unset, size: 8, FloatVector2 differenceSDF(f1;f1;.h offset: unset, size: 8, FloatVector2 sdCylinder(vf3;vf2;.d1 offset: unset, size: 8, FloatVector2 sdCylinder(vf3;vf2;.d2 offset: unset, size: 8, FloatVector2 opU(vf2;vf2;.resp offset: unset, size: 12, FloatVector3 opU(vf2;vf2;.p offset: unset, size: 8, FloatVector2 diso(vf3;.res offset: unset, size: 12, FloatVector3 diso(vf3;.param208 offset: unset, size: 8, FloatVector2 diso(vf3;.param211 offset: unset, size: 12, FloatVector3 diso(vf3;.param217 offset: unset, size: 8, FloatVector2 diso(vf3;.param220 offset: unset, size: 4, Float diso(vf3;.param223 offset: unset, size: 4, Float diso(vf3;.param225 offset: unset, size: 8, FloatVector2 diso(vf3;.param231 offset: unset, size: 8, FloatVector2 diso(vf3;.param233 offset: unset, size: 12, FloatVector3 diso(vf3;.p offset: unset, size: 4, Float DE(vf3;.scale offset: unset, size: 8, FloatVector2 DE(vf3;.res offset: unset, size: 4, Float DE(vf3;.dist offset: unset, size: 12, FloatVector3 DE(vf3;.param246 offset: unset, size: 4, Int32 DE(vf3;.i offset: unset, size: 12, FloatVector3 DE(vf3;.param260 offset: unset, size: 4, Float DE(vf3;.param262 offset: unset, size: 8, FloatVector2 DE(vf3;.param286 offset: unset, size: 8, FloatVector2 DE(vf3;.param288 offset: unset, size: 8, FloatVector2 DE(vf3;.param294 offset: unset, size: 8, FloatVector2 DE(vf3;.param296 offset: unset, size: 12, FloatVector3 DE(vf3;.ro offset: unset, size: 12, FloatVector3 DE(vf3;.rd offset: unset, size: 4, Float march(vf3;vf3;.t offset: unset, size: 4, Float march(vf3;vf3;.d offset: unset, size: 4, Float march(vf3;vf3;.it offset: unset, size: 4, Int32 march(vf3;vf3;.i offset: unset, size: 12, FloatVector3 march(vf3;vf3;.param324 offset: unset, size: 12, FloatVector3 march(vf3;vf3;.p offset: unset, size: 12, FloatVector3 march(vf3;vf3;.n offset: unset, size: 12, FloatVector3 march(vf3;vf3;.ld offset: unset, size: 4, Float getShadow(vf3;vf3;vf3;.t offset: unset, size: 4, Float getShadow(vf3;vf3;vf3;.d offset: unset, size: 4, Int32 getShadow(vf3;vf3;vf3;.i offset: unset, size: 12, FloatVector3 getShadow(vf3;vf3;vf3;.param369 offset: unset, size: 12, FloatVector3 getShadow(vf3;vf3;vf3;.p offset: unset, size: 12, FloatVector3 getNorm(vf3;.param395 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param401 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param408 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param414 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param421 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param427 offset: unset, size: 12, FloatVector3 getNorm(vf3;.p offset: unset, size: 12, FloatVector3 getNorm(vf3;.n offset: unset, size: 12, FloatVector3 light(vf3;vf3;.col offset: unset, size: 4, Int32 light(vf3;vf3;.i offset: unset, size: 4, Float light(vf3;vf3;.diff offset: unset, size: 12, FloatVector3 light(vf3;vf3;.param459 offset: unset, size: 12, FloatVector3 light(vf3;vf3;.param461 offset: unset, size: 12, FloatVector3 light(vf3;vf3;.param463 offset: unset, size: 4, Int32 light(vf3;vf3;.i offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param599 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param601 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param612 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.col offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.var616 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param622 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param624 offset: unset, size: 4, Int32 mainImage(vf4;vf2;.param637 Instructions: V_SUB_F32 vDst(VGPR14) src0(SGPR2) src1(VGPR14) // VOP2 # Void main() Function: Void main() # lb5 Label: lb5 # OpStore: : const82 >> lDir0 V_MOV_B32 vDst(VGPR27) src0(LITERAL_CONST) const: 0x3ed105ec V_MOV_B32 vDst(VGPR28) src0(LITERAL_CONST) const: 0x3f5105ec V_MOV_B32 vDst(VGPR29) src0(LITERAL_CONST) const: 0x3ed105ec V_MOV_B32 vDst(VGPR24) src0(VGPR27) V_MOV_B32 vDst(VGPR25) src0(VGPR28) V_MOV_B32 vDst(VGPR26) src0(VGPR29) # OpStore: : const86 >> lDir1 V_MOV_B32 vDst(VGPR33) src0(LITERAL_CONST) const: 0xbed105ec V_MOV_B32 vDst(VGPR34) src0(LITERAL_CONST) const: 0x3ed105ec V_MOV_B32 vDst(VGPR35) src0(LITERAL_CONST) const: 0xbf5105ec V_MOV_B32 vDst(VGPR30) src0(VGPR33) V_MOV_B32 vDst(VGPR31) src0(VGPR34) V_MOV_B32 vDst(VGPR32) src0(VGPR35) # OpStore: : const91 >> lCol0 V_MOV_B32 vDst(VGPR39) src0(1_0_F) V_MOV_B32 vDst(VGPR40) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR41) src0(0_5_F) V_MOV_B32 vDst(VGPR36) src0(VGPR39) V_MOV_B32 vDst(VGPR37) src0(VGPR40) V_MOV_B32 vDst(VGPR38) src0(VGPR41) # OpStore: : const94 >> lCol1 V_MOV_B32 vDst(VGPR45) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR46) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR47) src0(1_0_F) V_MOV_B32 vDst(VGPR42) src0(VGPR45) V_MOV_B32 vDst(VGPR43) src0(VGPR46) V_MOV_B32 vDst(VGPR44) src0(VGPR47) # 659: OpLoad: FloatVector4: tmp659 << gl_FragCoord V_MOV_B32 vDst(VGPR48) src0(VGPR13) V_MOV_B32 vDst(VGPR49) src0(VGPR14) V_MOV_B32 vDst(VGPR50) src0(VGPR15) V_MOV_B32 vDst(VGPR51) src0(VGPR16) # 660: OpVectorShuffle: FloatVector2: tmp660 << tmp659, tmp659, 0, 1 V_MOV_B32 vDst(VGPR52) src0(VGPR48) V_MOV_B32 vDst(VGPR53) src0(VGPR49) # OpStore: : tmp660 >> param658 V_MOV_B32 vDst(VGPR22) src0(VGPR52) V_MOV_B32 vDst(VGPR23) src0(VGPR53) # 661: OpFunctionCall: Void: mainImage(vf4;vf2;(param657, param658) S_ADD_U32 sDst(SGPR12) src0(LITERAL_CONST) src1(0) const: 0x12 # VGPR[18:21] S_ADD_U32 sDst(SGPR13) src0(LITERAL_CONST) src1(0) const: 0x16 # VGPR[22:23] S_MOV_B64 sDst(SGPR14) src0(EXEC) # Indirect branch to mainImage(vf4;vf2;: ??? S_GETPC_B64 sDst(SGPR10) src0(SGPR10) S_ADD_U32 sDst(SGPR10) src0(SGPR10) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR11) src0(SGPR11) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR10) src0(SGPR10) S_MOV_B64 sDst(EXEC) src0(SGPR14) # .lbl0 # 662: OpLoad: FloatVector4: tmp662 << param657 # OpStore: : tmp662 >> finalColor V_MOV_B32 vDst(VGPR54) src0(VGPR18) V_MOV_B32 vDst(VGPR55) src0(VGPR19) V_MOV_B32 vDst(VGPR56) src0(VGPR20) V_MOV_B32 vDst(VGPR57) src0(VGPR21) # OpReturn: V_CVT_PKRTZ_F16_F32 vDst(VGPR54) src0(VGPR54) src1(VGPR55) // VOP2 V_CVT_PKRTZ_F16_F32 vDst(VGPR55) src0(VGPR56) src1(VGPR57) // VOP2 EXP en(0xf) tgt(0) compr(1) done(1) vm(1) vsrc0(VGPR54) vsrc1(VGPR55) vsrc2(VGPR56) vsrc3(VGPR57) S_WAITCNT 0 S_ENDPGM 0 # Float sdCross(vf3;(FloatVector3* p) Function: Float sdCross(vf3;() S_MOV_B64 sDst(SGPR20) src0(EXEC) # lb12 Label: lb12 # 95: OpLoad: FloatVector3: tmp95 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR58) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR59) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR60) src0(VGPR2) # 96: OpExtInst(FAbs): FloatVector3: tmp96 << tmp95 V_ADD_F32 vDst(VGPR61) src0(VGPR58) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR62) src0(VGPR59) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR63) src0(VGPR60) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp96 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR61) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR62) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR63) # 100: OpAccessChain: Float*: p[0] # 101: OpLoad: Float: tmp101 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR64) src0(VGPR0) # 103: OpAccessChain: Float*: p[1] # 104: OpLoad: Float: tmp104 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR65) src0(VGPR1) # 105: OpExtInst(FMax): Float: tmp105 << tmp101, tmp104 V_MAX_F32 vDst(VGPR66) src0(VGPR64) src1(VGPR65) // VOP2 # 106: OpAccessChain: Float*: p[1] # 107: OpLoad: Float: tmp107 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR67) src0(VGPR1) # 109: OpAccessChain: Float*: p[2] # 110: OpLoad: Float: tmp110 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR68) src0(VGPR2) # 111: OpExtInst(FMax): Float: tmp111 << tmp107, tmp110 V_MAX_F32 vDst(VGPR69) src0(VGPR67) src1(VGPR68) // VOP2 # 112: OpAccessChain: Float*: p[2] # 113: OpLoad: Float: tmp113 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR70) src0(VGPR2) # 114: OpAccessChain: Float*: p[0] # 115: OpLoad: Float: tmp115 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR71) src0(VGPR0) # 116: OpExtInst(FMax): Float: tmp116 << tmp113, tmp115 V_MAX_F32 vDst(VGPR72) src0(VGPR70) src1(VGPR71) // VOP2 # 117: OpCompositeConstruct: FloatVector3: tmp117 << tmp105, tmp111, tmp116 V_MOV_B32 vDst(VGPR73) src0(VGPR66) V_MOV_B32 vDst(VGPR74) src0(VGPR69) V_MOV_B32 vDst(VGPR75) src0(VGPR72) # 118: OpAccessChain: Float*: d[0] # 119: OpCompositeExtract: Float: tmp119 << tmp117, 0 V_MOV_B32 vDst(VGPR76) src0(VGPR73) # 120: OpAccessChain: Float*: d[1] # 121: OpCompositeExtract: Float: tmp121 << tmp117, 1 V_MOV_B32 vDst(VGPR77) src0(VGPR74) # 122: OpAccessChain: Float*: d[2] # 123: OpCompositeExtract: Float: tmp123 << tmp117, 2 V_MOV_B32 vDst(VGPR78) src0(VGPR75) # 124: OpExtInst(FMin): Float: tmp124 << tmp121, tmp123 V_MIN_F32 vDst(VGPR79) src0(VGPR77) src1(VGPR78) // VOP2 # 125: OpExtInst(FMin): Float: tmp125 << tmp119, tmp124 V_MIN_F32 vDst(VGPR80) src0(VGPR76) src1(VGPR79) // VOP2 # 127: OpFSub: Float: tmp127 << tmp125, const126 V_MOV_B32 vDst(VGPR81) src0(LITERAL_CONST) const: 0x3eaaaaab V_SUB_F32 vDst(VGPR82) src0(VGPR80) src1(VGPR81) // VOP2 # OpReturnValue: : << tmp127 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR82) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # Float sdCrossRep(vf3;(FloatVector3* p) Function: Float sdCrossRep(vf3;() S_MOV_B64 sDst(SGPR26) src0(EXEC) # lb15 Label: lb15 # 131: OpLoad: FloatVector3: tmp131 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR86) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR87) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR88) src0(VGPR2) # 132: OpCompositeConstruct: FloatVector3: tmp132 << const88, const88, const88 V_MOV_B32 vDst(VGPR89) src0(1_0_F) V_MOV_B32 vDst(VGPR90) src0(1_0_F) V_MOV_B32 vDst(VGPR91) src0(1_0_F) # 133: OpFAdd: FloatVector3: tmp133 << tmp131, tmp132 V_ADD_F32 vDst(VGPR92) src0(VGPR86) src1(VGPR89) // VOP2 V_ADD_F32 vDst(VGPR93) src0(VGPR87) src1(VGPR90) // VOP2 V_ADD_F32 vDst(VGPR94) src0(VGPR88) src1(VGPR91) // VOP2 # 135: OpCompositeConstruct: FloatVector3: tmp135 << const134, const134, const134 V_MOV_B32 vDst(VGPR95) src0(2_0_F) V_MOV_B32 vDst(VGPR96) src0(2_0_F) V_MOV_B32 vDst(VGPR97) src0(2_0_F) # 136: OpFMod: FloatVector3: tmp136 << tmp133, tmp135 V_RCP_F32 vDst(VGPR98) src0(VGPR95) V_MUL_F32 vDst(VGPR98) src0(VGPR92) src1(VGPR98) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR98) src0(VGPR98) src1(VGPR95) src2(VGPR92) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR98) src0(VGPR98) V_RCP_F32 vDst(VGPR99) src0(VGPR96) V_MUL_F32 vDst(VGPR99) src0(VGPR93) src1(VGPR99) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR99) src0(VGPR99) src1(VGPR96) src2(VGPR93) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR99) src0(VGPR99) V_RCP_F32 vDst(VGPR100) src0(VGPR97) V_MUL_F32 vDst(VGPR100) src0(VGPR94) src1(VGPR100) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR100) src0(VGPR100) src1(VGPR97) src2(VGPR94) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR100) src0(VGPR100) V_MAD_F32 vDst(VGPR98) src0(VGPR95) src1(VGPR98) src2(VGPR92) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR99) src0(VGPR96) src1(VGPR99) src2(VGPR93) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR100) src0(VGPR97) src1(VGPR100) src2(VGPR94) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 137: OpCompositeConstruct: FloatVector3: tmp137 << const88, const88, const88 V_MOV_B32 vDst(VGPR101) src0(1_0_F) V_MOV_B32 vDst(VGPR102) src0(1_0_F) V_MOV_B32 vDst(VGPR103) src0(1_0_F) # 138: OpFSub: FloatVector3: tmp138 << tmp136, tmp137 V_SUB_F32 vDst(VGPR104) src0(VGPR98) src1(VGPR101) // VOP2 V_SUB_F32 vDst(VGPR105) src0(VGPR99) src1(VGPR102) // VOP2 V_SUB_F32 vDst(VGPR106) src0(VGPR100) src1(VGPR103) // VOP2 # OpStore: : tmp138 >> param139 V_MOV_B32 vDst(VGPR83) src0(VGPR104) V_MOV_B32 vDst(VGPR84) src0(VGPR105) V_MOV_B32 vDst(VGPR85) src0(VGPR106) # 141: OpFunctionCall: Float: sdCross(vf3;(param139) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x53 # VGPR[83:85] S_MOV_B64 sDst(SGPR28) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x6b # VGPR107 # Indirect branch to sdCross(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR28) # .lbl1 # OpReturnValue: : << sdCross(vf3; S_MOV_B32 sDst(M0) src0(SGPR24) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR107) S_SETPC_B64 sDst(SGPR22) src0(SGPR22) # Float sdCrossRepScale(vf3;f1;(FloatVector3* p, Float* s) Function: Float sdCrossRepScale(vf3;f1;(, Float sdCrossRep(vf3;.s) S_MOV_B64 sDst(SGPR36) src0(EXEC) # lb21 Label: lb21 # 144: OpLoad: FloatVector3: tmp144 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR33) const: 0x0 V_MOVRELS_B32 vDst(VGPR111) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR112) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR113) src0(VGPR2) # 145: OpLoad: Float: tmp145 << s S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR34) const: 0x0 V_MOVRELS_B32 vDst(VGPR114) src0(VGPR0) # 146: OpVectorTimesScalar: FloatVector3: tmp146 << tmp144, tmp145 V_MUL_F32 vDst(VGPR115) src0(VGPR114) src1(VGPR111) // VOP2 V_MUL_F32 vDst(VGPR116) src0(VGPR114) src1(VGPR112) // VOP2 V_MUL_F32 vDst(VGPR117) src0(VGPR114) src1(VGPR113) // VOP2 # OpStore: : tmp146 >> param147 V_MOV_B32 vDst(VGPR108) src0(VGPR115) V_MOV_B32 vDst(VGPR109) src0(VGPR116) V_MOV_B32 vDst(VGPR110) src0(VGPR117) # 148: OpFunctionCall: Float: sdCrossRep(vf3;(param147) S_ADD_U32 sDst(SGPR25) src0(LITERAL_CONST) src1(0) const: 0x6c # VGPR[108:110] S_MOV_B64 sDst(SGPR38) src0(EXEC) S_MOV_B32 sDst(SGPR24) src0(LITERAL_CONST) const: 0x76 # VGPR118 # Indirect branch to sdCrossRep(vf3;: ??? S_GETPC_B64 sDst(SGPR22) src0(SGPR22) S_ADD_U32 sDst(SGPR22) src0(SGPR22) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR23) src0(SGPR23) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR22) src0(SGPR22) S_MOV_B64 sDst(EXEC) src0(SGPR38) # .lbl2 # 149: OpLoad: Float: tmp149 << s S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR34) const: 0x0 V_MOVRELS_B32 vDst(VGPR119) src0(VGPR0) # 150: OpFDiv: Float: tmp150 << sdCrossRep(vf3;, tmp149 V_RCP_F32 vDst(VGPR120) src0(VGPR119) V_MUL_F32 vDst(VGPR120) src0(VGPR118) src1(VGPR120) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR120) src0(VGPR120) src1(VGPR119) src2(VGPR118) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp150 S_MOV_B32 sDst(M0) src0(SGPR32) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR120) S_SETPC_B64 sDst(SGPR30) src0(SGPR30) # Float differenceSDF(f1;f1;(Float* distA, Float* distB) Function: Float differenceSDF(f1;f1;(, Float sdCrossRepScale(vf3;f1;.distB) S_MOV_B64 sDst(SGPR46) src0(EXEC) # lb26 Label: lb26 # 153: OpLoad: Float: tmp153 << distA S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR43) const: 0x0 V_MOVRELS_B32 vDst(VGPR121) src0(VGPR0) # 154: OpLoad: Float: tmp154 << distB S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR44) const: 0x0 V_MOVRELS_B32 vDst(VGPR122) src0(VGPR0) # 155: OpFNegate: Float: tmp155 << tmp154 V_MUL_F32 vDst(VGPR123) src0(M1_0_F) src1(VGPR122) // VOP2 # 156: OpExtInst(FMax): Float: tmp156 << tmp153, tmp155 V_MAX_F32 vDst(VGPR124) src0(VGPR121) src1(VGPR123) // VOP2 # OpReturnValue: : << tmp156 S_MOV_B32 sDst(M0) src0(SGPR42) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR124) S_SETPC_B64 sDst(SGPR40) src0(SGPR40) # Float sdCylinder(vf3;vf2;(FloatVector3* p, FloatVector2* h) Function: Float sdCylinder(vf3;vf2;(, FloatVector2 differenceSDF(f1;f1;.h) S_MOV_B64 sDst(SGPR54) src0(EXEC) # lb33 Label: lb33 # 160: OpLoad: FloatVector3: tmp160 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR51) const: 0x0 V_MOVRELS_B32 vDst(VGPR125) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR126) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR127) src0(VGPR2) # 161: OpVectorShuffle: FloatVector2: tmp161 << tmp160, tmp160, 0, 2 V_MOV_B32 vDst(VGPR128) src0(VGPR125) V_MOV_B32 vDst(VGPR129) src0(VGPR127) # 162: OpExtInst(Length): Float: tmp162 << tmp161 V_MUL_F32 vDst(VGPR130) src0(VGPR128) src1(VGPR128) // VOP2 V_MAC_F32 vDst(VGPR130) src0(VGPR129) src1(VGPR129) // VOP2 V_SQRT_F32 vDst(VGPR130) src0(VGPR130) # 163: OpAccessChain: Float*: p[1] # 164: OpLoad: Float: tmp164 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR51) const: 0x0 V_MOVRELS_B32 vDst(VGPR131) src0(VGPR1) # 165: OpCompositeConstruct: FloatVector2: tmp165 << tmp162, tmp164 V_MOV_B32 vDst(VGPR132) src0(VGPR130) V_MOV_B32 vDst(VGPR133) src0(VGPR131) # 166: OpExtInst(FAbs): FloatVector2: tmp166 << tmp165 V_ADD_F32 vDst(VGPR134) src0(VGPR132) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR135) src0(VGPR133) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 167: OpLoad: FloatVector2: tmp167 << h S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR52) const: 0x0 V_MOVRELS_B32 vDst(VGPR136) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR137) src0(VGPR1) # 168: OpFSub: FloatVector2: tmp168 << tmp166, tmp167 V_SUB_F32 vDst(VGPR138) src0(VGPR134) src1(VGPR136) // VOP2 V_SUB_F32 vDst(VGPR139) src0(VGPR135) src1(VGPR137) // VOP2 # 169: OpAccessChain: Float*: d[0] # 170: OpCompositeExtract: Float: tmp170 << tmp168, 0 V_MOV_B32 vDst(VGPR140) src0(VGPR138) # 171: OpAccessChain: Float*: d[1] # 172: OpCompositeExtract: Float: tmp172 << tmp168, 1 V_MOV_B32 vDst(VGPR141) src0(VGPR139) # 173: OpExtInst(FMax): Float: tmp173 << tmp170, tmp172 V_MAX_F32 vDst(VGPR142) src0(VGPR140) src1(VGPR141) // VOP2 # 175: OpExtInst(FMin): Float: tmp175 << tmp173, const174 V_MOV_B32 vDst(VGPR143) src0(LITERAL_CONST) const: 0x00000000 V_MIN_F32 vDst(VGPR144) src0(VGPR142) src1(VGPR143) // VOP2 # 177: OpCompositeConstruct: FloatVector2: tmp177 << const174, const174 V_MOV_B32 vDst(VGPR147) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR145) src0(VGPR147) V_MOV_B32 vDst(VGPR148) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR146) src0(VGPR148) # 178: OpExtInst(FMax): FloatVector2: tmp178 << tmp168, tmp177 V_MAX_F32 vDst(VGPR149) src0(VGPR138) src1(VGPR145) // VOP2 V_MAX_F32 vDst(VGPR150) src0(VGPR139) src1(VGPR146) // VOP2 # 179: OpExtInst(Length): Float: tmp179 << tmp178 V_MUL_F32 vDst(VGPR151) src0(VGPR149) src1(VGPR149) // VOP2 V_MAC_F32 vDst(VGPR151) src0(VGPR150) src1(VGPR150) // VOP2 V_SQRT_F32 vDst(VGPR151) src0(VGPR151) # 180: OpFAdd: Float: tmp180 << tmp175, tmp179 V_ADD_F32 vDst(VGPR152) src0(VGPR144) src1(VGPR151) // VOP2 # OpReturnValue: : << tmp180 S_MOV_B32 sDst(M0) src0(SGPR50) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR152) S_SETPC_B64 sDst(SGPR48) src0(SGPR48) # FloatVector2 opU(vf2;vf2;(FloatVector2* d1, FloatVector2* d2) Function: FloatVector2 opU(vf2;vf2;(, FloatVector2 sdCylinder(vf3;vf2;.d2) S_MOV_B64 sDst(SGPR62) src0(EXEC) # lb38 Label: lb38 # 183: OpAccessChain: Float*: d1[0] # 184: OpLoad: Float: tmp184 << d1[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR59) const: 0x0 V_MOVRELS_B32 vDst(VGPR155) src0(VGPR0) # 185: OpAccessChain: Float*: d2[0] # 186: OpLoad: Float: tmp186 << d2[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR60) const: 0x0 V_MOVRELS_B32 vDst(VGPR156) src0(VGPR0) # 188: OpFOrdLessThan: Bool: tmp188 << tmp184, tmp186 V_CMP_LT_F32 dst(SGPR64) src0(VGPR155) src1(VGPR156) // VOP3a # OpSelectionMerge: (merge: lb190) # CF Block: Merge: lb190 S_MOV_B64 sDst(SGPR66) src0(EXEC) # OpBranchConditional: if(tmp188) then branch to lb189, else branch to lb193 # CF Block: Cond Branch: true: lb189, false: lb193 S_AND_B64 sDst(EXEC) src0(SGPR64) src1(EXEC) S_CBRANCH_EXECZ ??? lb193 # lb189 Label: lb189 # 192: OpLoad: FloatVector2: tmp192 << d1 S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR59) const: 0x0 V_MOVRELS_B32 vDst(VGPR157) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR158) src0(VGPR1) # OpStore: : tmp192 >> resp V_MOV_B32 vDst(VGPR153) src0(VGPR157) V_MOV_B32 vDst(VGPR154) src0(VGPR158) # OpBranch: to lb190 # lb193 Label: lb193 S_ANDN2_B64 sDst(EXEC) src0(SGPR66) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR62) src1(EXEC) S_CBRANCH_EXECZ ??? lb190 # 194: OpLoad: FloatVector2: tmp194 << d2 S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR60) const: 0x0 V_MOVRELS_B32 vDst(VGPR159) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR160) src0(VGPR1) # OpStore: : tmp194 >> resp V_MOV_B32 vDst(VGPR153) src0(VGPR159) V_MOV_B32 vDst(VGPR154) src0(VGPR160) # OpBranch: to lb190 # lb190 Label: lb190 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR66) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR62) # 195: OpLoad: FloatVector2: tmp195 << resp # OpReturnValue: : << tmp195 S_MOV_B32 sDst(M0) src0(SGPR58) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR153) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR154) S_SETPC_B64 sDst(SGPR56) src0(SGPR56) # Float diso(vf3;(FloatVector3* p) Function: Float diso(vf3;() S_MOV_B64 sDst(SGPR72) src0(EXEC) # lb41 Label: lb41 # OpStore: : const200 >> res V_MOV_B32 vDst(VGPR179) src0(LITERAL_CONST) const: 0x461c3c00 V_MOV_B32 vDst(VGPR180) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR161) src0(VGPR179) V_MOV_B32 vDst(VGPR162) src0(VGPR180) # 201: OpAccessChain: Float*: p[2] # 202: OpLoad: Float: tmp202 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR181) src0(VGPR2) # 203: OpFMod: Float: tmp203 << tmp202, const134 V_MOV_B32 vDst(VGPR182) src0(2_0_F) V_RCP_F32 vDst(VGPR183) src0(VGPR182) V_MUL_F32 vDst(VGPR183) src0(VGPR181) src1(VGPR183) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR183) src0(VGPR183) src1(VGPR182) src2(VGPR181) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR183) src0(VGPR183) V_MAD_F32 vDst(VGPR183) src0(VGPR182) src1(VGPR183) src2(VGPR181) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 204: OpAccessChain: Float*: p[2] # OpStore: : tmp203 >> p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELD_B32 vDst(VGPR2) src0(VGPR183) # 209: OpLoad: FloatVector3: tmp209 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR184) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR185) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR186) src0(VGPR2) # 210: OpVectorShuffle: FloatVector3: tmp210 << tmp209, tmp209, 1, 2, 0 V_MOV_B32 vDst(VGPR187) src0(VGPR185) V_MOV_B32 vDst(VGPR188) src0(VGPR186) V_MOV_B32 vDst(VGPR189) src0(VGPR184) # OpStore: : tmp210 >> param208 V_MOV_B32 vDst(VGPR163) src0(VGPR187) V_MOV_B32 vDst(VGPR164) src0(VGPR188) V_MOV_B32 vDst(VGPR165) src0(VGPR189) # OpStore: : const207 >> param211 V_MOV_B32 vDst(VGPR190) src0(LITERAL_CONST) const: 0x40c00000 V_MOV_B32 vDst(VGPR191) src0(LITERAL_CONST) const: 0x40c00000 V_MOV_B32 vDst(VGPR166) src0(VGPR190) V_MOV_B32 vDst(VGPR167) src0(VGPR191) # 212: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param208, param211) S_ADD_U32 sDst(SGPR51) src0(LITERAL_CONST) src1(0) const: 0xa3 # VGPR[163:165] S_ADD_U32 sDst(SGPR52) src0(LITERAL_CONST) src1(0) const: 0xa6 # VGPR[166:167] S_MOV_B64 sDst(SGPR74) src0(EXEC) S_MOV_B32 sDst(SGPR50) src0(LITERAL_CONST) const: 0xc0 # VGPR192 # Indirect branch to sdCylinder(vf3;vf2;: ??? S_GETPC_B64 sDst(SGPR48) src0(SGPR48) S_ADD_U32 sDst(SGPR48) src0(SGPR48) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR49) src0(SGPR49) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR48) src0(SGPR48) S_MOV_B64 sDst(EXEC) src0(SGPR74) # .lbl3 # 218: OpLoad: FloatVector3: tmp218 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR193) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR194) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR195) src0(VGPR2) # 219: OpVectorShuffle: FloatVector3: tmp219 << tmp218, tmp218, 1, 2, 0 V_MOV_B32 vDst(VGPR196) src0(VGPR194) V_MOV_B32 vDst(VGPR197) src0(VGPR195) V_MOV_B32 vDst(VGPR198) src0(VGPR193) # OpStore: : tmp219 >> param217 V_MOV_B32 vDst(VGPR168) src0(VGPR196) V_MOV_B32 vDst(VGPR169) src0(VGPR197) V_MOV_B32 vDst(VGPR170) src0(VGPR198) # OpStore: : const216 >> param220 V_MOV_B32 vDst(VGPR199) src0(LITERAL_CONST) const: 0x3ff33333 V_MOV_B32 vDst(VGPR200) src0(LITERAL_CONST) const: 0x40d8f5c3 V_MOV_B32 vDst(VGPR171) src0(VGPR199) V_MOV_B32 vDst(VGPR172) src0(VGPR200) # 221: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param217, param220) S_ADD_U32 sDst(SGPR51) src0(LITERAL_CONST) src1(0) const: 0xa8 # VGPR[168:170] S_ADD_U32 sDst(SGPR52) src0(LITERAL_CONST) src1(0) const: 0xab # VGPR[171:172] S_MOV_B64 sDst(SGPR76) src0(EXEC) S_MOV_B32 sDst(SGPR50) src0(LITERAL_CONST) const: 0xc9 # VGPR201 # Indirect branch to sdCylinder(vf3;vf2;: ??? S_GETPC_B64 sDst(SGPR48) src0(SGPR48) S_ADD_U32 sDst(SGPR48) src0(SGPR48) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR49) src0(SGPR49) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR48) src0(SGPR48) S_MOV_B64 sDst(EXEC) src0(SGPR76) # .lbl4 # OpStore: : sdCylinder(vf3;vf2; >> param223 V_MOV_B32 vDst(VGPR173) src0(VGPR192) # OpStore: : sdCylinder(vf3;vf2; >> param225 V_MOV_B32 vDst(VGPR174) src0(VGPR201) # 227: OpFunctionCall: Float: differenceSDF(f1;f1;(param223, param225) S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0xad # VGPR173 S_ADD_U32 sDst(SGPR44) src0(LITERAL_CONST) src1(0) const: 0xae # VGPR174 S_MOV_B64 sDst(SGPR78) src0(EXEC) S_MOV_B32 sDst(SGPR42) src0(LITERAL_CONST) const: 0xca # VGPR202 # Indirect branch to differenceSDF(f1;f1;: ??? S_GETPC_B64 sDst(SGPR40) src0(SGPR40) S_ADD_U32 sDst(SGPR40) src0(SGPR40) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR41) src0(SGPR41) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR40) src0(SGPR40) S_MOV_B64 sDst(EXEC) src0(SGPR78) # .lbl5 # 230: OpCompositeConstruct: FloatVector2: tmp230 << differenceSDF(f1;f1;, const229 V_MOV_B32 vDst(VGPR203) src0(VGPR202) V_MOV_B32 vDst(VGPR205) src0(LITERAL_CONST) const: 0x41100000 V_MOV_B32 vDst(VGPR204) src0(VGPR205) # 232: OpLoad: FloatVector2: tmp232 << res # OpStore: : tmp232 >> param231 V_MOV_B32 vDst(VGPR175) src0(VGPR161) V_MOV_B32 vDst(VGPR176) src0(VGPR162) # OpStore: : tmp230 >> param233 V_MOV_B32 vDst(VGPR177) src0(VGPR203) V_MOV_B32 vDst(VGPR178) src0(VGPR204) # 234: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param231, param233) S_ADD_U32 sDst(SGPR59) src0(LITERAL_CONST) src1(0) const: 0xaf # VGPR[175:176] S_ADD_U32 sDst(SGPR60) src0(LITERAL_CONST) src1(0) const: 0xb1 # VGPR[177:178] S_MOV_B64 sDst(SGPR80) src0(EXEC) S_MOV_B32 sDst(SGPR58) src0(LITERAL_CONST) const: 0xce # VGPR[206:207] # Indirect branch to opU(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_ADD_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR80) # .lbl6 # OpStore: : opU(vf2;vf2; >> res V_MOV_B32 vDst(VGPR161) src0(VGPR206) V_MOV_B32 vDst(VGPR162) src0(VGPR207) # 235: OpAccessChain: Float*: res[0] # 236: OpLoad: Float: tmp236 << res[0] V_MOV_B32 vDst(VGPR208) src0(VGPR161) # OpReturnValue: : << tmp236 S_MOV_B32 sDst(M0) src0(SGPR70) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR208) S_SETPC_B64 sDst(SGPR68) src0(SGPR68) # Float DE(vf3;(FloatVector3* p) Function: Float DE(vf3;() S_MOV_B64 sDst(SGPR86) src0(EXEC) # lb44 Label: lb44 # OpStore: : const240 >> scale V_MOV_B32 vDst(VGPR229) src0(LITERAL_CONST) const: 0x3eb33333 V_MOV_B32 vDst(VGPR209) src0(VGPR229) # OpStore: : const243 >> res V_MOV_B32 vDst(VGPR230) src0(LITERAL_CONST) const: 0x461c3f9a V_MOV_B32 vDst(VGPR231) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR210) src0(VGPR230) V_MOV_B32 vDst(VGPR211) src0(VGPR231) # OpStore: : const245 >> dist V_MOV_B32 vDst(VGPR232) src0(LITERAL_CONST) const: 0xc479c000 V_MOV_B32 vDst(VGPR212) src0(VGPR232) # 247: OpLoad: FloatVector3: tmp247 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR233) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR234) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR235) src0(VGPR2) # OpStore: : tmp247 >> param246 V_MOV_B32 vDst(VGPR213) src0(VGPR233) V_MOV_B32 vDst(VGPR214) src0(VGPR234) V_MOV_B32 vDst(VGPR215) src0(VGPR235) # 248: OpFunctionCall: Float: diso(vf3;(param246) S_ADD_U32 sDst(SGPR71) src0(LITERAL_CONST) src1(0) const: 0xd5 # VGPR[213:215] S_MOV_B64 sDst(SGPR88) src0(EXEC) S_MOV_B32 sDst(SGPR70) src0(LITERAL_CONST) const: 0xec # VGPR236 # Indirect branch to diso(vf3;: ??? S_GETPC_B64 sDst(SGPR68) src0(SGPR68) S_ADD_U32 sDst(SGPR68) src0(SGPR68) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR69) src0(SGPR69) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR68) src0(SGPR68) S_MOV_B64 sDst(EXEC) src0(SGPR88) # .lbl7 # OpStore: : diso(vf3; >> dist V_MOV_B32 vDst(VGPR212) src0(VGPR236) # OpStore: : const250 >> i V_MOV_B32 vDst(VGPR216) src0(0) # OpBranch: to lb251 # lb251 Label: lb251 # OpLoopMerge: (merge: lb253, continue: lb254) # CF Block: Merge: lb253, Continue: lb254 S_MOV_B64 sDst(SGPR90) src0(EXEC) S_MOV_B64 sDst(SGPR92) src0(EXEC) S_MOV_B64 sDst(SGPR94) src0(EXEC) Label: lb251Loop # OpBranch: to lb255 # lb255 Label: lb255 # 256: OpLoad: Int: tmp256 << i Decorators: RelaxedPrecision # 258: OpSLessThan: Bool: tmp258 << tmp256, const257 V_MOV_B32 vDst(VGPR237) src0(5_INT) V_CMP_LT_I32 dst(SGPR96) src0(VGPR216) src1(VGPR237) // VOP3a # OpBranchConditional: if(tmp258) then branch to lb252, else branch to lb253 # CF Block: Cond Branch: true: lb252, false: lb253 S_AND_B64 sDst(EXEC) src0(SGPR96) src1(EXEC) S_CBRANCH_EXECZ ??? lb253 # lb252 Label: lb252 S_MOV_B64 sDst(SGPR92) src0(EXEC) S_MOV_B64 sDst(SGPR94) src0(EXEC) # 259: OpLoad: Float: tmp259 << dist # 261: OpLoad: FloatVector3: tmp261 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR238) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR239) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR240) src0(VGPR2) # OpStore: : tmp261 >> param260 V_MOV_B32 vDst(VGPR217) src0(VGPR238) V_MOV_B32 vDst(VGPR218) src0(VGPR239) V_MOV_B32 vDst(VGPR219) src0(VGPR240) # 263: OpLoad: Float: tmp263 << scale # OpStore: : tmp263 >> param262 V_MOV_B32 vDst(VGPR220) src0(VGPR209) # 264: OpFunctionCall: Float: sdCrossRepScale(vf3;f1;(param260, param262) S_ADD_U32 sDst(SGPR33) src0(LITERAL_CONST) src1(0) const: 0xd9 # VGPR[217:219] S_ADD_U32 sDst(SGPR34) src0(LITERAL_CONST) src1(0) const: 0xdc # VGPR220 S_MOV_B64 sDst(SGPR98) src0(EXEC) S_MOV_B32 sDst(SGPR32) src0(LITERAL_CONST) const: 0xf1 # VGPR241 # Indirect branch to sdCrossRepScale(vf3;f1;: ??? S_GETPC_B64 sDst(SGPR30) src0(SGPR30) S_ADD_U32 sDst(SGPR30) src0(SGPR30) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR31) src0(SGPR31) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR30) src0(SGPR30) S_MOV_B64 sDst(EXEC) src0(SGPR98) # .lbl8 # 265: OpFNegate: Float: tmp265 << sdCrossRepScale(vf3;f1; V_MUL_F32 vDst(VGPR242) src0(M1_0_F) src1(VGPR241) // VOP2 # 266: OpExtInst(FMax): Float: tmp266 << tmp259, tmp265 V_MAX_F32 vDst(VGPR243) src0(VGPR212) src1(VGPR242) // VOP2 # OpStore: : tmp266 >> dist V_MOV_B32 vDst(VGPR212) src0(VGPR243) # 268: OpLoad: Float: tmp268 << scale # 269: OpFMul: Float: tmp269 << tmp268, const267 V_MOV_B32 vDst(VGPR244) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR245) src0(VGPR209) src1(VGPR244) // VOP2 # OpStore: : tmp269 >> scale V_MOV_B32 vDst(VGPR209) src0(VGPR245) # OpBranch: to lb254 # lb254 Label: lb254 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR92) # 270: OpLoad: Int: tmp270 << i Decorators: RelaxedPrecision # 272: OpIAdd: Int: tmp272 << tmp270, const271 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR246) src0(1_INT) V_ADD_I32 vDst(VGPR247) src0(VGPR216) src1(VGPR246) // VOP2 # OpStore: : tmp272 >> i V_MOV_B32 vDst(VGPR216) src0(VGPR247) # OpBranch: to lb251 S_BRANCH ??? lb251Loop # lb253 Label: lb253 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR90) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR86) # 275: OpLoad: Float: tmp275 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR100) S_WAITCNT 0 # 276: OpExtInst(Floor): Float: tmp276 << tmp275 V_FLOOR_F32 vDst(VGPR248) src0(SGPR100) # 278: OpFMod: Float: tmp278 << tmp276, const277 V_MOV_B32 vDst(VGPR249) src0(LITERAL_CONST) const: 0x40a00000 V_RCP_F32 vDst(VGPR250) src0(VGPR249) V_MUL_F32 vDst(VGPR250) src0(VGPR248) src1(VGPR250) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR250) src0(VGPR250) src1(VGPR249) src2(VGPR248) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR250) src0(VGPR250) V_MAD_F32 vDst(VGPR250) src0(VGPR249) src1(VGPR250) src2(VGPR248) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 280: OpFOrdGreaterThan: Bool: tmp280 << tmp278, const279 V_MOV_B32 vDst(VGPR251) src0(LITERAL_CONST) const: 0x3ecccccd V_CMP_GT_F32 dst(SGPR102) src0(VGPR250) src1(VGPR251) // VOP3a # OpSelectionMerge: (merge: lb282) # CF Block: Merge: lb282 S_MOV_B64 sDst(SGPR104) src0(EXEC) # OpBranchConditional: if(tmp280) then branch to lb281, else branch to lb290 # CF Block: Cond Branch: true: lb281, false: lb290 S_AND_B64 sDst(EXEC) src0(SGPR102) src1(EXEC) S_CBRANCH_EXECZ ??? lb290 # lb281 Label: lb281 # 283: OpLoad: Float: tmp283 << dist # 285: OpCompositeConstruct: FloatVector2: tmp285 << tmp283, const284 V_MOV_B32 vDst(VGPR252) src0(VGPR212) V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x41000000 V_MOV_B32 vDst(VGPR253) src0(VGPR254) # 287: OpLoad: FloatVector2: tmp287 << res # OpStore: : tmp287 >> param286 V_MOV_B32 vDst(VGPR221) src0(VGPR210) V_MOV_B32 vDst(VGPR222) src0(VGPR211) # OpStore: : tmp285 >> param288 V_MOV_B32 vDst(VGPR223) src0(VGPR252) V_MOV_B32 vDst(VGPR224) src0(VGPR253) # 289: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param286, param288) S_ADD_U32 sDst(SGPR59) src0(LITERAL_CONST) src1(0) const: 0xdd # VGPR[221:222] S_ADD_U32 sDst(SGPR60) src0(LITERAL_CONST) src1(0) const: 0xdf # VGPR[223:224] S_MOV_B64 sDst(SGPR106) src0(EXEC) S_MOV_B32 sDst(SGPR58) src0(LITERAL_CONST) const: 0xff # VGPR[255:256] # Indirect branch to opU(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_ADD_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR106) # .lbl9 # OpStore: : opU(vf2;vf2; >> res V_MOV_B32 vDst(VGPR210) src0(VGPR255) V_MOV_B32 vDst(VGPR211) src0(VGPR256) # OpBranch: to lb282 # lb290 Label: lb290 S_ANDN2_B64 sDst(EXEC) src0(SGPR104) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR86) src1(EXEC) S_CBRANCH_EXECZ ??? lb282 # 291: OpLoad: Float: tmp291 << dist # 293: OpCompositeConstruct: FloatVector2: tmp293 << tmp291, const292 V_MOV_B32 vDst(VGPR257) src0(VGPR212) V_MOV_B32 vDst(VGPR259) src0(LITERAL_CONST) const: 0x40e00000 V_MOV_B32 vDst(VGPR258) src0(VGPR259) # 295: OpLoad: FloatVector2: tmp295 << res # OpStore: : tmp295 >> param294 V_MOV_B32 vDst(VGPR225) src0(VGPR210) V_MOV_B32 vDst(VGPR226) src0(VGPR211) # OpStore: : tmp293 >> param296 V_MOV_B32 vDst(VGPR227) src0(VGPR257) V_MOV_B32 vDst(VGPR228) src0(VGPR258) # 297: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param294, param296) S_ADD_U32 sDst(SGPR59) src0(LITERAL_CONST) src1(0) const: 0xe1 # VGPR[225:226] S_ADD_U32 sDst(SGPR60) src0(LITERAL_CONST) src1(0) const: 0xe3 # VGPR[227:228] S_MOV_B64 sDst(SGPR108) src0(EXEC) S_MOV_B32 sDst(SGPR58) src0(LITERAL_CONST) const: 0x104 # VGPR[260:261] # Indirect branch to opU(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_ADD_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR108) # .lbl10 # OpStore: : opU(vf2;vf2; >> res V_MOV_B32 vDst(VGPR210) src0(VGPR260) V_MOV_B32 vDst(VGPR211) src0(VGPR261) # OpBranch: to lb282 # lb282 Label: lb282 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR104) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR86) # 300: OpAccessChain: Float*: res[1] # 301: OpLoad: Float: tmp301 << res[1] V_MOV_B32 vDst(VGPR262) src0(VGPR211) # OpStore: : tmp301 >> NumCol V_MOV_B32 vDst(VGPR263) src0(VGPR262) # 302: OpAccessChain: Float*: res[0] # 303: OpLoad: Float: tmp303 << res[0] V_MOV_B32 vDst(VGPR264) src0(VGPR210) # OpReturnValue: : << tmp303 S_MOV_B32 sDst(M0) src0(SGPR84) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR264) S_SETPC_B64 sDst(SGPR82) src0(SGPR82) # FloatVector2 march(vf3;vf3;(FloatVector3* ro, FloatVector3* rd) Function: FloatVector2 march(vf3;vf3;(, FloatVector3 DE(vf3;.rd) S_MOV_B64 sDst(SGPR116) src0(EXEC) # lb49 Label: lb49 # OpStore: : const174 >> t V_MOV_B32 vDst(VGPR272) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR265) src0(VGPR272) # OpStore: : const308 >> d V_MOV_B32 vDst(VGPR273) src0(LITERAL_CONST) const: 0x41a00000 V_MOV_B32 vDst(VGPR266) src0(VGPR273) # OpStore: : const174 >> it V_MOV_B32 vDst(VGPR274) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR267) src0(VGPR274) # OpStore: : const250 >> i V_MOV_B32 vDst(VGPR268) src0(0) # OpBranch: to lb311 # lb311 Label: lb311 # OpLoopMerge: (merge: lb313, continue: lb314) # CF Block: Merge: lb313, Continue: lb314 S_MOV_B64 sDst(SGPR118) src0(EXEC) S_MOV_B64 sDst(SGPR120) src0(EXEC) S_MOV_B64 sDst(SGPR122) src0(EXEC) Label: lb311Loop # OpBranch: to lb315 # lb315 Label: lb315 # 316: OpLoad: Int: tmp316 << i Decorators: RelaxedPrecision # 318: OpSLessThan: Bool: tmp318 << tmp316, const317 V_MOV_B32 vDst(VGPR275) src0(LITERAL_CONST) const: 0x00000064 V_CMP_LT_I32 dst(SGPR124) src0(VGPR268) src1(VGPR275) // VOP3a # OpBranchConditional: if(tmp318) then branch to lb312, else branch to lb313 # CF Block: Cond Branch: true: lb312, false: lb313 S_AND_B64 sDst(EXEC) src0(SGPR124) src1(EXEC) S_CBRANCH_EXECZ ??? lb313 # lb312 Label: lb312 S_MOV_B64 sDst(SGPR120) src0(EXEC) S_MOV_B64 sDst(SGPR122) src0(EXEC) # 319: OpLoad: FloatVector3: tmp319 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR113) const: 0x0 V_MOVRELS_B32 vDst(VGPR276) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR277) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR278) src0(VGPR2) # 320: OpLoad: Float: tmp320 << t # 321: OpLoad: FloatVector3: tmp321 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR114) const: 0x0 V_MOVRELS_B32 vDst(VGPR279) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR280) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR281) src0(VGPR2) # 322: OpVectorTimesScalar: FloatVector3: tmp322 << tmp321, tmp320 V_MUL_F32 vDst(VGPR282) src0(VGPR265) src1(VGPR279) // VOP2 V_MUL_F32 vDst(VGPR283) src0(VGPR265) src1(VGPR280) // VOP2 V_MUL_F32 vDst(VGPR284) src0(VGPR265) src1(VGPR281) // VOP2 # 323: OpFAdd: FloatVector3: tmp323 << tmp319, tmp322 V_ADD_F32 vDst(VGPR285) src0(VGPR276) src1(VGPR282) // VOP2 V_ADD_F32 vDst(VGPR286) src0(VGPR277) src1(VGPR283) // VOP2 V_ADD_F32 vDst(VGPR287) src0(VGPR278) src1(VGPR284) // VOP2 # OpStore: : tmp323 >> param324 V_MOV_B32 vDst(VGPR269) src0(VGPR285) V_MOV_B32 vDst(VGPR270) src0(VGPR286) V_MOV_B32 vDst(VGPR271) src0(VGPR287) # 325: OpFunctionCall: Float: DE(vf3;(param324) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x10d # VGPR[269:271] S_MOV_B64 sDst(SGPR126) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x120 # VGPR288 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR126) # .lbl11 # OpStore: : DE(vf3; >> d V_MOV_B32 vDst(VGPR266) src0(VGPR288) # 326: OpLoad: Float: tmp326 << t # 327: OpFAdd: Float: tmp327 << tmp326, DE(vf3; V_ADD_F32 vDst(VGPR289) src0(VGPR265) src1(VGPR288) // VOP2 # OpStore: : tmp327 >> t V_MOV_B32 vDst(VGPR265) src0(VGPR289) # 328: OpLoad: Float: tmp328 << d # 330: OpFOrdLessThan: Bool: tmp330 << tmp328, const329 V_MOV_B32 vDst(VGPR290) src0(LITERAL_CONST) const: 0x3a83126f V_CMP_LT_F32 dst(SGPR128) src0(VGPR266) src1(VGPR290) // VOP3a # 331: OpLoad: Float: tmp331 << t # 332: OpFOrdGreaterThan: Bool: tmp332 << tmp331, const308 V_MOV_B32 vDst(VGPR291) src0(LITERAL_CONST) const: 0x41a00000 V_CMP_GT_F32 dst(SGPR130) src0(VGPR265) src1(VGPR291) // VOP3a # 333: OpLogicalOr: Bool: tmp333 << tmp330, tmp332 S_OR_B64 sDst(SGPR132) src0(SGPR128) src1(SGPR130) # OpSelectionMerge: (merge: lb335) # CF Block: Merge: lb335 S_MOV_B64 sDst(SGPR134) src0(EXEC) # OpBranchConditional: if(tmp333) then branch to lb334, else branch to lb335 # CF Block: Cond Branch: true: lb334, false: lb335 S_AND_B64 sDst(EXEC) src0(SGPR132) src1(EXEC) S_CBRANCH_EXECZ ??? lb335 # lb334 Label: lb334 # OpBranch: to lb313 S_ANDN2_B64 sDst(SGPR120) src0(SGPR120) src1(EXEC) S_ANDN2_B64 sDst(SGPR122) src0(SGPR122) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR122) src1(EXEC) # lb335 Label: lb335 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR134) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR122) # 337: OpLoad: Float: tmp337 << it # 338: OpFAdd: Float: tmp338 << tmp337, const88 V_MOV_B32 vDst(VGPR292) src0(1_0_F) V_ADD_F32 vDst(VGPR293) src0(VGPR267) src1(VGPR292) // VOP2 # OpStore: : tmp338 >> it V_MOV_B32 vDst(VGPR267) src0(VGPR293) # OpBranch: to lb314 # lb314 Label: lb314 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR120) # 339: OpLoad: Int: tmp339 << i Decorators: RelaxedPrecision # 340: OpIAdd: Int: tmp340 << tmp339, const271 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR294) src0(1_INT) V_ADD_I32 vDst(VGPR295) src0(VGPR268) src1(VGPR294) // VOP2 # OpStore: : tmp340 >> i V_MOV_B32 vDst(VGPR268) src0(VGPR295) # OpBranch: to lb311 S_BRANCH ??? lb311Loop # lb313 Label: lb313 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR118) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR116) # 341: OpLoad: Float: tmp341 << t # 342: OpLoad: Float: tmp342 << it # 344: OpFDiv: Float: tmp344 << tmp342, const343 V_MOV_B32 vDst(VGPR296) src0(LITERAL_CONST) const: 0x42c80000 V_RCP_F32 vDst(VGPR297) src0(VGPR296) V_MUL_F32 vDst(VGPR297) src0(VGPR267) src1(VGPR297) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR297) src0(VGPR297) src1(VGPR296) src2(VGPR267) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 345: OpCompositeConstruct: FloatVector2: tmp345 << tmp341, tmp344 V_MOV_B32 vDst(VGPR298) src0(VGPR265) V_MOV_B32 vDst(VGPR299) src0(VGPR297) # OpReturnValue: : << tmp345 S_MOV_B32 sDst(M0) src0(SGPR112) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR298) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR299) S_SETPC_B64 sDst(SGPR110) src0(SGPR110) # Float getShadow(vf3;vf3;vf3;(FloatVector3* p, FloatVector3* n, FloatVector3* ld) Function: Float getShadow(vf3;vf3;vf3;(, FloatVector3 march(vf3;vf3;.n, FloatVector3 march(vf3;vf3;.ld) S_MOV_B64 sDst(SGPR142) src0(EXEC) # lb55 Label: lb55 # 349: OpLoad: FloatVector3: tmp349 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR140) const: 0x0 V_MOVRELS_B32 vDst(VGPR306) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR307) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR308) src0(VGPR2) # 350: OpVectorTimesScalar: FloatVector3: tmp350 << tmp349, const348 V_MOV_B32 vDst(VGPR312) src0(LITERAL_CONST) const: 0x3b03126f V_MUL_F32 vDst(VGPR309) src0(VGPR312) src1(VGPR306) // VOP2 V_MUL_F32 vDst(VGPR310) src0(VGPR312) src1(VGPR307) // VOP2 V_MUL_F32 vDst(VGPR311) src0(VGPR312) src1(VGPR308) // VOP2 # 351: OpLoad: FloatVector3: tmp351 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR139) const: 0x0 V_MOVRELS_B32 vDst(VGPR313) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR314) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR315) src0(VGPR2) # 352: OpFAdd: FloatVector3: tmp352 << tmp351, tmp350 V_ADD_F32 vDst(VGPR316) src0(VGPR313) src1(VGPR309) // VOP2 V_ADD_F32 vDst(VGPR317) src0(VGPR314) src1(VGPR310) // VOP2 V_ADD_F32 vDst(VGPR318) src0(VGPR315) src1(VGPR311) // VOP2 # OpStore: : tmp352 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR139) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR316) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR317) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR318) # OpStore: : const174 >> t V_MOV_B32 vDst(VGPR319) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR300) src0(VGPR319) # OpStore: : const308 >> d V_MOV_B32 vDst(VGPR320) src0(LITERAL_CONST) const: 0x41a00000 V_MOV_B32 vDst(VGPR301) src0(VGPR320) # OpStore: : const250 >> i V_MOV_B32 vDst(VGPR302) src0(0) # OpBranch: to lb356 # lb356 Label: lb356 # OpLoopMerge: (merge: lb358, continue: lb359) # CF Block: Merge: lb358, Continue: lb359 S_MOV_B64 sDst(SGPR144) src0(EXEC) S_MOV_B64 sDst(SGPR146) src0(EXEC) S_MOV_B64 sDst(SGPR148) src0(EXEC) Label: lb356Loop # OpBranch: to lb360 # lb360 Label: lb360 # 361: OpLoad: Int: tmp361 << i Decorators: RelaxedPrecision # 363: OpSLessThan: Bool: tmp363 << tmp361, const362 V_MOV_B32 vDst(VGPR321) src0(50_INT) V_CMP_LT_I32 dst(SGPR150) src0(VGPR302) src1(VGPR321) // VOP3a # OpBranchConditional: if(tmp363) then branch to lb357, else branch to lb358 # CF Block: Cond Branch: true: lb357, false: lb358 S_AND_B64 sDst(EXEC) src0(SGPR150) src1(EXEC) S_CBRANCH_EXECZ ??? lb358 # lb357 Label: lb357 S_MOV_B64 sDst(SGPR146) src0(EXEC) S_MOV_B64 sDst(SGPR148) src0(EXEC) # 364: OpLoad: FloatVector3: tmp364 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR139) const: 0x0 V_MOVRELS_B32 vDst(VGPR322) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR323) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR324) src0(VGPR2) # 365: OpLoad: Float: tmp365 << t # 366: OpLoad: FloatVector3: tmp366 << ld S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR141) const: 0x0 V_MOVRELS_B32 vDst(VGPR325) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR326) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR327) src0(VGPR2) # 367: OpVectorTimesScalar: FloatVector3: tmp367 << tmp366, tmp365 V_MUL_F32 vDst(VGPR328) src0(VGPR300) src1(VGPR325) // VOP2 V_MUL_F32 vDst(VGPR329) src0(VGPR300) src1(VGPR326) // VOP2 V_MUL_F32 vDst(VGPR330) src0(VGPR300) src1(VGPR327) // VOP2 # 368: OpFAdd: FloatVector3: tmp368 << tmp364, tmp367 V_ADD_F32 vDst(VGPR331) src0(VGPR322) src1(VGPR328) // VOP2 V_ADD_F32 vDst(VGPR332) src0(VGPR323) src1(VGPR329) // VOP2 V_ADD_F32 vDst(VGPR333) src0(VGPR324) src1(VGPR330) // VOP2 # OpStore: : tmp368 >> param369 V_MOV_B32 vDst(VGPR303) src0(VGPR331) V_MOV_B32 vDst(VGPR304) src0(VGPR332) V_MOV_B32 vDst(VGPR305) src0(VGPR333) # 370: OpFunctionCall: Float: DE(vf3;(param369) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x12f # VGPR[303:305] S_MOV_B64 sDst(SGPR152) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x14e # VGPR334 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR152) # .lbl12 # OpStore: : DE(vf3; >> d V_MOV_B32 vDst(VGPR301) src0(VGPR334) # 371: OpLoad: Float: tmp371 << t # 372: OpFAdd: Float: tmp372 << tmp371, DE(vf3; V_ADD_F32 vDst(VGPR335) src0(VGPR300) src1(VGPR334) // VOP2 # OpStore: : tmp372 >> t V_MOV_B32 vDst(VGPR300) src0(VGPR335) # 373: OpLoad: Float: tmp373 << d # 374: OpFOrdLessThan: Bool: tmp374 << tmp373, const329 V_MOV_B32 vDst(VGPR336) src0(LITERAL_CONST) const: 0x3a83126f V_CMP_LT_F32 dst(SGPR154) src0(VGPR301) src1(VGPR336) // VOP3a # 375: OpLoad: Float: tmp375 << t # 376: OpFOrdGreaterThan: Bool: tmp376 << tmp375, const267 V_MOV_B32 vDst(VGPR337) src0(LITERAL_CONST) const: 0x40400000 V_CMP_GT_F32 dst(SGPR156) src0(VGPR300) src1(VGPR337) // VOP3a # 377: OpLogicalOr: Bool: tmp377 << tmp374, tmp376 S_OR_B64 sDst(SGPR158) src0(SGPR154) src1(SGPR156) # OpSelectionMerge: (merge: lb379) # CF Block: Merge: lb379 S_MOV_B64 sDst(SGPR160) src0(EXEC) # OpBranchConditional: if(tmp377) then branch to lb378, else branch to lb379 # CF Block: Cond Branch: true: lb378, false: lb379 S_AND_B64 sDst(EXEC) src0(SGPR158) src1(EXEC) S_CBRANCH_EXECZ ??? lb379 # lb378 Label: lb378 # OpBranch: to lb358 S_ANDN2_B64 sDst(SGPR146) src0(SGPR146) src1(EXEC) S_ANDN2_B64 sDst(SGPR148) src0(SGPR148) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR148) src1(EXEC) # lb379 Label: lb379 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR160) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR148) # OpBranch: to lb359 # lb359 Label: lb359 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR146) # 381: OpLoad: Int: tmp381 << i Decorators: RelaxedPrecision # 382: OpIAdd: Int: tmp382 << tmp381, const271 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR338) src0(1_INT) V_ADD_I32 vDst(VGPR339) src0(VGPR302) src1(VGPR338) // VOP2 # OpStore: : tmp382 >> i V_MOV_B32 vDst(VGPR302) src0(VGPR339) # OpBranch: to lb356 S_BRANCH ??? lb356Loop # lb358 Label: lb358 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR144) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR142) # 383: OpLoad: Float: tmp383 << t # 384: OpFOrdLessThanEqual: Bool: tmp384 << tmp383, const267 V_MOV_B32 vDst(VGPR340) src0(LITERAL_CONST) const: 0x40400000 V_CMP_LE_F32 dst(SGPR162) src0(VGPR300) src1(VGPR340) // VOP3a # 386: OpSelect: Float: tmp386 << tmp384, const385, const88 # CF Block: Merge: .lbl14 S_MOV_B64 sDst(SGPR164) src0(EXEC) # CF Block: Cond Branch: true: .lbl15, false: .lbl13 S_AND_B64 sDst(EXEC) src0(SGPR162) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl13 Label: .lbl15 V_MOV_B32 vDst(VGPR342) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR341) src0(VGPR342) Label: .lbl13 S_ANDN2_B64 sDst(EXEC) src0(SGPR164) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR142) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl14 V_MOV_B32 vDst(VGPR341) src0(1_0_F) Label: .lbl14 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR164) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR142) # OpReturnValue: : << tmp386 S_MOV_B32 sDst(M0) src0(SGPR138) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR341) S_SETPC_B64 sDst(SGPR136) src0(SGPR136) # FloatVector3 getNorm(vf3;(FloatVector3* p) Function: FloatVector3 getNorm(vf3;() S_MOV_B64 sDst(SGPR170) src0(EXEC) # lb59 Label: lb59 # 391: OpLoad: FloatVector3: tmp391 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR361) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR362) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR363) src0(VGPR2) # 393: OpVectorShuffle: FloatVector3: tmp393 << const390, const390, 0, 1, 1 V_MOV_B32 vDst(VGPR364) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR365) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR366) src0(VGPR364) V_MOV_B32 vDst(VGPR367) src0(VGPR365) V_MOV_B32 vDst(VGPR368) src0(VGPR365) # 394: OpFAdd: FloatVector3: tmp394 << tmp391, tmp393 V_ADD_F32 vDst(VGPR369) src0(VGPR361) src1(VGPR366) // VOP2 V_ADD_F32 vDst(VGPR370) src0(VGPR362) src1(VGPR367) // VOP2 V_ADD_F32 vDst(VGPR371) src0(VGPR363) src1(VGPR368) // VOP2 # OpStore: : tmp394 >> param395 V_MOV_B32 vDst(VGPR343) src0(VGPR369) V_MOV_B32 vDst(VGPR344) src0(VGPR370) V_MOV_B32 vDst(VGPR345) src0(VGPR371) # 396: OpFunctionCall: Float: DE(vf3;(param395) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x157 # VGPR[343:345] S_MOV_B64 sDst(SGPR172) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x174 # VGPR372 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR172) # .lbl16 # 397: OpLoad: FloatVector3: tmp397 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR373) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR374) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR375) src0(VGPR2) # 399: OpVectorShuffle: FloatVector3: tmp399 << const390, const390, 0, 1, 1 V_MOV_B32 vDst(VGPR376) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR377) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR378) src0(VGPR376) V_MOV_B32 vDst(VGPR379) src0(VGPR377) V_MOV_B32 vDst(VGPR380) src0(VGPR377) # 400: OpFSub: FloatVector3: tmp400 << tmp397, tmp399 V_SUB_F32 vDst(VGPR381) src0(VGPR373) src1(VGPR378) // VOP2 V_SUB_F32 vDst(VGPR382) src0(VGPR374) src1(VGPR379) // VOP2 V_SUB_F32 vDst(VGPR383) src0(VGPR375) src1(VGPR380) // VOP2 # OpStore: : tmp400 >> param401 V_MOV_B32 vDst(VGPR346) src0(VGPR381) V_MOV_B32 vDst(VGPR347) src0(VGPR382) V_MOV_B32 vDst(VGPR348) src0(VGPR383) # 402: OpFunctionCall: Float: DE(vf3;(param401) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x15a # VGPR[346:348] S_MOV_B64 sDst(SGPR174) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x180 # VGPR384 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR174) # .lbl17 # 403: OpFSub: Float: tmp403 << DE(vf3;, DE(vf3; V_SUB_F32 vDst(VGPR385) src0(VGPR372) src1(VGPR384) // VOP2 # 404: OpLoad: FloatVector3: tmp404 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR386) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR387) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR388) src0(VGPR2) # 406: OpVectorShuffle: FloatVector3: tmp406 << const390, const390, 1, 0, 1 V_MOV_B32 vDst(VGPR389) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR390) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR391) src0(VGPR390) V_MOV_B32 vDst(VGPR392) src0(VGPR389) V_MOV_B32 vDst(VGPR393) src0(VGPR390) # 407: OpFAdd: FloatVector3: tmp407 << tmp404, tmp406 V_ADD_F32 vDst(VGPR394) src0(VGPR386) src1(VGPR391) // VOP2 V_ADD_F32 vDst(VGPR395) src0(VGPR387) src1(VGPR392) // VOP2 V_ADD_F32 vDst(VGPR396) src0(VGPR388) src1(VGPR393) // VOP2 # OpStore: : tmp407 >> param408 V_MOV_B32 vDst(VGPR349) src0(VGPR394) V_MOV_B32 vDst(VGPR350) src0(VGPR395) V_MOV_B32 vDst(VGPR351) src0(VGPR396) # 409: OpFunctionCall: Float: DE(vf3;(param408) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x15d # VGPR[349:351] S_MOV_B64 sDst(SGPR176) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x18d # VGPR397 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR176) # .lbl18 # 410: OpLoad: FloatVector3: tmp410 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR398) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR399) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR400) src0(VGPR2) # 412: OpVectorShuffle: FloatVector3: tmp412 << const390, const390, 1, 0, 1 V_MOV_B32 vDst(VGPR401) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR402) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR403) src0(VGPR402) V_MOV_B32 vDst(VGPR404) src0(VGPR401) V_MOV_B32 vDst(VGPR405) src0(VGPR402) # 413: OpFSub: FloatVector3: tmp413 << tmp410, tmp412 V_SUB_F32 vDst(VGPR406) src0(VGPR398) src1(VGPR403) // VOP2 V_SUB_F32 vDst(VGPR407) src0(VGPR399) src1(VGPR404) // VOP2 V_SUB_F32 vDst(VGPR408) src0(VGPR400) src1(VGPR405) // VOP2 # OpStore: : tmp413 >> param414 V_MOV_B32 vDst(VGPR352) src0(VGPR406) V_MOV_B32 vDst(VGPR353) src0(VGPR407) V_MOV_B32 vDst(VGPR354) src0(VGPR408) # 415: OpFunctionCall: Float: DE(vf3;(param414) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x160 # VGPR[352:354] S_MOV_B64 sDst(SGPR178) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x199 # VGPR409 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR178) # .lbl19 # 416: OpFSub: Float: tmp416 << DE(vf3;, DE(vf3; V_SUB_F32 vDst(VGPR410) src0(VGPR397) src1(VGPR409) // VOP2 # 417: OpLoad: FloatVector3: tmp417 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR411) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR412) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR413) src0(VGPR2) # 419: OpVectorShuffle: FloatVector3: tmp419 << const390, const390, 1, 1, 0 V_MOV_B32 vDst(VGPR414) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR415) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR416) src0(VGPR415) V_MOV_B32 vDst(VGPR417) src0(VGPR415) V_MOV_B32 vDst(VGPR418) src0(VGPR414) # 420: OpFAdd: FloatVector3: tmp420 << tmp417, tmp419 V_ADD_F32 vDst(VGPR419) src0(VGPR411) src1(VGPR416) // VOP2 V_ADD_F32 vDst(VGPR420) src0(VGPR412) src1(VGPR417) // VOP2 V_ADD_F32 vDst(VGPR421) src0(VGPR413) src1(VGPR418) // VOP2 # OpStore: : tmp420 >> param421 V_MOV_B32 vDst(VGPR355) src0(VGPR419) V_MOV_B32 vDst(VGPR356) src0(VGPR420) V_MOV_B32 vDst(VGPR357) src0(VGPR421) # 422: OpFunctionCall: Float: DE(vf3;(param421) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x163 # VGPR[355:357] S_MOV_B64 sDst(SGPR180) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x1a6 # VGPR422 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR180) # .lbl20 # 423: OpLoad: FloatVector3: tmp423 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR423) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR424) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR425) src0(VGPR2) # 425: OpVectorShuffle: FloatVector3: tmp425 << const390, const390, 1, 1, 0 V_MOV_B32 vDst(VGPR426) src0(LITERAL_CONST) const: 0x3a83126f V_MOV_B32 vDst(VGPR427) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR428) src0(VGPR427) V_MOV_B32 vDst(VGPR429) src0(VGPR427) V_MOV_B32 vDst(VGPR430) src0(VGPR426) # 426: OpFSub: FloatVector3: tmp426 << tmp423, tmp425 V_SUB_F32 vDst(VGPR431) src0(VGPR423) src1(VGPR428) // VOP2 V_SUB_F32 vDst(VGPR432) src0(VGPR424) src1(VGPR429) // VOP2 V_SUB_F32 vDst(VGPR433) src0(VGPR425) src1(VGPR430) // VOP2 # OpStore: : tmp426 >> param427 V_MOV_B32 vDst(VGPR358) src0(VGPR431) V_MOV_B32 vDst(VGPR359) src0(VGPR432) V_MOV_B32 vDst(VGPR360) src0(VGPR433) # 428: OpFunctionCall: Float: DE(vf3;(param427) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x166 # VGPR[358:360] S_MOV_B64 sDst(SGPR182) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x1b2 # VGPR434 # Indirect branch to DE(vf3;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR182) # .lbl21 # 429: OpFSub: Float: tmp429 << DE(vf3;, DE(vf3; V_SUB_F32 vDst(VGPR435) src0(VGPR422) src1(VGPR434) // VOP2 # 430: OpCompositeConstruct: FloatVector3: tmp430 << tmp403, tmp416, tmp429 V_MOV_B32 vDst(VGPR436) src0(VGPR385) V_MOV_B32 vDst(VGPR437) src0(VGPR410) V_MOV_B32 vDst(VGPR438) src0(VGPR435) # 431: OpExtInst(Normalize): FloatVector3: tmp431 << tmp430 V_MUL_F32 vDst(VGPR439) src0(VGPR436) src1(VGPR436) // VOP2 V_MAC_F32 vDst(VGPR439) src0(VGPR437) src1(VGPR437) // VOP2 V_MAC_F32 vDst(VGPR439) src0(VGPR438) src1(VGPR438) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR439) src0(VGPR439) V_MUL_F32 vDst(VGPR440) src0(VGPR436) src1(VGPR439) // VOP2 V_MUL_F32 vDst(VGPR441) src0(VGPR437) src1(VGPR439) // VOP2 V_MUL_F32 vDst(VGPR442) src0(VGPR438) src1(VGPR439) // VOP2 # OpReturnValue: : << tmp431 S_MOV_B32 sDst(M0) src0(SGPR168) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR440) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR441) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR442) S_SETPC_B64 sDst(SGPR166) src0(SGPR166) # FloatVector3 light(vf3;vf3;(FloatVector3* p, FloatVector3* n) Function: FloatVector3 light(vf3;vf3;(, FloatVector3 getNorm(vf3;.n) S_MOV_B64 sDst(SGPR190) src0(EXEC) # lb64 Label: lb64 # OpStore: : const436 >> col V_MOV_B32 vDst(VGPR457) src0(LITERAL_CONST) const: 0x3c23d70a V_MOV_B32 vDst(VGPR458) src0(LITERAL_CONST) const: 0x3c23d70a V_MOV_B32 vDst(VGPR459) src0(LITERAL_CONST) const: 0x3c23d70a V_MOV_B32 vDst(VGPR443) src0(VGPR457) V_MOV_B32 vDst(VGPR444) src0(VGPR458) V_MOV_B32 vDst(VGPR445) src0(VGPR459) # OpStore: : const250 >> i V_MOV_B32 vDst(VGPR446) src0(0) # OpBranch: to lb438 # lb438 Label: lb438 # OpLoopMerge: (merge: lb440, continue: lb441) # CF Block: Merge: lb440, Continue: lb441 S_MOV_B64 sDst(SGPR192) src0(EXEC) S_MOV_B64 sDst(SGPR194) src0(EXEC) S_MOV_B64 sDst(SGPR196) src0(EXEC) Label: lb438Loop # OpBranch: to lb442 # lb442 Label: lb442 # 443: OpLoad: Int: tmp443 << i Decorators: RelaxedPrecision # 445: OpSLessThan: Bool: tmp445 << tmp443, const444 V_MOV_B32 vDst(VGPR460) src0(2_INT) V_CMP_LT_I32 dst(SGPR198) src0(VGPR446) src1(VGPR460) // VOP3a # OpBranchConditional: if(tmp445) then branch to lb439, else branch to lb440 # CF Block: Cond Branch: true: lb439, false: lb440 S_AND_B64 sDst(EXEC) src0(SGPR198) src1(EXEC) S_CBRANCH_EXECZ ??? lb440 # lb439 Label: lb439 S_MOV_B64 sDst(SGPR194) src0(EXEC) S_MOV_B64 sDst(SGPR196) src0(EXEC) # 447: OpLoad: Int: tmp447 << i Decorators: RelaxedPrecision # 448: OpIEqual: Bool: tmp448 << tmp447, const250 V_MOV_B32 vDst(VGPR461) src0(0) V_CMP_EQ_I32 dst(SGPR200) src0(VGPR446) src1(VGPR461) // VOP3a # 449: OpLoad: FloatVector3: tmp449 << lDir0 # 450: OpLoad: FloatVector3: tmp450 << lDir1 # 452: OpCompositeConstruct: BoolVector3: tmp452 << tmp448, tmp448, tmp448 S_MOV_B64 sDst(SGPR202) src0(SGPR200) S_MOV_B64 sDst(SGPR204) src0(SGPR200) S_MOV_B64 sDst(SGPR206) src0(SGPR200) # 453: OpSelect: FloatVector3: tmp453 << tmp452, tmp449, tmp450 S_OR_B64 sDst(SGPR208) src0(SGPR202) src1(SGPR204) S_OR_B64 sDst(SGPR208) src0(SGPR206) src1(SGPR208) # CF Block: Merge: .lbl23 S_MOV_B64 sDst(SGPR210) src0(EXEC) # CF Block: Cond Branch: true: .lbl24, false: .lbl22 S_AND_B64 sDst(EXEC) src0(SGPR208) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl22 Label: .lbl24 V_MOV_B32 vDst(VGPR462) src0(VGPR24) V_MOV_B32 vDst(VGPR463) src0(VGPR25) V_MOV_B32 vDst(VGPR464) src0(VGPR26) Label: .lbl22 S_ANDN2_B64 sDst(EXEC) src0(SGPR210) src1(EXEC) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) S_CBRANCH_EXECZ ??? .lbl23 V_MOV_B32 vDst(VGPR462) src0(VGPR30) V_MOV_B32 vDst(VGPR463) src0(VGPR31) V_MOV_B32 vDst(VGPR464) src0(VGPR32) Label: .lbl23 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR210) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) # 455: OpLoad: FloatVector3: tmp455 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR188) const: 0x0 V_MOVRELS_B32 vDst(VGPR465) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR466) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR467) src0(VGPR2) # 457: OpDot: Float: tmp457 << tmp455, tmp453 V_MUL_F32 vDst(VGPR468) src0(VGPR465) src1(VGPR462) // VOP2 V_MAC_F32 vDst(VGPR468) src0(VGPR466) src1(VGPR463) // VOP2 V_MAC_F32 vDst(VGPR468) src0(VGPR467) src1(VGPR464) // VOP2 # 458: OpExtInst(FMax): Float: tmp458 << tmp457, const174 V_MOV_B32 vDst(VGPR469) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR470) src0(VGPR468) src1(VGPR469) // VOP2 # OpStore: : tmp458 >> diff V_MOV_B32 vDst(VGPR447) src0(VGPR470) # 460: OpLoad: FloatVector3: tmp460 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR187) const: 0x0 V_MOVRELS_B32 vDst(VGPR471) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR472) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR473) src0(VGPR2) # OpStore: : tmp460 >> param459 V_MOV_B32 vDst(VGPR448) src0(VGPR471) V_MOV_B32 vDst(VGPR449) src0(VGPR472) V_MOV_B32 vDst(VGPR450) src0(VGPR473) # 462: OpLoad: FloatVector3: tmp462 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR188) const: 0x0 V_MOVRELS_B32 vDst(VGPR474) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR475) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR476) src0(VGPR2) # OpStore: : tmp462 >> param461 V_MOV_B32 vDst(VGPR451) src0(VGPR474) V_MOV_B32 vDst(VGPR452) src0(VGPR475) V_MOV_B32 vDst(VGPR453) src0(VGPR476) # OpStore: : tmp453 >> param463 V_MOV_B32 vDst(VGPR454) src0(VGPR462) V_MOV_B32 vDst(VGPR455) src0(VGPR463) V_MOV_B32 vDst(VGPR456) src0(VGPR464) # 465: OpFunctionCall: Float: getShadow(vf3;vf3;vf3;(param459, param461, param463) S_ADD_U32 sDst(SGPR139) src0(LITERAL_CONST) src1(0) const: 0x1c0 # VGPR[448:450] S_ADD_U32 sDst(SGPR140) src0(LITERAL_CONST) src1(0) const: 0x1c3 # VGPR[451:453] S_ADD_U32 sDst(SGPR141) src0(LITERAL_CONST) src1(0) const: 0x1c6 # VGPR[454:456] S_MOV_B64 sDst(SGPR212) src0(EXEC) S_MOV_B32 sDst(SGPR138) src0(LITERAL_CONST) const: 0x1dd # VGPR477 # Indirect branch to getShadow(vf3;vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR136) src0(SGPR136) S_ADD_U32 sDst(SGPR136) src0(SGPR136) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR137) src0(SGPR137) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR136) src0(SGPR136) S_MOV_B64 sDst(EXEC) src0(SGPR212) # .lbl25 # 466: OpLoad: Float: tmp466 << diff # 467: OpFMul: Float: tmp467 << tmp466, getShadow(vf3;vf3;vf3; V_MUL_F32 vDst(VGPR478) src0(VGPR447) src1(VGPR477) // VOP2 # OpStore: : tmp467 >> diff V_MOV_B32 vDst(VGPR447) src0(VGPR478) # 468: OpLoad: Float: tmp468 << diff # 469: OpLoad: Int: tmp469 << i Decorators: RelaxedPrecision # 470: OpIEqual: Bool: tmp470 << tmp469, const250 V_MOV_B32 vDst(VGPR479) src0(0) V_CMP_EQ_I32 dst(SGPR214) src0(VGPR446) src1(VGPR479) // VOP3a # 471: OpLoad: FloatVector3: tmp471 << lCol0 # 472: OpLoad: FloatVector3: tmp472 << lCol1 # 473: OpCompositeConstruct: BoolVector3: tmp473 << tmp470, tmp470, tmp470 S_MOV_B64 sDst(SGPR216) src0(SGPR214) S_MOV_B64 sDst(SGPR218) src0(SGPR214) S_MOV_B64 sDst(SGPR220) src0(SGPR214) # 474: OpSelect: FloatVector3: tmp474 << tmp473, tmp471, tmp472 S_OR_B64 sDst(SGPR222) src0(SGPR216) src1(SGPR218) S_OR_B64 sDst(SGPR222) src0(SGPR220) src1(SGPR222) # CF Block: Merge: .lbl27 S_MOV_B64 sDst(SGPR224) src0(EXEC) # CF Block: Cond Branch: true: .lbl28, false: .lbl26 S_AND_B64 sDst(EXEC) src0(SGPR222) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl26 Label: .lbl28 V_MOV_B32 vDst(VGPR480) src0(VGPR36) V_MOV_B32 vDst(VGPR481) src0(VGPR37) V_MOV_B32 vDst(VGPR482) src0(VGPR38) Label: .lbl26 S_ANDN2_B64 sDst(EXEC) src0(SGPR224) src1(EXEC) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) S_CBRANCH_EXECZ ??? .lbl27 V_MOV_B32 vDst(VGPR480) src0(VGPR42) V_MOV_B32 vDst(VGPR481) src0(VGPR43) V_MOV_B32 vDst(VGPR482) src0(VGPR44) Label: .lbl27 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR224) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR196) # 475: OpVectorTimesScalar: FloatVector3: tmp475 << tmp474, tmp468 V_MUL_F32 vDst(VGPR483) src0(VGPR447) src1(VGPR480) // VOP2 V_MUL_F32 vDst(VGPR484) src0(VGPR447) src1(VGPR481) // VOP2 V_MUL_F32 vDst(VGPR485) src0(VGPR447) src1(VGPR482) // VOP2 # 476: OpLoad: FloatVector3: tmp476 << col # 477: OpFAdd: FloatVector3: tmp477 << tmp476, tmp475 V_ADD_F32 vDst(VGPR486) src0(VGPR443) src1(VGPR483) // VOP2 V_ADD_F32 vDst(VGPR487) src0(VGPR444) src1(VGPR484) // VOP2 V_ADD_F32 vDst(VGPR488) src0(VGPR445) src1(VGPR485) // VOP2 # OpStore: : tmp477 >> col V_MOV_B32 vDst(VGPR443) src0(VGPR486) V_MOV_B32 vDst(VGPR444) src0(VGPR487) V_MOV_B32 vDst(VGPR445) src0(VGPR488) # OpBranch: to lb441 # lb441 Label: lb441 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR194) # 478: OpLoad: Int: tmp478 << i Decorators: RelaxedPrecision # 479: OpIAdd: Int: tmp479 << tmp478, const271 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR489) src0(1_INT) V_ADD_I32 vDst(VGPR490) src0(VGPR446) src1(VGPR489) // VOP2 # OpStore: : tmp479 >> i V_MOV_B32 vDst(VGPR446) src0(VGPR490) # OpBranch: to lb438 S_BRANCH ??? lb438Loop # lb440 Label: lb440 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR192) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR190) # 480: OpLoad: FloatVector3: tmp480 << col # 482: OpVectorTimesScalar: FloatVector3: tmp482 << tmp480, const481 V_MOV_B32 vDst(VGPR494) src0(LITERAL_CONST) const: 0x3f333333 V_MUL_F32 vDst(VGPR491) src0(VGPR494) src1(VGPR443) // VOP2 V_MUL_F32 vDst(VGPR492) src0(VGPR494) src1(VGPR444) // VOP2 V_MUL_F32 vDst(VGPR493) src0(VGPR494) src1(VGPR445) // VOP2 # OpReturnValue: : << tmp482 S_MOV_B32 sDst(M0) src0(SGPR186) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR491) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR492) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR493) S_SETPC_B64 sDst(SGPR184) src0(SGPR184) # FloatVector3 getSphereColor(i1;(Int* i) Function: FloatVector3 getSphereColor(i1;() S_MOV_B64 sDst(SGPR230) src0(EXEC) # lb70 Label: lb70 # 485: OpLoad: Int: tmp485 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR495) src0(VGPR0) # 486: OpIEqual: Bool: tmp486 << tmp485, const250 V_MOV_B32 vDst(VGPR496) src0(0) V_CMP_EQ_I32 dst(SGPR232) src0(VGPR495) src1(VGPR496) // VOP3a # OpSelectionMerge: (merge: lb488) # CF Block: Merge: lb488 S_MOV_B64 sDst(SGPR234) src0(EXEC) # OpBranchConditional: if(tmp486) then branch to lb487, else branch to lb488 # CF Block: Cond Branch: true: lb487, false: lb488 S_AND_B64 sDst(EXEC) src0(SGPR232) src1(EXEC) S_CBRANCH_EXECZ ??? lb488 # lb487 Label: lb487 # OpReturnValue: : << const489 V_MOV_B32 vDst(VGPR497) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR498) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR499) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR497) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR498) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR499) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb488 Label: lb488 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR234) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 491: OpLoad: Int: tmp491 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR500) src0(VGPR0) # 492: OpIEqual: Bool: tmp492 << tmp491, const271 V_MOV_B32 vDst(VGPR501) src0(1_INT) V_CMP_EQ_I32 dst(SGPR236) src0(VGPR500) src1(VGPR501) // VOP3a # OpSelectionMerge: (merge: lb494) # CF Block: Merge: lb494 S_MOV_B64 sDst(SGPR238) src0(EXEC) # OpBranchConditional: if(tmp492) then branch to lb493, else branch to lb494 # CF Block: Cond Branch: true: lb493, false: lb494 S_AND_B64 sDst(EXEC) src0(SGPR236) src1(EXEC) S_CBRANCH_EXECZ ??? lb494 # lb493 Label: lb493 # OpReturnValue: : << const495 V_MOV_B32 vDst(VGPR502) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR503) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR504) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR502) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR503) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR504) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb494 Label: lb494 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR238) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR505) src0(VGPR0) # 498: OpIEqual: Bool: tmp498 << tmp497, const444 V_MOV_B32 vDst(VGPR506) src0(2_INT) V_CMP_EQ_I32 dst(SGPR240) src0(VGPR505) src1(VGPR506) // VOP3a # OpSelectionMerge: (merge: lb500) # CF Block: Merge: lb500 S_MOV_B64 sDst(SGPR242) src0(EXEC) # OpBranchConditional: if(tmp498) then branch to lb499, else branch to lb500 # CF Block: Cond Branch: true: lb499, false: lb500 S_AND_B64 sDst(EXEC) src0(SGPR240) src1(EXEC) S_CBRANCH_EXECZ ??? lb500 # lb499 Label: lb499 # OpReturnValue: : << const501 V_MOV_B32 vDst(VGPR507) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR508) src0(1_0_F) V_MOV_B32 vDst(VGPR509) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR507) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR508) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR509) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb500 Label: lb500 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR242) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 503: OpLoad: Int: tmp503 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR510) src0(VGPR0) # 505: OpIEqual: Bool: tmp505 << tmp503, const504 V_MOV_B32 vDst(VGPR511) src0(3_INT) V_CMP_EQ_I32 dst(SGPR244) src0(VGPR510) src1(VGPR511) // VOP3a # OpSelectionMerge: (merge: lb507) # CF Block: Merge: lb507 S_MOV_B64 sDst(SGPR246) src0(EXEC) # OpBranchConditional: if(tmp505) then branch to lb506, else branch to lb507 # CF Block: Cond Branch: true: lb506, false: lb507 S_AND_B64 sDst(EXEC) src0(SGPR244) src1(EXEC) S_CBRANCH_EXECZ ??? lb507 # lb506 Label: lb506 # OpReturnValue: : << const508 V_MOV_B32 vDst(VGPR512) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR513) src0(1_0_F) V_MOV_B32 vDst(VGPR514) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR512) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR513) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR514) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb507 Label: lb507 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR246) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 510: OpLoad: Int: tmp510 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR515) src0(VGPR0) # 512: OpIEqual: Bool: tmp512 << tmp510, const511 V_MOV_B32 vDst(VGPR516) src0(4_INT) V_CMP_EQ_I32 dst(SGPR248) src0(VGPR515) src1(VGPR516) // VOP3a # OpSelectionMerge: (merge: lb514) # CF Block: Merge: lb514 S_MOV_B64 sDst(SGPR250) src0(EXEC) # OpBranchConditional: if(tmp512) then branch to lb513, else branch to lb514 # CF Block: Cond Branch: true: lb513, false: lb514 S_AND_B64 sDst(EXEC) src0(SGPR248) src1(EXEC) S_CBRANCH_EXECZ ??? lb514 # lb513 Label: lb513 # OpReturnValue: : << const515 V_MOV_B32 vDst(VGPR517) src0(1_0_F) V_MOV_B32 vDst(VGPR518) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR519) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR517) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR518) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR519) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb514 Label: lb514 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR250) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 517: OpLoad: Int: tmp517 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR520) src0(VGPR0) # 518: OpIEqual: Bool: tmp518 << tmp517, const257 V_MOV_B32 vDst(VGPR521) src0(5_INT) V_CMP_EQ_I32 dst(SGPR252) src0(VGPR520) src1(VGPR521) // VOP3a # OpSelectionMerge: (merge: lb520) # CF Block: Merge: lb520 S_MOV_B64 sDst(SGPR254) src0(EXEC) # OpBranchConditional: if(tmp518) then branch to lb519, else branch to lb520 # CF Block: Cond Branch: true: lb519, false: lb520 S_AND_B64 sDst(EXEC) src0(SGPR252) src1(EXEC) S_CBRANCH_EXECZ ??? lb520 # lb519 Label: lb519 # OpReturnValue: : << const521 V_MOV_B32 vDst(VGPR522) src0(1_0_F) V_MOV_B32 vDst(VGPR523) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR524) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR522) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR523) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR524) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb520 Label: lb520 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR254) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 523: OpLoad: Int: tmp523 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR525) src0(VGPR0) # 525: OpIEqual: Bool: tmp525 << tmp523, const524 V_MOV_B32 vDst(VGPR526) src0(6_INT) V_CMP_EQ_I32 dst(SGPR256) src0(VGPR525) src1(VGPR526) // VOP3a # OpSelectionMerge: (merge: lb527) # CF Block: Merge: lb527 S_MOV_B64 sDst(SGPR258) src0(EXEC) # OpBranchConditional: if(tmp525) then branch to lb526, else branch to lb527 # CF Block: Cond Branch: true: lb526, false: lb527 S_AND_B64 sDst(EXEC) src0(SGPR256) src1(EXEC) S_CBRANCH_EXECZ ??? lb527 # lb526 Label: lb526 # OpBranch: to lb527 # lb527 Label: lb527 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR258) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 528: OpLoad: Int: tmp528 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR527) src0(VGPR0) # 530: OpIEqual: Bool: tmp530 << tmp528, const529 V_MOV_B32 vDst(VGPR528) src0(7_INT) V_CMP_EQ_I32 dst(SGPR260) src0(VGPR527) src1(VGPR528) // VOP3a # OpSelectionMerge: (merge: lb532) # CF Block: Merge: lb532 S_MOV_B64 sDst(SGPR262) src0(EXEC) # OpBranchConditional: if(tmp530) then branch to lb531, else branch to lb532 # CF Block: Cond Branch: true: lb531, false: lb532 S_AND_B64 sDst(EXEC) src0(SGPR260) src1(EXEC) S_CBRANCH_EXECZ ??? lb532 # lb531 Label: lb531 # OpReturnValue: : << const533 V_MOV_B32 vDst(VGPR529) src0(1_0_F) V_MOV_B32 vDst(VGPR530) src0(1_0_F) V_MOV_B32 vDst(VGPR531) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR529) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR530) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR531) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb532 Label: lb532 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR262) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 535: OpLoad: Int: tmp535 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR532) src0(VGPR0) # 537: OpIEqual: Bool: tmp537 << tmp535, const536 V_MOV_B32 vDst(VGPR533) src0(8_INT) V_CMP_EQ_I32 dst(SGPR264) src0(VGPR532) src1(VGPR533) // VOP3a # OpSelectionMerge: (merge: lb539) # CF Block: Merge: lb539 S_MOV_B64 sDst(SGPR266) src0(EXEC) # OpBranchConditional: if(tmp537) then branch to lb538, else branch to lb539 # CF Block: Cond Branch: true: lb538, false: lb539 S_AND_B64 sDst(EXEC) src0(SGPR264) src1(EXEC) S_CBRANCH_EXECZ ??? lb539 # lb538 Label: lb538 # OpReturnValue: : << const543 V_MOV_B32 vDst(VGPR534) src0(LITERAL_CONST) const: 0x3ed9999a V_MOV_B32 vDst(VGPR535) src0(LITERAL_CONST) const: 0x3f0f5c29 V_MOV_B32 vDst(VGPR536) src0(LITERAL_CONST) const: 0x3f666666 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR534) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR535) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR536) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb539 Label: lb539 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR266) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 545: OpLoad: Int: tmp545 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR537) src0(VGPR0) # 547: OpIEqual: Bool: tmp547 << tmp545, const546 V_MOV_B32 vDst(VGPR538) src0(9_INT) V_CMP_EQ_I32 dst(SGPR268) src0(VGPR537) src1(VGPR538) // VOP3a # OpSelectionMerge: (merge: lb549) # CF Block: Merge: lb549 S_MOV_B64 sDst(SGPR270) src0(EXEC) # OpBranchConditional: if(tmp547) then branch to lb548, else branch to lb549 # CF Block: Cond Branch: true: lb548, false: lb549 S_AND_B64 sDst(EXEC) src0(SGPR268) src1(EXEC) S_CBRANCH_EXECZ ??? lb549 # lb548 Label: lb548 # OpReturnValue: : << const550 V_MOV_B32 vDst(VGPR539) src0(0_5_F) V_MOV_B32 vDst(VGPR540) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR541) src0(LITERAL_CONST) const: 0x3f19999a S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR539) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR540) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR541) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb549 Label: lb549 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR270) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 552: OpLoad: Int: tmp552 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR542) src0(VGPR0) # 554: OpIEqual: Bool: tmp554 << tmp552, const553 V_MOV_B32 vDst(VGPR543) src0(10_INT) V_CMP_EQ_I32 dst(SGPR272) src0(VGPR542) src1(VGPR543) // VOP3a # OpSelectionMerge: (merge: lb556) # CF Block: Merge: lb556 S_MOV_B64 sDst(SGPR274) src0(EXEC) # OpBranchConditional: if(tmp554) then branch to lb555, else branch to lb556 # CF Block: Cond Branch: true: lb555, false: lb556 S_AND_B64 sDst(EXEC) src0(SGPR272) src1(EXEC) S_CBRANCH_EXECZ ??? lb556 # lb555 Label: lb555 # OpReturnValue: : << const501 V_MOV_B32 vDst(VGPR544) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR545) src0(1_0_F) V_MOV_B32 vDst(VGPR546) src0(LITERAL_CONST) const: 0x00000000 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR544) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR545) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR546) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb556 Label: lb556 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR274) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 558: OpLoad: Int: tmp558 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR229) const: 0x0 V_MOVRELS_B32 vDst(VGPR547) src0(VGPR0) # 560: OpIEqual: Bool: tmp560 << tmp558, const559 V_MOV_B32 vDst(VGPR548) src0(11_INT) V_CMP_EQ_I32 dst(SGPR276) src0(VGPR547) src1(VGPR548) // VOP3a # OpSelectionMerge: (merge: lb562) # CF Block: Merge: lb562 S_MOV_B64 sDst(SGPR278) src0(EXEC) # OpBranchConditional: if(tmp560) then branch to lb561, else branch to lb562 # CF Block: Cond Branch: true: lb561, false: lb562 S_AND_B64 sDst(EXEC) src0(SGPR276) src1(EXEC) S_CBRANCH_EXECZ ??? lb562 # lb561 Label: lb561 # OpReturnValue: : << const563 V_MOV_B32 vDst(VGPR549) src0(0_5_F) V_MOV_B32 vDst(VGPR550) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR551) src0(LITERAL_CONST) const: 0x3f666666 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR549) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR550) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR551) S_ANDN2_B64 sDst(SGPR230) src0(SGPR230) src1(EXEC) # lb562 Label: lb562 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR278) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR230) # 565: OpUndef: FloatVector3: tmp565 << # OpReturnValue: : << tmp565 S_MOV_B32 sDst(M0) src0(SGPR228) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR280) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR281) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR282) S_SETPC_B64 sDst(SGPR226) src0(SGPR226) # Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) Function: Void mainImage(vf4;vf2;(, FloatVector2 main.fragCoord) S_MOV_B64 sDst(SGPR284) src0(EXEC) # lb77 Label: lb77 # 567: OpLoad: Float: tmp567 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR286) S_WAITCNT 0 # 568: OpFMul: Float: tmp568 << tmp567, const90 V_MOV_B32 vDst(VGPR574) src0(0_5_F) V_MUL_F32 vDst(VGPR575) src0(SGPR286) src1(VGPR574) // VOP2 # 570: OpLoad: FloatVector2: tmp570 << fragCoord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR13) const: 0x0 V_MOVRELS_B32 vDst(VGPR576) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR577) src0(VGPR1) # 573: OpLoad: FloatVector3: tmp573 << iResolution S_LOAD_DWORDX2_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR[288:289]) S_WAITCNT 0 S_LOAD_DWORD_IMM offset(12) sBase(SGPR[0:1]) sDst(SGPR290) S_WAITCNT 0 # 574: OpVectorShuffle: FloatVector2: tmp574 << tmp573, tmp573, 0, 1 V_MOV_B32 vDst(VGPR578) src0(SGPR288) V_MOV_B32 vDst(VGPR579) src0(SGPR289) # 575: OpVectorTimesScalar: FloatVector2: tmp575 << tmp574, const90 V_MOV_B32 vDst(VGPR582) src0(0_5_F) V_MUL_F32 vDst(VGPR580) src0(VGPR582) src1(VGPR578) // VOP2 V_MUL_F32 vDst(VGPR581) src0(VGPR582) src1(VGPR579) // VOP2 # 576: OpFSub: FloatVector2: tmp576 << tmp570, tmp575 V_SUB_F32 vDst(VGPR583) src0(VGPR576) src1(VGPR580) // VOP2 V_SUB_F32 vDst(VGPR584) src0(VGPR577) src1(VGPR581) // VOP2 # 577: OpAccessChain: Float*: iResolution[1] # 578: OpLoad: Float: tmp578 << iResolution[1] S_LOAD_DWORD_IMM offset(8) sBase(SGPR[0:1]) sDst(SGPR291) S_WAITCNT 0 # 579: OpCompositeConstruct: FloatVector2: tmp579 << tmp578, tmp578 V_MOV_B32 vDst(VGPR585) src0(SGPR291) V_MOV_B32 vDst(VGPR586) src0(SGPR291) # 580: OpFDiv: FloatVector2: tmp580 << tmp576, tmp579 V_RCP_F32 vDst(VGPR587) src0(VGPR585) V_RCP_F32 vDst(VGPR588) src0(VGPR586) V_MUL_F32 vDst(VGPR587) src0(VGPR583) src1(VGPR587) // VOP2 V_MUL_F32 vDst(VGPR588) src0(VGPR584) src1(VGPR588) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR587) src0(VGPR587) src1(VGPR585) src2(VGPR583) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR588) src0(VGPR588) src1(VGPR586) src2(VGPR584) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 583: OpLoad: Float: tmp583 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR292) S_WAITCNT 0 # 584: OpExtInst(Sin): Float: tmp584 << tmp583 V_MOV_B32 vDst(VGPR659) src0(LITERAL_CONST) const: 0x3e22f983 V_MUL_F32 vDst(VGPR589) src0(VGPR659) src1(SGPR292) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FRACT_F32 vDst(VGPR589) src0(VGPR589) V_SIN_F32 vDst(VGPR589) src0(VGPR589) # 585: OpFMul: Float: tmp585 << const90, tmp584 V_MUL_F32 vDst(VGPR590) src0(0_5_F) src1(VGPR589) // VOP2 # 586: OpFAdd: Float: tmp586 << const582, tmp585 V_ADD_F32 vDst(VGPR591) src0(M1_0_F) src1(VGPR590) // VOP2 # 588: OpLoad: Float: tmp588 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR293) S_WAITCNT 0 # 589: OpFMul: Float: tmp589 << tmp588, const90 V_MOV_B32 vDst(VGPR592) src0(0_5_F) V_MUL_F32 vDst(VGPR593) src0(SGPR293) src1(VGPR592) // VOP2 # 590: OpFAdd: Float: tmp590 << const587, tmp589 V_MOV_B32 vDst(VGPR594) src0(LITERAL_CONST) const: 0xc0a00000 V_ADD_F32 vDst(VGPR595) src0(VGPR594) src1(VGPR593) // VOP2 # 591: OpCompositeConstruct: FloatVector3: tmp591 << const174, tmp586, tmp590 V_MOV_B32 vDst(VGPR599) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR596) src0(VGPR599) V_MOV_B32 vDst(VGPR597) src0(VGPR591) V_MOV_B32 vDst(VGPR598) src0(VGPR595) # 594: OpCompositeExtract: Float: tmp594 << tmp580, 0 V_MOV_B32 vDst(VGPR600) src0(VGPR587) # 595: OpCompositeExtract: Float: tmp595 << tmp580, 1 V_MOV_B32 vDst(VGPR601) src0(VGPR588) # 596: OpCompositeConstruct: FloatVector3: tmp596 << tmp594, tmp595, const88 V_MOV_B32 vDst(VGPR602) src0(VGPR600) V_MOV_B32 vDst(VGPR603) src0(VGPR601) V_MOV_B32 vDst(VGPR604) src0(1_0_F) # 597: OpExtInst(Normalize): FloatVector3: tmp597 << tmp596 V_MUL_F32 vDst(VGPR605) src0(VGPR602) src1(VGPR602) // VOP2 V_MAC_F32 vDst(VGPR605) src0(VGPR603) src1(VGPR603) // VOP2 V_MAC_F32 vDst(VGPR605) src0(VGPR604) src1(VGPR604) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR605) src0(VGPR605) V_MUL_F32 vDst(VGPR606) src0(VGPR602) src1(VGPR605) // VOP2 V_MUL_F32 vDst(VGPR607) src0(VGPR603) src1(VGPR605) // VOP2 V_MUL_F32 vDst(VGPR608) src0(VGPR604) src1(VGPR605) // VOP2 # OpStore: : tmp591 >> param599 V_MOV_B32 vDst(VGPR552) src0(VGPR596) V_MOV_B32 vDst(VGPR553) src0(VGPR597) V_MOV_B32 vDst(VGPR554) src0(VGPR598) # OpStore: : tmp597 >> param601 V_MOV_B32 vDst(VGPR555) src0(VGPR606) V_MOV_B32 vDst(VGPR556) src0(VGPR607) V_MOV_B32 vDst(VGPR557) src0(VGPR608) # 603: OpFunctionCall: FloatVector2: march(vf3;vf3;(param599, param601) S_ADD_U32 sDst(SGPR113) src0(LITERAL_CONST) src1(0) const: 0x228 # VGPR[552:554] S_ADD_U32 sDst(SGPR114) src0(LITERAL_CONST) src1(0) const: 0x22b # VGPR[555:557] S_MOV_B64 sDst(SGPR294) src0(EXEC) S_MOV_B32 sDst(SGPR112) src0(LITERAL_CONST) const: 0x261 # VGPR[609:610] # Indirect branch to march(vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR110) src0(SGPR110) S_ADD_U32 sDst(SGPR110) src0(SGPR110) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR111) src0(SGPR111) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR110) src0(SGPR110) S_MOV_B64 sDst(EXEC) src0(SGPR294) # .lbl29 # 606: OpAccessChain: Float*: hit[0] # 607: OpCompositeExtract: Float: tmp607 << march(vf3;vf3;, 0 V_MOV_B32 vDst(VGPR611) src0(VGPR609) # 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp597, tmp607 V_MUL_F32 vDst(VGPR612) src0(VGPR611) src1(VGPR606) // VOP2 V_MUL_F32 vDst(VGPR613) src0(VGPR611) src1(VGPR607) // VOP2 V_MUL_F32 vDst(VGPR614) src0(VGPR611) src1(VGPR608) // VOP2 # 610: OpFAdd: FloatVector3: tmp610 << tmp591, tmp609 V_ADD_F32 vDst(VGPR615) src0(VGPR596) src1(VGPR612) // VOP2 V_ADD_F32 vDst(VGPR616) src0(VGPR597) src1(VGPR613) // VOP2 V_ADD_F32 vDst(VGPR617) src0(VGPR598) src1(VGPR614) // VOP2 # OpStore: : tmp610 >> param612 V_MOV_B32 vDst(VGPR558) src0(VGPR615) V_MOV_B32 vDst(VGPR559) src0(VGPR616) V_MOV_B32 vDst(VGPR560) src0(VGPR617) # 614: OpFunctionCall: FloatVector3: getNorm(vf3;(param612) S_ADD_U32 sDst(SGPR169) src0(LITERAL_CONST) src1(0) const: 0x22e # VGPR[558:560] S_MOV_B64 sDst(SGPR296) src0(EXEC) S_MOV_B32 sDst(SGPR168) src0(LITERAL_CONST) const: 0x26a # VGPR[618:620] # Indirect branch to getNorm(vf3;: ??? S_GETPC_B64 sDst(SGPR166) src0(SGPR166) S_ADD_U32 sDst(SGPR166) src0(SGPR166) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR167) src0(SGPR167) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR166) src0(SGPR166) S_MOV_B64 sDst(EXEC) src0(SGPR296) # .lbl30 # 617: OpAccessChain: Float*: hit[0] # 618: OpCompositeExtract: Float: tmp618 << march(vf3;vf3;, 0 V_MOV_B32 vDst(VGPR621) src0(VGPR609) # 619: OpFOrdLessThan: Bool: tmp619 << tmp618, const308 V_MOV_B32 vDst(VGPR622) src0(LITERAL_CONST) const: 0x41a00000 V_CMP_LT_F32 dst(SGPR298) src0(VGPR621) src1(VGPR622) // VOP3a # OpSelectionMerge: (merge: lb621) # CF Block: Merge: lb621 S_MOV_B64 sDst(SGPR300) src0(EXEC) # OpBranchConditional: if(tmp619) then branch to lb620, else branch to lb627 # CF Block: Cond Branch: true: lb620, false: lb627 S_AND_B64 sDst(EXEC) src0(SGPR298) src1(EXEC) S_CBRANCH_EXECZ ??? lb627 # lb620 Label: lb620 # OpStore: : tmp610 >> param622 V_MOV_B32 vDst(VGPR567) src0(VGPR615) V_MOV_B32 vDst(VGPR568) src0(VGPR616) V_MOV_B32 vDst(VGPR569) src0(VGPR617) # OpStore: : getNorm(vf3; >> param624 V_MOV_B32 vDst(VGPR570) src0(VGPR618) V_MOV_B32 vDst(VGPR571) src0(VGPR619) V_MOV_B32 vDst(VGPR572) src0(VGPR620) # 626: OpFunctionCall: FloatVector3: light(vf3;vf3;(param622, param624) S_ADD_U32 sDst(SGPR187) src0(LITERAL_CONST) src1(0) const: 0x237 # VGPR[567:569] S_ADD_U32 sDst(SGPR188) src0(LITERAL_CONST) src1(0) const: 0x23a # VGPR[570:572] S_MOV_B64 sDst(SGPR302) src0(EXEC) S_MOV_B32 sDst(SGPR186) src0(LITERAL_CONST) const: 0x26f # VGPR[623:625] # Indirect branch to light(vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR184) src0(SGPR184) S_ADD_U32 sDst(SGPR184) src0(SGPR184) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR185) src0(SGPR185) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR184) src0(SGPR184) S_MOV_B64 sDst(EXEC) src0(SGPR302) # .lbl31 # OpStore: : light(vf3;vf3; >> var616 V_MOV_B32 vDst(VGPR564) src0(VGPR623) V_MOV_B32 vDst(VGPR565) src0(VGPR624) V_MOV_B32 vDst(VGPR566) src0(VGPR625) # OpBranch: to lb621 # lb627 Label: lb627 S_ANDN2_B64 sDst(EXEC) src0(SGPR300) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR284) src1(EXEC) S_CBRANCH_EXECZ ??? lb621 # 629: OpExtInst(Length): Float: tmp629 << tmp580 V_MUL_F32 vDst(VGPR626) src0(VGPR587) src1(VGPR587) // VOP2 V_MAC_F32 vDst(VGPR626) src0(VGPR588) src1(VGPR588) // VOP2 V_SQRT_F32 vDst(VGPR626) src0(VGPR626) # 630: OpFSub: Float: tmp630 << const88, tmp629 V_SUB_F32 vDst(VGPR627) src0(1_0_F) src1(VGPR626) // VOP2 # 631: OpFMul: Float: tmp631 << const385, tmp630 V_MOV_B32 vDst(VGPR628) src0(LITERAL_CONST) const: 0x3dcccccd V_MUL_F32 vDst(VGPR629) src0(VGPR628) src1(VGPR627) // VOP2 # 632: OpCompositeConstruct: FloatVector3: tmp632 << tmp631, tmp631, tmp631 V_MOV_B32 vDst(VGPR630) src0(VGPR629) V_MOV_B32 vDst(VGPR631) src0(VGPR629) V_MOV_B32 vDst(VGPR632) src0(VGPR629) # OpStore: : tmp632 >> var616 V_MOV_B32 vDst(VGPR564) src0(VGPR630) V_MOV_B32 vDst(VGPR565) src0(VGPR631) V_MOV_B32 vDst(VGPR566) src0(VGPR632) # OpBranch: to lb621 # lb621 Label: lb621 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR300) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR284) # 633: OpLoad: FloatVector3: tmp633 << var616 # OpStore: : tmp633 >> col V_MOV_B32 vDst(VGPR561) src0(VGPR564) V_MOV_B32 vDst(VGPR562) src0(VGPR565) V_MOV_B32 vDst(VGPR563) src0(VGPR566) # 635: OpLoad: Float: tmp635 << NumCol # 636: OpConvertFToS: Int: tmp636 << tmp635 V_CVT_I32_F32 vDst(VGPR633) src0(VGPR263) # OpStore: : tmp636 >> param637 V_MOV_B32 vDst(VGPR573) src0(VGPR633) # 638: OpFunctionCall: FloatVector3: getSphereColor(i1;(param637) S_ADD_U32 sDst(SGPR229) src0(LITERAL_CONST) src1(0) const: 0x23d # VGPR573 S_MOV_B64 sDst(SGPR304) src0(EXEC) S_MOV_B32 sDst(SGPR228) src0(LITERAL_CONST) const: 0x27a # VGPR[634:636] # Indirect branch to getSphereColor(i1;: ??? S_GETPC_B64 sDst(SGPR226) src0(SGPR226) S_ADD_U32 sDst(SGPR226) src0(SGPR226) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR227) src0(SGPR227) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR226) src0(SGPR226) S_MOV_B64 sDst(EXEC) src0(SGPR304) # .lbl32 # 640: OpLoad: FloatVector3: tmp640 << col # 641: OpFMul: FloatVector3: tmp641 << tmp640, getSphereColor(i1; V_MUL_F32 vDst(VGPR637) src0(VGPR561) src1(VGPR634) // VOP2 V_MUL_F32 vDst(VGPR638) src0(VGPR562) src1(VGPR635) // VOP2 V_MUL_F32 vDst(VGPR639) src0(VGPR563) src1(VGPR636) // VOP2 # OpStore: : tmp641 >> col V_MOV_B32 vDst(VGPR561) src0(VGPR637) V_MOV_B32 vDst(VGPR562) src0(VGPR638) V_MOV_B32 vDst(VGPR563) src0(VGPR639) # 642: OpAccessChain: Float*: hit[1] # 643: OpCompositeExtract: Float: tmp643 << march(vf3;vf3;, 1 V_MOV_B32 vDst(VGPR640) src0(VGPR610) # 644: OpExtInst(Pow): Float: tmp644 << tmp643, const267 V_MOV_B32 vDst(VGPR641) src0(LITERAL_CONST) const: 0x40400000 V_LOG_F32 vDst(VGPR642) src0(VGPR640) V_MUL_F32 vDst(VGPR642) src0(VGPR641) src1(VGPR642) // VOP2 V_EXP_F32 vDst(VGPR642) src0(VGPR642) # 645: OpLoad: FloatVector3: tmp645 << col # 646: OpCompositeConstruct: FloatVector3: tmp646 << tmp644, tmp644, tmp644 V_MOV_B32 vDst(VGPR643) src0(VGPR642) V_MOV_B32 vDst(VGPR644) src0(VGPR642) V_MOV_B32 vDst(VGPR645) src0(VGPR642) # 647: OpFAdd: FloatVector3: tmp647 << tmp645, tmp646 V_ADD_F32 vDst(VGPR646) src0(VGPR561) src1(VGPR643) // VOP2 V_ADD_F32 vDst(VGPR647) src0(VGPR562) src1(VGPR644) // VOP2 V_ADD_F32 vDst(VGPR648) src0(VGPR563) src1(VGPR645) // VOP2 # OpStore: : tmp647 >> col V_MOV_B32 vDst(VGPR561) src0(VGPR646) V_MOV_B32 vDst(VGPR562) src0(VGPR647) V_MOV_B32 vDst(VGPR563) src0(VGPR648) # 648: OpLoad: FloatVector3: tmp648 << col # 649: OpExtInst(Sqrt): FloatVector3: tmp649 << tmp648 V_SQRT_F32 vDst(VGPR649) src0(VGPR561) V_SQRT_F32 vDst(VGPR650) src0(VGPR562) V_SQRT_F32 vDst(VGPR651) src0(VGPR563) # 650: OpCompositeExtract: Float: tmp650 << tmp649, 0 V_MOV_B32 vDst(VGPR652) src0(VGPR649) # 651: OpCompositeExtract: Float: tmp651 << tmp649, 1 V_MOV_B32 vDst(VGPR653) src0(VGPR650) # 652: OpCompositeExtract: Float: tmp652 << tmp649, 2 V_MOV_B32 vDst(VGPR654) src0(VGPR651) # 653: OpCompositeConstruct: FloatVector4: tmp653 << tmp650, tmp651, tmp652, const88 V_MOV_B32 vDst(VGPR655) src0(VGPR652) V_MOV_B32 vDst(VGPR656) src0(VGPR653) V_MOV_B32 vDst(VGPR657) src0(VGPR654) V_MOV_B32 vDst(VGPR658) src0(1_0_F) # OpStore: : tmp653 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR655) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR656) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR657) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR658) # OpReturn: S_SETPC_B64 sDst(SGPR10) src0(SGPR10) Performing register allocation... Register VGPR[24:26] contains scalar/constant data. Will try converting to SGPR. Register VGPR[27:29] contains scalar/constant data. Will try converting to SGPR. Register VGPR[30:32] contains scalar/constant data. Will try converting to SGPR. Register VGPR[33:35] contains scalar/constant data. Will try converting to SGPR. Register VGPR[36:38] contains scalar/constant data. Will try converting to SGPR. Register VGPR[39:41] contains scalar/constant data. Will try converting to SGPR. Register VGPR[42:44] contains scalar/constant data. Will try converting to SGPR. Register VGPR[45:47] contains scalar/constant data. Will try converting to SGPR. Register VGPR[48:51] contains scalar/constant data. Will try converting to SGPR. Register VGPR[52:53] contains scalar/constant data. Will try converting to SGPR. Register VGPR81 contains scalar/constant data. Will try converting to SGPR. Register VGPR81 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR82) src0(VGPR80) src1(VGPR81) // VOP2 Register VGPR[89:91] contains scalar/constant data. Will try converting to SGPR. Register VGPR[89:91] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR92) src0(VGPR86) src1(VGPR89) // VOP2 Register VGPR[95:97] contains scalar/constant data. Will try converting to SGPR. Register VGPR[95:97] can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR98) src0(VGPR95) Register VGPR[101:103] contains scalar/constant data. Will try converting to SGPR. Register VGPR[101:103] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR104) src0(VGPR98) src1(VGPR101) // VOP2 Register VGPR143 contains scalar/constant data. Will try converting to SGPR. Register VGPR143 can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR144) src0(VGPR142) src1(VGPR143) // VOP2 Register VGPR[145:146] contains scalar/constant data. Will try converting to SGPR. Register VGPR[145:146] can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR149) src0(VGPR138) src1(VGPR145) // VOP2 Register VGPR147 contains scalar/constant data. Will try converting to SGPR. Register VGPR148 contains scalar/constant data. Will try converting to SGPR. Register VGPR[179:180] contains scalar/constant data. Will try converting to SGPR. Register VGPR182 contains scalar/constant data. Will try converting to SGPR. Register VGPR182 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR183) src0(VGPR182) Register VGPR[190:191] contains scalar/constant data. Will try converting to SGPR. Register VGPR[199:200] contains scalar/constant data. Will try converting to SGPR. Register VGPR205 contains scalar/constant data. Will try converting to SGPR. Register VGPR209 contains scalar/constant data. Will try converting to SGPR. Register VGPR209 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR245) src0(VGPR209) src1(VGPR244) // VOP2 Register VGPR216 contains scalar/constant data. Will try converting to SGPR. Register VGPR229 contains scalar/constant data. Will try converting to SGPR. Register VGPR[230:231] contains scalar/constant data. Will try converting to SGPR. Register VGPR232 contains scalar/constant data. Will try converting to SGPR. Register VGPR237 contains scalar/constant data. Will try converting to SGPR. Register VGPR244 contains scalar/constant data. Will try converting to SGPR. Register VGPR244 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR245) src0(VGPR209) src1(VGPR244) // VOP2 Register VGPR245 contains scalar/constant data. Will try converting to SGPR. Register VGPR245 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR245) src0(VGPR209) src1(VGPR244) // VOP2 Register VGPR246 contains scalar/constant data. Will try converting to SGPR. Register VGPR247 contains scalar/constant data. Will try converting to SGPR. Register VGPR248 contains scalar/constant data. Will try converting to SGPR. Register VGPR248 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR250) src0(VGPR248) src1(VGPR250) // VOP2 Register VGPR249 contains scalar/constant data. Will try converting to SGPR. Register VGPR249 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR250) src0(VGPR249) Register VGPR250 contains scalar/constant data. Will try converting to SGPR. Register VGPR250 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR250) src0(VGPR249) Register VGPR251 contains scalar/constant data. Will try converting to SGPR. Register VGPR254 contains scalar/constant data. Will try converting to SGPR. Register VGPR259 contains scalar/constant data. Will try converting to SGPR. Register VGPR267 contains scalar/constant data. Will try converting to SGPR. Register VGPR267 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR293) src0(VGPR267) src1(VGPR292) // VOP2 Register VGPR268 contains scalar/constant data. Will try converting to SGPR. Register VGPR272 contains scalar/constant data. Will try converting to SGPR. Register VGPR273 contains scalar/constant data. Will try converting to SGPR. Register VGPR274 contains scalar/constant data. Will try converting to SGPR. Register VGPR275 contains scalar/constant data. Will try converting to SGPR. Register VGPR290 contains scalar/constant data. Will try converting to SGPR. Register VGPR291 contains scalar/constant data. Will try converting to SGPR. Register VGPR292 contains scalar/constant data. Will try converting to SGPR. Register VGPR292 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR293) src0(VGPR267) src1(VGPR292) // VOP2 Register VGPR293 contains scalar/constant data. Will try converting to SGPR. Register VGPR293 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR293) src0(VGPR267) src1(VGPR292) // VOP2 Register VGPR294 contains scalar/constant data. Will try converting to SGPR. Register VGPR295 contains scalar/constant data. Will try converting to SGPR. Register VGPR296 contains scalar/constant data. Will try converting to SGPR. Register VGPR296 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR297) src0(VGPR296) Register VGPR297 contains scalar/constant data. Will try converting to SGPR. Register VGPR297 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR297) src0(VGPR296) Register VGPR302 contains scalar/constant data. Will try converting to SGPR. Register VGPR312 contains scalar/constant data. Will try converting to SGPR. Register VGPR312 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR309) src0(VGPR312) src1(VGPR306) // VOP2 Register VGPR319 contains scalar/constant data. Will try converting to SGPR. Register VGPR320 contains scalar/constant data. Will try converting to SGPR. Register VGPR321 contains scalar/constant data. Will try converting to SGPR. Register VGPR336 contains scalar/constant data. Will try converting to SGPR. Register VGPR337 contains scalar/constant data. Will try converting to SGPR. Register VGPR338 contains scalar/constant data. Will try converting to SGPR. Register VGPR339 contains scalar/constant data. Will try converting to SGPR. Register VGPR340 contains scalar/constant data. Will try converting to SGPR. Register VGPR342 contains scalar/constant data. Will try converting to SGPR. Register VGPR[364:365] contains scalar/constant data. Will try converting to SGPR. Register VGPR[366:368] contains scalar/constant data. Will try converting to SGPR. Register VGPR[366:368] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR369) src0(VGPR361) src1(VGPR366) // VOP2 Register VGPR[376:377] contains scalar/constant data. Will try converting to SGPR. Register VGPR[378:380] contains scalar/constant data. Will try converting to SGPR. Register VGPR[378:380] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR381) src0(VGPR373) src1(VGPR378) // VOP2 Register VGPR[389:390] contains scalar/constant data. Will try converting to SGPR. Register VGPR[391:393] contains scalar/constant data. Will try converting to SGPR. Register VGPR[391:393] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR394) src0(VGPR386) src1(VGPR391) // VOP2 Register VGPR[401:402] contains scalar/constant data. Will try converting to SGPR. Register VGPR[403:405] contains scalar/constant data. Will try converting to SGPR. Register VGPR[403:405] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR406) src0(VGPR398) src1(VGPR403) // VOP2 Register VGPR[414:415] contains scalar/constant data. Will try converting to SGPR. Register VGPR[416:418] contains scalar/constant data. Will try converting to SGPR. Register VGPR[416:418] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR419) src0(VGPR411) src1(VGPR416) // VOP2 Register VGPR[426:427] contains scalar/constant data. Will try converting to SGPR. Register VGPR[428:430] contains scalar/constant data. Will try converting to SGPR. Register VGPR[428:430] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR431) src0(VGPR423) src1(VGPR428) // VOP2 Register VGPR446 contains scalar/constant data. Will try converting to SGPR. Register VGPR[457:459] contains scalar/constant data. Will try converting to SGPR. Register VGPR460 contains scalar/constant data. Will try converting to SGPR. Register VGPR461 contains scalar/constant data. Will try converting to SGPR. Register VGPR[462:464] contains scalar/constant data. Will try converting to SGPR. Register VGPR[462:464] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR468) src0(VGPR465) src1(VGPR462) // VOP2 Register VGPR469 contains scalar/constant data. Will try converting to SGPR. Register VGPR469 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR470) src0(VGPR468) src1(VGPR469) // VOP2 Register VGPR479 contains scalar/constant data. Will try converting to SGPR. Register VGPR[480:482] contains scalar/constant data. Will try converting to SGPR. Register VGPR[480:482] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR483) src0(VGPR447) src1(VGPR480) // VOP2 Register VGPR489 contains scalar/constant data. Will try converting to SGPR. Register VGPR490 contains scalar/constant data. Will try converting to SGPR. Register VGPR494 contains scalar/constant data. Will try converting to SGPR. Register VGPR494 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR491) src0(VGPR494) src1(VGPR443) // VOP2 Register VGPR496 contains scalar/constant data. Will try converting to SGPR. Register VGPR[497:499] contains scalar/constant data. Will try converting to SGPR. Register VGPR501 contains scalar/constant data. Will try converting to SGPR. Register VGPR[502:504] contains scalar/constant data. Will try converting to SGPR. Register VGPR506 contains scalar/constant data. Will try converting to SGPR. Register VGPR[507:509] contains scalar/constant data. Will try converting to SGPR. Register VGPR511 contains scalar/constant data. Will try converting to SGPR. Register VGPR[512:514] contains scalar/constant data. Will try converting to SGPR. Register VGPR516 contains scalar/constant data. Will try converting to SGPR. Register VGPR[517:519] contains scalar/constant data. Will try converting to SGPR. Register VGPR521 contains scalar/constant data. Will try converting to SGPR. Register VGPR[522:524] contains scalar/constant data. Will try converting to SGPR. Register VGPR526 contains scalar/constant data. Will try converting to SGPR. Register VGPR528 contains scalar/constant data. Will try converting to SGPR. Register VGPR[529:531] contains scalar/constant data. Will try converting to SGPR. Register VGPR533 contains scalar/constant data. Will try converting to SGPR. Register VGPR[534:536] contains scalar/constant data. Will try converting to SGPR. Register VGPR538 contains scalar/constant data. Will try converting to SGPR. Register VGPR[539:541] contains scalar/constant data. Will try converting to SGPR. Register VGPR543 contains scalar/constant data. Will try converting to SGPR. Register VGPR[544:546] contains scalar/constant data. Will try converting to SGPR. Register VGPR548 contains scalar/constant data. Will try converting to SGPR. Register VGPR[549:551] contains scalar/constant data. Will try converting to SGPR. Register VGPR574 contains scalar/constant data. Will try converting to SGPR. Register VGPR574 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR575) src0(SGPR286) src1(VGPR574) // VOP2 Register VGPR575 contains scalar/constant data. Will try converting to SGPR. Register VGPR575 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR575) src0(SGPR286) src1(VGPR574) // VOP2 Register VGPR[578:579] contains scalar/constant data. Will try converting to SGPR. Register VGPR[578:579] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR580) src0(VGPR582) src1(VGPR578) // VOP2 Register VGPR[580:581] contains scalar/constant data. Will try converting to SGPR. Register VGPR[580:581] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR580) src0(VGPR582) src1(VGPR578) // VOP2 Register VGPR582 contains scalar/constant data. Will try converting to SGPR. Register VGPR582 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR580) src0(VGPR582) src1(VGPR578) // VOP2 Register VGPR[585:586] contains scalar/constant data. Will try converting to SGPR. Register VGPR[585:586] can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR587) src0(VGPR585) Register VGPR589 contains scalar/constant data. Will try converting to SGPR. Register VGPR589 can't be converted to SGPR, because the following instruction can't be converted: V_MOV_B32 vDst(VGPR659) src0(LITERAL_CONST) const: 0x3e22f983 V_MUL_F32 vDst(VGPR589) src0(VGPR659) src1(SGPR292) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR590 contains scalar/constant data. Will try converting to SGPR. Register VGPR590 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR590) src0(0_5_F) src1(VGPR589) // VOP2 Register VGPR591 contains scalar/constant data. Will try converting to SGPR. Register VGPR591 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR591) src0(M1_0_F) src1(VGPR590) // VOP2 Register VGPR592 contains scalar/constant data. Will try converting to SGPR. Register VGPR592 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR593) src0(SGPR293) src1(VGPR592) // VOP2 Register VGPR593 contains scalar/constant data. Will try converting to SGPR. Register VGPR593 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR593) src0(SGPR293) src1(VGPR592) // VOP2 Register VGPR594 contains scalar/constant data. Will try converting to SGPR. Register VGPR594 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR595) src0(VGPR594) src1(VGPR593) // VOP2 Register VGPR595 contains scalar/constant data. Will try converting to SGPR. Register VGPR595 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR595) src0(VGPR594) src1(VGPR593) // VOP2 Register VGPR[596:598] contains scalar/constant data. Will try converting to SGPR. Register VGPR[596:598] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR615) src0(VGPR596) src1(VGPR612) // VOP2 Register VGPR599 contains scalar/constant data. Will try converting to SGPR. Register VGPR622 contains scalar/constant data. Will try converting to SGPR. Register VGPR628 contains scalar/constant data. Will try converting to SGPR. Register VGPR628 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR629) src0(VGPR628) src1(VGPR627) // VOP2 Register VGPR641 contains scalar/constant data. Will try converting to SGPR. Register VGPR641 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR642) src0(VGPR641) src1(VGPR642) // VOP2 Register VGPR659 contains scalar/constant data. Will try converting to SGPR. Register VGPR659 can't be converted to SGPR, because the following instruction can't be converted: V_MOV_B32 vDst(VGPR659) src0(LITERAL_CONST) const: 0x3e22f983 V_MUL_F32 vDst(VGPR589) src0(VGPR659) src1(SGPR292) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR[24:26] contains scalar/constant data. Will try converting to SGPR. Register VGPR[27:29] contains scalar/constant data. Will try converting to SGPR. Register VGPR[30:32] contains scalar/constant data. Will try converting to SGPR. Register VGPR[33:35] contains scalar/constant data. Will try converting to SGPR. Register VGPR[36:38] contains scalar/constant data. Will try converting to SGPR. Register VGPR[39:41] contains scalar/constant data. Will try converting to SGPR. Register VGPR[42:44] contains scalar/constant data. Will try converting to SGPR. Register VGPR[45:47] contains scalar/constant data. Will try converting to SGPR. Register VGPR147 contains scalar/constant data. Will try converting to SGPR. Register VGPR148 contains scalar/constant data. Will try converting to SGPR. Register VGPR[179:180] contains scalar/constant data. Will try converting to SGPR. Register VGPR[190:191] contains scalar/constant data. Will try converting to SGPR. Register VGPR[199:200] contains scalar/constant data. Will try converting to SGPR. Register VGPR205 contains scalar/constant data. Will try converting to SGPR. Register VGPR216 contains scalar/constant data. Will try converting to SGPR. Register VGPR229 contains scalar/constant data. Will try converting to SGPR. Register VGPR[230:231] contains scalar/constant data. Will try converting to SGPR. Register VGPR232 contains scalar/constant data. Will try converting to SGPR. Register VGPR237 contains scalar/constant data. Will try converting to SGPR. Register VGPR246 contains scalar/constant data. Will try converting to SGPR. Register VGPR247 contains scalar/constant data. Will try converting to SGPR. Register VGPR251 contains scalar/constant data. Will try converting to SGPR. Register VGPR254 contains scalar/constant data. Will try converting to SGPR. Register VGPR259 contains scalar/constant data. Will try converting to SGPR. Register VGPR268 contains scalar/constant data. Will try converting to SGPR. Register VGPR272 contains scalar/constant data. Will try converting to SGPR. Register VGPR273 contains scalar/constant data. Will try converting to SGPR. Register VGPR274 contains scalar/constant data. Will try converting to SGPR. Register VGPR275 contains scalar/constant data. Will try converting to SGPR. Register VGPR290 contains scalar/constant data. Will try converting to SGPR. Register VGPR291 contains scalar/constant data. Will try converting to SGPR. Register VGPR294 contains scalar/constant data. Will try converting to SGPR. Register VGPR295 contains scalar/constant data. Will try converting to SGPR. Register VGPR302 contains scalar/constant data. Will try converting to SGPR. Register VGPR319 contains scalar/constant data. Will try converting to SGPR. Register VGPR320 contains scalar/constant data. Will try converting to SGPR. Register VGPR321 contains scalar/constant data. Will try converting to SGPR. Register VGPR336 contains scalar/constant data. Will try converting to SGPR. Register VGPR337 contains scalar/constant data. Will try converting to SGPR. Register VGPR338 contains scalar/constant data. Will try converting to SGPR. Register VGPR339 contains scalar/constant data. Will try converting to SGPR. Register VGPR340 contains scalar/constant data. Will try converting to SGPR. Register VGPR342 contains scalar/constant data. Will try converting to SGPR. Register VGPR[364:365] contains scalar/constant data. Will try converting to SGPR. Register VGPR[376:377] contains scalar/constant data. Will try converting to SGPR. Register VGPR[389:390] contains scalar/constant data. Will try converting to SGPR. Register VGPR[401:402] contains scalar/constant data. Will try converting to SGPR. Register VGPR[414:415] contains scalar/constant data. Will try converting to SGPR. Register VGPR[426:427] contains scalar/constant data. Will try converting to SGPR. Register VGPR446 contains scalar/constant data. Will try converting to SGPR. Register VGPR[457:459] contains scalar/constant data. Will try converting to SGPR. Register VGPR460 contains scalar/constant data. Will try converting to SGPR. Register VGPR461 contains scalar/constant data. Will try converting to SGPR. Register VGPR479 contains scalar/constant data. Will try converting to SGPR. Register VGPR489 contains scalar/constant data. Will try converting to SGPR. Register VGPR490 contains scalar/constant data. Will try converting to SGPR. Register VGPR496 contains scalar/constant data. Will try converting to SGPR. Register VGPR[497:499] contains scalar/constant data. Will try converting to SGPR. Register VGPR501 contains scalar/constant data. Will try converting to SGPR. Register VGPR[502:504] contains scalar/constant data. Will try converting to SGPR. Register VGPR506 contains scalar/constant data. Will try converting to SGPR. Register VGPR[507:509] contains scalar/constant data. Will try converting to SGPR. Register VGPR511 contains scalar/constant data. Will try converting to SGPR. Register VGPR[512:514] contains scalar/constant data. Will try converting to SGPR. Register VGPR516 contains scalar/constant data. Will try converting to SGPR. Register VGPR[517:519] contains scalar/constant data. Will try converting to SGPR. Register VGPR521 contains scalar/constant data. Will try converting to SGPR. Register VGPR[522:524] contains scalar/constant data. Will try converting to SGPR. Register VGPR526 contains scalar/constant data. Will try converting to SGPR. Register VGPR528 contains scalar/constant data. Will try converting to SGPR. Register VGPR[529:531] contains scalar/constant data. Will try converting to SGPR. Register VGPR533 contains scalar/constant data. Will try converting to SGPR. Register VGPR[534:536] contains scalar/constant data. Will try converting to SGPR. Register VGPR538 contains scalar/constant data. Will try converting to SGPR. Register VGPR[539:541] contains scalar/constant data. Will try converting to SGPR. Register VGPR543 contains scalar/constant data. Will try converting to SGPR. Register VGPR[544:546] contains scalar/constant data. Will try converting to SGPR. Register VGPR548 contains scalar/constant data. Will try converting to SGPR. Register VGPR[549:551] contains scalar/constant data. Will try converting to SGPR. Register VGPR599 contains scalar/constant data. Will try converting to SGPR. Register VGPR622 contains scalar/constant data. Will try converting to SGPR. No need to convert VGPR237 because it's only used for VGPR comparisons. No need to convert VGPR251 because it's only used for VGPR comparisons. No need to convert VGPR275 because it's only used for VGPR comparisons. No need to convert VGPR290 because it's only used for VGPR comparisons. No need to convert VGPR291 because it's only used for VGPR comparisons. No need to convert VGPR321 because it's only used for VGPR comparisons. No need to convert VGPR336 because it's only used for VGPR comparisons. No need to convert VGPR337 because it's only used for VGPR comparisons. No need to convert VGPR340 because it's only used for VGPR comparisons. No need to convert VGPR460 because it's only used for VGPR comparisons. No need to convert VGPR461 because it's only used for VGPR comparisons. No need to convert VGPR479 because it's only used for VGPR comparisons. No need to convert VGPR496 because it's only used for VGPR comparisons. No need to convert VGPR501 because it's only used for VGPR comparisons. No need to convert VGPR506 because it's only used for VGPR comparisons. No need to convert VGPR511 because it's only used for VGPR comparisons. No need to convert VGPR516 because it's only used for VGPR comparisons. No need to convert VGPR521 because it's only used for VGPR comparisons. No need to convert VGPR526 because it's only used for VGPR comparisons. No need to convert VGPR528 because it's only used for VGPR comparisons. No need to convert VGPR533 because it's only used for VGPR comparisons. No need to convert VGPR538 because it's only used for VGPR comparisons. No need to convert VGPR543 because it's only used for VGPR comparisons. No need to convert VGPR548 because it's only used for VGPR comparisons. No need to convert VGPR622 because it's only used for VGPR comparisons. Converting VGPR[24:26] to SGPR, and adjusting instructions. Converting VGPR[27:29] to SGPR, and adjusting instructions. Converting VGPR[30:32] to SGPR, and adjusting instructions. Converting VGPR[33:35] to SGPR, and adjusting instructions. Converting VGPR[36:38] to SGPR, and adjusting instructions. Converting VGPR[39:41] to SGPR, and adjusting instructions. Converting VGPR[42:44] to SGPR, and adjusting instructions. Converting VGPR[45:47] to SGPR, and adjusting instructions. Converting VGPR147 to SGPR, and adjusting instructions. Converting VGPR148 to SGPR, and adjusting instructions. Converting VGPR[179:180] to SGPR, and adjusting instructions. Converting VGPR[190:191] to SGPR, and adjusting instructions. Converting VGPR[199:200] to SGPR, and adjusting instructions. Converting VGPR205 to SGPR, and adjusting instructions. Converting VGPR216 to SGPR, and adjusting instructions. Converting VGPR229 to SGPR, and adjusting instructions. Converting VGPR[230:231] to SGPR, and adjusting instructions. Converting VGPR232 to SGPR, and adjusting instructions. Converting VGPR246 to SGPR, and adjusting instructions. Converting VGPR247 to SGPR, and adjusting instructions. Converting VGPR254 to SGPR, and adjusting instructions. Converting VGPR259 to SGPR, and adjusting instructions. Converting VGPR268 to SGPR, and adjusting instructions. Converting VGPR272 to SGPR, and adjusting instructions. Converting VGPR273 to SGPR, and adjusting instructions. Converting VGPR274 to SGPR, and adjusting instructions. Converting VGPR294 to SGPR, and adjusting instructions. Converting VGPR295 to SGPR, and adjusting instructions. Converting VGPR302 to SGPR, and adjusting instructions. Converting VGPR319 to SGPR, and adjusting instructions. Converting VGPR320 to SGPR, and adjusting instructions. Converting VGPR338 to SGPR, and adjusting instructions. Converting VGPR339 to SGPR, and adjusting instructions. Converting VGPR342 to SGPR, and adjusting instructions. Converting VGPR[364:365] to SGPR, and adjusting instructions. Converting VGPR[376:377] to SGPR, and adjusting instructions. Converting VGPR[389:390] to SGPR, and adjusting instructions. Converting VGPR[401:402] to SGPR, and adjusting instructions. Converting VGPR[414:415] to SGPR, and adjusting instructions. Converting VGPR[426:427] to SGPR, and adjusting instructions. Converting VGPR446 to SGPR, and adjusting instructions. Converting VGPR[457:459] to SGPR, and adjusting instructions. Converting VGPR489 to SGPR, and adjusting instructions. Converting VGPR490 to SGPR, and adjusting instructions. Converting VGPR[497:499] to SGPR, and adjusting instructions. Converting VGPR[502:504] to SGPR, and adjusting instructions. Converting VGPR[507:509] to SGPR, and adjusting instructions. Converting VGPR[512:514] to SGPR, and adjusting instructions. Converting VGPR[517:519] to SGPR, and adjusting instructions. Converting VGPR[522:524] to SGPR, and adjusting instructions. Converting VGPR[529:531] to SGPR, and adjusting instructions. Converting VGPR[534:536] to SGPR, and adjusting instructions. Converting VGPR[539:541] to SGPR, and adjusting instructions. Converting VGPR[544:546] to SGPR, and adjusting instructions. Converting VGPR[549:551] to SGPR, and adjusting instructions. Converting VGPR599 to SGPR, and adjusting instructions. VGPR=>SGPR conversions done. Register lifetime ranges REG NAME START END SGPR[0:1] 0 2030 fixed SGPR2 0 2030 fixed SGPR3 0 2030 fixed SGPR[4:5] 0 2030 fixed SGPR[6:7] 0 2030 fixed SGPR8 0 2030 fixed SGPR[10:11] 0 2030 keep-active SGPR12 0 2030 keep-active SGPR13 0 2030 keep-active SGPR[14:15] 0 2030 keep-active SGPR[16:17] 0 2030 keep-active SGPR18 135 192 SGPR19 71 189 SGPR[20:21] 67 67 SGPR[22:23] 0 2030 keep-active SGPR24 198 226 SGPR25 0 2030 keep-active SGPR[26:27] 140 140 SGPR[28:29] 0 2030 keep-active SGPR[30:31] 0 2030 keep-active SGPR32 0 2030 keep-active SGPR33 0 2030 keep-active SGPR34 0 2030 keep-active SGPR[36:37] 203 203 SGPR[38:39] 0 2030 keep-active SGPR[40:41] 0 2030 keep-active SGPR42 0 2030 keep-active SGPR43 0 2030 keep-active SGPR44 0 2030 keep-active SGPR[46:47] 244 244 SGPR[48:49] 0 2030 keep-active SGPR50 0 2030 keep-active SGPR51 0 2030 keep-active SGPR52 0 2030 keep-active SGPR[54:55] 263 263 SGPR[56:57] 0 2030 keep-active SGPR58 0 2030 keep-active SGPR59 0 2030 keep-active SGPR60 0 2030 keep-active SGPR[62:63] 326 372 SGPR[64:65] 338 343 SGPR[66:67] 340 371 SGPR[68:69] 0 2030 keep-active SGPR70 506 538 SGPR71 0 2030 keep-active SGPR[72:73] 381 381 SGPR[74:75] 0 2030 keep-active SGPR[76:77] 0 2030 keep-active SGPR[78:79] 0 2030 keep-active SGPR[80:81] 0 2030 keep-active SGPR[82:83] 0 2030 keep-active SGPR84 0 2030 keep-active SGPR85 0 2030 keep-active SGPR[86:87] 0 2030 keep-active SGPR[88:89] 0 2030 keep-active SGPR[90:91] 0 2030 keep-active SGPR[92:93] 0 2030 keep-active SGPR[94:95] 0 2030 keep-active SGPR[96:97] 559 562 SGPR[98:99] 0 2030 keep-active SGPR100 623 626 SGPR[102:103] 636 641 SGPR[104:105] 0 2030 keep-active SGPR[106:107] 0 2030 keep-active SGPR[108:109] 0 2030 keep-active SGPR[110:111] 0 2030 keep-active SGPR112 0 2030 keep-active SGPR113 0 2030 keep-active SGPR114 0 2030 keep-active SGPR[116:117] 0 2030 keep-active SGPR[118:119] 0 2030 keep-active SGPR[120:121] 0 2030 keep-active SGPR[122:123] 0 2030 keep-active SGPR[124:125] 749 752 SGPR[126:127] 0 2030 keep-active SGPR[128:129] 800 806 SGPR[130:131] 804 806 SGPR[132:133] 806 811 SGPR[134:135] 808 822 SGPR[136:137] 0 2030 keep-active SGPR138 0 2030 keep-active SGPR139 0 2030 keep-active SGPR140 0 2030 keep-active SGPR141 0 2030 keep-active SGPR[142:143] 0 2030 keep-active SGPR[144:145] 0 2030 keep-active SGPR[146:147] 0 2030 keep-active SGPR[148:149] 0 2030 keep-active SGPR[150:151] 912 915 SGPR[152:153] 0 2030 keep-active SGPR[154:155] 963 969 SGPR[156:157] 967 969 SGPR[158:159] 969 974 SGPR[160:161] 971 985 SGPR[162:163] 1008 1012 SGPR[164:165] 1010 1024 SGPR[166:167] 0 2030 keep-active SGPR168 0 2030 keep-active SGPR169 0 2030 keep-active SGPR[170:171] 1032 1032 SGPR[172:173] 0 2030 keep-active SGPR[174:175] 0 2030 keep-active SGPR[176:177] 0 2030 keep-active SGPR[178:179] 0 2030 keep-active SGPR[180:181] 0 2030 keep-active SGPR[182:183] 0 2030 keep-active SGPR[184:185] 0 2030 keep-active SGPR186 0 2030 keep-active SGPR187 0 2030 keep-active SGPR188 0 2030 keep-active SGPR[190:191] 0 2030 keep-active SGPR[192:193] 0 2030 keep-active SGPR[194:195] 0 2030 keep-active SGPR[196:197] 0 2030 keep-active SGPR[198:199] 1253 1256 SGPR[200:201] 1265 1271 SGPR[202:207] 1269 1274 SGPR[208:209] 1273 1277 SGPR[210:211] 1275 1292 SGPR[212:213] 0 2030 keep-active SGPR[214:215] 1352 1358 SGPR[216:221] 1356 1361 SGPR[222:223] 1360 1364 SGPR[224:225] 1362 1379 SGPR[226:227] 0 2030 keep-active SGPR228 0 2030 keep-active SGPR229 0 2030 keep-active SGPR[230:231] 1426 1756 SGPR[232:233] 1434 1439 SGPR[234:235] 1436 1455 SGPR[236:237] 1462 1467 SGPR[238:239] 1464 1483 SGPR[240:241] 1490 1495 SGPR[242:243] 1492 1511 SGPR[244:245] 1518 1523 SGPR[246:247] 1520 1539 SGPR[248:249] 1546 1551 SGPR[250:251] 1548 1567 SGPR[252:253] 1574 1579 SGPR[254:255] 1576 1595 SGPR[256:257] 1602 1607 SGPR[258:259] 1604 1615 SGPR[260:261] 1622 1627 SGPR[262:263] 1624 1643 SGPR[264:265] 1650 1655 SGPR[266:267] 1652 1671 SGPR[268:269] 1678 1683 SGPR[270:271] 1680 1699 SGPR[272:273] 1706 1711 SGPR[274:275] 1708 1727 SGPR[276:277] 1734 1739 SGPR[278:279] 1736 1755 SGPR[280:282] 1760 1762 SGPR[284:285] 0 2030 keep-active SGPR286 1770 1774 SGPR[288:290] 1780 1786 SGPR291 1796 1800 SGPR292 1809 1812 SGPR293 1820 1824 SGPR[294:295] 0 2030 keep-active SGPR[296:297] 0 2030 keep-active SGPR[298:299] 1897 1902 SGPR[300:301] 0 2030 keep-active SGPR[302:303] 0 2030 keep-active SGPR[304:305] 0 2030 keep-active SGPR[306:308] 0 2030 keep-active SGPR[309:311] 6 11 SGPR[312:314] 0 2030 keep-active SGPR[315:317] 13 18 SGPR[318:320] 0 2030 keep-active SGPR[321:323] 20 25 SGPR[324:326] 0 2030 keep-active SGPR[327:329] 27 32 SGPR330 307 308 SGPR331 309 310 SGPR[332:333] 385 388 SGPR[334:335] 418 421 SGPR[336:337] 447 450 SGPR338 479 480 SGPR339 0 2030 keep-active SGPR340 515 516 SGPR[341:342] 518 521 SGPR343 523 524 SGPR344 611 612 SGPR345 612 614 SGPR346 648 649 SGPR347 680 681 SGPR348 0 2030 keep-active SGPR349 727 728 SGPR350 730 731 SGPR351 733 734 SGPR352 837 838 SGPR353 838 840 SGPR354 0 2030 keep-active SGPR355 893 894 SGPR356 896 897 SGPR357 994 995 SGPR358 995 997 SGPR359 1015 1016 SGPR[360:361] 1041 1045 SGPR[362:363] 1069 1073 SGPR[364:365] 1099 1103 SGPR[366:367] 1127 1131 SGPR[368:369] 1157 1161 SGPR[370:371] 1185 1189 SGPR372 0 2030 keep-active SGPR[373:375] 1233 1238 SGPR376 1401 1402 SGPR377 1402 1404 SGPR[378:380] 1444 1450 SGPR[381:383] 1472 1478 SGPR[384:386] 1500 1506 SGPR[387:389] 1528 1534 SGPR[390:392] 1556 1562 SGPR[393:395] 1584 1590 SGPR[396:398] 1632 1638 SGPR[399:401] 1660 1666 SGPR[402:404] 1688 1694 SGPR[405:407] 1716 1722 SGPR[408:410] 1744 1750 SGPR411 1829 1830 VGPR[0:1] 0 2030 fixed VGPR[0:1] 0 2030 fixed VGPR[4:5] 0 2030 fixed VGPR[6:7] 0 2030 fixed VGPR[8:9] 0 2030 fixed VGPR[10:11] 0 2030 fixed VGPR12 0 2030 fixed VGPR[2:5] 0 2030 fixed VGPR17 0 2030 fixed VGPR[18:21] 0 2030 keep-active VGPR[22:23] 0 2030 keep-active VGPR[48:51] 34 40 VGPR[52:53] 39 43 VGPR[54:57] 55 62 VGPR[58:60] 72 78 VGPR[61:63] 76 83 VGPR64 87 93 VGPR65 91 93 VGPR66 93 115 VGPR67 97 103 VGPR68 101 103 VGPR69 103 116 VGPR70 107 113 VGPR71 111 113 VGPR72 113 117 VGPR[73:75] 115 126 VGPR76 120 130 VGPR77 123 128 VGPR78 126 128 VGPR79 128 130 VGPR80 130 133 VGPR81 132 133 VGPR82 133 136 VGPR[83:85] 0 2030 keep-active VGPR[86:88] 145 155 VGPR[89:91] 149 155 VGPR[92:94] 153 175 VGPR[95:97] 157 175 VGPR[98:100] 161 183 VGPR[101:103] 177 183 VGPR[104:106] 181 187 VGPR107 0 2030 keep-active VGPR[108:110] 0 2030 keep-active VGPR[111:113] 208 217 VGPR114 213 217 VGPR[115:117] 215 221 VGPR118 0 2030 keep-active VGPR119 233 237 VGPR120 235 240 VGPR121 249 256 VGPR122 252 254 VGPR123 254 256 VGPR124 256 259 VGPR[125:127] 268 273 VGPR[128:129] 272 276 VGPR130 275 283 VGPR131 281 284 VGPR[132:133] 283 287 VGPR[134:135] 286 294 VGPR[136:137] 290 294 VGPR[138:139] 293 313 VGPR140 297 302 VGPR141 300 302 VGPR142 302 305 VGPR143 304 305 VGPR144 305 319 VGPR[145:146] 308 313 VGPR[149:150] 312 316 VGPR151 315 319 VGPR152 319 322 VGPR[153:154] 352 377 VGPR155 332 338 VGPR156 336 338 VGPR[157:158] 349 353 VGPR[159:160] 362 366 VGPR[161:162] 0 2030 keep-active VGPR[163:165] 0 2030 keep-active VGPR[166:167] 0 2030 keep-active VGPR[168:170] 0 2030 keep-active VGPR[171:172] 0 2030 keep-active VGPR173 0 2030 keep-active VGPR174 0 2030 keep-active VGPR[175:176] 0 2030 keep-active VGPR[177:178] 0 2030 keep-active VGPR181 392 399 VGPR182 394 399 VGPR183 395 403 VGPR[184:186] 406 412 VGPR[187:189] 410 416 VGPR192 0 2030 keep-active VGPR[193:195] 435 441 VGPR[196:198] 439 445 VGPR201 0 2030 keep-active VGPR202 0 2030 keep-active VGPR[203:204] 478 487 VGPR[206:207] 0 2030 keep-active VGPR208 504 507 VGPR209 0 2030 keep-active VGPR[210:211] 0 2030 keep-active VGPR212 0 2030 keep-active VGPR[213:215] 0 2030 keep-active VGPR[217:219] 0 2030 keep-active VGPR220 0 2030 keep-active VGPR[221:222] 0 2030 keep-active VGPR[223:224] 0 2030 keep-active VGPR[225:226] 0 2030 keep-active VGPR[227:228] 0 2030 keep-active VGPR[233:235] 527 533 VGPR236 0 2030 keep-active VGPR237 558 559 VGPR[238:240] 571 577 VGPR241 0 2030 keep-active VGPR242 593 595 VGPR243 595 597 VGPR244 600 601 VGPR245 601 603 VGPR248 626 633 VGPR249 628 633 VGPR250 629 636 VGPR251 635 636 VGPR[252:253] 647 656 VGPR[255:256] 0 2030 keep-active VGPR[257:258] 679 688 VGPR[260:261] 0 2030 keep-active VGPR262 711 713 VGPR263 0 2030 keep-active VGPR264 716 719 VGPR265 0 2030 keep-active VGPR266 0 2030 keep-active VGPR267 0 2030 keep-active VGPR[269:271] 0 2030 keep-active VGPR275 748 749 VGPR[276:278] 760 776 VGPR[279:281] 766 772 VGPR[282:284] 770 776 VGPR[285:287] 774 780 VGPR288 0 2030 keep-active VGPR289 794 796 VGPR290 799 800 VGPR291 803 804 VGPR292 826 827 VGPR293 827 829 VGPR296 851 854 VGPR297 852 857 VGPR[298:299] 856 861 VGPR300 0 2030 keep-active VGPR301 0 2030 keep-active VGPR[303:305] 0 2030 keep-active VGPR[306:308] 870 877 VGPR[309:311] 875 886 VGPR312 874 877 VGPR[313:315] 880 886 VGPR[316:318] 884 891 VGPR321 911 912 VGPR[322:324] 923 939 VGPR[325:327] 929 935 VGPR[328:330] 933 939 VGPR[331:333] 937 943 VGPR334 0 2030 keep-active VGPR335 957 959 VGPR336 962 963 VGPR337 966 967 VGPR340 1007 1008 VGPR341 1016 1028 VGPR[343:345] 0 2030 keep-active VGPR[346:348] 0 2030 keep-active VGPR[349:351] 0 2030 keep-active VGPR[352:354] 0 2030 keep-active VGPR[355:357] 0 2030 keep-active VGPR[358:360] 0 2030 keep-active VGPR[361:363] 1037 1049 VGPR[366:368] 1043 1049 VGPR[369:371] 1047 1053 VGPR372 0 2030 keep-active VGPR[373:375] 1065 1077 VGPR[378:380] 1071 1077 VGPR[381:383] 1075 1081 VGPR384 0 2030 keep-active VGPR385 0 2030 keep-active VGPR[386:388] 1095 1107 VGPR[391:393] 1101 1107 VGPR[394:396] 1105 1111 VGPR397 0 2030 keep-active VGPR[398:400] 1123 1135 VGPR[403:405] 1129 1135 VGPR[406:408] 1133 1139 VGPR409 0 2030 keep-active VGPR410 0 2030 keep-active VGPR[411:413] 1153 1165 VGPR[416:418] 1159 1165 VGPR[419:421] 1163 1169 VGPR422 0 2030 keep-active VGPR[423:425] 1181 1193 VGPR[428:430] 1187 1193 VGPR[431:433] 1191 1197 VGPR434 0 2030 keep-active VGPR435 1208 1212 VGPR[436:438] 1210 1220 VGPR439 1214 1220 VGPR[440:442] 1218 1225 VGPR[443:445] 0 2030 keep-active VGPR447 0 2030 keep-active VGPR[448:450] 0 2030 keep-active VGPR[451:453] 0 2030 keep-active VGPR[454:456] 0 2030 keep-active VGPR460 1252 1253 VGPR461 1264 1265 VGPR[462:464] 1280 1329 VGPR[465:467] 1296 1302 VGPR468 1300 1305 VGPR469 1304 1305 VGPR470 1305 1307 VGPR[471:473] 1310 1316 VGPR[474:476] 1319 1325 VGPR477 0 2030 keep-active VGPR478 1345 1347 VGPR479 1351 1352 VGPR[480:482] 1367 1384 VGPR[483:485] 1382 1389 VGPR[486:488] 1387 1393 VGPR[491:493] 1415 1422 VGPR494 1414 1417 VGPR495 1431 1434 VGPR496 1433 1434 VGPR500 1459 1462 VGPR501 1461 1462 VGPR505 1487 1490 VGPR506 1489 1490 VGPR510 1515 1518 VGPR511 1517 1518 VGPR515 1543 1546 VGPR516 1545 1546 VGPR520 1571 1574 VGPR521 1573 1574 VGPR525 1599 1602 VGPR526 1601 1602 VGPR527 1619 1622 VGPR528 1621 1622 VGPR532 1647 1650 VGPR533 1649 1650 VGPR537 1675 1678 VGPR538 1677 1678 VGPR542 1703 1706 VGPR543 1705 1706 VGPR547 1731 1734 VGPR548 1733 1734 VGPR[552:554] 0 2030 keep-active VGPR[555:557] 0 2030 keep-active VGPR[558:560] 0 2030 keep-active VGPR[561:563] 0 2030 keep-active VGPR[564:566] 1926 1962 VGPR[567:569] 0 2030 keep-active VGPR[570:572] 0 2030 keep-active VGPR573 0 2030 keep-active VGPR574 1773 1774 VGPR575 1774 1774 VGPR[576:577] 1777 1793 VGPR[578:579] 1785 1790 VGPR[580:581] 1789 1793 VGPR582 1788 1790 VGPR[583:584] 1792 1807 VGPR[585:586] 1799 1807 VGPR[587:588] 0 2030 keep-active VGPR589 1812 1816 VGPR590 1816 1818 VGPR591 1818 1831 VGPR592 1823 1824 VGPR593 1824 1827 VGPR594 1826 1827 VGPR595 1827 1832 VGPR[596:598] 0 2030 keep-active VGPR600 1834 1838 VGPR601 1836 1839 VGPR[602:604] 1838 1848 VGPR605 1842 1848 VGPR[606:608] 0 2030 keep-active VGPR[609:610] 0 2030 keep-active VGPR611 1870 1874 VGPR[612:614] 1872 1878 VGPR[615:617] 0 2030 keep-active VGPR[618:620] 0 2030 keep-active VGPR621 1894 1897 VGPR622 1896 1897 VGPR[623:625] 0 2030 keep-active VGPR626 1936 1940 VGPR627 1940 1943 VGPR628 1942 1943 VGPR629 1943 1947 VGPR[630:632] 1945 1951 VGPR633 1965 1967 VGPR[634:636] 0 2030 keep-active VGPR[637:639] 1979 1985 VGPR640 1988 1991 VGPR641 1990 1992 VGPR642 1991 1998 VGPR[643:645] 1996 2002 VGPR[646:648] 2000 2006 VGPR[649:651] 2009 2017 VGPR652 2013 2019 VGPR653 2015 2020 VGPR654 2017 2021 VGPR[655:658] 2019 2028 VGPR659 1812 1812 Register final registers REG NAME START END SGPR[0:1] 0 2030 fixed SGPR2 0 2030 fixed SGPR3 0 2030 fixed SGPR[4:5] 0 2030 fixed SGPR[6:7] 0 2030 fixed SGPR8 0 2030 fixed SGPR9 0 2030 keep-active SGPR[10:11] 0 2030 keep-active SGPR12 0 2030 keep-active SGPR13 0 2030 keep-active SGPR[14:15] 0 2030 keep-active SGPR[16:17] 0 2030 keep-active SGPR[18:19] 0 2030 keep-active SGPR[20:21] 0 2030 keep-active SGPR[22:23] 0 2030 keep-active SGPR24 0 2030 keep-active SGPR25 0 2030 keep-active SGPR26 0 2030 keep-active SGPR27 0 2030 keep-active SGPR[28:29] 0 2030 keep-active SGPR[30:31] 0 2030 keep-active SGPR32 0 2030 keep-active SGPR33 0 2030 keep-active SGPR[34:35] 0 2030 keep-active SGPR36 0 2030 keep-active SGPR37 0 2030 keep-active SGPR38 0 2030 keep-active SGPR39 0 2030 keep-active SGPR[40:41] 0 2030 keep-active SGPR42 0 2030 keep-active SGPR43 0 2030 keep-active SGPR[44:45] 0 2030 keep-active SGPR46 0 2030 keep-active SGPR47 0 2030 keep-active SGPR[48:49] 0 2030 keep-active SGPR[50:51] 0 2030 keep-active SGPR[52:53] 0 2030 keep-active SGPR[54:55] 0 2030 keep-active SGPR[56:57] 0 2030 keep-active SGPR58 0 2030 keep-active SGPR59 0 2030 keep-active SGPR[60:61] 0 2030 keep-active SGPR[62:63] 0 2030 keep-active SGPR[64:65] 0 2030 keep-active SGPR[66:67] 0 2030 keep-active SGPR[68:69] 0 2030 keep-active SGPR[70:71] 0 2030 keep-active SGPR[72:73] 0 2030 keep-active SGPR[74:75] 0 2030 keep-active SGPR[76:77] 0 2030 keep-active SGPR[78:79] 0 2030 keep-active SGPR80 0 2030 keep-active SGPR81 0 2030 keep-active SGPR[82:83] 0 2030 keep-active SGPR[84:85] 0 2030 keep-active SGPR[86:87] 0 2030 keep-active SGPR[88:89] 0 2030 keep-active SGPR[90:91] 0 2030 keep-active SGPR[92:93] 0 2030 keep-active SGPR94 0 2030 keep-active SGPR95 0 2030 keep-active SGPR96 0 2030 keep-active SGPR97 0 2030 keep-active SGPR[98:99] 0 2030 keep-active SGPR[100:101] 0 2030 keep-active SGPR[102:103] 0 2030 keep-active SGPR[104:105] 0 2030 keep-active SGPR[106:107] 0 2030 keep-active SGPR[108:109] 0 2030 keep-active SGPR110 0 2030 keep-active SGPR111 0 2030 keep-active SGPR[112:113] 0 2030 keep-active SGPR[114:115] 0 2030 keep-active SGPR[116:117] 0 2030 keep-active SGPR[118:119] 0 2030 keep-active SGPR[120:121] 0 2030 keep-active SGPR[122:123] 0 2030 keep-active SGPR[124:125] 0 2030 keep-active SGPR126 0 2030 keep-active SGPR127 0 2030 keep-active SGPR128 0 2030 keep-active SGPR129 0 2030 keep-active SGPR[130:131] 0 2030 keep-active SGPR[132:133] 0 2030 keep-active SGPR[134:135] 0 2030 keep-active SGPR[136:137] 0 2030 keep-active SGPR[138:139] 0 2030 keep-active SGPR[140:141] 0 2030 keep-active SGPR142 0 2030 keep-active SGPR143 0 2030 keep-active SGPR[144:145] 0 2030 keep-active SGPR[146:147] 0 2030 keep-active SGPR[148:149] 0 2030 keep-active SGPR[150:151] 0 2030 keep-active SGPR[152:153] 0 2030 keep-active SGPR[154:155] 0 2030 keep-active SGPR[156:158] 0 2030 keep-active SGPR[159:161] 0 2030 keep-active SGPR[162:164] 0 2030 keep-active SGPR[165:167] 0 2030 keep-active SGPR168 0 2030 keep-active SGPR169 0 2030 keep-active SGPR170 0 2030 keep-active SGPR[171:173] 6 11 SGPR[171:173] 13 18 SGPR[171:173] 20 25 SGPR[171:173] 27 32 SGPR171 71 189 SGPR171 198 226 SGPR171 307 308 SGPR171 309 310 SGPR[171:172] 385 388 SGPR[171:172] 418 421 SGPR[171:172] 447 450 SGPR171 479 480 SGPR171 506 538 SGPR171 611 612 SGPR171 623 626 SGPR171 648 649 SGPR171 680 681 SGPR171 727 728 SGPR171 730 731 SGPR171 733 734 SGPR171 837 838 SGPR171 893 894 SGPR171 896 897 SGPR171 994 995 SGPR171 1015 1016 SGPR[171:172] 1041 1045 SGPR[171:172] 1069 1073 SGPR[171:172] 1099 1103 SGPR[171:172] 1127 1131 SGPR[171:172] 1157 1161 SGPR[171:172] 1185 1189 SGPR[171:173] 1233 1238 SGPR[171:172] 1273 1277 SGPR[171:172] 1360 1364 SGPR171 1401 1402 SGPR[171:173] 1444 1450 SGPR[171:173] 1472 1478 SGPR[171:173] 1500 1506 SGPR[171:173] 1528 1534 SGPR[171:173] 1556 1562 SGPR[171:173] 1584 1590 SGPR[171:173] 1632 1638 SGPR[171:173] 1660 1666 SGPR[171:173] 1688 1694 SGPR[171:173] 1716 1722 SGPR[171:173] 1744 1750 SGPR[171:173] 1760 1762 SGPR171 1770 1774 SGPR171 1796 1800 SGPR171 1809 1812 SGPR171 1820 1824 SGPR171 1829 1830 SGPR[172:173] 67 67 SGPR172 135 192 SGPR[172:173] 203 203 SGPR[172:173] 263 263 SGPR[172:173] 326 372 SGPR[172:173] 381 381 SGPR172 515 516 SGPR[172:173] 518 521 SGPR172 523 524 SGPR172 612 614 SGPR[172:173] 749 752 SGPR[172:173] 800 806 SGPR[172:173] 808 822 SGPR172 838 840 SGPR[172:173] 963 969 SGPR[172:173] 971 985 SGPR172 995 997 SGPR[172:173] 1010 1024 SGPR[172:173] 1253 1256 SGPR[172:173] 1265 1271 SGPR[172:173] 1352 1358 SGPR172 1402 1404 SGPR[172:173] 1434 1439 SGPR[172:173] 1462 1467 SGPR[172:173] 1490 1495 SGPR[172:173] 1518 1523 SGPR[172:173] 1546 1551 SGPR[172:173] 1574 1579 SGPR[172:173] 1602 1607 SGPR[172:173] 1622 1627 SGPR[172:173] 1650 1655 SGPR[172:173] 1678 1683 SGPR[172:173] 1706 1711 SGPR[172:173] 1734 1739 SGPR[172:174] 1780 1786 SGPR[172:173] 1897 1902 SGPR[174:175] 140 140 SGPR[174:175] 244 244 SGPR[174:175] 338 343 SGPR[174:175] 559 562 SGPR[174:175] 636 641 SGPR[174:175] 804 806 SGPR[174:175] 912 915 SGPR[174:175] 967 969 SGPR[174:175] 1008 1012 SGPR[174:175] 1032 1032 SGPR[174:179] 1269 1274 SGPR[174:175] 1275 1292 SGPR[174:179] 1356 1361 SGPR[174:175] 1362 1379 SGPR[174:175] 1426 1756 SGPR[176:177] 340 371 SGPR[176:177] 806 811 SGPR[176:177] 969 974 SGPR[176:177] 1436 1455 SGPR[176:177] 1464 1483 SGPR[176:177] 1492 1511 SGPR[176:177] 1520 1539 SGPR[176:177] 1548 1567 SGPR[176:177] 1576 1595 SGPR[176:177] 1604 1615 SGPR[176:177] 1624 1643 SGPR[176:177] 1652 1671 SGPR[176:177] 1680 1699 SGPR[176:177] 1708 1727 SGPR[176:177] 1736 1755 VGPR[0:1] 0 2030 fixed VGPR[0:1] 0 2030 fixed VGPR[2:5] 0 2030 fixed VGPR[4:5] 0 2030 fixed VGPR[6:7] 0 2030 fixed VGPR[8:9] 0 2030 fixed VGPR[10:11] 0 2030 fixed VGPR12 0 2030 fixed VGPR[13:16] 0 2030 keep-active VGPR17 0 2030 fixed VGPR[18:19] 0 2030 keep-active VGPR[20:22] 0 2030 keep-active VGPR23 0 2030 keep-active VGPR[24:26] 0 2030 keep-active VGPR27 0 2030 keep-active VGPR[28:29] 0 2030 keep-active VGPR[30:32] 0 2030 keep-active VGPR[33:34] 0 2030 keep-active VGPR[35:37] 0 2030 keep-active VGPR[38:39] 0 2030 keep-active VGPR40 0 2030 keep-active VGPR41 0 2030 keep-active VGPR[42:43] 0 2030 keep-active VGPR[44:45] 0 2030 keep-active VGPR46 0 2030 keep-active VGPR47 0 2030 keep-active VGPR48 0 2030 keep-active VGPR[49:50] 0 2030 keep-active VGPR51 0 2030 keep-active VGPR[52:53] 0 2030 keep-active VGPR54 0 2030 keep-active VGPR[55:57] 0 2030 keep-active VGPR[58:60] 0 2030 keep-active VGPR61 0 2030 keep-active VGPR[62:63] 0 2030 keep-active VGPR[64:65] 0 2030 keep-active VGPR[66:67] 0 2030 keep-active VGPR[68:69] 0 2030 keep-active VGPR70 0 2030 keep-active VGPR71 0 2030 keep-active VGPR[72:73] 0 2030 keep-active VGPR[74:75] 0 2030 keep-active VGPR76 0 2030 keep-active VGPR77 0 2030 keep-active VGPR78 0 2030 keep-active VGPR79 0 2030 keep-active VGPR[80:82] 0 2030 keep-active VGPR83 0 2030 keep-active VGPR84 0 2030 keep-active VGPR85 0 2030 keep-active VGPR[86:88] 0 2030 keep-active VGPR89 0 2030 keep-active VGPR[90:92] 0 2030 keep-active VGPR[93:95] 0 2030 keep-active VGPR[96:98] 0 2030 keep-active VGPR[99:101] 0 2030 keep-active VGPR[102:104] 0 2030 keep-active VGPR[105:107] 0 2030 keep-active VGPR108 0 2030 keep-active VGPR109 0 2030 keep-active VGPR110 0 2030 keep-active VGPR111 0 2030 keep-active VGPR112 0 2030 keep-active VGPR113 0 2030 keep-active VGPR114 0 2030 keep-active VGPR115 0 2030 keep-active VGPR[116:118] 0 2030 keep-active VGPR119 0 2030 keep-active VGPR[120:122] 0 2030 keep-active VGPR[123:125] 0 2030 keep-active VGPR[126:128] 0 2030 keep-active VGPR129 0 2030 keep-active VGPR[130:132] 0 2030 keep-active VGPR[133:135] 0 2030 keep-active VGPR[136:138] 0 2030 keep-active VGPR[139:141] 0 2030 keep-active VGPR[142:144] 0 2030 keep-active VGPR[145:147] 0 2030 keep-active VGPR148 0 2030 keep-active VGPR[149:150] 0 2030 keep-active VGPR[151:153] 0 2030 keep-active VGPR[154:156] 0 2030 keep-active VGPR[157:158] 0 2030 keep-active VGPR[159:161] 0 2030 keep-active VGPR[162:164] 0 2030 keep-active VGPR[165:167] 0 2030 keep-active VGPR[168:170] 0 2030 keep-active VGPR[171:174] 34 40 VGPR[171:174] 55 62 VGPR[171:173] 72 78 VGPR171 87 93 VGPR171 97 103 VGPR171 107 113 VGPR171 120 130 VGPR171 132 133 VGPR[171:173] 145 155 VGPR[171:173] 157 175 VGPR[171:173] 177 183 VGPR[171:173] 208 217 VGPR171 233 237 VGPR171 249 256 VGPR[171:173] 268 273 VGPR171 275 283 VGPR[171:172] 290 294 VGPR171 297 302 VGPR171 304 305 VGPR171 315 319 VGPR171 332 338 VGPR[171:172] 349 353 VGPR[171:172] 362 366 VGPR171 392 399 VGPR[171:173] 406 412 VGPR[171:173] 435 441 VGPR[171:172] 478 487 VGPR171 504 507 VGPR[171:173] 527 533 VGPR171 558 559 VGPR[171:173] 571 577 VGPR171 593 595 VGPR171 600 601 VGPR171 626 633 VGPR171 635 636 VGPR[171:172] 647 656 VGPR[171:172] 679 688 VGPR171 711 713 VGPR171 716 719 VGPR171 748 749 VGPR[171:173] 760 776 VGPR171 794 796 VGPR171 799 800 VGPR171 803 804 VGPR171 826 827 VGPR171 851 854 VGPR171 874 877 VGPR171 911 912 VGPR[171:173] 923 939 VGPR171 957 959 VGPR171 962 963 VGPR171 966 967 VGPR171 1007 1008 VGPR171 1016 1028 VGPR[171:173] 1037 1049 VGPR[171:173] 1065 1077 VGPR[171:173] 1095 1107 VGPR[171:173] 1123 1135 VGPR[171:173] 1153 1165 VGPR[171:173] 1181 1193 VGPR171 1208 1212 VGPR171 1214 1220 VGPR171 1252 1253 VGPR171 1264 1265 VGPR[171:173] 1280 1329 VGPR171 1345 1347 VGPR171 1351 1352 VGPR[171:173] 1367 1384 VGPR[171:173] 1387 1393 VGPR171 1414 1417 VGPR171 1431 1434 VGPR171 1459 1462 VGPR171 1487 1490 VGPR171 1515 1518 VGPR171 1543 1546 VGPR171 1571 1574 VGPR171 1599 1602 VGPR171 1619 1622 VGPR171 1647 1650 VGPR171 1675 1678 VGPR171 1703 1706 VGPR171 1731 1734 VGPR171 1773 1774 VGPR[171:172] 1785 1790 VGPR[171:172] 1792 1807 VGPR171 1812 1812 VGPR171 1816 1818 VGPR171 1823 1824 VGPR171 1826 1827 VGPR171 1834 1838 VGPR171 1842 1848 VGPR171 1870 1874 VGPR171 1894 1897 VGPR171 1936 1940 VGPR171 1942 1943 VGPR171 1965 1967 VGPR[171:173] 1979 1985 VGPR171 1988 1991 VGPR[171:173] 2009 2017 VGPR172 91 93 VGPR172 101 103 VGPR172 111 113 VGPR172 123 128 VGPR172 130 133 VGPR172 235 240 VGPR172 252 254 VGPR172 256 259 VGPR172 281 284 VGPR172 300 302 VGPR172 305 319 VGPR172 336 338 VGPR172 394 399 VGPR172 595 597 VGPR172 601 603 VGPR172 628 633 VGPR172 827 829 VGPR172 852 857 VGPR[172:174] 875 886 VGPR[172:174] 1210 1220 VGPR[172:174] 1415 1422 VGPR172 1433 1434 VGPR172 1461 1462 VGPR172 1489 1490 VGPR172 1517 1518 VGPR172 1545 1546 VGPR172 1573 1574 VGPR172 1601 1602 VGPR172 1621 1622 VGPR172 1649 1650 VGPR172 1677 1678 VGPR172 1705 1706 VGPR172 1733 1734 VGPR172 1774 1774 VGPR172 1812 1816 VGPR172 1818 1831 VGPR172 1836 1839 VGPR[172:174] 1872 1878 VGPR172 1896 1897 VGPR172 1940 1943 VGPR172 1990 1992 VGPR173 93 115 VGPR173 126 128 VGPR173 133 136 VGPR173 254 256 VGPR[173:174] 283 287 VGPR[173:174] 293 313 VGPR173 319 322 VGPR[173:174] 352 377 VGPR173 395 403 VGPR173 629 636 VGPR[173:174] 856 861 VGPR[173:174] 1777 1793 VGPR[173:174] 1799 1807 VGPR173 1824 1827 VGPR[173:175] 1838 1848 VGPR[173:175] 1926 1962 VGPR173 1991 1998 VGPR[174:176] 76 83 VGPR174 103 116 VGPR174 128 130 VGPR[174:176] 149 155 VGPR[174:176] 161 183 VGPR174 213 217 VGPR[174:175] 272 276 VGPR[174:176] 410 416 VGPR[174:176] 439 445 VGPR[174:176] 766 772 VGPR[174:176] 774 780 VGPR[174:176] 929 935 VGPR[174:176] 937 943 VGPR[174:176] 1043 1049 VGPR[174:176] 1071 1077 VGPR[174:176] 1101 1107 VGPR[174:176] 1129 1135 VGPR[174:176] 1159 1165 VGPR[174:176] 1187 1193 VGPR[174:176] 1296 1302 VGPR174 1304 1305 VGPR[174:176] 1310 1316 VGPR[174:176] 1319 1325 VGPR[174:176] 1382 1389 VGPR174 1827 1832 VGPR[174:176] 1996 2002 VGPR174 2013 2019 VGPR[175:176] 39 43 VGPR175 113 117 VGPR[175:177] 215 221 VGPR[175:176] 286 294 VGPR175 302 305 VGPR[175:176] 308 313 VGPR[175:177] 870 877 VGPR[175:177] 880 886 VGPR[175:177] 1218 1225 VGPR175 1305 1307 VGPR175 1788 1790 VGPR175 2015 2020 VGPR[176:178] 115 126 VGPR[176:177] 1789 1793 VGPR176 1943 1947 VGPR176 2017 2021 VGPR[177:179] 153 175 VGPR[177:179] 181 187 VGPR[177:178] 312 316 VGPR[177:179] 770 776 VGPR[177:179] 933 939 VGPR[177:179] 1047 1053 VGPR[177:179] 1075 1081 VGPR[177:179] 1105 1111 VGPR[177:179] 1133 1139 VGPR[177:179] 1163 1169 VGPR[177:179] 1191 1197 VGPR177 1300 1305 VGPR[177:179] 1945 1951 VGPR[177:179] 2000 2006 VGPR[177:180] 2019 2028 VGPR[178:180] 884 891 Linking branch instructions to their targets... Final disassembly: Program Type: Fragment Special Input Variables: offset: unset, size: 16, FloatVector4 gl_FragCoord BuiltIn(FragCoord) Textures: offset: 0, size: 4, Float iChannel0 offset: 1, size: 4, Float iChannel1 offset: 2, size: 4, Float iChannel2 offset: 3, size: 4, Float iChannel3 Output Variables: offset: 0, size: 16, FloatVector4 finalColor Uniform Constants: offset: 0, size: 4, Float iTime offset: 4, size: 12, FloatVector3 iResolution offset: 16, size: 16, FloatVector4 iMouse offset: 32, size: 16, FloatVector4 iDate offset: 48, size: 4, Float iFrame offset: 52, size: 48, FloatVector3 iChannelResolution[4] Private Global Variables: offset: unset, size: 12, FloatVector3 lDir0 offset: unset, size: 12, FloatVector3 lDir1 offset: unset, size: 12, FloatVector3 lCol0 offset: unset, size: 12, FloatVector3 lCol1 offset: unset, size: 4, Float NumCol Constants: Float const80: 0.408248 Float const81: 0.816497 FloatVector3 const82: {0.408248, 0.816497, 0.408248} Float const84: -0.408248 Float const85: -0.816497 FloatVector3 const86: {-0.408248, 0.408248, -0.816497} Float const88: 1 Float const89: 0.8 Float const90: 0.5 FloatVector3 const91: {1, 0.8, 0.5} Float const93: 0.6 FloatVector3 const94: {0.6, 0.8, 1} UInt32 const99: 0 UInt32 const102: 1 UInt32 const108: 2 Float const126: 0.333333 Float const134: 2 Float const174: 0 Float const199: 9999 FloatVector2 const200: {9999, 0} Float const206: 6 FloatVector2 const207: {6, 6} Float const214: 1.9 Float const215: 6.78 FloatVector2 const216: {1.9, 6.78} Float const229: 9 Float const240: 0.35 Float const242: 9999.9 FloatVector2 const243: {9999.9, 0} Float const245: -999 Int32 const250: 0 Int32 const257: 5 Float const267: 3 Int32 const271: 1 Float const277: 5 Float const279: 0.4 Float const284: 8 Float const292: 7 Float const308: 20 Int32 const317: 100 Float const329: 0.001 Float const343: 100 Float const348: 0.002 Int32 const362: 50 Float const385: 0.1 FloatVector2 const390: {0.001, 0} Float const435: 0.01 FloatVector3 const436: {0.01, 0.01, 0.01} Int32 const444: 2 Float const481: 0.7 FloatVector3 const489: {0, 0, 0} FloatVector3 const495: {0, 0, 1} FloatVector3 const501: {0, 1, 0} Int32 const504: 3 FloatVector3 const508: {0, 1, 1} Int32 const511: 4 FloatVector3 const515: {1, 0, 0} FloatVector3 const521: {1, 0, 1} Int32 const524: 6 Int32 const529: 7 FloatVector3 const533: {1, 1, 1} Int32 const536: 8 Float const540: 0.425 Float const541: 0.56 Float const542: 0.9 FloatVector3 const543: {0.425, 0.56, 0.9} Int32 const546: 9 FloatVector3 const550: {0.5, 0.6, 0.6} Int32 const553: 10 Int32 const559: 11 FloatVector3 const563: {0.5, 0.8, 0.9} Float const582: -1 Float const587: -5 UInt32 const670: 4 Int32 const681: 64 Float const682: 0.0001 Function Local Variables: offset: unset, size: 16, FloatVector4 main.param657 offset: unset, size: 8, FloatVector2 main.param658 offset: unset, size: 16, FloatVector4 main.fragColor offset: unset, size: 8, FloatVector2 main.fragCoord offset: unset, size: 12, FloatVector3 main.p offset: unset, size: 12, FloatVector3 sdCross(vf3;.p offset: unset, size: 12, FloatVector3 sdCrossRep(vf3;.param139 offset: unset, size: 12, FloatVector3 sdCrossRep(vf3;.p offset: unset, size: 4, Float sdCrossRep(vf3;.s offset: unset, size: 12, FloatVector3 sdCrossRepScale(vf3;f1;.param147 offset: unset, size: 4, Float sdCrossRepScale(vf3;f1;.distA offset: unset, size: 4, Float sdCrossRepScale(vf3;f1;.distB offset: unset, size: 12, FloatVector3 differenceSDF(f1;f1;.p offset: unset, size: 8, FloatVector2 differenceSDF(f1;f1;.h offset: unset, size: 8, FloatVector2 sdCylinder(vf3;vf2;.d1 offset: unset, size: 8, FloatVector2 sdCylinder(vf3;vf2;.d2 offset: unset, size: 8, FloatVector2 opU(vf2;vf2;.resp offset: unset, size: 12, FloatVector3 opU(vf2;vf2;.p offset: unset, size: 8, FloatVector2 diso(vf3;.res offset: unset, size: 12, FloatVector3 diso(vf3;.param208 offset: unset, size: 8, FloatVector2 diso(vf3;.param211 offset: unset, size: 12, FloatVector3 diso(vf3;.param217 offset: unset, size: 8, FloatVector2 diso(vf3;.param220 offset: unset, size: 4, Float diso(vf3;.param223 offset: unset, size: 4, Float diso(vf3;.param225 offset: unset, size: 8, FloatVector2 diso(vf3;.param231 offset: unset, size: 8, FloatVector2 diso(vf3;.param233 offset: unset, size: 12, FloatVector3 diso(vf3;.p offset: unset, size: 4, Float DE(vf3;.scale offset: unset, size: 8, FloatVector2 DE(vf3;.res offset: unset, size: 4, Float DE(vf3;.dist offset: unset, size: 12, FloatVector3 DE(vf3;.param246 offset: unset, size: 4, Int32 DE(vf3;.i offset: unset, size: 12, FloatVector3 DE(vf3;.param260 offset: unset, size: 4, Float DE(vf3;.param262 offset: unset, size: 8, FloatVector2 DE(vf3;.param286 offset: unset, size: 8, FloatVector2 DE(vf3;.param288 offset: unset, size: 8, FloatVector2 DE(vf3;.param294 offset: unset, size: 8, FloatVector2 DE(vf3;.param296 offset: unset, size: 12, FloatVector3 DE(vf3;.ro offset: unset, size: 12, FloatVector3 DE(vf3;.rd offset: unset, size: 4, Float march(vf3;vf3;.t offset: unset, size: 4, Float march(vf3;vf3;.d offset: unset, size: 4, Float march(vf3;vf3;.it offset: unset, size: 4, Int32 march(vf3;vf3;.i offset: unset, size: 12, FloatVector3 march(vf3;vf3;.param324 offset: unset, size: 12, FloatVector3 march(vf3;vf3;.p offset: unset, size: 12, FloatVector3 march(vf3;vf3;.n offset: unset, size: 12, FloatVector3 march(vf3;vf3;.ld offset: unset, size: 4, Float getShadow(vf3;vf3;vf3;.t offset: unset, size: 4, Float getShadow(vf3;vf3;vf3;.d offset: unset, size: 4, Int32 getShadow(vf3;vf3;vf3;.i offset: unset, size: 12, FloatVector3 getShadow(vf3;vf3;vf3;.param369 offset: unset, size: 12, FloatVector3 getShadow(vf3;vf3;vf3;.p offset: unset, size: 12, FloatVector3 getNorm(vf3;.param395 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param401 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param408 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param414 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param421 offset: unset, size: 12, FloatVector3 getNorm(vf3;.param427 offset: unset, size: 12, FloatVector3 getNorm(vf3;.p offset: unset, size: 12, FloatVector3 getNorm(vf3;.n offset: unset, size: 12, FloatVector3 light(vf3;vf3;.col offset: unset, size: 4, Int32 light(vf3;vf3;.i offset: unset, size: 4, Float light(vf3;vf3;.diff offset: unset, size: 12, FloatVector3 light(vf3;vf3;.param459 offset: unset, size: 12, FloatVector3 light(vf3;vf3;.param461 offset: unset, size: 12, FloatVector3 light(vf3;vf3;.param463 offset: unset, size: 4, Int32 light(vf3;vf3;.i offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param599 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param601 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param612 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.col offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.var616 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param622 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param624 offset: unset, size: 4, Int32 mainImage(vf4;vf2;.param637 Instructions: V_SUB_F32 vDst(VGPR3) src0(SGPR2) src1(VGPR3) // VOP2 # Void main() Function: Void main() # lb5 Label: lb5 # OpStore: : const82 >> lDir0 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3ed105ec S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x3f5105ec S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x3ed105ec S_MOV_B32 sDst(SGPR156) src0(SGPR171) S_MOV_B32 sDst(SGPR157) src0(SGPR172) S_MOV_B32 sDst(SGPR158) src0(SGPR173) # OpStore: : const86 >> lDir1 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0xbed105ec S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x3ed105ec S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0xbf5105ec S_MOV_B32 sDst(SGPR159) src0(SGPR171) S_MOV_B32 sDst(SGPR160) src0(SGPR172) S_MOV_B32 sDst(SGPR161) src0(SGPR173) # OpStore: : const91 >> lCol0 S_MOV_B32 sDst(SGPR171) src0(1_0_F) S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x3f4ccccd S_MOV_B32 sDst(SGPR173) src0(0_5_F) S_MOV_B32 sDst(SGPR162) src0(SGPR171) S_MOV_B32 sDst(SGPR163) src0(SGPR172) S_MOV_B32 sDst(SGPR164) src0(SGPR173) # OpStore: : const94 >> lCol1 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3f19999a S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x3f4ccccd S_MOV_B32 sDst(SGPR173) src0(1_0_F) S_MOV_B32 sDst(SGPR165) src0(SGPR171) S_MOV_B32 sDst(SGPR166) src0(SGPR172) S_MOV_B32 sDst(SGPR167) src0(SGPR173) # 659: OpLoad: FloatVector4: tmp659 << gl_FragCoord V_MOV_B32 vDst(VGPR171) src0(VGPR2) V_MOV_B32 vDst(VGPR172) src0(VGPR3) V_MOV_B32 vDst(VGPR173) src0(VGPR4) V_MOV_B32 vDst(VGPR174) src0(VGPR5) # 660: OpVectorShuffle: FloatVector2: tmp660 << tmp659, tmp659, 0, 1 V_MOV_B32 vDst(VGPR175) src0(VGPR171) V_MOV_B32 vDst(VGPR176) src0(VGPR172) # OpStore: : tmp660 >> param658 V_MOV_B32 vDst(VGPR18) src0(VGPR175) V_MOV_B32 vDst(VGPR19) src0(VGPR176) # 661: OpFunctionCall: Void: mainImage(vf4;vf2;(param657, param658) S_ADD_U32 sDst(SGPR9) src0(LITERAL_CONST) src1(0) const: 0xd # VGPR[18:21] S_ADD_U32 sDst(SGPR12) src0(LITERAL_CONST) src1(0) const: 0x12 # VGPR[22:23] S_MOV_B64 sDst(SGPR14) src0(EXEC) # Indirect branch to mainImage(vf4;vf2;: 5380 S_GETPC_B64 sDst(SGPR10) src0(SGPR10) S_ADD_U32 sDst(SGPR10) src0(SGPR10) src1(LITERAL_CONST) const: 0x1504 S_ADDC_U32 sDst(SGPR11) src0(SGPR11) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR10) src0(SGPR10) S_MOV_B64 sDst(EXEC) src0(SGPR14) # .lbl0 # 662: OpLoad: FloatVector4: tmp662 << param657 # OpStore: : tmp662 >> finalColor V_MOV_B32 vDst(VGPR171) src0(VGPR13) V_MOV_B32 vDst(VGPR172) src0(VGPR14) V_MOV_B32 vDst(VGPR173) src0(VGPR15) V_MOV_B32 vDst(VGPR174) src0(VGPR16) # OpReturn: V_CVT_PKRTZ_F16_F32 vDst(VGPR171) src0(VGPR171) src1(VGPR172) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_CVT_PKRTZ_F16_F32 vDst(VGPR172) src0(VGPR173) src1(VGPR174) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a EXP en(0xf) tgt(0) compr(1) done(1) vm(1) vsrc0(VGPR171) vsrc1(VGPR172) vsrc2(VGPR173) vsrc3(VGPR174) S_WAITCNT 0 S_ENDPGM 0 # Float sdCross(vf3;(FloatVector3* p) Function: Float sdCross(vf3;() S_MOV_B64 sDst(SGPR172) src0(EXEC) # lb12 Label: lb12 # 95: OpLoad: FloatVector3: tmp95 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR171) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 96: OpExtInst(FAbs): FloatVector3: tmp96 << tmp95 V_ADD_F32 vDst(VGPR174) src0(VGPR171) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR175) src0(VGPR172) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR176) src0(VGPR173) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp96 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR171) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR174) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR175) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR176) # 100: OpAccessChain: Float*: p[0] # 101: OpLoad: Float: tmp101 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR171) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 103: OpAccessChain: Float*: p[1] # 104: OpLoad: Float: tmp104 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR171) const: 0x0 V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) # 105: OpExtInst(FMax): Float: tmp105 << tmp101, tmp104 V_MAX_F32 vDst(VGPR173) src0(VGPR171) src1(VGPR172) // VOP2 # 106: OpAccessChain: Float*: p[1] # 107: OpLoad: Float: tmp107 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR171) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR1) # 109: OpAccessChain: Float*: p[2] # 110: OpLoad: Float: tmp110 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR171) const: 0x0 V_MOVRELS_B32 vDst(VGPR172) src0(VGPR2) # 111: OpExtInst(FMax): Float: tmp111 << tmp107, tmp110 V_MAX_F32 vDst(VGPR174) src0(VGPR171) src1(VGPR172) // VOP2 # 112: OpAccessChain: Float*: p[2] # 113: OpLoad: Float: tmp113 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR171) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR2) # 114: OpAccessChain: Float*: p[0] # 115: OpLoad: Float: tmp115 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR171) const: 0x0 V_MOVRELS_B32 vDst(VGPR172) src0(VGPR0) # 116: OpExtInst(FMax): Float: tmp116 << tmp113, tmp115 V_MAX_F32 vDst(VGPR175) src0(VGPR171) src1(VGPR172) // VOP2 # 117: OpCompositeConstruct: FloatVector3: tmp117 << tmp105, tmp111, tmp116 V_MOV_B32 vDst(VGPR176) src0(VGPR173) V_MOV_B32 vDst(VGPR177) src0(VGPR174) V_MOV_B32 vDst(VGPR178) src0(VGPR175) # 118: OpAccessChain: Float*: d[0] # 119: OpCompositeExtract: Float: tmp119 << tmp117, 0 V_MOV_B32 vDst(VGPR171) src0(VGPR176) # 120: OpAccessChain: Float*: d[1] # 121: OpCompositeExtract: Float: tmp121 << tmp117, 1 V_MOV_B32 vDst(VGPR172) src0(VGPR177) # 122: OpAccessChain: Float*: d[2] # 123: OpCompositeExtract: Float: tmp123 << tmp117, 2 V_MOV_B32 vDst(VGPR173) src0(VGPR178) # 124: OpExtInst(FMin): Float: tmp124 << tmp121, tmp123 V_MIN_F32 vDst(VGPR174) src0(VGPR172) src1(VGPR173) // VOP2 # 125: OpExtInst(FMin): Float: tmp125 << tmp119, tmp124 V_MIN_F32 vDst(VGPR172) src0(VGPR171) src1(VGPR174) // VOP2 # 127: OpFSub: Float: tmp127 << tmp125, const126 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x3eaaaaab V_SUB_F32 vDst(VGPR173) src0(VGPR172) src1(VGPR171) // VOP2 # OpReturnValue: : << tmp127 S_MOV_B32 sDst(M0) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR173) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # Float sdCrossRep(vf3;(FloatVector3* p) Function: Float sdCrossRep(vf3;() S_MOV_B64 sDst(SGPR174) src0(EXEC) # lb15 Label: lb15 # 131: OpLoad: FloatVector3: tmp131 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR13) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 132: OpCompositeConstruct: FloatVector3: tmp132 << const88, const88, const88 V_MOV_B32 vDst(VGPR174) src0(1_0_F) V_MOV_B32 vDst(VGPR175) src0(1_0_F) V_MOV_B32 vDst(VGPR176) src0(1_0_F) # 133: OpFAdd: FloatVector3: tmp133 << tmp131, tmp132 V_ADD_F32 vDst(VGPR177) src0(VGPR171) src1(VGPR174) // VOP2 V_ADD_F32 vDst(VGPR178) src0(VGPR172) src1(VGPR175) // VOP2 V_ADD_F32 vDst(VGPR179) src0(VGPR173) src1(VGPR176) // VOP2 # 135: OpCompositeConstruct: FloatVector3: tmp135 << const134, const134, const134 V_MOV_B32 vDst(VGPR171) src0(2_0_F) V_MOV_B32 vDst(VGPR172) src0(2_0_F) V_MOV_B32 vDst(VGPR173) src0(2_0_F) # 136: OpFMod: FloatVector3: tmp136 << tmp133, tmp135 V_RCP_F32 vDst(VGPR174) src0(VGPR171) V_MUL_F32 vDst(VGPR174) src0(VGPR177) src1(VGPR174) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR174) src0(VGPR174) src1(VGPR171) src2(VGPR177) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR174) src0(VGPR174) V_RCP_F32 vDst(VGPR175) src0(VGPR172) V_MUL_F32 vDst(VGPR175) src0(VGPR178) src1(VGPR175) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR175) src0(VGPR175) src1(VGPR172) src2(VGPR178) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR175) src0(VGPR175) V_RCP_F32 vDst(VGPR176) src0(VGPR173) V_MUL_F32 vDst(VGPR176) src0(VGPR179) src1(VGPR176) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR176) src0(VGPR176) src1(VGPR173) src2(VGPR179) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR176) src0(VGPR176) V_MAD_F32 vDst(VGPR174) src0(VGPR171) src1(VGPR174) src2(VGPR177) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR175) src0(VGPR172) src1(VGPR175) src2(VGPR178) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR176) src0(VGPR173) src1(VGPR176) src2(VGPR179) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 137: OpCompositeConstruct: FloatVector3: tmp137 << const88, const88, const88 V_MOV_B32 vDst(VGPR171) src0(1_0_F) V_MOV_B32 vDst(VGPR172) src0(1_0_F) V_MOV_B32 vDst(VGPR173) src0(1_0_F) # 138: OpFSub: FloatVector3: tmp138 << tmp136, tmp137 V_SUB_F32 vDst(VGPR177) src0(VGPR174) src1(VGPR171) // VOP2 V_SUB_F32 vDst(VGPR178) src0(VGPR175) src1(VGPR172) // VOP2 V_SUB_F32 vDst(VGPR179) src0(VGPR176) src1(VGPR173) // VOP2 # OpStore: : tmp138 >> param139 V_MOV_B32 vDst(VGPR20) src0(VGPR177) V_MOV_B32 vDst(VGPR21) src0(VGPR178) V_MOV_B32 vDst(VGPR22) src0(VGPR179) # 141: OpFunctionCall: Float: sdCross(vf3;(param139) S_ADD_U32 sDst(SGPR171) src0(LITERAL_CONST) src1(0) const: 0x14 # VGPR[83:85] S_MOV_B64 sDst(SGPR20) src0(EXEC) S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x17 # VGPR107 # Indirect branch to sdCross(vf3;: -412 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x19c S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR20) # .lbl1 # OpReturnValue: : << sdCross(vf3; S_MOV_B32 sDst(M0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR23) S_SETPC_B64 sDst(SGPR18) src0(SGPR18) # Float sdCrossRepScale(vf3;f1;(FloatVector3* p, Float* s) Function: Float sdCrossRepScale(vf3;f1;(, Float sdCrossRep(vf3;.s) S_MOV_B64 sDst(SGPR172) src0(EXEC) # lb21 Label: lb21 # 144: OpLoad: FloatVector3: tmp144 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 145: OpLoad: Float: tmp145 << s S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR26) const: 0x0 V_MOVRELS_B32 vDst(VGPR174) src0(VGPR0) # 146: OpVectorTimesScalar: FloatVector3: tmp146 << tmp144, tmp145 V_MUL_F32 vDst(VGPR175) src0(VGPR174) src1(VGPR171) // VOP2 V_MUL_F32 vDst(VGPR176) src0(VGPR174) src1(VGPR172) // VOP2 V_MUL_F32 vDst(VGPR177) src0(VGPR174) src1(VGPR173) // VOP2 # OpStore: : tmp146 >> param147 V_MOV_B32 vDst(VGPR24) src0(VGPR175) V_MOV_B32 vDst(VGPR25) src0(VGPR176) V_MOV_B32 vDst(VGPR26) src0(VGPR177) # 148: OpFunctionCall: Float: sdCrossRep(vf3;(param147) S_ADD_U32 sDst(SGPR13) src0(LITERAL_CONST) src1(0) const: 0x18 # VGPR[108:110] S_MOV_B64 sDst(SGPR28) src0(EXEC) S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x1b # VGPR118 # Indirect branch to sdCrossRep(vf3;: -324 S_GETPC_B64 sDst(SGPR18) src0(SGPR18) S_SUB_U32 sDst(SGPR18) src0(SGPR18) src1(LITERAL_CONST) const: 0x144 S_SUBB_U32 sDst(SGPR19) src0(SGPR19) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR18) src0(SGPR18) S_MOV_B64 sDst(EXEC) src0(SGPR28) # .lbl2 # 149: OpLoad: Float: tmp149 << s S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR26) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 150: OpFDiv: Float: tmp150 << sdCrossRep(vf3;, tmp149 V_RCP_F32 vDst(VGPR172) src0(VGPR171) V_MUL_F32 vDst(VGPR172) src0(VGPR27) src1(VGPR172) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR172) src0(VGPR172) src1(VGPR171) src2(VGPR27) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp150 S_MOV_B32 sDst(M0) src0(SGPR24) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR172) S_SETPC_B64 sDst(SGPR22) src0(SGPR22) # Float differenceSDF(f1;f1;(Float* distA, Float* distB) Function: Float differenceSDF(f1;f1;(, Float sdCrossRepScale(vf3;f1;.distB) S_MOV_B64 sDst(SGPR174) src0(EXEC) # lb26 Label: lb26 # 153: OpLoad: Float: tmp153 << distA S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR32) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 154: OpLoad: Float: tmp154 << distB S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR33) const: 0x0 V_MOVRELS_B32 vDst(VGPR172) src0(VGPR0) # 155: OpFNegate: Float: tmp155 << tmp154 V_MUL_F32 vDst(VGPR173) src0(M1_0_F) src1(VGPR172) // VOP2 # 156: OpExtInst(FMax): Float: tmp156 << tmp153, tmp155 V_MAX_F32 vDst(VGPR172) src0(VGPR171) src1(VGPR173) // VOP2 # OpReturnValue: : << tmp156 S_MOV_B32 sDst(M0) src0(SGPR27) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR172) S_SETPC_B64 sDst(SGPR30) src0(SGPR30) # Float sdCylinder(vf3;vf2;(FloatVector3* p, FloatVector2* h) Function: Float sdCylinder(vf3;vf2;(, FloatVector2 differenceSDF(f1;f1;.h) S_MOV_B64 sDst(SGPR172) src0(EXEC) # lb33 Label: lb33 # 160: OpLoad: FloatVector3: tmp160 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR37) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 161: OpVectorShuffle: FloatVector2: tmp161 << tmp160, tmp160, 0, 2 V_MOV_B32 vDst(VGPR174) src0(VGPR171) V_MOV_B32 vDst(VGPR175) src0(VGPR173) # 162: OpExtInst(Length): Float: tmp162 << tmp161 V_MUL_F32 vDst(VGPR171) src0(VGPR174) src1(VGPR174) // VOP2 V_MAC_F32 vDst(VGPR171) src0(VGPR175) src1(VGPR175) // VOP2 V_SQRT_F32 vDst(VGPR171) src0(VGPR171) # 163: OpAccessChain: Float*: p[1] # 164: OpLoad: Float: tmp164 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR37) const: 0x0 V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) # 165: OpCompositeConstruct: FloatVector2: tmp165 << tmp162, tmp164 V_MOV_B32 vDst(VGPR173) src0(VGPR171) V_MOV_B32 vDst(VGPR174) src0(VGPR172) # 166: OpExtInst(FAbs): FloatVector2: tmp166 << tmp165 V_ADD_F32 vDst(VGPR175) src0(VGPR173) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR176) src0(VGPR174) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 167: OpLoad: FloatVector2: tmp167 << h S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR38) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) # 168: OpFSub: FloatVector2: tmp168 << tmp166, tmp167 V_SUB_F32 vDst(VGPR173) src0(VGPR175) src1(VGPR171) // VOP2 V_SUB_F32 vDst(VGPR174) src0(VGPR176) src1(VGPR172) // VOP2 # 169: OpAccessChain: Float*: d[0] # 170: OpCompositeExtract: Float: tmp170 << tmp168, 0 V_MOV_B32 vDst(VGPR171) src0(VGPR173) # 171: OpAccessChain: Float*: d[1] # 172: OpCompositeExtract: Float: tmp172 << tmp168, 1 V_MOV_B32 vDst(VGPR172) src0(VGPR174) # 173: OpExtInst(FMax): Float: tmp173 << tmp170, tmp172 V_MAX_F32 vDst(VGPR175) src0(VGPR171) src1(VGPR172) // VOP2 # 175: OpExtInst(FMin): Float: tmp175 << tmp173, const174 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x00000000 V_MIN_F32 vDst(VGPR172) src0(VGPR175) src1(VGPR171) // VOP2 # 177: OpCompositeConstruct: FloatVector2: tmp177 << const174, const174 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR175) src0(SGPR171) S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR176) src0(SGPR171) # 178: OpExtInst(FMax): FloatVector2: tmp178 << tmp168, tmp177 V_MAX_F32 vDst(VGPR177) src0(VGPR173) src1(VGPR175) // VOP2 V_MAX_F32 vDst(VGPR178) src0(VGPR174) src1(VGPR176) // VOP2 # 179: OpExtInst(Length): Float: tmp179 << tmp178 V_MUL_F32 vDst(VGPR171) src0(VGPR177) src1(VGPR177) // VOP2 V_MAC_F32 vDst(VGPR171) src0(VGPR178) src1(VGPR178) // VOP2 V_SQRT_F32 vDst(VGPR171) src0(VGPR171) # 180: OpFAdd: Float: tmp180 << tmp175, tmp179 V_ADD_F32 vDst(VGPR173) src0(VGPR172) src1(VGPR171) // VOP2 # OpReturnValue: : << tmp180 S_MOV_B32 sDst(M0) src0(SGPR36) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR173) S_SETPC_B64 sDst(SGPR34) src0(SGPR34) # FloatVector2 opU(vf2;vf2;(FloatVector2* d1, FloatVector2* d2) Function: FloatVector2 opU(vf2;vf2;(, FloatVector2 sdCylinder(vf3;vf2;.d2) S_MOV_B64 sDst(SGPR172) src0(EXEC) # lb38 Label: lb38 # 183: OpAccessChain: Float*: d1[0] # 184: OpLoad: Float: tmp184 << d1[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR42) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 185: OpAccessChain: Float*: d2[0] # 186: OpLoad: Float: tmp186 << d2[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR43) const: 0x0 V_MOVRELS_B32 vDst(VGPR172) src0(VGPR0) # 188: OpFOrdLessThan: Bool: tmp188 << tmp184, tmp186 V_CMP_LT_F32 dst(SGPR174) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb190) # CF Block: Merge: lb190 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp188) then branch to lb189, else branch to lb193 # CF Block: Cond Branch: true: lb189, false: lb193 S_AND_B64 sDst(EXEC) src0(SGPR174) src1(EXEC) S_CBRANCH_EXECZ 6 lb193 # lb189 Label: lb189 # 192: OpLoad: FloatVector2: tmp192 << d1 S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR42) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) # OpStore: : tmp192 >> resp V_MOV_B32 vDst(VGPR173) src0(VGPR171) V_MOV_B32 vDst(VGPR174) src0(VGPR172) # OpBranch: to lb190 # lb193 Label: lb193 S_ANDN2_B64 sDst(EXEC) src0(SGPR176) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 6 lb190 # 194: OpLoad: FloatVector2: tmp194 << d2 S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR43) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) # OpStore: : tmp194 >> resp V_MOV_B32 vDst(VGPR173) src0(VGPR171) V_MOV_B32 vDst(VGPR174) src0(VGPR172) # OpBranch: to lb190 # lb190 Label: lb190 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR172) # 195: OpLoad: FloatVector2: tmp195 << resp # OpReturnValue: : << tmp195 S_MOV_B32 sDst(M0) src0(SGPR39) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR173) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR174) S_SETPC_B64 sDst(SGPR40) src0(SGPR40) # Float diso(vf3;(FloatVector3* p) Function: Float diso(vf3;() S_MOV_B64 sDst(SGPR172) src0(EXEC) # lb41 Label: lb41 # OpStore: : const200 >> res S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x461c3c00 S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR28) src0(SGPR171) V_MOV_B32 vDst(VGPR29) src0(SGPR172) # 201: OpAccessChain: Float*: p[2] # 202: OpLoad: Float: tmp202 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR46) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR2) # 203: OpFMod: Float: tmp203 << tmp202, const134 V_MOV_B32 vDst(VGPR172) src0(2_0_F) V_RCP_F32 vDst(VGPR173) src0(VGPR172) V_MUL_F32 vDst(VGPR173) src0(VGPR171) src1(VGPR173) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR173) src0(VGPR173) src1(VGPR172) src2(VGPR171) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR173) src0(VGPR173) V_MAD_F32 vDst(VGPR173) src0(VGPR172) src1(VGPR173) src2(VGPR171) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 204: OpAccessChain: Float*: p[2] # OpStore: : tmp203 >> p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR46) const: 0x0 V_MOVRELD_B32 vDst(VGPR2) src0(VGPR173) # 209: OpLoad: FloatVector3: tmp209 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR46) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 210: OpVectorShuffle: FloatVector3: tmp210 << tmp209, tmp209, 1, 2, 0 V_MOV_B32 vDst(VGPR174) src0(VGPR172) V_MOV_B32 vDst(VGPR175) src0(VGPR173) V_MOV_B32 vDst(VGPR176) src0(VGPR171) # OpStore: : tmp210 >> param208 V_MOV_B32 vDst(VGPR30) src0(VGPR174) V_MOV_B32 vDst(VGPR31) src0(VGPR175) V_MOV_B32 vDst(VGPR32) src0(VGPR176) # OpStore: : const207 >> param211 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x40c00000 S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x40c00000 V_MOV_B32 vDst(VGPR33) src0(SGPR171) V_MOV_B32 vDst(VGPR34) src0(SGPR172) # 212: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param208, param211) S_ADD_U32 sDst(SGPR37) src0(LITERAL_CONST) src1(0) const: 0x1e # VGPR[163:165] S_ADD_U32 sDst(SGPR38) src0(LITERAL_CONST) src1(0) const: 0x21 # VGPR[166:167] S_MOV_B64 sDst(SGPR48) src0(EXEC) S_MOV_B32 sDst(SGPR36) src0(LITERAL_CONST) const: 0x2e # VGPR192 # Indirect branch to sdCylinder(vf3;vf2;: -504 S_GETPC_B64 sDst(SGPR34) src0(SGPR34) S_SUB_U32 sDst(SGPR34) src0(SGPR34) src1(LITERAL_CONST) const: 0x1f8 S_SUBB_U32 sDst(SGPR35) src0(SGPR35) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR34) src0(SGPR34) S_MOV_B64 sDst(EXEC) src0(SGPR48) # .lbl3 # 218: OpLoad: FloatVector3: tmp218 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR46) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 219: OpVectorShuffle: FloatVector3: tmp219 << tmp218, tmp218, 1, 2, 0 V_MOV_B32 vDst(VGPR174) src0(VGPR172) V_MOV_B32 vDst(VGPR175) src0(VGPR173) V_MOV_B32 vDst(VGPR176) src0(VGPR171) # OpStore: : tmp219 >> param217 V_MOV_B32 vDst(VGPR35) src0(VGPR174) V_MOV_B32 vDst(VGPR36) src0(VGPR175) V_MOV_B32 vDst(VGPR37) src0(VGPR176) # OpStore: : const216 >> param220 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3ff33333 S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x40d8f5c3 V_MOV_B32 vDst(VGPR38) src0(SGPR171) V_MOV_B32 vDst(VGPR39) src0(SGPR172) # 221: OpFunctionCall: Float: sdCylinder(vf3;vf2;(param217, param220) S_ADD_U32 sDst(SGPR37) src0(LITERAL_CONST) src1(0) const: 0x23 # VGPR[168:170] S_ADD_U32 sDst(SGPR38) src0(LITERAL_CONST) src1(0) const: 0x26 # VGPR[171:172] S_MOV_B64 sDst(SGPR50) src0(EXEC) S_MOV_B32 sDst(SGPR36) src0(LITERAL_CONST) const: 0x2f # VGPR201 # Indirect branch to sdCylinder(vf3;vf2;: -628 S_GETPC_B64 sDst(SGPR34) src0(SGPR34) S_SUB_U32 sDst(SGPR34) src0(SGPR34) src1(LITERAL_CONST) const: 0x274 S_SUBB_U32 sDst(SGPR35) src0(SGPR35) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR34) src0(SGPR34) S_MOV_B64 sDst(EXEC) src0(SGPR50) # .lbl4 # OpStore: : sdCylinder(vf3;vf2; >> param223 V_MOV_B32 vDst(VGPR40) src0(VGPR46) # OpStore: : sdCylinder(vf3;vf2; >> param225 V_MOV_B32 vDst(VGPR41) src0(VGPR47) # 227: OpFunctionCall: Float: differenceSDF(f1;f1;(param223, param225) S_ADD_U32 sDst(SGPR32) src0(LITERAL_CONST) src1(0) const: 0x28 # VGPR173 S_ADD_U32 sDst(SGPR33) src0(LITERAL_CONST) src1(0) const: 0x29 # VGPR174 S_MOV_B64 sDst(SGPR52) src0(EXEC) S_MOV_B32 sDst(SGPR27) src0(LITERAL_CONST) const: 0x30 # VGPR202 # Indirect branch to differenceSDF(f1;f1;: -740 S_GETPC_B64 sDst(SGPR30) src0(SGPR30) S_SUB_U32 sDst(SGPR30) src0(SGPR30) src1(LITERAL_CONST) const: 0x2e4 S_SUBB_U32 sDst(SGPR31) src0(SGPR31) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR30) src0(SGPR30) S_MOV_B64 sDst(EXEC) src0(SGPR52) # .lbl5 # 230: OpCompositeConstruct: FloatVector2: tmp230 << differenceSDF(f1;f1;, const229 V_MOV_B32 vDst(VGPR171) src0(VGPR48) S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x41100000 V_MOV_B32 vDst(VGPR172) src0(SGPR171) # 232: OpLoad: FloatVector2: tmp232 << res # OpStore: : tmp232 >> param231 V_MOV_B32 vDst(VGPR42) src0(VGPR28) V_MOV_B32 vDst(VGPR43) src0(VGPR29) # OpStore: : tmp230 >> param233 V_MOV_B32 vDst(VGPR44) src0(VGPR171) V_MOV_B32 vDst(VGPR45) src0(VGPR172) # 234: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param231, param233) S_ADD_U32 sDst(SGPR42) src0(LITERAL_CONST) src1(0) const: 0x2a # VGPR[175:176] S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0x2c # VGPR[177:178] S_MOV_B64 sDst(SGPR54) src0(EXEC) S_MOV_B32 sDst(SGPR39) src0(LITERAL_CONST) const: 0x31 # VGPR[206:207] # Indirect branch to opU(vf2;vf2;: -592 S_GETPC_B64 sDst(SGPR40) src0(SGPR40) S_SUB_U32 sDst(SGPR40) src0(SGPR40) src1(LITERAL_CONST) const: 0x250 S_SUBB_U32 sDst(SGPR41) src0(SGPR41) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR40) src0(SGPR40) S_MOV_B64 sDst(EXEC) src0(SGPR54) # .lbl6 # OpStore: : opU(vf2;vf2; >> res V_MOV_B32 vDst(VGPR28) src0(VGPR49) V_MOV_B32 vDst(VGPR29) src0(VGPR50) # 235: OpAccessChain: Float*: res[0] # 236: OpLoad: Float: tmp236 << res[0] V_MOV_B32 vDst(VGPR171) src0(VGPR28) # OpReturnValue: : << tmp236 S_MOV_B32 sDst(M0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR171) S_SETPC_B64 sDst(SGPR44) src0(SGPR44) # Float DE(vf3;(FloatVector3* p) Function: Float DE(vf3;() S_MOV_B64 sDst(SGPR60) src0(EXEC) # lb44 Label: lb44 # OpStore: : const240 >> scale S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x3eb33333 V_MOV_B32 vDst(VGPR51) src0(SGPR172) # OpStore: : const243 >> res S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x461c3f9a S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR52) src0(SGPR172) V_MOV_B32 vDst(VGPR53) src0(SGPR173) # OpStore: : const245 >> dist S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0xc479c000 V_MOV_B32 vDst(VGPR54) src0(SGPR172) # 247: OpLoad: FloatVector3: tmp247 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR58) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # OpStore: : tmp247 >> param246 V_MOV_B32 vDst(VGPR55) src0(VGPR171) V_MOV_B32 vDst(VGPR56) src0(VGPR172) V_MOV_B32 vDst(VGPR57) src0(VGPR173) # 248: OpFunctionCall: Float: diso(vf3;(param246) S_ADD_U32 sDst(SGPR46) src0(LITERAL_CONST) src1(0) const: 0x37 # VGPR[213:215] S_MOV_B64 sDst(SGPR62) src0(EXEC) S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x46 # VGPR236 # Indirect branch to diso(vf3;: -616 S_GETPC_B64 sDst(SGPR44) src0(SGPR44) S_SUB_U32 sDst(SGPR44) src0(SGPR44) src1(LITERAL_CONST) const: 0x268 S_SUBB_U32 sDst(SGPR45) src0(SGPR45) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR44) src0(SGPR44) S_MOV_B64 sDst(EXEC) src0(SGPR62) # .lbl7 # OpStore: : diso(vf3; >> dist V_MOV_B32 vDst(VGPR54) src0(VGPR70) # OpStore: : const250 >> i S_MOV_B32 sDst(SGPR143) src0(0) # OpBranch: to lb251 # lb251 Label: lb251 # OpLoopMerge: (merge: lb253, continue: lb254) # CF Block: Merge: lb253, Continue: lb254 S_MOV_B64 sDst(SGPR64) src0(EXEC) S_MOV_B64 sDst(SGPR66) src0(EXEC) S_MOV_B64 sDst(SGPR68) src0(EXEC) Label: lb251Loop # OpBranch: to lb255 # lb255 Label: lb255 # 256: OpLoad: Int: tmp256 << i Decorators: RelaxedPrecision # 258: OpSLessThan: Bool: tmp258 << tmp256, const257 V_MOV_B32 vDst(VGPR171) src0(5_INT) V_CMP_LT_I32 dst(SGPR174) src0(SGPR143) src1(VGPR171) // VOP3a # OpBranchConditional: if(tmp258) then branch to lb252, else branch to lb253 # CF Block: Cond Branch: true: lb252, false: lb253 S_AND_B64 sDst(EXEC) src0(SGPR174) src1(EXEC) S_CBRANCH_EXECZ 37 lb253 # lb252 Label: lb252 S_MOV_B64 sDst(SGPR66) src0(EXEC) S_MOV_B64 sDst(SGPR68) src0(EXEC) # 259: OpLoad: Float: tmp259 << dist # 261: OpLoad: FloatVector3: tmp261 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR58) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # OpStore: : tmp261 >> param260 V_MOV_B32 vDst(VGPR58) src0(VGPR171) V_MOV_B32 vDst(VGPR59) src0(VGPR172) V_MOV_B32 vDst(VGPR60) src0(VGPR173) # 263: OpLoad: Float: tmp263 << scale # OpStore: : tmp263 >> param262 V_MOV_B32 vDst(VGPR61) src0(VGPR51) # 264: OpFunctionCall: Float: sdCrossRepScale(vf3;f1;(param260, param262) S_ADD_U32 sDst(SGPR25) src0(LITERAL_CONST) src1(0) const: 0x3a # VGPR[217:219] S_ADD_U32 sDst(SGPR26) src0(LITERAL_CONST) src1(0) const: 0x3d # VGPR220 S_MOV_B64 sDst(SGPR70) src0(EXEC) S_MOV_B32 sDst(SGPR24) src0(LITERAL_CONST) const: 0x47 # VGPR241 # Indirect branch to sdCrossRepScale(vf3;f1;: -1272 S_GETPC_B64 sDst(SGPR22) src0(SGPR22) S_SUB_U32 sDst(SGPR22) src0(SGPR22) src1(LITERAL_CONST) const: 0x4f8 S_SUBB_U32 sDst(SGPR23) src0(SGPR23) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR22) src0(SGPR22) S_MOV_B64 sDst(EXEC) src0(SGPR70) # .lbl8 # 265: OpFNegate: Float: tmp265 << sdCrossRepScale(vf3;f1; V_MUL_F32 vDst(VGPR171) src0(M1_0_F) src1(VGPR71) // VOP2 # 266: OpExtInst(FMax): Float: tmp266 << tmp259, tmp265 V_MAX_F32 vDst(VGPR172) src0(VGPR54) src1(VGPR171) // VOP2 # OpStore: : tmp266 >> dist V_MOV_B32 vDst(VGPR54) src0(VGPR172) # 268: OpLoad: Float: tmp268 << scale # 269: OpFMul: Float: tmp269 << tmp268, const267 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x40400000 V_MUL_F32 vDst(VGPR172) src0(VGPR51) src1(VGPR171) // VOP2 # OpStore: : tmp269 >> scale V_MOV_B32 vDst(VGPR51) src0(VGPR172) # OpBranch: to lb254 # lb254 Label: lb254 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR66) # 270: OpLoad: Int: tmp270 << i Decorators: RelaxedPrecision # 272: OpIAdd: Int: tmp272 << tmp270, const271 Decorators: RelaxedPrecision S_MOV_B32 sDst(SGPR171) src0(1_INT) S_ADD_I32 sDst(SGPR172) src0(SGPR143) src1(SGPR171) # OpStore: : tmp272 >> i S_MOV_B32 sDst(SGPR143) src0(SGPR172) # OpBranch: to lb251 S_BRANCH -42 lb251Loop # lb253 Label: lb253 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR64) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR60) # 275: OpLoad: Float: tmp275 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR171) S_WAITCNT 0 # 276: OpExtInst(Floor): Float: tmp276 << tmp275 V_FLOOR_F32 vDst(VGPR171) src0(SGPR171) # 278: OpFMod: Float: tmp278 << tmp276, const277 V_MOV_B32 vDst(VGPR172) src0(LITERAL_CONST) const: 0x40a00000 V_RCP_F32 vDst(VGPR173) src0(VGPR172) V_MUL_F32 vDst(VGPR173) src0(VGPR171) src1(VGPR173) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR173) src0(VGPR173) src1(VGPR172) src2(VGPR171) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR173) src0(VGPR173) V_MAD_F32 vDst(VGPR173) src0(VGPR172) src1(VGPR173) src2(VGPR171) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 280: OpFOrdGreaterThan: Bool: tmp280 << tmp278, const279 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x3ecccccd V_CMP_GT_F32 dst(SGPR174) src0(VGPR173) src1(VGPR171) // VOP3a # OpSelectionMerge: (merge: lb282) # CF Block: Merge: lb282 S_MOV_B64 sDst(SGPR72) src0(EXEC) # OpBranchConditional: if(tmp280) then branch to lb281, else branch to lb290 # CF Block: Cond Branch: true: lb281, false: lb290 S_AND_B64 sDst(EXEC) src0(SGPR174) src1(EXEC) S_CBRANCH_EXECZ 24 lb290 # lb281 Label: lb281 # 283: OpLoad: Float: tmp283 << dist # 285: OpCompositeConstruct: FloatVector2: tmp285 << tmp283, const284 V_MOV_B32 vDst(VGPR171) src0(VGPR54) S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x41000000 V_MOV_B32 vDst(VGPR172) src0(SGPR171) # 287: OpLoad: FloatVector2: tmp287 << res # OpStore: : tmp287 >> param286 V_MOV_B32 vDst(VGPR62) src0(VGPR52) V_MOV_B32 vDst(VGPR63) src0(VGPR53) # OpStore: : tmp285 >> param288 V_MOV_B32 vDst(VGPR64) src0(VGPR171) V_MOV_B32 vDst(VGPR65) src0(VGPR172) # 289: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param286, param288) S_ADD_U32 sDst(SGPR42) src0(LITERAL_CONST) src1(0) const: 0x3e # VGPR[221:222] S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0x40 # VGPR[223:224] S_MOV_B64 sDst(SGPR74) src0(EXEC) S_MOV_B32 sDst(SGPR39) src0(LITERAL_CONST) const: 0x48 # VGPR[255:256] # Indirect branch to opU(vf2;vf2;: -1112 S_GETPC_B64 sDst(SGPR40) src0(SGPR40) S_SUB_U32 sDst(SGPR40) src0(SGPR40) src1(LITERAL_CONST) const: 0x458 S_SUBB_U32 sDst(SGPR41) src0(SGPR41) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR40) src0(SGPR40) S_MOV_B64 sDst(EXEC) src0(SGPR74) # .lbl9 # OpStore: : opU(vf2;vf2; >> res V_MOV_B32 vDst(VGPR52) src0(VGPR72) V_MOV_B32 vDst(VGPR53) src0(VGPR73) # OpBranch: to lb282 # lb290 Label: lb290 S_ANDN2_B64 sDst(EXEC) src0(SGPR72) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR60) src1(EXEC) S_CBRANCH_EXECZ 24 lb282 # 291: OpLoad: Float: tmp291 << dist # 293: OpCompositeConstruct: FloatVector2: tmp293 << tmp291, const292 V_MOV_B32 vDst(VGPR171) src0(VGPR54) S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x40e00000 V_MOV_B32 vDst(VGPR172) src0(SGPR171) # 295: OpLoad: FloatVector2: tmp295 << res # OpStore: : tmp295 >> param294 V_MOV_B32 vDst(VGPR66) src0(VGPR52) V_MOV_B32 vDst(VGPR67) src0(VGPR53) # OpStore: : tmp293 >> param296 V_MOV_B32 vDst(VGPR68) src0(VGPR171) V_MOV_B32 vDst(VGPR69) src0(VGPR172) # 297: OpFunctionCall: FloatVector2: opU(vf2;vf2;(param294, param296) S_ADD_U32 sDst(SGPR42) src0(LITERAL_CONST) src1(0) const: 0x42 # VGPR[225:226] S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0x44 # VGPR[227:228] S_MOV_B64 sDst(SGPR76) src0(EXEC) S_MOV_B32 sDst(SGPR39) src0(LITERAL_CONST) const: 0x4a # VGPR[260:261] # Indirect branch to opU(vf2;vf2;: -1220 S_GETPC_B64 sDst(SGPR40) src0(SGPR40) S_SUB_U32 sDst(SGPR40) src0(SGPR40) src1(LITERAL_CONST) const: 0x4c4 S_SUBB_U32 sDst(SGPR41) src0(SGPR41) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR40) src0(SGPR40) S_MOV_B64 sDst(EXEC) src0(SGPR76) # .lbl10 # OpStore: : opU(vf2;vf2; >> res V_MOV_B32 vDst(VGPR52) src0(VGPR74) V_MOV_B32 vDst(VGPR53) src0(VGPR75) # OpBranch: to lb282 # lb282 Label: lb282 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR72) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR60) # 300: OpAccessChain: Float*: res[1] # 301: OpLoad: Float: tmp301 << res[1] V_MOV_B32 vDst(VGPR171) src0(VGPR53) # OpStore: : tmp301 >> NumCol V_MOV_B32 vDst(VGPR76) src0(VGPR171) # 302: OpAccessChain: Float*: res[0] # 303: OpLoad: Float: tmp303 << res[0] V_MOV_B32 vDst(VGPR171) src0(VGPR52) # OpReturnValue: : << tmp303 S_MOV_B32 sDst(M0) src0(SGPR47) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR171) S_SETPC_B64 sDst(SGPR56) src0(SGPR56) # FloatVector2 march(vf3;vf3;(FloatVector3* ro, FloatVector3* rd) Function: FloatVector2 march(vf3;vf3;(, FloatVector3 DE(vf3;.rd) S_MOV_B64 sDst(SGPR82) src0(EXEC) # lb49 Label: lb49 # OpStore: : const174 >> t S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR77) src0(SGPR171) # OpStore: : const308 >> d S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x41a00000 V_MOV_B32 vDst(VGPR78) src0(SGPR171) # OpStore: : const174 >> it S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR79) src0(SGPR171) # OpStore: : const250 >> i S_MOV_B32 sDst(SGPR168) src0(0) # OpBranch: to lb311 # lb311 Label: lb311 # OpLoopMerge: (merge: lb313, continue: lb314) # CF Block: Merge: lb313, Continue: lb314 S_MOV_B64 sDst(SGPR84) src0(EXEC) S_MOV_B64 sDst(SGPR86) src0(EXEC) S_MOV_B64 sDst(SGPR88) src0(EXEC) Label: lb311Loop # OpBranch: to lb315 # lb315 Label: lb315 # 316: OpLoad: Int: tmp316 << i Decorators: RelaxedPrecision # 318: OpSLessThan: Bool: tmp318 << tmp316, const317 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x00000064 V_CMP_LT_I32 dst(SGPR172) src0(SGPR168) src1(VGPR171) // VOP3a # OpBranchConditional: if(tmp318) then branch to lb312, else branch to lb313 # CF Block: Cond Branch: true: lb312, false: lb313 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 61 lb313 # lb312 Label: lb312 S_MOV_B64 sDst(SGPR86) src0(EXEC) S_MOV_B64 sDst(SGPR88) src0(EXEC) # 319: OpLoad: FloatVector3: tmp319 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR80) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 320: OpLoad: Float: tmp320 << t # 321: OpLoad: FloatVector3: tmp321 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR81) const: 0x0 V_MOVRELS_B32 vDst(VGPR174) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR175) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR176) src0(VGPR2) # 322: OpVectorTimesScalar: FloatVector3: tmp322 << tmp321, tmp320 V_MUL_F32 vDst(VGPR177) src0(VGPR77) src1(VGPR174) // VOP2 V_MUL_F32 vDst(VGPR178) src0(VGPR77) src1(VGPR175) // VOP2 V_MUL_F32 vDst(VGPR179) src0(VGPR77) src1(VGPR176) // VOP2 # 323: OpFAdd: FloatVector3: tmp323 << tmp319, tmp322 V_ADD_F32 vDst(VGPR174) src0(VGPR171) src1(VGPR177) // VOP2 V_ADD_F32 vDst(VGPR175) src0(VGPR172) src1(VGPR178) // VOP2 V_ADD_F32 vDst(VGPR176) src0(VGPR173) src1(VGPR179) // VOP2 # OpStore: : tmp323 >> param324 V_MOV_B32 vDst(VGPR80) src0(VGPR174) V_MOV_B32 vDst(VGPR81) src0(VGPR175) V_MOV_B32 vDst(VGPR82) src0(VGPR176) # 325: OpFunctionCall: Float: DE(vf3;(param324) S_ADD_U32 sDst(SGPR58) src0(LITERAL_CONST) src1(0) const: 0x50 # VGPR[269:271] S_MOV_B64 sDst(SGPR90) src0(EXEC) S_MOV_B32 sDst(SGPR47) src0(LITERAL_CONST) const: 0x53 # VGPR288 # Indirect branch to DE(vf3;: -832 S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_SUB_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x340 S_SUBB_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR90) # .lbl11 # OpStore: : DE(vf3; >> d V_MOV_B32 vDst(VGPR78) src0(VGPR83) # 326: OpLoad: Float: tmp326 << t # 327: OpFAdd: Float: tmp327 << tmp326, DE(vf3; V_ADD_F32 vDst(VGPR171) src0(VGPR77) src1(VGPR83) // VOP2 # OpStore: : tmp327 >> t V_MOV_B32 vDst(VGPR77) src0(VGPR171) # 328: OpLoad: Float: tmp328 << d # 330: OpFOrdLessThan: Bool: tmp330 << tmp328, const329 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x3a83126f V_CMP_LT_F32 dst(SGPR172) src0(VGPR78) src1(VGPR171) // VOP3a # 331: OpLoad: Float: tmp331 << t # 332: OpFOrdGreaterThan: Bool: tmp332 << tmp331, const308 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x41a00000 V_CMP_GT_F32 dst(SGPR174) src0(VGPR77) src1(VGPR171) // VOP3a # 333: OpLogicalOr: Bool: tmp333 << tmp330, tmp332 S_OR_B64 sDst(SGPR176) src0(SGPR172) src1(SGPR174) # OpSelectionMerge: (merge: lb335) # CF Block: Merge: lb335 S_MOV_B64 sDst(SGPR172) src0(EXEC) # OpBranchConditional: if(tmp333) then branch to lb334, else branch to lb335 # CF Block: Cond Branch: true: lb334, false: lb335 S_AND_B64 sDst(EXEC) src0(SGPR176) src1(EXEC) S_CBRANCH_EXECZ 3 lb335 # lb334 Label: lb334 # OpBranch: to lb313 S_ANDN2_B64 sDst(SGPR86) src0(SGPR86) src1(EXEC) S_ANDN2_B64 sDst(SGPR88) src0(SGPR88) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR88) src1(EXEC) # lb335 Label: lb335 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR172) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR88) # 337: OpLoad: Float: tmp337 << it # 338: OpFAdd: Float: tmp338 << tmp337, const88 V_MOV_B32 vDst(VGPR171) src0(1_0_F) V_ADD_F32 vDst(VGPR172) src0(VGPR79) src1(VGPR171) // VOP2 # OpStore: : tmp338 >> it V_MOV_B32 vDst(VGPR79) src0(VGPR172) # OpBranch: to lb314 # lb314 Label: lb314 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR86) # 339: OpLoad: Int: tmp339 << i Decorators: RelaxedPrecision # 340: OpIAdd: Int: tmp340 << tmp339, const271 Decorators: RelaxedPrecision S_MOV_B32 sDst(SGPR171) src0(1_INT) S_ADD_I32 sDst(SGPR172) src0(SGPR168) src1(SGPR171) # OpStore: : tmp340 >> i S_MOV_B32 sDst(SGPR168) src0(SGPR172) # OpBranch: to lb311 S_BRANCH -67 lb311Loop # lb313 Label: lb313 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR84) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR82) # 341: OpLoad: Float: tmp341 << t # 342: OpLoad: Float: tmp342 << it # 344: OpFDiv: Float: tmp344 << tmp342, const343 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x42c80000 V_RCP_F32 vDst(VGPR172) src0(VGPR171) V_MUL_F32 vDst(VGPR172) src0(VGPR79) src1(VGPR172) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR172) src0(VGPR172) src1(VGPR171) src2(VGPR79) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 345: OpCompositeConstruct: FloatVector2: tmp345 << tmp341, tmp344 V_MOV_B32 vDst(VGPR173) src0(VGPR77) V_MOV_B32 vDst(VGPR174) src0(VGPR172) # OpReturnValue: : << tmp345 S_MOV_B32 sDst(M0) src0(SGPR59) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR173) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR174) S_SETPC_B64 sDst(SGPR78) src0(SGPR78) # Float getShadow(vf3;vf3;vf3;(FloatVector3* p, FloatVector3* n, FloatVector3* ld) Function: Float getShadow(vf3;vf3;vf3;(, FloatVector3 march(vf3;vf3;.n, FloatVector3 march(vf3;vf3;.ld) S_MOV_B64 sDst(SGPR98) src0(EXEC) # lb55 Label: lb55 # 349: OpLoad: FloatVector3: tmp349 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR96) const: 0x0 V_MOVRELS_B32 vDst(VGPR175) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR176) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR177) src0(VGPR2) # 350: OpVectorTimesScalar: FloatVector3: tmp350 << tmp349, const348 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x3b03126f V_MUL_F32 vDst(VGPR172) src0(VGPR171) src1(VGPR175) // VOP2 V_MUL_F32 vDst(VGPR173) src0(VGPR171) src1(VGPR176) // VOP2 V_MUL_F32 vDst(VGPR174) src0(VGPR171) src1(VGPR177) // VOP2 # 351: OpLoad: FloatVector3: tmp351 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR95) const: 0x0 V_MOVRELS_B32 vDst(VGPR175) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR176) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR177) src0(VGPR2) # 352: OpFAdd: FloatVector3: tmp352 << tmp351, tmp350 V_ADD_F32 vDst(VGPR178) src0(VGPR175) src1(VGPR172) // VOP2 V_ADD_F32 vDst(VGPR179) src0(VGPR176) src1(VGPR173) // VOP2 V_ADD_F32 vDst(VGPR180) src0(VGPR177) src1(VGPR174) // VOP2 # OpStore: : tmp352 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR95) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR178) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR179) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR180) # OpStore: : const174 >> t S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR84) src0(SGPR171) # OpStore: : const308 >> d S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x41a00000 V_MOV_B32 vDst(VGPR85) src0(SGPR171) # OpStore: : const250 >> i S_MOV_B32 sDst(SGPR169) src0(0) # OpBranch: to lb356 # lb356 Label: lb356 # OpLoopMerge: (merge: lb358, continue: lb359) # CF Block: Merge: lb358, Continue: lb359 S_MOV_B64 sDst(SGPR100) src0(EXEC) S_MOV_B64 sDst(SGPR102) src0(EXEC) S_MOV_B64 sDst(SGPR104) src0(EXEC) Label: lb356Loop # OpBranch: to lb360 # lb360 Label: lb360 # 361: OpLoad: Int: tmp361 << i Decorators: RelaxedPrecision # 363: OpSLessThan: Bool: tmp363 << tmp361, const362 V_MOV_B32 vDst(VGPR171) src0(50_INT) V_CMP_LT_I32 dst(SGPR174) src0(SGPR169) src1(VGPR171) // VOP3a # OpBranchConditional: if(tmp363) then branch to lb357, else branch to lb358 # CF Block: Cond Branch: true: lb357, false: lb358 S_AND_B64 sDst(EXEC) src0(SGPR174) src1(EXEC) S_CBRANCH_EXECZ 58 lb358 # lb357 Label: lb357 S_MOV_B64 sDst(SGPR102) src0(EXEC) S_MOV_B64 sDst(SGPR104) src0(EXEC) # 364: OpLoad: FloatVector3: tmp364 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR95) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 365: OpLoad: Float: tmp365 << t # 366: OpLoad: FloatVector3: tmp366 << ld S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR97) const: 0x0 V_MOVRELS_B32 vDst(VGPR174) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR175) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR176) src0(VGPR2) # 367: OpVectorTimesScalar: FloatVector3: tmp367 << tmp366, tmp365 V_MUL_F32 vDst(VGPR177) src0(VGPR84) src1(VGPR174) // VOP2 V_MUL_F32 vDst(VGPR178) src0(VGPR84) src1(VGPR175) // VOP2 V_MUL_F32 vDst(VGPR179) src0(VGPR84) src1(VGPR176) // VOP2 # 368: OpFAdd: FloatVector3: tmp368 << tmp364, tmp367 V_ADD_F32 vDst(VGPR174) src0(VGPR171) src1(VGPR177) // VOP2 V_ADD_F32 vDst(VGPR175) src0(VGPR172) src1(VGPR178) // VOP2 V_ADD_F32 vDst(VGPR176) src0(VGPR173) src1(VGPR179) // VOP2 # OpStore: : tmp368 >> param369 V_MOV_B32 vDst(VGPR86) src0(VGPR174) V_MOV_B32 vDst(VGPR87) src0(VGPR175) V_MOV_B32 vDst(VGPR88) src0(VGPR176) # 370: OpFunctionCall: Float: DE(vf3;(param369) S_ADD_U32 sDst(SGPR58) src0(LITERAL_CONST) src1(0) const: 0x56 # VGPR[303:305] S_MOV_B64 sDst(SGPR106) src0(EXEC) S_MOV_B32 sDst(SGPR47) src0(LITERAL_CONST) const: 0x59 # VGPR334 # Indirect branch to DE(vf3;: -1288 S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_SUB_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x508 S_SUBB_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR106) # .lbl12 # OpStore: : DE(vf3; >> d V_MOV_B32 vDst(VGPR85) src0(VGPR89) # 371: OpLoad: Float: tmp371 << t # 372: OpFAdd: Float: tmp372 << tmp371, DE(vf3; V_ADD_F32 vDst(VGPR171) src0(VGPR84) src1(VGPR89) // VOP2 # OpStore: : tmp372 >> t V_MOV_B32 vDst(VGPR84) src0(VGPR171) # 373: OpLoad: Float: tmp373 << d # 374: OpFOrdLessThan: Bool: tmp374 << tmp373, const329 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x3a83126f V_CMP_LT_F32 dst(SGPR172) src0(VGPR85) src1(VGPR171) // VOP3a # 375: OpLoad: Float: tmp375 << t # 376: OpFOrdGreaterThan: Bool: tmp376 << tmp375, const267 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x40400000 V_CMP_GT_F32 dst(SGPR174) src0(VGPR84) src1(VGPR171) // VOP3a # 377: OpLogicalOr: Bool: tmp377 << tmp374, tmp376 S_OR_B64 sDst(SGPR176) src0(SGPR172) src1(SGPR174) # OpSelectionMerge: (merge: lb379) # CF Block: Merge: lb379 S_MOV_B64 sDst(SGPR172) src0(EXEC) # OpBranchConditional: if(tmp377) then branch to lb378, else branch to lb379 # CF Block: Cond Branch: true: lb378, false: lb379 S_AND_B64 sDst(EXEC) src0(SGPR176) src1(EXEC) S_CBRANCH_EXECZ 3 lb379 # lb378 Label: lb378 # OpBranch: to lb358 S_ANDN2_B64 sDst(SGPR102) src0(SGPR102) src1(EXEC) S_ANDN2_B64 sDst(SGPR104) src0(SGPR104) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR104) src1(EXEC) # lb379 Label: lb379 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR172) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR104) # OpBranch: to lb359 # lb359 Label: lb359 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR102) # 381: OpLoad: Int: tmp381 << i Decorators: RelaxedPrecision # 382: OpIAdd: Int: tmp382 << tmp381, const271 Decorators: RelaxedPrecision S_MOV_B32 sDst(SGPR171) src0(1_INT) S_ADD_I32 sDst(SGPR172) src0(SGPR169) src1(SGPR171) # OpStore: : tmp382 >> i S_MOV_B32 sDst(SGPR169) src0(SGPR172) # OpBranch: to lb356 S_BRANCH -63 lb356Loop # lb358 Label: lb358 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR100) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR98) # 383: OpLoad: Float: tmp383 << t # 384: OpFOrdLessThanEqual: Bool: tmp384 << tmp383, const267 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x40400000 V_CMP_LE_F32 dst(SGPR174) src0(VGPR84) src1(VGPR171) // VOP3a # 386: OpSelect: Float: tmp386 << tmp384, const385, const88 # CF Block: Merge: .lbl14 S_MOV_B64 sDst(SGPR172) src0(EXEC) # CF Block: Cond Branch: true: .lbl15, false: .lbl13 S_AND_B64 sDst(EXEC) src0(SGPR174) src1(EXEC) S_CBRANCH_EXECZ 3 .lbl13 Label: .lbl15 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3dcccccd V_MOV_B32 vDst(VGPR171) src0(SGPR171) Label: .lbl13 S_ANDN2_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR98) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl14 V_MOV_B32 vDst(VGPR171) src0(1_0_F) Label: .lbl14 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR172) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR98) # OpReturnValue: : << tmp386 S_MOV_B32 sDst(M0) src0(SGPR94) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR171) S_SETPC_B64 sDst(SGPR92) src0(SGPR92) # FloatVector3 getNorm(vf3;(FloatVector3* p) Function: FloatVector3 getNorm(vf3;() S_MOV_B64 sDst(SGPR174) src0(EXEC) # lb59 Label: lb59 # 391: OpLoad: FloatVector3: tmp391 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR111) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 393: OpVectorShuffle: FloatVector3: tmp393 << const390, const390, 0, 1, 1 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3a83126f S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR174) src0(SGPR171) V_MOV_B32 vDst(VGPR175) src0(SGPR172) V_MOV_B32 vDst(VGPR176) src0(SGPR172) # 394: OpFAdd: FloatVector3: tmp394 << tmp391, tmp393 V_ADD_F32 vDst(VGPR177) src0(VGPR171) src1(VGPR174) // VOP2 V_ADD_F32 vDst(VGPR178) src0(VGPR172) src1(VGPR175) // VOP2 V_ADD_F32 vDst(VGPR179) src0(VGPR173) src1(VGPR176) // VOP2 # OpStore: : tmp394 >> param395 V_MOV_B32 vDst(VGPR90) src0(VGPR177) V_MOV_B32 vDst(VGPR91) src0(VGPR178) V_MOV_B32 vDst(VGPR92) src0(VGPR179) # 396: OpFunctionCall: Float: DE(vf3;(param395) S_ADD_U32 sDst(SGPR58) src0(LITERAL_CONST) src1(0) const: 0x5a # VGPR[343:345] S_MOV_B64 sDst(SGPR112) src0(EXEC) S_MOV_B32 sDst(SGPR47) src0(LITERAL_CONST) const: 0x6c # VGPR372 # Indirect branch to DE(vf3;: -1596 S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_SUB_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x63c S_SUBB_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR112) # .lbl16 # 397: OpLoad: FloatVector3: tmp397 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR111) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 399: OpVectorShuffle: FloatVector3: tmp399 << const390, const390, 0, 1, 1 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3a83126f S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR174) src0(SGPR171) V_MOV_B32 vDst(VGPR175) src0(SGPR172) V_MOV_B32 vDst(VGPR176) src0(SGPR172) # 400: OpFSub: FloatVector3: tmp400 << tmp397, tmp399 V_SUB_F32 vDst(VGPR177) src0(VGPR171) src1(VGPR174) // VOP2 V_SUB_F32 vDst(VGPR178) src0(VGPR172) src1(VGPR175) // VOP2 V_SUB_F32 vDst(VGPR179) src0(VGPR173) src1(VGPR176) // VOP2 # OpStore: : tmp400 >> param401 V_MOV_B32 vDst(VGPR93) src0(VGPR177) V_MOV_B32 vDst(VGPR94) src0(VGPR178) V_MOV_B32 vDst(VGPR95) src0(VGPR179) # 402: OpFunctionCall: Float: DE(vf3;(param401) S_ADD_U32 sDst(SGPR58) src0(LITERAL_CONST) src1(0) const: 0x5d # VGPR[346:348] S_MOV_B64 sDst(SGPR114) src0(EXEC) S_MOV_B32 sDst(SGPR47) src0(LITERAL_CONST) const: 0x6d # VGPR384 # Indirect branch to DE(vf3;: -1716 S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_SUB_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x6b4 S_SUBB_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR114) # .lbl17 # 403: OpFSub: Float: tmp403 << DE(vf3;, DE(vf3; V_SUB_F32 vDst(VGPR110) src0(VGPR108) src1(VGPR109) // VOP2 # 404: OpLoad: FloatVector3: tmp404 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR111) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 406: OpVectorShuffle: FloatVector3: tmp406 << const390, const390, 1, 0, 1 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3a83126f S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR174) src0(SGPR172) V_MOV_B32 vDst(VGPR175) src0(SGPR171) V_MOV_B32 vDst(VGPR176) src0(SGPR172) # 407: OpFAdd: FloatVector3: tmp407 << tmp404, tmp406 V_ADD_F32 vDst(VGPR177) src0(VGPR171) src1(VGPR174) // VOP2 V_ADD_F32 vDst(VGPR178) src0(VGPR172) src1(VGPR175) // VOP2 V_ADD_F32 vDst(VGPR179) src0(VGPR173) src1(VGPR176) // VOP2 # OpStore: : tmp407 >> param408 V_MOV_B32 vDst(VGPR96) src0(VGPR177) V_MOV_B32 vDst(VGPR97) src0(VGPR178) V_MOV_B32 vDst(VGPR98) src0(VGPR179) # 409: OpFunctionCall: Float: DE(vf3;(param408) S_ADD_U32 sDst(SGPR58) src0(LITERAL_CONST) src1(0) const: 0x60 # VGPR[349:351] S_MOV_B64 sDst(SGPR116) src0(EXEC) S_MOV_B32 sDst(SGPR47) src0(LITERAL_CONST) const: 0x6f # VGPR397 # Indirect branch to DE(vf3;: -1840 S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_SUB_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x730 S_SUBB_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR116) # .lbl18 # 410: OpLoad: FloatVector3: tmp410 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR111) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 412: OpVectorShuffle: FloatVector3: tmp412 << const390, const390, 1, 0, 1 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3a83126f S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR174) src0(SGPR172) V_MOV_B32 vDst(VGPR175) src0(SGPR171) V_MOV_B32 vDst(VGPR176) src0(SGPR172) # 413: OpFSub: FloatVector3: tmp413 << tmp410, tmp412 V_SUB_F32 vDst(VGPR177) src0(VGPR171) src1(VGPR174) // VOP2 V_SUB_F32 vDst(VGPR178) src0(VGPR172) src1(VGPR175) // VOP2 V_SUB_F32 vDst(VGPR179) src0(VGPR173) src1(VGPR176) // VOP2 # OpStore: : tmp413 >> param414 V_MOV_B32 vDst(VGPR99) src0(VGPR177) V_MOV_B32 vDst(VGPR100) src0(VGPR178) V_MOV_B32 vDst(VGPR101) src0(VGPR179) # 415: OpFunctionCall: Float: DE(vf3;(param414) S_ADD_U32 sDst(SGPR58) src0(LITERAL_CONST) src1(0) const: 0x63 # VGPR[352:354] S_MOV_B64 sDst(SGPR118) src0(EXEC) S_MOV_B32 sDst(SGPR47) src0(LITERAL_CONST) const: 0x70 # VGPR409 # Indirect branch to DE(vf3;: -1960 S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_SUB_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x7a8 S_SUBB_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR118) # .lbl19 # 416: OpFSub: Float: tmp416 << DE(vf3;, DE(vf3; V_SUB_F32 vDst(VGPR113) src0(VGPR111) src1(VGPR112) // VOP2 # 417: OpLoad: FloatVector3: tmp417 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR111) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 419: OpVectorShuffle: FloatVector3: tmp419 << const390, const390, 1, 1, 0 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3a83126f S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR174) src0(SGPR172) V_MOV_B32 vDst(VGPR175) src0(SGPR172) V_MOV_B32 vDst(VGPR176) src0(SGPR171) # 420: OpFAdd: FloatVector3: tmp420 << tmp417, tmp419 V_ADD_F32 vDst(VGPR177) src0(VGPR171) src1(VGPR174) // VOP2 V_ADD_F32 vDst(VGPR178) src0(VGPR172) src1(VGPR175) // VOP2 V_ADD_F32 vDst(VGPR179) src0(VGPR173) src1(VGPR176) // VOP2 # OpStore: : tmp420 >> param421 V_MOV_B32 vDst(VGPR102) src0(VGPR177) V_MOV_B32 vDst(VGPR103) src0(VGPR178) V_MOV_B32 vDst(VGPR104) src0(VGPR179) # 422: OpFunctionCall: Float: DE(vf3;(param421) S_ADD_U32 sDst(SGPR58) src0(LITERAL_CONST) src1(0) const: 0x66 # VGPR[355:357] S_MOV_B64 sDst(SGPR120) src0(EXEC) S_MOV_B32 sDst(SGPR47) src0(LITERAL_CONST) const: 0x72 # VGPR422 # Indirect branch to DE(vf3;: -2084 S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_SUB_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x824 S_SUBB_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR120) # .lbl20 # 423: OpLoad: FloatVector3: tmp423 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR111) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR172) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR173) src0(VGPR2) # 425: OpVectorShuffle: FloatVector3: tmp425 << const390, const390, 1, 1, 0 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3a83126f S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR174) src0(SGPR172) V_MOV_B32 vDst(VGPR175) src0(SGPR172) V_MOV_B32 vDst(VGPR176) src0(SGPR171) # 426: OpFSub: FloatVector3: tmp426 << tmp423, tmp425 V_SUB_F32 vDst(VGPR177) src0(VGPR171) src1(VGPR174) // VOP2 V_SUB_F32 vDst(VGPR178) src0(VGPR172) src1(VGPR175) // VOP2 V_SUB_F32 vDst(VGPR179) src0(VGPR173) src1(VGPR176) // VOP2 # OpStore: : tmp426 >> param427 V_MOV_B32 vDst(VGPR105) src0(VGPR177) V_MOV_B32 vDst(VGPR106) src0(VGPR178) V_MOV_B32 vDst(VGPR107) src0(VGPR179) # 428: OpFunctionCall: Float: DE(vf3;(param427) S_ADD_U32 sDst(SGPR58) src0(LITERAL_CONST) src1(0) const: 0x69 # VGPR[358:360] S_MOV_B64 sDst(SGPR122) src0(EXEC) S_MOV_B32 sDst(SGPR47) src0(LITERAL_CONST) const: 0x73 # VGPR434 # Indirect branch to DE(vf3;: -2204 S_GETPC_B64 sDst(SGPR56) src0(SGPR56) S_SUB_U32 sDst(SGPR56) src0(SGPR56) src1(LITERAL_CONST) const: 0x89c S_SUBB_U32 sDst(SGPR57) src0(SGPR57) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR56) src0(SGPR56) S_MOV_B64 sDst(EXEC) src0(SGPR122) # .lbl21 # 429: OpFSub: Float: tmp429 << DE(vf3;, DE(vf3; V_SUB_F32 vDst(VGPR171) src0(VGPR114) src1(VGPR115) // VOP2 # 430: OpCompositeConstruct: FloatVector3: tmp430 << tmp403, tmp416, tmp429 V_MOV_B32 vDst(VGPR172) src0(VGPR110) V_MOV_B32 vDst(VGPR173) src0(VGPR113) V_MOV_B32 vDst(VGPR174) src0(VGPR171) # 431: OpExtInst(Normalize): FloatVector3: tmp431 << tmp430 V_MUL_F32 vDst(VGPR171) src0(VGPR172) src1(VGPR172) // VOP2 V_MAC_F32 vDst(VGPR171) src0(VGPR173) src1(VGPR173) // VOP2 V_MAC_F32 vDst(VGPR171) src0(VGPR174) src1(VGPR174) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR171) src0(VGPR171) V_MUL_F32 vDst(VGPR175) src0(VGPR172) src1(VGPR171) // VOP2 V_MUL_F32 vDst(VGPR176) src0(VGPR173) src1(VGPR171) // VOP2 V_MUL_F32 vDst(VGPR177) src0(VGPR174) src1(VGPR171) // VOP2 # OpReturnValue: : << tmp431 S_MOV_B32 sDst(M0) src0(SGPR110) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR175) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR176) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR177) S_SETPC_B64 sDst(SGPR108) src0(SGPR108) # FloatVector3 light(vf3;vf3;(FloatVector3* p, FloatVector3* n) Function: FloatVector3 light(vf3;vf3;(, FloatVector3 getNorm(vf3;.n) S_MOV_B64 sDst(SGPR130) src0(EXEC) # lb64 Label: lb64 # OpStore: : const436 >> col S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3c23d70a S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x3c23d70a S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x3c23d70a V_MOV_B32 vDst(VGPR116) src0(SGPR171) V_MOV_B32 vDst(VGPR117) src0(SGPR172) V_MOV_B32 vDst(VGPR118) src0(SGPR173) # OpStore: : const250 >> i S_MOV_B32 sDst(SGPR170) src0(0) # OpBranch: to lb438 # lb438 Label: lb438 # OpLoopMerge: (merge: lb440, continue: lb441) # CF Block: Merge: lb440, Continue: lb441 S_MOV_B64 sDst(SGPR132) src0(EXEC) S_MOV_B64 sDst(SGPR134) src0(EXEC) S_MOV_B64 sDst(SGPR136) src0(EXEC) Label: lb438Loop # OpBranch: to lb442 # lb442 Label: lb442 # 443: OpLoad: Int: tmp443 << i Decorators: RelaxedPrecision # 445: OpSLessThan: Bool: tmp445 << tmp443, const444 V_MOV_B32 vDst(VGPR171) src0(2_INT) V_CMP_LT_I32 dst(SGPR172) src0(SGPR170) src1(VGPR171) // VOP3a # OpBranchConditional: if(tmp445) then branch to lb439, else branch to lb440 # CF Block: Cond Branch: true: lb439, false: lb440 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 109 lb440 # lb439 Label: lb439 S_MOV_B64 sDst(SGPR134) src0(EXEC) S_MOV_B64 sDst(SGPR136) src0(EXEC) # 447: OpLoad: Int: tmp447 << i Decorators: RelaxedPrecision # 448: OpIEqual: Bool: tmp448 << tmp447, const250 V_MOV_B32 vDst(VGPR171) src0(0) V_CMP_EQ_I32 dst(SGPR172) src0(SGPR170) src1(VGPR171) // VOP3a # 449: OpLoad: FloatVector3: tmp449 << lDir0 # 450: OpLoad: FloatVector3: tmp450 << lDir1 # 452: OpCompositeConstruct: BoolVector3: tmp452 << tmp448, tmp448, tmp448 S_MOV_B64 sDst(SGPR174) src0(SGPR172) S_MOV_B64 sDst(SGPR176) src0(SGPR172) S_MOV_B64 sDst(SGPR178) src0(SGPR172) # 453: OpSelect: FloatVector3: tmp453 << tmp452, tmp449, tmp450 S_OR_B64 sDst(SGPR171) src0(SGPR174) src1(SGPR176) S_OR_B64 sDst(SGPR171) src0(SGPR178) src1(SGPR171) # CF Block: Merge: .lbl23 S_MOV_B64 sDst(SGPR174) src0(EXEC) # CF Block: Cond Branch: true: .lbl24, false: .lbl22 S_AND_B64 sDst(EXEC) src0(SGPR171) src1(EXEC) S_CBRANCH_EXECZ 3 .lbl22 Label: .lbl24 V_MOV_B32 vDst(VGPR171) src0(SGPR156) V_MOV_B32 vDst(VGPR172) src0(SGPR157) V_MOV_B32 vDst(VGPR173) src0(SGPR158) Label: .lbl22 S_ANDN2_B64 sDst(EXEC) src0(SGPR174) src1(EXEC) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR136) S_CBRANCH_EXECZ 3 .lbl23 V_MOV_B32 vDst(VGPR171) src0(SGPR159) V_MOV_B32 vDst(VGPR172) src0(SGPR160) V_MOV_B32 vDst(VGPR173) src0(SGPR161) Label: .lbl23 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR174) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR136) # 455: OpLoad: FloatVector3: tmp455 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR128) const: 0x0 V_MOVRELS_B32 vDst(VGPR174) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR175) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR176) src0(VGPR2) # 457: OpDot: Float: tmp457 << tmp455, tmp453 V_MUL_F32 vDst(VGPR177) src0(VGPR174) src1(VGPR171) // VOP2 V_MAC_F32 vDst(VGPR177) src0(VGPR175) src1(VGPR172) // VOP2 V_MAC_F32 vDst(VGPR177) src0(VGPR176) src1(VGPR173) // VOP2 # 458: OpExtInst(FMax): Float: tmp458 << tmp457, const174 V_MOV_B32 vDst(VGPR174) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR175) src0(VGPR177) src1(VGPR174) // VOP2 # OpStore: : tmp458 >> diff V_MOV_B32 vDst(VGPR119) src0(VGPR175) # 460: OpLoad: FloatVector3: tmp460 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR127) const: 0x0 V_MOVRELS_B32 vDst(VGPR174) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR175) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR176) src0(VGPR2) # OpStore: : tmp460 >> param459 V_MOV_B32 vDst(VGPR120) src0(VGPR174) V_MOV_B32 vDst(VGPR121) src0(VGPR175) V_MOV_B32 vDst(VGPR122) src0(VGPR176) # 462: OpLoad: FloatVector3: tmp462 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR128) const: 0x0 V_MOVRELS_B32 vDst(VGPR174) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR175) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR176) src0(VGPR2) # OpStore: : tmp462 >> param461 V_MOV_B32 vDst(VGPR123) src0(VGPR174) V_MOV_B32 vDst(VGPR124) src0(VGPR175) V_MOV_B32 vDst(VGPR125) src0(VGPR176) # OpStore: : tmp453 >> param463 V_MOV_B32 vDst(VGPR126) src0(VGPR171) V_MOV_B32 vDst(VGPR127) src0(VGPR172) V_MOV_B32 vDst(VGPR128) src0(VGPR173) # 465: OpFunctionCall: Float: getShadow(vf3;vf3;vf3;(param459, param461, param463) S_ADD_U32 sDst(SGPR95) src0(LITERAL_CONST) src1(0) const: 0x78 # VGPR[448:450] S_ADD_U32 sDst(SGPR96) src0(LITERAL_CONST) src1(0) const: 0x7b # VGPR[451:453] S_ADD_U32 sDst(SGPR97) src0(LITERAL_CONST) src1(0) const: 0x7e # VGPR[454:456] S_MOV_B64 sDst(SGPR138) src0(EXEC) S_MOV_B32 sDst(SGPR94) src0(LITERAL_CONST) const: 0x81 # VGPR477 # Indirect branch to getShadow(vf3;vf3;vf3;: -1604 S_GETPC_B64 sDst(SGPR92) src0(SGPR92) S_SUB_U32 sDst(SGPR92) src0(SGPR92) src1(LITERAL_CONST) const: 0x644 S_SUBB_U32 sDst(SGPR93) src0(SGPR93) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR92) src0(SGPR92) S_MOV_B64 sDst(EXEC) src0(SGPR138) # .lbl25 # 466: OpLoad: Float: tmp466 << diff # 467: OpFMul: Float: tmp467 << tmp466, getShadow(vf3;vf3;vf3; V_MUL_F32 vDst(VGPR171) src0(VGPR119) src1(VGPR129) // VOP2 # OpStore: : tmp467 >> diff V_MOV_B32 vDst(VGPR119) src0(VGPR171) # 468: OpLoad: Float: tmp468 << diff # 469: OpLoad: Int: tmp469 << i Decorators: RelaxedPrecision # 470: OpIEqual: Bool: tmp470 << tmp469, const250 V_MOV_B32 vDst(VGPR171) src0(0) V_CMP_EQ_I32 dst(SGPR172) src0(SGPR170) src1(VGPR171) // VOP3a # 471: OpLoad: FloatVector3: tmp471 << lCol0 # 472: OpLoad: FloatVector3: tmp472 << lCol1 # 473: OpCompositeConstruct: BoolVector3: tmp473 << tmp470, tmp470, tmp470 S_MOV_B64 sDst(SGPR174) src0(SGPR172) S_MOV_B64 sDst(SGPR176) src0(SGPR172) S_MOV_B64 sDst(SGPR178) src0(SGPR172) # 474: OpSelect: FloatVector3: tmp474 << tmp473, tmp471, tmp472 S_OR_B64 sDst(SGPR171) src0(SGPR174) src1(SGPR176) S_OR_B64 sDst(SGPR171) src0(SGPR178) src1(SGPR171) # CF Block: Merge: .lbl27 S_MOV_B64 sDst(SGPR174) src0(EXEC) # CF Block: Cond Branch: true: .lbl28, false: .lbl26 S_AND_B64 sDst(EXEC) src0(SGPR171) src1(EXEC) S_CBRANCH_EXECZ 3 .lbl26 Label: .lbl28 V_MOV_B32 vDst(VGPR171) src0(SGPR162) V_MOV_B32 vDst(VGPR172) src0(SGPR163) V_MOV_B32 vDst(VGPR173) src0(SGPR164) Label: .lbl26 S_ANDN2_B64 sDst(EXEC) src0(SGPR174) src1(EXEC) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR136) S_CBRANCH_EXECZ 3 .lbl27 V_MOV_B32 vDst(VGPR171) src0(SGPR165) V_MOV_B32 vDst(VGPR172) src0(SGPR166) V_MOV_B32 vDst(VGPR173) src0(SGPR167) Label: .lbl27 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR174) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR136) # 475: OpVectorTimesScalar: FloatVector3: tmp475 << tmp474, tmp468 V_MUL_F32 vDst(VGPR174) src0(VGPR119) src1(VGPR171) // VOP2 V_MUL_F32 vDst(VGPR175) src0(VGPR119) src1(VGPR172) // VOP2 V_MUL_F32 vDst(VGPR176) src0(VGPR119) src1(VGPR173) // VOP2 # 476: OpLoad: FloatVector3: tmp476 << col # 477: OpFAdd: FloatVector3: tmp477 << tmp476, tmp475 V_ADD_F32 vDst(VGPR171) src0(VGPR116) src1(VGPR174) // VOP2 V_ADD_F32 vDst(VGPR172) src0(VGPR117) src1(VGPR175) // VOP2 V_ADD_F32 vDst(VGPR173) src0(VGPR118) src1(VGPR176) // VOP2 # OpStore: : tmp477 >> col V_MOV_B32 vDst(VGPR116) src0(VGPR171) V_MOV_B32 vDst(VGPR117) src0(VGPR172) V_MOV_B32 vDst(VGPR118) src0(VGPR173) # OpBranch: to lb441 # lb441 Label: lb441 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR134) # 478: OpLoad: Int: tmp478 << i Decorators: RelaxedPrecision # 479: OpIAdd: Int: tmp479 << tmp478, const271 Decorators: RelaxedPrecision S_MOV_B32 sDst(SGPR171) src0(1_INT) S_ADD_I32 sDst(SGPR172) src0(SGPR170) src1(SGPR171) # OpStore: : tmp479 >> i S_MOV_B32 sDst(SGPR170) src0(SGPR172) # OpBranch: to lb438 S_BRANCH -114 lb438Loop # lb440 Label: lb440 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR132) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR130) # 480: OpLoad: FloatVector3: tmp480 << col # 482: OpVectorTimesScalar: FloatVector3: tmp482 << tmp480, const481 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x3f333333 V_MUL_F32 vDst(VGPR172) src0(VGPR171) src1(VGPR116) // VOP2 V_MUL_F32 vDst(VGPR173) src0(VGPR171) src1(VGPR117) // VOP2 V_MUL_F32 vDst(VGPR174) src0(VGPR171) src1(VGPR118) // VOP2 # OpReturnValue: : << tmp482 S_MOV_B32 sDst(M0) src0(SGPR126) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR172) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR173) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR174) S_SETPC_B64 sDst(SGPR124) src0(SGPR124) # FloatVector3 getSphereColor(i1;(Int* i) Function: FloatVector3 getSphereColor(i1;() S_MOV_B64 sDst(SGPR174) src0(EXEC) # lb70 Label: lb70 # 485: OpLoad: Int: tmp485 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 486: OpIEqual: Bool: tmp486 << tmp485, const250 V_MOV_B32 vDst(VGPR172) src0(0) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb488) # CF Block: Merge: lb488 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp486) then branch to lb487, else branch to lb488 # CF Block: Cond Branch: true: lb487, false: lb488 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 11 lb488 # lb487 Label: lb487 # OpReturnValue: : << const489 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb488 Label: lb488 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 491: OpLoad: Int: tmp491 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 492: OpIEqual: Bool: tmp492 << tmp491, const271 V_MOV_B32 vDst(VGPR172) src0(1_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb494) # CF Block: Merge: lb494 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp492) then branch to lb493, else branch to lb494 # CF Block: Cond Branch: true: lb493, false: lb494 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 10 lb494 # lb493 Label: lb493 # OpReturnValue: : << const495 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR173) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb494 Label: lb494 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 497: OpLoad: Int: tmp497 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 498: OpIEqual: Bool: tmp498 << tmp497, const444 V_MOV_B32 vDst(VGPR172) src0(2_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb500) # CF Block: Merge: lb500 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp498) then branch to lb499, else branch to lb500 # CF Block: Cond Branch: true: lb499, false: lb500 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 10 lb500 # lb499 Label: lb499 # OpReturnValue: : << const501 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR172) src0(1_0_F) S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb500 Label: lb500 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 503: OpLoad: Int: tmp503 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 505: OpIEqual: Bool: tmp505 << tmp503, const504 V_MOV_B32 vDst(VGPR172) src0(3_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb507) # CF Block: Merge: lb507 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp505) then branch to lb506, else branch to lb507 # CF Block: Cond Branch: true: lb506, false: lb507 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 9 lb507 # lb506 Label: lb506 # OpReturnValue: : << const508 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR172) src0(1_0_F) S_MOV_B32 sDst(SGPR173) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb507 Label: lb507 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 510: OpLoad: Int: tmp510 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 512: OpIEqual: Bool: tmp512 << tmp510, const511 V_MOV_B32 vDst(VGPR172) src0(4_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb514) # CF Block: Merge: lb514 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp512) then branch to lb513, else branch to lb514 # CF Block: Cond Branch: true: lb513, false: lb514 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 10 lb514 # lb513 Label: lb513 # OpReturnValue: : << const515 S_MOV_B32 sDst(SGPR171) src0(1_0_F) S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb514 Label: lb514 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 517: OpLoad: Int: tmp517 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 518: OpIEqual: Bool: tmp518 << tmp517, const257 V_MOV_B32 vDst(VGPR172) src0(5_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb520) # CF Block: Merge: lb520 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp518) then branch to lb519, else branch to lb520 # CF Block: Cond Branch: true: lb519, false: lb520 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 9 lb520 # lb519 Label: lb519 # OpReturnValue: : << const521 S_MOV_B32 sDst(SGPR171) src0(1_0_F) S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR173) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb520 Label: lb520 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 523: OpLoad: Int: tmp523 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 525: OpIEqual: Bool: tmp525 << tmp523, const524 V_MOV_B32 vDst(VGPR172) src0(6_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb527) # CF Block: Merge: lb527 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp525) then branch to lb526, else branch to lb527 # CF Block: Cond Branch: true: lb526, false: lb527 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 0 lb527 # lb526 Label: lb526 # OpBranch: to lb527 # lb527 Label: lb527 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 528: OpLoad: Int: tmp528 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 530: OpIEqual: Bool: tmp530 << tmp528, const529 V_MOV_B32 vDst(VGPR172) src0(7_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb532) # CF Block: Merge: lb532 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp530) then branch to lb531, else branch to lb532 # CF Block: Cond Branch: true: lb531, false: lb532 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 8 lb532 # lb531 Label: lb531 # OpReturnValue: : << const533 S_MOV_B32 sDst(SGPR171) src0(1_0_F) S_MOV_B32 sDst(SGPR172) src0(1_0_F) S_MOV_B32 sDst(SGPR173) src0(1_0_F) S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb532 Label: lb532 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 535: OpLoad: Int: tmp535 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 537: OpIEqual: Bool: tmp537 << tmp535, const536 V_MOV_B32 vDst(VGPR172) src0(8_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb539) # CF Block: Merge: lb539 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp537) then branch to lb538, else branch to lb539 # CF Block: Cond Branch: true: lb538, false: lb539 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 11 lb539 # lb538 Label: lb538 # OpReturnValue: : << const543 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x3ed9999a S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x3f0f5c29 S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x3f666666 S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb539 Label: lb539 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 545: OpLoad: Int: tmp545 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 547: OpIEqual: Bool: tmp547 << tmp545, const546 V_MOV_B32 vDst(VGPR172) src0(9_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb549) # CF Block: Merge: lb549 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp547) then branch to lb548, else branch to lb549 # CF Block: Cond Branch: true: lb548, false: lb549 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 10 lb549 # lb548 Label: lb548 # OpReturnValue: : << const550 S_MOV_B32 sDst(SGPR171) src0(0_5_F) S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x3f19999a S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x3f19999a S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb549 Label: lb549 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 552: OpLoad: Int: tmp552 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 554: OpIEqual: Bool: tmp554 << tmp552, const553 V_MOV_B32 vDst(VGPR172) src0(10_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb556) # CF Block: Merge: lb556 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp554) then branch to lb555, else branch to lb556 # CF Block: Cond Branch: true: lb555, false: lb556 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 10 lb556 # lb555 Label: lb555 # OpReturnValue: : << const501 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(SGPR172) src0(1_0_F) S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x0 S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb556 Label: lb556 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 558: OpLoad: Int: tmp558 << i Decorators: RelaxedPrecision S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR142) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR0) # 560: OpIEqual: Bool: tmp560 << tmp558, const559 V_MOV_B32 vDst(VGPR172) src0(11_INT) V_CMP_EQ_I32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb562) # CF Block: Merge: lb562 S_MOV_B64 sDst(SGPR176) src0(EXEC) # OpBranchConditional: if(tmp560) then branch to lb561, else branch to lb562 # CF Block: Cond Branch: true: lb561, false: lb562 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 10 lb562 # lb561 Label: lb561 # OpReturnValue: : << const563 S_MOV_B32 sDst(SGPR171) src0(0_5_F) S_MOV_B32 sDst(SGPR172) src0(LITERAL_CONST) const: 0x3f4ccccd S_MOV_B32 sDst(SGPR173) src0(LITERAL_CONST) const: 0x3f666666 S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_ANDN2_B64 sDst(SGPR174) src0(SGPR174) src1(EXEC) # lb562 Label: lb562 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR176) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR174) # 565: OpUndef: FloatVector3: tmp565 << # OpReturnValue: : << tmp565 S_MOV_B32 sDst(M0) src0(SGPR129) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR171) V_MOVRELD_B32 vDst(VGPR1) src0(SGPR172) V_MOVRELD_B32 vDst(VGPR2) src0(SGPR173) S_SETPC_B64 sDst(SGPR140) src0(SGPR140) # Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) Function: Void mainImage(vf4;vf2;(, FloatVector2 main.fragCoord) S_MOV_B64 sDst(SGPR144) src0(EXEC) # lb77 Label: lb77 # 567: OpLoad: Float: tmp567 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR171) S_WAITCNT 0 # 568: OpFMul: Float: tmp568 << tmp567, const90 V_MOV_B32 vDst(VGPR171) src0(0_5_F) V_MUL_F32 vDst(VGPR172) src0(SGPR171) src1(VGPR171) // VOP2 # 570: OpLoad: FloatVector2: tmp570 << fragCoord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR173) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR174) src0(VGPR1) # 573: OpLoad: FloatVector3: tmp573 << iResolution S_LOAD_DWORDX2_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR[172:173]) S_WAITCNT 0 S_LOAD_DWORD_IMM offset(12) sBase(SGPR[0:1]) sDst(SGPR174) S_WAITCNT 0 # 574: OpVectorShuffle: FloatVector2: tmp574 << tmp573, tmp573, 0, 1 V_MOV_B32 vDst(VGPR171) src0(SGPR172) V_MOV_B32 vDst(VGPR172) src0(SGPR173) # 575: OpVectorTimesScalar: FloatVector2: tmp575 << tmp574, const90 V_MOV_B32 vDst(VGPR175) src0(0_5_F) V_MUL_F32 vDst(VGPR176) src0(VGPR175) src1(VGPR171) // VOP2 V_MUL_F32 vDst(VGPR177) src0(VGPR175) src1(VGPR172) // VOP2 # 576: OpFSub: FloatVector2: tmp576 << tmp570, tmp575 V_SUB_F32 vDst(VGPR171) src0(VGPR173) src1(VGPR176) // VOP2 V_SUB_F32 vDst(VGPR172) src0(VGPR174) src1(VGPR177) // VOP2 # 577: OpAccessChain: Float*: iResolution[1] # 578: OpLoad: Float: tmp578 << iResolution[1] S_LOAD_DWORD_IMM offset(8) sBase(SGPR[0:1]) sDst(SGPR171) S_WAITCNT 0 # 579: OpCompositeConstruct: FloatVector2: tmp579 << tmp578, tmp578 V_MOV_B32 vDst(VGPR173) src0(SGPR171) V_MOV_B32 vDst(VGPR174) src0(SGPR171) # 580: OpFDiv: FloatVector2: tmp580 << tmp576, tmp579 V_RCP_F32 vDst(VGPR149) src0(VGPR173) V_RCP_F32 vDst(VGPR150) src0(VGPR174) V_MUL_F32 vDst(VGPR149) src0(VGPR171) src1(VGPR149) // VOP2 V_MUL_F32 vDst(VGPR150) src0(VGPR172) src1(VGPR150) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR149) src0(VGPR149) src1(VGPR173) src2(VGPR171) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR150) src0(VGPR150) src1(VGPR174) src2(VGPR172) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 583: OpLoad: Float: tmp583 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR171) S_WAITCNT 0 # 584: OpExtInst(Sin): Float: tmp584 << tmp583 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x3e22f983 V_MUL_F32 vDst(VGPR172) src0(VGPR171) src1(SGPR171) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FRACT_F32 vDst(VGPR172) src0(VGPR172) V_SIN_F32 vDst(VGPR172) src0(VGPR172) # 585: OpFMul: Float: tmp585 << const90, tmp584 V_MUL_F32 vDst(VGPR171) src0(0_5_F) src1(VGPR172) // VOP2 # 586: OpFAdd: Float: tmp586 << const582, tmp585 V_ADD_F32 vDst(VGPR172) src0(M1_0_F) src1(VGPR171) // VOP2 # 588: OpLoad: Float: tmp588 << iTime S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR171) S_WAITCNT 0 # 589: OpFMul: Float: tmp589 << tmp588, const90 V_MOV_B32 vDst(VGPR171) src0(0_5_F) V_MUL_F32 vDst(VGPR173) src0(SGPR171) src1(VGPR171) // VOP2 # 590: OpFAdd: Float: tmp590 << const587, tmp589 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0xc0a00000 V_ADD_F32 vDst(VGPR174) src0(VGPR171) src1(VGPR173) // VOP2 # 591: OpCompositeConstruct: FloatVector3: tmp591 << const174, tmp586, tmp590 S_MOV_B32 sDst(SGPR171) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR151) src0(SGPR171) V_MOV_B32 vDst(VGPR152) src0(VGPR172) V_MOV_B32 vDst(VGPR153) src0(VGPR174) # 594: OpCompositeExtract: Float: tmp594 << tmp580, 0 V_MOV_B32 vDst(VGPR171) src0(VGPR149) # 595: OpCompositeExtract: Float: tmp595 << tmp580, 1 V_MOV_B32 vDst(VGPR172) src0(VGPR150) # 596: OpCompositeConstruct: FloatVector3: tmp596 << tmp594, tmp595, const88 V_MOV_B32 vDst(VGPR173) src0(VGPR171) V_MOV_B32 vDst(VGPR174) src0(VGPR172) V_MOV_B32 vDst(VGPR175) src0(1_0_F) # 597: OpExtInst(Normalize): FloatVector3: tmp597 << tmp596 V_MUL_F32 vDst(VGPR171) src0(VGPR173) src1(VGPR173) // VOP2 V_MAC_F32 vDst(VGPR171) src0(VGPR174) src1(VGPR174) // VOP2 V_MAC_F32 vDst(VGPR171) src0(VGPR175) src1(VGPR175) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR171) src0(VGPR171) V_MUL_F32 vDst(VGPR154) src0(VGPR173) src1(VGPR171) // VOP2 V_MUL_F32 vDst(VGPR155) src0(VGPR174) src1(VGPR171) // VOP2 V_MUL_F32 vDst(VGPR156) src0(VGPR175) src1(VGPR171) // VOP2 # OpStore: : tmp591 >> param599 V_MOV_B32 vDst(VGPR130) src0(VGPR151) V_MOV_B32 vDst(VGPR131) src0(VGPR152) V_MOV_B32 vDst(VGPR132) src0(VGPR153) # OpStore: : tmp597 >> param601 V_MOV_B32 vDst(VGPR133) src0(VGPR154) V_MOV_B32 vDst(VGPR134) src0(VGPR155) V_MOV_B32 vDst(VGPR135) src0(VGPR156) # 603: OpFunctionCall: FloatVector2: march(vf3;vf3;(param599, param601) S_ADD_U32 sDst(SGPR80) src0(LITERAL_CONST) src1(0) const: 0x82 # VGPR[552:554] S_ADD_U32 sDst(SGPR81) src0(LITERAL_CONST) src1(0) const: 0x85 # VGPR[555:557] S_MOV_B64 sDst(SGPR146) src0(EXEC) S_MOV_B32 sDst(SGPR59) src0(LITERAL_CONST) const: 0x9d # VGPR[609:610] # Indirect branch to march(vf3;vf3;: -3536 S_GETPC_B64 sDst(SGPR78) src0(SGPR78) S_SUB_U32 sDst(SGPR78) src0(SGPR78) src1(LITERAL_CONST) const: 0xdd0 S_SUBB_U32 sDst(SGPR79) src0(SGPR79) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR78) src0(SGPR78) S_MOV_B64 sDst(EXEC) src0(SGPR146) # .lbl29 # 606: OpAccessChain: Float*: hit[0] # 607: OpCompositeExtract: Float: tmp607 << march(vf3;vf3;, 0 V_MOV_B32 vDst(VGPR171) src0(VGPR157) # 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp597, tmp607 V_MUL_F32 vDst(VGPR172) src0(VGPR171) src1(VGPR154) // VOP2 V_MUL_F32 vDst(VGPR173) src0(VGPR171) src1(VGPR155) // VOP2 V_MUL_F32 vDst(VGPR174) src0(VGPR171) src1(VGPR156) // VOP2 # 610: OpFAdd: FloatVector3: tmp610 << tmp591, tmp609 V_ADD_F32 vDst(VGPR159) src0(VGPR151) src1(VGPR172) // VOP2 V_ADD_F32 vDst(VGPR160) src0(VGPR152) src1(VGPR173) // VOP2 V_ADD_F32 vDst(VGPR161) src0(VGPR153) src1(VGPR174) // VOP2 # OpStore: : tmp610 >> param612 V_MOV_B32 vDst(VGPR136) src0(VGPR159) V_MOV_B32 vDst(VGPR137) src0(VGPR160) V_MOV_B32 vDst(VGPR138) src0(VGPR161) # 614: OpFunctionCall: FloatVector3: getNorm(vf3;(param612) S_ADD_U32 sDst(SGPR111) src0(LITERAL_CONST) src1(0) const: 0x88 # VGPR[558:560] S_MOV_B64 sDst(SGPR148) src0(EXEC) S_MOV_B32 sDst(SGPR110) src0(LITERAL_CONST) const: 0xa2 # VGPR[618:620] # Indirect branch to getNorm(vf3;: -2772 S_GETPC_B64 sDst(SGPR108) src0(SGPR108) S_SUB_U32 sDst(SGPR108) src0(SGPR108) src1(LITERAL_CONST) const: 0xad4 S_SUBB_U32 sDst(SGPR109) src0(SGPR109) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR108) src0(SGPR108) S_MOV_B64 sDst(EXEC) src0(SGPR148) # .lbl30 # 617: OpAccessChain: Float*: hit[0] # 618: OpCompositeExtract: Float: tmp618 << march(vf3;vf3;, 0 V_MOV_B32 vDst(VGPR171) src0(VGPR157) # 619: OpFOrdLessThan: Bool: tmp619 << tmp618, const308 V_MOV_B32 vDst(VGPR172) src0(LITERAL_CONST) const: 0x41a00000 V_CMP_LT_F32 dst(SGPR172) src0(VGPR171) src1(VGPR172) // VOP3a # OpSelectionMerge: (merge: lb621) # CF Block: Merge: lb621 S_MOV_B64 sDst(SGPR150) src0(EXEC) # OpBranchConditional: if(tmp619) then branch to lb620, else branch to lb627 # CF Block: Cond Branch: true: lb620, false: lb627 S_AND_B64 sDst(EXEC) src0(SGPR172) src1(EXEC) S_CBRANCH_EXECZ 23 lb627 # lb620 Label: lb620 # OpStore: : tmp610 >> param622 V_MOV_B32 vDst(VGPR142) src0(VGPR159) V_MOV_B32 vDst(VGPR143) src0(VGPR160) V_MOV_B32 vDst(VGPR144) src0(VGPR161) # OpStore: : getNorm(vf3; >> param624 V_MOV_B32 vDst(VGPR145) src0(VGPR162) V_MOV_B32 vDst(VGPR146) src0(VGPR163) V_MOV_B32 vDst(VGPR147) src0(VGPR164) # 626: OpFunctionCall: FloatVector3: light(vf3;vf3;(param622, param624) S_ADD_U32 sDst(SGPR127) src0(LITERAL_CONST) src1(0) const: 0x8e # VGPR[567:569] S_ADD_U32 sDst(SGPR128) src0(LITERAL_CONST) src1(0) const: 0x91 # VGPR[570:572] S_MOV_B64 sDst(SGPR152) src0(EXEC) S_MOV_B32 sDst(SGPR126) src0(LITERAL_CONST) const: 0xa5 # VGPR[623:625] # Indirect branch to light(vf3;vf3;: -2088 S_GETPC_B64 sDst(SGPR124) src0(SGPR124) S_SUB_U32 sDst(SGPR124) src0(SGPR124) src1(LITERAL_CONST) const: 0x828 S_SUBB_U32 sDst(SGPR125) src0(SGPR125) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR124) src0(SGPR124) S_MOV_B64 sDst(EXEC) src0(SGPR152) # .lbl31 # OpStore: : light(vf3;vf3; >> var616 V_MOV_B32 vDst(VGPR173) src0(VGPR165) V_MOV_B32 vDst(VGPR174) src0(VGPR166) V_MOV_B32 vDst(VGPR175) src0(VGPR167) # OpBranch: to lb621 # lb627 Label: lb627 S_ANDN2_B64 sDst(EXEC) src0(SGPR150) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR144) src1(EXEC) S_CBRANCH_EXECZ 13 lb621 # 629: OpExtInst(Length): Float: tmp629 << tmp580 V_MUL_F32 vDst(VGPR171) src0(VGPR149) src1(VGPR149) // VOP2 V_MAC_F32 vDst(VGPR171) src0(VGPR150) src1(VGPR150) // VOP2 V_SQRT_F32 vDst(VGPR171) src0(VGPR171) # 630: OpFSub: Float: tmp630 << const88, tmp629 V_SUB_F32 vDst(VGPR172) src0(1_0_F) src1(VGPR171) // VOP2 # 631: OpFMul: Float: tmp631 << const385, tmp630 V_MOV_B32 vDst(VGPR171) src0(LITERAL_CONST) const: 0x3dcccccd V_MUL_F32 vDst(VGPR176) src0(VGPR171) src1(VGPR172) // VOP2 # 632: OpCompositeConstruct: FloatVector3: tmp632 << tmp631, tmp631, tmp631 V_MOV_B32 vDst(VGPR177) src0(VGPR176) V_MOV_B32 vDst(VGPR178) src0(VGPR176) V_MOV_B32 vDst(VGPR179) src0(VGPR176) # OpStore: : tmp632 >> var616 V_MOV_B32 vDst(VGPR173) src0(VGPR177) V_MOV_B32 vDst(VGPR174) src0(VGPR178) V_MOV_B32 vDst(VGPR175) src0(VGPR179) # OpBranch: to lb621 # lb621 Label: lb621 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR150) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR144) # 633: OpLoad: FloatVector3: tmp633 << var616 # OpStore: : tmp633 >> col V_MOV_B32 vDst(VGPR139) src0(VGPR173) V_MOV_B32 vDst(VGPR140) src0(VGPR174) V_MOV_B32 vDst(VGPR141) src0(VGPR175) # 635: OpLoad: Float: tmp635 << NumCol # 636: OpConvertFToS: Int: tmp636 << tmp635 V_CVT_I32_F32 vDst(VGPR171) src0(VGPR76) # OpStore: : tmp636 >> param637 V_MOV_B32 vDst(VGPR148) src0(VGPR171) # 638: OpFunctionCall: FloatVector3: getSphereColor(i1;(param637) S_ADD_U32 sDst(SGPR142) src0(LITERAL_CONST) src1(0) const: 0x94 # VGPR573 S_MOV_B64 sDst(SGPR154) src0(EXEC) S_MOV_B32 sDst(SGPR129) src0(LITERAL_CONST) const: 0xa8 # VGPR[634:636] # Indirect branch to getSphereColor(i1;: -1680 S_GETPC_B64 sDst(SGPR140) src0(SGPR140) S_SUB_U32 sDst(SGPR140) src0(SGPR140) src1(LITERAL_CONST) const: 0x690 S_SUBB_U32 sDst(SGPR141) src0(SGPR141) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR140) src0(SGPR140) S_MOV_B64 sDst(EXEC) src0(SGPR154) # .lbl32 # 640: OpLoad: FloatVector3: tmp640 << col # 641: OpFMul: FloatVector3: tmp641 << tmp640, getSphereColor(i1; V_MUL_F32 vDst(VGPR171) src0(VGPR139) src1(VGPR168) // VOP2 V_MUL_F32 vDst(VGPR172) src0(VGPR140) src1(VGPR169) // VOP2 V_MUL_F32 vDst(VGPR173) src0(VGPR141) src1(VGPR170) // VOP2 # OpStore: : tmp641 >> col V_MOV_B32 vDst(VGPR139) src0(VGPR171) V_MOV_B32 vDst(VGPR140) src0(VGPR172) V_MOV_B32 vDst(VGPR141) src0(VGPR173) # 642: OpAccessChain: Float*: hit[1] # 643: OpCompositeExtract: Float: tmp643 << march(vf3;vf3;, 1 V_MOV_B32 vDst(VGPR171) src0(VGPR158) # 644: OpExtInst(Pow): Float: tmp644 << tmp643, const267 V_MOV_B32 vDst(VGPR172) src0(LITERAL_CONST) const: 0x40400000 V_LOG_F32 vDst(VGPR173) src0(VGPR171) V_MUL_F32 vDst(VGPR173) src0(VGPR172) src1(VGPR173) // VOP2 V_EXP_F32 vDst(VGPR173) src0(VGPR173) # 645: OpLoad: FloatVector3: tmp645 << col # 646: OpCompositeConstruct: FloatVector3: tmp646 << tmp644, tmp644, tmp644 V_MOV_B32 vDst(VGPR174) src0(VGPR173) V_MOV_B32 vDst(VGPR175) src0(VGPR173) V_MOV_B32 vDst(VGPR176) src0(VGPR173) # 647: OpFAdd: FloatVector3: tmp647 << tmp645, tmp646 V_ADD_F32 vDst(VGPR177) src0(VGPR139) src1(VGPR174) // VOP2 V_ADD_F32 vDst(VGPR178) src0(VGPR140) src1(VGPR175) // VOP2 V_ADD_F32 vDst(VGPR179) src0(VGPR141) src1(VGPR176) // VOP2 # OpStore: : tmp647 >> col V_MOV_B32 vDst(VGPR139) src0(VGPR177) V_MOV_B32 vDst(VGPR140) src0(VGPR178) V_MOV_B32 vDst(VGPR141) src0(VGPR179) # 648: OpLoad: FloatVector3: tmp648 << col # 649: OpExtInst(Sqrt): FloatVector3: tmp649 << tmp648 V_SQRT_F32 vDst(VGPR171) src0(VGPR139) V_SQRT_F32 vDst(VGPR172) src0(VGPR140) V_SQRT_F32 vDst(VGPR173) src0(VGPR141) # 650: OpCompositeExtract: Float: tmp650 << tmp649, 0 V_MOV_B32 vDst(VGPR174) src0(VGPR171) # 651: OpCompositeExtract: Float: tmp651 << tmp649, 1 V_MOV_B32 vDst(VGPR175) src0(VGPR172) # 652: OpCompositeExtract: Float: tmp652 << tmp649, 2 V_MOV_B32 vDst(VGPR176) src0(VGPR173) # 653: OpCompositeConstruct: FloatVector4: tmp653 << tmp650, tmp651, tmp652, const88 V_MOV_B32 vDst(VGPR177) src0(VGPR174) V_MOV_B32 vDst(VGPR178) src0(VGPR175) V_MOV_B32 vDst(VGPR179) src0(VGPR176) V_MOV_B32 vDst(VGPR180) src0(1_0_F) # OpStore: : tmp653 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR177) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR178) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR179) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR180) # OpReturn: S_SETPC_B64 sDst(SGPR10) src0(SGPR10) Generating the final byte-code... ERROR: Code generation failed. Error log: Need 182 SGPRs, which exceeds the maximum of 102 Done.