W3DNShaderInfo - Get shader information Verbose mode Shader: 10.frag.spv Compiling 10.frag.spv failed (23) with error: shader compilation failed due to errors Log: Shader size: 21464 bytes Parsing SPIR-V code Module Version: 1.2.0 Generator Magic Number: 0x80003 Upper bound on ids: 897 Parsed instructions: OpCapability: : Shader 1: OpExtInstImport: : GLSL.std.450 OpMemoryModel: : addressing: Logical, memory: GLSL450 4: OpEntryPoint: : main, execution model: Fragment 4: OpExecutionMode: : OriginLowerLeft OpSource: : ESSL ver 310 4: OpName: : main 11: OpName: : hash(vf3; 10: OpName: : uv 14: OpName: : noise(vf3; 13: OpName: : uv 17: OpName: : fbm(vf3; 16: OpName: : uv 25: OpName: : tRotate(vf2;f1; 23: OpName: : p 24: OpName: : angel 30: OpName: : tTwist(vf3;f1; 28: OpName: : p 29: OpName: : a 35: OpName: : tRepeat2(vf2;vf2; 33: OpName: : p 34: OpName: : r 40: OpName: : sdRect(vf2;vf2; 38: OpName: : p 39: OpName: : r 45: OpName: : sdCircle(vf2;f1; 43: OpName: : p 44: OpName: : r 50: OpName: : opU(f1;f1; 48: OpName: : a 49: OpName: : b 54: OpName: : opS(f1;f1; 52: OpName: : a 53: OpName: : b 57: OpName: : map(vf3; 56: OpName: : p 64: OpName: : trace(vf3;vf3;f1;f1; 60: OpName: : ro 61: OpName: : rd 62: OpName: : maxDist 63: OpName: : steps 68: OpName: : getNormal(vf3; 67: OpName: : p 73: OpName: : calculateAO(vf3;vf3; 71: OpName: : p 72: OpName: : n 78: OpName: : isWall(vf3; 77: OpName: : p 81: OpName: : _texture(vf3; 80: OpName: : p 88: OpName: : mainImage(vf4;vf2; 86: OpName: : fragColor 87: OpName: : fragCoord 91: OpName: : _twist 93: OpName: : f 107: OpName: : fuv 110: OpName: : cell0 114: OpName: : param114 120: OpName: : param120 125: OpName: : param125 130: OpName: : param130 133: OpName: : axis0 145: OpName: : val0 155: OpName: : cell1 159: OpName: : param159 164: OpName: : param164 169: OpName: : param169 174: OpName: : param174 177: OpName: : axis1 187: OpName: : val1 205: OpName: : f 206: OpName: : r 209: OpName: : i 225: OpName: : param225 243: OpName: : s 246: OpName: : c 264: OpName: : param264 267: OpName: : param267 272: OpName: : id 327: OpName: : param327 329: OpName: : param329 335: OpName: : param335 338: OpName: : param338 351: OpName: : d 357: OpName: : w 364: OpName: : param364 365: OpName: : param365 373: OpName: : param373 374: OpName: : param374 376: OpName: : param376 377: OpName: : param377 379: OpName: : param379 381: OpName: : param381 392: OpName: : param392 393: OpName: : param393 395: OpName: : param395 397: OpName: : param397 404: OpName: : param404 405: OpName: : param405 407: OpName: : param407 409: OpName: : param409 422: OpName: : param422 423: OpName: : param423 425: OpName: : param425 427: OpName: : param427 436: OpName: : param436 438: OpName: : param438 443: OpName: : total 444: OpName: : i 455: OpName: : d 461: OpName: : param461 481: OpName: : e 488: OpName: : param488 494: OpName: : param494 501: OpName: : param501 507: OpName: : param507 514: OpName: : param514 520: OpName: : param520 527: OpName: : r 528: OpName: : w 529: OpName: : i 538: OpName: : d 549: OpName: : param549 569: OpName: : param569 572: OpName: : param572 588: OpName: : param588 590: OpName: : param590 595: OpName: : wall 596: OpName: : param596 599: OpName: : t 610: OpName: : param610 620: OpName: : param620 628: OpName: : param628 646: OpName: : uv 649: OpName: : iResolution 666: OpName: : time 667: OpName: : iTime 673: OpName: : ro 683: OpName: : rd 692: OpName: : light 710: OpName: : param710 713: OpName: : param713 723: OpName: : param723 726: OpName: : param726 736: OpName: : param736 739: OpName: : param739 749: OpName: : param749 752: OpName: : param752 757: OpName: : dist 758: OpName: : steps 759: OpName: : param759 761: OpName: : param761 763: OpName: : param763 764: OpName: : param764 767: OpName: : p 773: OpName: : normal 774: OpName: : param774 777: OpName: : l 782: OpName: : shadowStart 788: OpName: : shadowDistance 792: OpName: : shadow 793: OpName: : shadowSteps 794: OpName: : param794 796: OpName: : param796 798: OpName: : param798 800: OpName: : param800 813: OpName: : ambient 814: OpName: : diffuse 819: OpName: : specular 830: OpName: : ao 831: OpName: : param831 833: OpName: : param833 837: OpName: : param837 870: OpName: : color 872: OpName: : gl_FragCoord 873: OpName: : param873 874: OpName: : param874 880: OpName: : finalColor 883: OpName: : iMouse 884: OpName: : iDate 885: OpName: : iFrame 889: OpName: : iChannelResolution 893: OpName: : iChannel0 894: OpName: : iChannel1 895: OpName: : iChannel2 896: OpName: : iChannel3 209: OpDecorate: : RelaxedPrecision 216: OpDecorate: : RelaxedPrecision 233: OpDecorate: : RelaxedPrecision 235: OpDecorate: : RelaxedPrecision 444: OpDecorate: : RelaxedPrecision 450: OpDecorate: : RelaxedPrecision 476: OpDecorate: : RelaxedPrecision 477: OpDecorate: : RelaxedPrecision 872: OpDecorate: : BuiltIn(FragCoord) 893: OpDecorate: : RelaxedPrecision 893: OpDecorate: : DescriptorSet(0) 894: OpDecorate: : RelaxedPrecision 894: OpDecorate: : DescriptorSet(0) 895: OpDecorate: : RelaxedPrecision 895: OpDecorate: : DescriptorSet(0) 896: OpDecorate: : RelaxedPrecision 896: OpDecorate: : DescriptorSet(0) 2: OpTypeVoid: Void 3: OpTypeFunction: 2 << func() 6: OpTypeFloat: Float: 32 bits 7: OpTypeVector: ???Vector3: num-elements: 3, element type id: 6 8: OpTypePointer: ???Ptr: storage class: Function 9: OpTypeFunction: 6 << func(8) 19: OpTypeVector: ???Vector2: num-elements: 2, element type id: 6 20: OpTypePointer: ???Ptr: storage class: Function 21: OpTypePointer: ???Ptr: storage class: Function 22: OpTypeFunction: 2 << func(20, 21) 27: OpTypeFunction: 2 << func(8, 21) 32: OpTypeFunction: 19 << func(20, 20) 37: OpTypeFunction: 6 << func(20, 20) 42: OpTypeFunction: 6 << func(20, 21) 47: OpTypeFunction: 6 << func(21, 21) 59: OpTypeFunction: 6 << func(8, 8, 21, 21) 66: OpTypeFunction: 7 << func(8) 70: OpTypeFunction: 6 << func(8, 8) 75: OpTypeBool: Bool 76: OpTypeFunction: 75 << func(8) 83: OpTypeVector: ???Vector4: num-elements: 4, element type id: 6 84: OpTypePointer: ???Ptr: storage class: Function 85: OpTypeFunction: 2 << func(84, 20) 90: OpTypePointer: ???Ptr: storage class: Private 91: OpVariable: 90: var91: storage class: Private 92: OpConstant: 6 const92 = 0x0 95: OpConstant: 6 const95 = 0x3c157c67 96: OpConstant: 6 const96 = 0x3b178a76 97: OpConstant: 6 const97 = 0x3bae6706 98: OpConstantComposite: 7 const98 = {id:95, id:96, id:97} 101: OpConstant: 6 const101 = 0x47d903c6 112: OpConstantComposite: 7 const112 = {id:92, id:92, id:92} 117: OpConstant: 6 const117 = 0x3f800000 118: OpConstantComposite: 7 const118 = {id:92, id:117, id:92} 123: OpConstantComposite: 7 const123 = {id:117, id:92, id:92} 128: OpConstantComposite: 7 const128 = {id:117, id:117, id:92} 138: OpTypeInt: UInt: 32 bits, unsigned 139: OpConstant: 138 const139 = 0x1 146: OpConstant: 138 const146 = 0x0 157: OpConstantComposite: 7 const157 = {id:92, id:92, id:117} 162: OpConstantComposite: 7 const162 = {id:92, id:117, id:117} 167: OpConstantComposite: 7 const167 = {id:117, id:92, id:117} 172: OpConstantComposite: 7 const172 = {id:117, id:117, id:117} 198: OpConstant: 138 const198 = 0x2 207: OpTypeInt: Int: 32 bits, signed 208: OpTypePointer: ???Ptr: storage class: Function 210: OpConstant: 207 const210 = 0x0 217: OpConstant: 207 const217 = 0x5 220: OpConstant: 6 const220 = 0x41200000 227: OpConstant: 6 const227 = 0x40000000 234: OpConstant: 207 const234 = 0x1 254: OpTypeMatrix: Matrix?x?: num-columns: 2, column type id: 19 275: OpConstant: 6 const275 = 0x3f000000 333: OpConstant: 6 const333 = 0x3f333333 334: OpConstantComposite: 19 const334 = {id:333, id:117} 355: OpConstant: 6 const355 = 0x3e19999a 360: OpConstant: 6 const360 = 0x3f400000 361: OpConstantComposite: 19 const361 = {id:92, id:360} 363: OpConstant: 6 const363 = 0x3e800000 369: OpConstant: 6 const369 = 0x3ec00000 370: OpConstantComposite: 19 const370 = {id:92, id:369} 372: OpConstantComposite: 19 const372 = {id:363, id:369} 386: OpConstant: 6 const386 = 0x3eb33333 387: OpConstantComposite: 19 const387 = {id:92, id:386} 389: OpConstant: 6 const389 = 0x3ee66666 390: OpConstant: 6 const390 = 0x3e99999a 391: OpConstantComposite: 19 const391 = {id:389, id:390} 401: OpConstantComposite: 19 const401 = {id:386, id:92} 403: OpConstant: 6 const403 = 0x3d99999a 417: OpConstant: 6 const417 = 0x3f19999a 418: OpConstantComposite: 19 const418 = {id:417, id:275} 420: OpConstant: 6 const420 = 0x3ecccccd 421: OpConstantComposite: 19 const421 = {id:417, id:420} 434: OpConstant: 6 const434 = 0x3f4ccccd 451: OpConstant: 207 const451 = 0x64 467: OpConstant: 6 const467 = 0x3727c5ac 482: OpConstant: 6 const482 = 0x38d1b717 483: OpConstantComposite: 19 const483 = {id:482, id:92} 536: OpConstant: 6 const536 = 0x40a00000 594: OpTypePointer: ???Ptr: storage class: Function 606: OpConstant: 6 const606 = 0x3dcccccd 607: OpConstant: 6 const607 = 0x3f666666 617: OpConstant: 6 const617 = 0x41a00000 618: OpConstantComposite: 7 const618 = {id:536, id:617, id:536} 622: OpConstantComposite: 7 const622 = {id:117, id:333, id:420} 626: OpConstantComposite: 7 const626 = {id:227, id:220, id:227} 630: OpConstantComposite: 7 const630 = {id:117, id:434, id:275} 648: OpTypePointer: ???Ptr: storage class: UniformConstant 649: OpVariable: 648: var649: storage class: UniformConstant 656: OpTypePointer: ???Ptr: storage class: UniformConstant 667: OpVariable: 656: var667: storage class: UniformConstant 675: OpConstant: 6 const675 = 0x40490fdb 685: OpConstant: 6 const685 = 0x3fc00000 807: OpConstant: 6 const807 = 0x42c80000 828: OpConstant: 6 const828 = 0x41000000 857: OpConstantComposite: 83 const857 = {id:607, id:434, id:333, id:117} 861: OpConstant: 6 const861 = 0x3cf5c28f 867: OpConstant: 6 const867 = 0x3ee8ba2f 868: OpConstantComposite: 83 const868 = {id:867, id:867, id:867, id:867} 871: OpTypePointer: ???Ptr: storage class: Input 872: OpVariable: 871: var872: storage class: Input 879: OpTypePointer: ???Ptr: storage class: Output 880: OpVariable: 879: var880: storage class: Output 882: OpTypePointer: ???Ptr: storage class: UniformConstant 883: OpVariable: 882: var883: storage class: UniformConstant 884: OpVariable: 882: var884: storage class: UniformConstant 885: OpVariable: 656: var885: storage class: UniformConstant 886: OpConstant: 138 const886 = 0x4 887: OpTypeArray: ???[]: length id: 886, element type id: 7 888: OpTypePointer: ???Ptr: storage class: UniformConstant 889: OpVariable: 888: var889: storage class: UniformConstant 890: OpTypeImage: Image(6): 2D, no-depth, sampled, ReadOnly 891: OpTypeSampledImage: SampledImage(890) 892: OpTypePointer: ???Ptr: storage class: UniformConstant 893: OpVariable: 892: var893: storage class: UniformConstant 894: OpVariable: 892: var894: storage class: UniformConstant 895: OpVariable: 892: var895: storage class: UniformConstant 896: OpVariable: 892: var896: storage class: UniformConstant 4: OpFunction: func4(type: 3) 5: OpLabel: 870: OpVariable: 84: var870: storage class: Function 873: OpVariable: 84: var873: storage class: Function 874: OpVariable: 20: var874: storage class: Function OpStore: : 92 >> 91 875: OpLoad: 83: tmp875 << 872 876: OpVectorShuffle: 19: tmp876 << 875, 875, 0, 1 OpStore: : 876 >> 874 877: OpFunctionCall: 2: tmp877(873, 874) 878: OpLoad: 83: tmp878 << 873 OpStore: : 878 >> 870 881: OpLoad: 83: tmp881 << 870 OpStore: : 881 >> 880 OpReturn: OpFunctionEnd: 11: OpFunction: func11(type: 9) 10: OpFunctionParameter: 8: var10: storage class: Function 12: OpLabel: 93: OpVariable: 21: var93: storage class: Function 94: OpLoad: 7: tmp94 << 10 99: OpDot: 6: tmp99 << 94, 98 100: OpExtInst(13): 6: tmp100 << 99 102: OpFMul: 6: tmp102 << 100, 101 103: OpExtInst(10): 6: tmp103 << 102 OpStore: : 103 >> 93 104: OpLoad: 6: tmp104 << 93 OpReturnValue: : << 104 OpFunctionEnd: 14: OpFunction: func14(type: 9) 13: OpFunctionParameter: 8: var13: storage class: Function 15: OpLabel: 107: OpVariable: 8: var107: storage class: Function 110: OpVariable: 84: var110: storage class: Function 114: OpVariable: 8: var114: storage class: Function 120: OpVariable: 8: var120: storage class: Function 125: OpVariable: 8: var125: storage class: Function 130: OpVariable: 8: var130: storage class: Function 133: OpVariable: 20: var133: storage class: Function 145: OpVariable: 21: var145: storage class: Function 155: OpVariable: 84: var155: storage class: Function 159: OpVariable: 8: var159: storage class: Function 164: OpVariable: 8: var164: storage class: Function 169: OpVariable: 8: var169: storage class: Function 174: OpVariable: 8: var174: storage class: Function 177: OpVariable: 20: var177: storage class: Function 187: OpVariable: 21: var187: storage class: Function 108: OpLoad: 7: tmp108 << 13 109: OpExtInst(8): 7: tmp109 << 108 OpStore: : 109 >> 107 111: OpLoad: 7: tmp111 << 107 113: OpFAdd: 7: tmp113 << 111, 112 OpStore: : 113 >> 114 115: OpFunctionCall: 6: tmp115(114) 116: OpLoad: 7: tmp116 << 107 119: OpFAdd: 7: tmp119 << 116, 118 OpStore: : 119 >> 120 121: OpFunctionCall: 6: tmp121(120) 122: OpLoad: 7: tmp122 << 107 124: OpFAdd: 7: tmp124 << 122, 123 OpStore: : 124 >> 125 126: OpFunctionCall: 6: tmp126(125) 127: OpLoad: 7: tmp127 << 107 129: OpFAdd: 7: tmp129 << 127, 128 OpStore: : 129 >> 130 131: OpFunctionCall: 6: tmp131(130) 132: OpCompositeConstruct: 83: tmp132 << 115, 121, 126, 131 OpStore: : 132 >> 110 134: OpLoad: 83: tmp134 << 110 135: OpVectorShuffle: 19: tmp135 << 134, 134, 0, 2 136: OpLoad: 83: tmp136 << 110 137: OpVectorShuffle: 19: tmp137 << 136, 136, 1, 3 140: OpAccessChain: 21: 13[139] 141: OpLoad: 6: tmp141 << 140 142: OpExtInst(10): 6: tmp142 << 141 143: OpCompositeConstruct: 19: tmp143 << 142, 142 144: OpExtInst(46): 19: tmp144 << 135, 137, 143 OpStore: : 144 >> 133 147: OpAccessChain: 21: 133[146] 148: OpLoad: 6: tmp148 << 147 149: OpAccessChain: 21: 133[139] 150: OpLoad: 6: tmp150 << 149 151: OpAccessChain: 21: 13[146] 152: OpLoad: 6: tmp152 << 151 153: OpExtInst(10): 6: tmp153 << 152 154: OpExtInst(46): 6: tmp154 << 148, 150, 153 OpStore: : 154 >> 145 156: OpLoad: 7: tmp156 << 107 158: OpFAdd: 7: tmp158 << 156, 157 OpStore: : 158 >> 159 160: OpFunctionCall: 6: tmp160(159) 161: OpLoad: 7: tmp161 << 107 163: OpFAdd: 7: tmp163 << 161, 162 OpStore: : 163 >> 164 165: OpFunctionCall: 6: tmp165(164) 166: OpLoad: 7: tmp166 << 107 168: OpFAdd: 7: tmp168 << 166, 167 OpStore: : 168 >> 169 170: OpFunctionCall: 6: tmp170(169) 171: OpLoad: 7: tmp171 << 107 173: OpFAdd: 7: tmp173 << 171, 172 OpStore: : 173 >> 174 175: OpFunctionCall: 6: tmp175(174) 176: OpCompositeConstruct: 83: tmp176 << 160, 165, 170, 175 OpStore: : 176 >> 155 178: OpLoad: 83: tmp178 << 155 179: OpVectorShuffle: 19: tmp179 << 178, 178, 0, 2 180: OpLoad: 83: tmp180 << 155 181: OpVectorShuffle: 19: tmp181 << 180, 180, 1, 3 182: OpAccessChain: 21: 13[139] 183: OpLoad: 6: tmp183 << 182 184: OpExtInst(10): 6: tmp184 << 183 185: OpCompositeConstruct: 19: tmp185 << 184, 184 186: OpExtInst(46): 19: tmp186 << 179, 181, 185 OpStore: : 186 >> 177 188: OpAccessChain: 21: 177[146] 189: OpLoad: 6: tmp189 << 188 190: OpAccessChain: 21: 177[139] 191: OpLoad: 6: tmp191 << 190 192: OpAccessChain: 21: 13[146] 193: OpLoad: 6: tmp193 << 192 194: OpExtInst(10): 6: tmp194 << 193 195: OpExtInst(46): 6: tmp195 << 189, 191, 194 OpStore: : 195 >> 187 196: OpLoad: 6: tmp196 << 145 197: OpLoad: 6: tmp197 << 187 199: OpAccessChain: 21: 13[198] 200: OpLoad: 6: tmp200 << 199 201: OpExtInst(10): 6: tmp201 << 200 202: OpExtInst(46): 6: tmp202 << 196, 197, 201 OpReturnValue: : << 202 OpFunctionEnd: 17: OpFunction: func17(type: 9) 16: OpFunctionParameter: 8: var16: storage class: Function 18: OpLabel: 205: OpVariable: 21: var205: storage class: Function 206: OpVariable: 21: var206: storage class: Function 209: OpVariable: 208: var209: storage class: Function 225: OpVariable: 8: var225: storage class: Function OpStore: : 92 >> 205 OpStore: : 117 >> 206 OpStore: : 210 >> 209 OpBranch: to 211 211: OpLabel: OpLoopMerge: (merge: 213, continue: 214) OpBranch: to 215 215: OpLabel: 216: OpLoad: 207: tmp216 << 209 218: OpSLessThan: 75: tmp218 << 216, 217 OpBranchConditional: if(218) then branch to 212, else branch to 213 212: OpLabel: 219: OpLoad: 7: tmp219 << 16 221: OpCompositeConstruct: 7: tmp221 << 220, 220, 220 222: OpFAdd: 7: tmp222 << 219, 221 223: OpLoad: 6: tmp223 << 206 224: OpVectorTimesScalar: 7: tmp224 << 222, 223 OpStore: : 224 >> 225 226: OpFunctionCall: 6: tmp226(225) 228: OpLoad: 6: tmp228 << 206 229: OpFMul: 6: tmp229 << 228, 227 OpStore: : 229 >> 206 230: OpFDiv: 6: tmp230 << 226, 229 231: OpLoad: 6: tmp231 << 205 232: OpFAdd: 6: tmp232 << 231, 230 OpStore: : 232 >> 205 OpBranch: to 214 214: OpLabel: 233: OpLoad: 207: tmp233 << 209 235: OpIAdd: 207: tmp235 << 233, 234 OpStore: : 235 >> 209 OpBranch: to 211 213: OpLabel: 236: OpLoad: 6: tmp236 << 205 237: OpLoad: 6: tmp237 << 206 238: OpFDiv: 6: tmp238 << 117, 237 239: OpFSub: 6: tmp239 << 117, 238 240: OpFDiv: 6: tmp240 << 236, 239 OpReturnValue: : << 240 OpFunctionEnd: 25: OpFunction: func25(type: 22) 23: OpFunctionParameter: 20: var23: storage class: Function 24: OpFunctionParameter: 21: var24: storage class: Function 26: OpLabel: 243: OpVariable: 21: var243: storage class: Function 246: OpVariable: 21: var246: storage class: Function 244: OpLoad: 6: tmp244 << 24 245: OpExtInst(13): 6: tmp245 << 244 OpStore: : 245 >> 243 247: OpLoad: 6: tmp247 << 24 248: OpExtInst(14): 6: tmp248 << 247 OpStore: : 248 >> 246 249: OpLoad: 6: tmp249 << 246 250: OpLoad: 6: tmp250 << 243 251: OpFNegate: 6: tmp251 << 250 252: OpLoad: 6: tmp252 << 243 253: OpLoad: 6: tmp253 << 246 255: OpCompositeConstruct: 19: tmp255 << 249, 251 256: OpCompositeConstruct: 19: tmp256 << 252, 253 257: OpCompositeConstruct: 254: tmp257 << 255, 256 258: OpLoad: 19: tmp258 << 23 259: OpVectorTimesMatrix: 19: tmp259 << 258, 257 OpStore: : 259 >> 23 OpReturn: OpFunctionEnd: 30: OpFunction: func30(type: 27) 28: OpFunctionParameter: 8: var28: storage class: Function 29: OpFunctionParameter: 21: var29: storage class: Function 31: OpLabel: 264: OpVariable: 20: var264: storage class: Function 267: OpVariable: 21: var267: storage class: Function 260: OpAccessChain: 21: 28[198] 261: OpLoad: 6: tmp261 << 260 262: OpLoad: 6: tmp262 << 29 263: OpFMul: 6: tmp263 << 261, 262 265: OpLoad: 7: tmp265 << 28 266: OpVectorShuffle: 19: tmp266 << 265, 265, 0, 1 OpStore: : 266 >> 264 OpStore: : 263 >> 267 268: OpFunctionCall: 2: tmp268(264, 267) 269: OpLoad: 19: tmp269 << 264 270: OpLoad: 7: tmp270 << 28 271: OpVectorShuffle: 7: tmp271 << 270, 269, 3, 4, 2 OpStore: : 271 >> 28 OpReturn: OpFunctionEnd: 35: OpFunction: func35(type: 32) 33: OpFunctionParameter: 20: var33: storage class: Function 34: OpFunctionParameter: 20: var34: storage class: Function 36: OpLabel: 272: OpVariable: 20: var272: storage class: Function 273: OpLoad: 19: tmp273 << 33 274: OpLoad: 19: tmp274 << 34 276: OpVectorTimesScalar: 19: tmp276 << 274, 275 277: OpFAdd: 19: tmp277 << 273, 276 278: OpLoad: 19: tmp278 << 34 279: OpFDiv: 19: tmp279 << 277, 278 280: OpExtInst(8): 19: tmp280 << 279 OpStore: : 280 >> 272 281: OpLoad: 19: tmp281 << 33 282: OpLoad: 19: tmp282 << 34 283: OpVectorTimesScalar: 19: tmp283 << 282, 275 284: OpFAdd: 19: tmp284 << 281, 283 285: OpLoad: 19: tmp285 << 34 286: OpFMod: 19: tmp286 << 284, 285 287: OpLoad: 19: tmp287 << 34 288: OpVectorTimesScalar: 19: tmp288 << 287, 275 289: OpFSub: 19: tmp289 << 286, 288 OpStore: : 289 >> 33 290: OpLoad: 19: tmp290 << 272 OpReturnValue: : << 290 OpFunctionEnd: 40: OpFunction: func40(type: 37) 38: OpFunctionParameter: 20: var38: storage class: Function 39: OpFunctionParameter: 20: var39: storage class: Function 41: OpLabel: 293: OpLoad: 19: tmp293 << 38 294: OpExtInst(4): 19: tmp294 << 293 295: OpLoad: 19: tmp295 << 39 296: OpFSub: 19: tmp296 << 294, 295 OpStore: : 296 >> 38 297: OpAccessChain: 21: 38[146] 298: OpLoad: 6: tmp298 << 297 299: OpAccessChain: 21: 38[139] 300: OpLoad: 6: tmp300 << 299 301: OpExtInst(40): 6: tmp301 << 298, 300 302: OpExtInst(37): 6: tmp302 << 301, 92 303: OpLoad: 19: tmp303 << 38 304: OpCompositeConstruct: 19: tmp304 << 92, 92 305: OpExtInst(40): 19: tmp305 << 303, 304 306: OpExtInst(66): 6: tmp306 << 305 307: OpFAdd: 6: tmp307 << 302, 306 OpReturnValue: : << 307 OpFunctionEnd: 45: OpFunction: func45(type: 42) 43: OpFunctionParameter: 20: var43: storage class: Function 44: OpFunctionParameter: 21: var44: storage class: Function 46: OpLabel: 310: OpLoad: 19: tmp310 << 43 311: OpExtInst(66): 6: tmp311 << 310 312: OpLoad: 6: tmp312 << 44 313: OpFSub: 6: tmp313 << 311, 312 OpReturnValue: : << 313 OpFunctionEnd: 50: OpFunction: func50(type: 47) 48: OpFunctionParameter: 21: var48: storage class: Function 49: OpFunctionParameter: 21: var49: storage class: Function 51: OpLabel: 316: OpLoad: 6: tmp316 << 48 317: OpLoad: 6: tmp317 << 49 318: OpExtInst(37): 6: tmp318 << 316, 317 OpReturnValue: : << 318 OpFunctionEnd: 54: OpFunction: func54(type: 47) 52: OpFunctionParameter: 21: var52: storage class: Function 53: OpFunctionParameter: 21: var53: storage class: Function 55: OpLabel: 321: OpLoad: 6: tmp321 << 52 322: OpLoad: 6: tmp322 << 53 323: OpFNegate: 6: tmp323 << 322 324: OpExtInst(40): 6: tmp324 << 321, 323 OpReturnValue: : << 324 OpFunctionEnd: 57: OpFunction: func57(type: 9) 56: OpFunctionParameter: 8: var56: storage class: Function 58: OpLabel: 327: OpVariable: 8: var327: storage class: Function 329: OpVariable: 21: var329: storage class: Function 335: OpVariable: 20: var335: storage class: Function 338: OpVariable: 20: var338: storage class: Function 351: OpVariable: 21: var351: storage class: Function 357: OpVariable: 21: var357: storage class: Function 364: OpVariable: 20: var364: storage class: Function 365: OpVariable: 21: var365: storage class: Function 373: OpVariable: 20: var373: storage class: Function 374: OpVariable: 20: var374: storage class: Function 376: OpVariable: 21: var376: storage class: Function 377: OpVariable: 21: var377: storage class: Function 379: OpVariable: 21: var379: storage class: Function 381: OpVariable: 21: var381: storage class: Function 392: OpVariable: 20: var392: storage class: Function 393: OpVariable: 20: var393: storage class: Function 395: OpVariable: 21: var395: storage class: Function 397: OpVariable: 21: var397: storage class: Function 404: OpVariable: 20: var404: storage class: Function 405: OpVariable: 21: var405: storage class: Function 407: OpVariable: 21: var407: storage class: Function 409: OpVariable: 21: var409: storage class: Function 422: OpVariable: 20: var422: storage class: Function 423: OpVariable: 20: var423: storage class: Function 425: OpVariable: 21: var425: storage class: Function 427: OpVariable: 21: var427: storage class: Function 436: OpVariable: 21: var436: storage class: Function 438: OpVariable: 21: var438: storage class: Function 328: OpLoad: 7: tmp328 << 56 OpStore: : 328 >> 327 330: OpLoad: 6: tmp330 << 91 OpStore: : 330 >> 329 331: OpFunctionCall: 2: tmp331(327, 329) 332: OpLoad: 7: tmp332 << 327 OpStore: : 332 >> 56 336: OpLoad: 7: tmp336 << 56 337: OpVectorShuffle: 19: tmp337 << 336, 336, 0, 2 OpStore: : 337 >> 335 OpStore: : 334 >> 338 339: OpFunctionCall: 19: tmp339(335, 338) 340: OpLoad: 19: tmp340 << 335 341: OpLoad: 7: tmp341 << 56 342: OpVectorShuffle: 7: tmp342 << 341, 340, 3, 1, 4 OpStore: : 342 >> 56 343: OpAccessChain: 21: 56[146] 344: OpLoad: 6: tmp344 << 343 345: OpExtInst(4): 6: tmp345 << 344 346: OpAccessChain: 21: 56[146] OpStore: : 345 >> 346 347: OpAccessChain: 21: 56[139] 348: OpLoad: 6: tmp348 << 347 349: OpFAdd: 6: tmp349 << 348, 275 350: OpAccessChain: 21: 56[139] OpStore: : 349 >> 350 352: OpAccessChain: 21: 56[198] 353: OpLoad: 6: tmp353 << 352 354: OpExtInst(4): 6: tmp354 << 353 356: OpFSub: 6: tmp356 << 354, 355 OpStore: : 356 >> 351 358: OpLoad: 7: tmp358 << 56 359: OpVectorShuffle: 19: tmp359 << 358, 358, 0, 1 362: OpFSub: 19: tmp362 << 359, 361 OpStore: : 362 >> 364 OpStore: : 363 >> 365 366: OpFunctionCall: 6: tmp366(364, 365) 367: OpLoad: 7: tmp367 << 56 368: OpVectorShuffle: 19: tmp368 << 367, 367, 0, 1 371: OpFSub: 19: tmp371 << 368, 370 OpStore: : 371 >> 373 OpStore: : 372 >> 374 375: OpFunctionCall: 6: tmp375(373, 374) OpStore: : 366 >> 376 OpStore: : 375 >> 377 378: OpFunctionCall: 6: tmp378(376, 377) OpStore: : 378 >> 357 380: OpLoad: 6: tmp380 << 351 OpStore: : 380 >> 379 382: OpLoad: 6: tmp382 << 357 OpStore: : 382 >> 381 383: OpFunctionCall: 6: tmp383(379, 381) OpStore: : 383 >> 351 384: OpLoad: 7: tmp384 << 56 385: OpVectorShuffle: 19: tmp385 << 384, 384, 0, 1 388: OpFSub: 19: tmp388 << 385, 387 OpStore: : 388 >> 392 OpStore: : 391 >> 393 394: OpFunctionCall: 6: tmp394(392, 393) 396: OpLoad: 6: tmp396 << 351 OpStore: : 396 >> 395 OpStore: : 394 >> 397 398: OpFunctionCall: 6: tmp398(395, 397) OpStore: : 398 >> 351 399: OpLoad: 7: tmp399 << 56 400: OpVectorShuffle: 19: tmp400 << 399, 399, 0, 2 402: OpFSub: 19: tmp402 << 400, 401 OpStore: : 402 >> 404 OpStore: : 403 >> 405 406: OpFunctionCall: 6: tmp406(404, 405) 408: OpLoad: 6: tmp408 << 351 OpStore: : 408 >> 407 OpStore: : 406 >> 409 410: OpFunctionCall: 6: tmp410(407, 409) OpStore: : 410 >> 351 411: OpAccessChain: 21: 56[198] 412: OpLoad: 6: tmp412 << 411 413: OpExtInst(4): 6: tmp413 << 412 414: OpAccessChain: 21: 56[198] OpStore: : 413 >> 414 415: OpLoad: 7: tmp415 << 56 416: OpVectorShuffle: 19: tmp416 << 415, 415, 1, 2 419: OpFSub: 19: tmp419 << 416, 418 OpStore: : 419 >> 422 OpStore: : 421 >> 423 424: OpFunctionCall: 6: tmp424(422, 423) 426: OpLoad: 6: tmp426 << 351 OpStore: : 426 >> 425 OpStore: : 424 >> 427 428: OpFunctionCall: 6: tmp428(425, 427) OpStore: : 428 >> 351 429: OpAccessChain: 21: 56[139] 430: OpLoad: 6: tmp430 << 429 431: OpFSub: 6: tmp431 << 430, 275 432: OpExtInst(4): 6: tmp432 << 431 433: OpFNegate: 6: tmp433 << 432 435: OpFAdd: 6: tmp435 << 433, 434 437: OpLoad: 6: tmp437 << 351 OpStore: : 437 >> 436 OpStore: : 435 >> 438 439: OpFunctionCall: 6: tmp439(436, 438) OpStore: : 439 >> 351 440: OpLoad: 6: tmp440 << 351 OpReturnValue: : << 440 OpFunctionEnd: 64: OpFunction: func64(type: 59) 60: OpFunctionParameter: 8: var60: storage class: Function 61: OpFunctionParameter: 8: var61: storage class: Function 62: OpFunctionParameter: 21: var62: storage class: Function 63: OpFunctionParameter: 21: var63: storage class: Function 65: OpLabel: 443: OpVariable: 21: var443: storage class: Function 444: OpVariable: 208: var444: storage class: Function 455: OpVariable: 21: var455: storage class: Function 461: OpVariable: 8: var461: storage class: Function OpStore: : 92 >> 443 OpStore: : 92 >> 63 OpStore: : 210 >> 444 OpBranch: to 445 445: OpLabel: OpLoopMerge: (merge: 447, continue: 448) OpBranch: to 449 449: OpLabel: 450: OpLoad: 207: tmp450 << 444 452: OpSLessThan: 75: tmp452 << 450, 451 OpBranchConditional: if(452) then branch to 446, else branch to 447 446: OpLabel: 453: OpLoad: 6: tmp453 << 63 454: OpFAdd: 6: tmp454 << 453, 117 OpStore: : 454 >> 63 456: OpLoad: 7: tmp456 << 60 457: OpLoad: 7: tmp457 << 61 458: OpLoad: 6: tmp458 << 443 459: OpVectorTimesScalar: 7: tmp459 << 457, 458 460: OpFAdd: 7: tmp460 << 456, 459 OpStore: : 460 >> 461 462: OpFunctionCall: 6: tmp462(461) OpStore: : 462 >> 455 463: OpLoad: 6: tmp463 << 455 464: OpLoad: 6: tmp464 << 443 465: OpFAdd: 6: tmp465 << 464, 463 OpStore: : 465 >> 443 466: OpLoad: 6: tmp466 << 455 468: OpFOrdLessThan: 75: tmp468 << 466, 467 469: OpLoad: 6: tmp469 << 62 470: OpLoad: 6: tmp470 << 443 471: OpFOrdLessThan: 75: tmp471 << 469, 470 472: OpLogicalOr: 75: tmp472 << 468, 471 OpSelectionMerge: (merge: 474) OpBranchConditional: if(472) then branch to 473, else branch to 474 473: OpLabel: OpBranch: to 447 474: OpLabel: OpBranch: to 448 448: OpLabel: 476: OpLoad: 207: tmp476 << 444 477: OpIAdd: 207: tmp477 << 476, 234 OpStore: : 477 >> 444 OpBranch: to 445 447: OpLabel: 478: OpLoad: 6: tmp478 << 443 OpReturnValue: : << 478 OpFunctionEnd: 68: OpFunction: func68(type: 66) 67: OpFunctionParameter: 8: var67: storage class: Function 69: OpLabel: 481: OpVariable: 20: var481: storage class: Function 488: OpVariable: 8: var488: storage class: Function 494: OpVariable: 8: var494: storage class: Function 501: OpVariable: 8: var501: storage class: Function 507: OpVariable: 8: var507: storage class: Function 514: OpVariable: 8: var514: storage class: Function 520: OpVariable: 8: var520: storage class: Function OpStore: : 483 >> 481 484: OpLoad: 7: tmp484 << 67 485: OpLoad: 19: tmp485 << 481 486: OpVectorShuffle: 7: tmp486 << 485, 485, 0, 1, 1 487: OpFAdd: 7: tmp487 << 484, 486 OpStore: : 487 >> 488 489: OpFunctionCall: 6: tmp489(488) 490: OpLoad: 7: tmp490 << 67 491: OpLoad: 19: tmp491 << 481 492: OpVectorShuffle: 7: tmp492 << 491, 491, 0, 1, 1 493: OpFSub: 7: tmp493 << 490, 492 OpStore: : 493 >> 494 495: OpFunctionCall: 6: tmp495(494) 496: OpFSub: 6: tmp496 << 489, 495 497: OpLoad: 7: tmp497 << 67 498: OpLoad: 19: tmp498 << 481 499: OpVectorShuffle: 7: tmp499 << 498, 498, 1, 0, 1 500: OpFAdd: 7: tmp500 << 497, 499 OpStore: : 500 >> 501 502: OpFunctionCall: 6: tmp502(501) 503: OpLoad: 7: tmp503 << 67 504: OpLoad: 19: tmp504 << 481 505: OpVectorShuffle: 7: tmp505 << 504, 504, 1, 0, 1 506: OpFSub: 7: tmp506 << 503, 505 OpStore: : 506 >> 507 508: OpFunctionCall: 6: tmp508(507) 509: OpFSub: 6: tmp509 << 502, 508 510: OpLoad: 7: tmp510 << 67 511: OpLoad: 19: tmp511 << 481 512: OpVectorShuffle: 7: tmp512 << 511, 511, 1, 1, 0 513: OpFAdd: 7: tmp513 << 510, 512 OpStore: : 513 >> 514 515: OpFunctionCall: 6: tmp515(514) 516: OpLoad: 7: tmp516 << 67 517: OpLoad: 19: tmp517 << 481 518: OpVectorShuffle: 7: tmp518 << 517, 517, 1, 1, 0 519: OpFSub: 7: tmp519 << 516, 518 OpStore: : 519 >> 520 521: OpFunctionCall: 6: tmp521(520) 522: OpFSub: 6: tmp522 << 515, 521 523: OpCompositeConstruct: 7: tmp523 << 496, 509, 522 524: OpExtInst(69): 7: tmp524 << 523 OpReturnValue: : << 524 OpFunctionEnd: 73: OpFunction: func73(type: 70) 71: OpFunctionParameter: 8: var71: storage class: Function 72: OpFunctionParameter: 8: var72: storage class: Function 74: OpLabel: 527: OpVariable: 21: var527: storage class: Function 528: OpVariable: 21: var528: storage class: Function 529: OpVariable: 21: var529: storage class: Function 538: OpVariable: 21: var538: storage class: Function 549: OpVariable: 8: var549: storage class: Function OpStore: : 92 >> 527 OpStore: : 117 >> 528 OpStore: : 117 >> 529 OpBranch: to 530 530: OpLabel: OpLoopMerge: (merge: 532, continue: 533) OpBranch: to 534 534: OpLabel: 535: OpLoad: 6: tmp535 << 529 537: OpFOrdLessThanEqual: 75: tmp537 << 535, 536 OpBranchConditional: if(537) then branch to 531, else branch to 532 531: OpLabel: 539: OpLoad: 6: tmp539 << 529 540: OpFDiv: 6: tmp540 << 539, 536 541: OpFDiv: 6: tmp541 << 540, 220 OpStore: : 541 >> 538 542: OpLoad: 6: tmp542 << 528 543: OpLoad: 6: tmp543 << 538 544: OpLoad: 7: tmp544 << 71 545: OpLoad: 7: tmp545 << 72 546: OpLoad: 6: tmp546 << 538 547: OpVectorTimesScalar: 7: tmp547 << 545, 546 548: OpFAdd: 7: tmp548 << 544, 547 OpStore: : 548 >> 549 550: OpFunctionCall: 6: tmp550(549) 551: OpFSub: 6: tmp551 << 543, 550 552: OpFMul: 6: tmp552 << 542, 551 553: OpLoad: 6: tmp553 << 527 554: OpFAdd: 6: tmp554 << 553, 552 OpStore: : 554 >> 527 555: OpLoad: 6: tmp555 << 528 556: OpFMul: 6: tmp556 << 555, 275 OpStore: : 556 >> 528 OpBranch: to 533 533: OpLabel: 557: OpLoad: 6: tmp557 << 529 558: OpFAdd: 6: tmp558 << 557, 117 OpStore: : 558 >> 529 OpBranch: to 530 532: OpLabel: 559: OpLoad: 6: tmp559 << 527 560: OpFMul: 6: tmp560 << 559, 220 561: OpExtInst(43): 6: tmp561 << 560, 92, 117 562: OpFSub: 6: tmp562 << 117, 561 OpReturnValue: : << 562 OpFunctionEnd: 78: OpFunction: func78(type: 76) 77: OpFunctionParameter: 8: var77: storage class: Function 79: OpLabel: 569: OpVariable: 20: var569: storage class: Function 572: OpVariable: 20: var572: storage class: Function 565: OpAccessChain: 21: 77[146] 566: OpLoad: 6: tmp566 << 565 567: OpFAdd: 6: tmp567 << 566, 386 568: OpAccessChain: 21: 77[146] OpStore: : 567 >> 568 570: OpLoad: 7: tmp570 << 77 571: OpVectorShuffle: 19: tmp571 << 570, 570, 0, 2 OpStore: : 571 >> 569 OpStore: : 334 >> 572 573: OpFunctionCall: 19: tmp573(569, 572) 574: OpLoad: 19: tmp574 << 569 575: OpLoad: 7: tmp575 << 77 576: OpVectorShuffle: 7: tmp576 << 575, 574, 3, 1, 4 OpStore: : 576 >> 77 577: OpAccessChain: 21: 77[139] 578: OpLoad: 6: tmp578 << 577 579: OpFAdd: 6: tmp579 << 578, 355 580: OpExtInst(4): 6: tmp580 << 579 581: OpLoad: 7: tmp581 << 77 582: OpVectorShuffle: 19: tmp582 << 581, 581, 0, 2 583: OpExtInst(66): 6: tmp583 << 582 584: OpFAdd: 6: tmp584 << 580, 583 585: OpFOrdLessThan: 75: tmp585 << 369, 584 OpReturnValue: : << 585 OpFunctionEnd: 81: OpFunction: func81(type: 66) 80: OpFunctionParameter: 8: var80: storage class: Function 82: OpLabel: 588: OpVariable: 8: var588: storage class: Function 590: OpVariable: 21: var590: storage class: Function 595: OpVariable: 594: var595: storage class: Function 596: OpVariable: 8: var596: storage class: Function 599: OpVariable: 8: var599: storage class: Function 601: OpVariable: 21: var601: storage class: Function 610: OpVariable: 8: var610: storage class: Function 620: OpVariable: 8: var620: storage class: Function 628: OpVariable: 8: var628: storage class: Function 589: OpLoad: 7: tmp589 << 80 OpStore: : 589 >> 588 591: OpLoad: 6: tmp591 << 91 OpStore: : 591 >> 590 592: OpFunctionCall: 2: tmp592(588, 590) 593: OpLoad: 7: tmp593 << 588 OpStore: : 593 >> 80 597: OpLoad: 7: tmp597 << 80 OpStore: : 597 >> 596 598: OpFunctionCall: 75: tmp598(596) OpStore: : 598 >> 595 600: OpLoad: 7: tmp600 << 80 602: OpLoad: 75: tmp602 << 595 OpSelectionMerge: (merge: 604) OpBranchConditional: if(602) then branch to 603, else branch to 605 603: OpLabel: OpStore: : 92 >> 601 OpBranch: to 604 605: OpLabel: 608: OpLoad: 7: tmp608 << 80 609: OpVectorTimesScalar: 7: tmp609 << 608, 536 OpStore: : 609 >> 610 611: OpFunctionCall: 6: tmp611(610) 612: OpFMul: 6: tmp612 << 607, 611 613: OpFAdd: 6: tmp613 << 606, 612 OpStore: : 613 >> 601 OpBranch: to 604 604: OpLabel: 614: OpLoad: 6: tmp614 << 601 615: OpCompositeConstruct: 7: tmp615 << 614, 614, 614 616: OpFAdd: 7: tmp616 << 600, 615 619: OpFMul: 7: tmp619 << 616, 618 OpStore: : 619 >> 620 621: OpFunctionCall: 6: tmp621(620) 623: OpVectorTimesScalar: 7: tmp623 << 622, 621 624: OpVectorTimesScalar: 7: tmp624 << 623, 360 625: OpLoad: 7: tmp625 << 80 627: OpFMul: 7: tmp627 << 625, 626 OpStore: : 627 >> 628 629: OpFunctionCall: 6: tmp629(628) 631: OpVectorTimesScalar: 7: tmp631 << 630, 629 632: OpVectorTimesScalar: 7: tmp632 << 631, 363 633: OpFAdd: 7: tmp633 << 624, 632 OpStore: : 633 >> 599 634: OpLoad: 75: tmp634 << 595 OpSelectionMerge: (merge: 636) OpBranchConditional: if(634) then branch to 635, else branch to 636 635: OpLabel: 637: OpLoad: 7: tmp637 << 599 638: OpCompositeConstruct: 7: tmp638 << 275, 275, 275 639: OpExtInst(46): 7: tmp639 << 637, 172, 638 OpStore: : 639 >> 599 OpBranch: to 636 636: OpLabel: 640: OpLoad: 7: tmp640 << 599 641: OpCompositeConstruct: 7: tmp641 << 92, 92, 92 642: OpCompositeConstruct: 7: tmp642 << 117, 117, 117 643: OpExtInst(43): 7: tmp643 << 640, 641, 642 OpReturnValue: : << 643 OpFunctionEnd: 88: OpFunction: func88(type: 85) 86: OpFunctionParameter: 84: var86: storage class: Function 87: OpFunctionParameter: 20: var87: storage class: Function 89: OpLabel: 646: OpVariable: 20: var646: storage class: Function 666: OpVariable: 21: var666: storage class: Function 673: OpVariable: 8: var673: storage class: Function 683: OpVariable: 8: var683: storage class: Function 692: OpVariable: 8: var692: storage class: Function 710: OpVariable: 20: var710: storage class: Function 713: OpVariable: 21: var713: storage class: Function 723: OpVariable: 20: var723: storage class: Function 726: OpVariable: 21: var726: storage class: Function 736: OpVariable: 20: var736: storage class: Function 739: OpVariable: 21: var739: storage class: Function 749: OpVariable: 20: var749: storage class: Function 752: OpVariable: 21: var752: storage class: Function 757: OpVariable: 21: var757: storage class: Function 758: OpVariable: 21: var758: storage class: Function 759: OpVariable: 8: var759: storage class: Function 761: OpVariable: 8: var761: storage class: Function 763: OpVariable: 21: var763: storage class: Function 764: OpVariable: 21: var764: storage class: Function 767: OpVariable: 8: var767: storage class: Function 773: OpVariable: 8: var773: storage class: Function 774: OpVariable: 8: var774: storage class: Function 777: OpVariable: 8: var777: storage class: Function 782: OpVariable: 8: var782: storage class: Function 788: OpVariable: 21: var788: storage class: Function 792: OpVariable: 21: var792: storage class: Function 793: OpVariable: 21: var793: storage class: Function 794: OpVariable: 8: var794: storage class: Function 796: OpVariable: 8: var796: storage class: Function 798: OpVariable: 21: var798: storage class: Function 800: OpVariable: 21: var800: storage class: Function 813: OpVariable: 21: var813: storage class: Function 814: OpVariable: 21: var814: storage class: Function 819: OpVariable: 21: var819: storage class: Function 830: OpVariable: 21: var830: storage class: Function 831: OpVariable: 8: var831: storage class: Function 833: OpVariable: 8: var833: storage class: Function 837: OpVariable: 8: var837: storage class: Function 647: OpLoad: 19: tmp647 << 87 650: OpLoad: 7: tmp650 << 649 651: OpVectorShuffle: 19: tmp651 << 650, 650, 0, 1 652: OpFDiv: 19: tmp652 << 647, 651 653: OpVectorTimesScalar: 19: tmp653 << 652, 227 654: OpCompositeConstruct: 19: tmp654 << 117, 117 655: OpFSub: 19: tmp655 << 653, 654 OpStore: : 655 >> 646 657: OpAccessChain: 656: 649[146] 658: OpLoad: 6: tmp658 << 657 659: OpAccessChain: 656: 649[139] 660: OpLoad: 6: tmp660 << 659 661: OpFDiv: 6: tmp661 << 658, 660 662: OpAccessChain: 21: 646[146] 663: OpLoad: 6: tmp663 << 662 664: OpFMul: 6: tmp664 << 663, 661 665: OpAccessChain: 21: 646[146] OpStore: : 664 >> 665 668: OpLoad: 6: tmp668 << 667 669: OpFMul: 6: tmp669 << 668, 275 OpStore: : 669 >> 666 670: OpLoad: 6: tmp670 << 666 671: OpExtInst(13): 6: tmp671 << 670 672: OpFMul: 6: tmp672 << 671, 420 OpStore: : 672 >> 91 674: OpLoad: 6: tmp674 << 666 676: OpFMul: 6: tmp676 << 674, 675 677: OpFDiv: 6: tmp677 << 676, 227 678: OpFAdd: 6: tmp678 << 677, 117 679: OpExtInst(13): 6: tmp679 << 678 680: OpFMul: 6: tmp680 << 679, 117 681: OpLoad: 6: tmp681 << 666 682: OpCompositeConstruct: 7: tmp682 << 680, 92, 681 OpStore: : 682 >> 673 684: OpLoad: 19: tmp684 << 646 686: OpCompositeExtract: 6: tmp686 << 684, 0 687: OpCompositeExtract: 6: tmp687 << 684, 1 688: OpCompositeConstruct: 7: tmp688 << 686, 687, 685 689: OpExtInst(69): 7: tmp689 << 688 OpStore: : 689 >> 683 690: OpLoad: 6: tmp690 << 666 691: OpFAdd: 6: tmp691 << 690, 227 OpStore: : 691 >> 666 693: OpLoad: 6: tmp693 << 666 694: OpFMul: 6: tmp694 << 693, 675 695: OpFDiv: 6: tmp695 << 694, 227 696: OpFAdd: 6: tmp696 << 695, 117 697: OpExtInst(13): 6: tmp697 << 696 698: OpFMul: 6: tmp698 << 697, 117 699: OpLoad: 6: tmp699 << 666 700: OpCompositeConstruct: 7: tmp700 << 698, 92, 699 OpStore: : 700 >> 692 701: OpLoad: 6: tmp701 << 666 702: OpFSub: 6: tmp702 << 701, 227 OpStore: : 702 >> 666 703: OpLoad: 6: tmp703 << 666 704: OpFMul: 6: tmp704 << 703, 675 705: OpFDiv: 6: tmp705 << 704, 227 706: OpFAdd: 6: tmp706 << 705, 117 707: OpExtInst(14): 6: tmp707 << 706 708: OpFNegate: 6: tmp708 << 707 709: OpFMul: 6: tmp709 << 708, 275 711: OpLoad: 7: tmp711 << 683 712: OpVectorShuffle: 19: tmp712 << 711, 711, 0, 2 OpStore: : 712 >> 710 OpStore: : 709 >> 713 714: OpFunctionCall: 2: tmp714(710, 713) 715: OpLoad: 19: tmp715 << 710 716: OpLoad: 7: tmp716 << 683 717: OpVectorShuffle: 7: tmp717 << 716, 715, 3, 1, 4 OpStore: : 717 >> 683 718: OpAccessChain: 21: 673[198] 719: OpLoad: 6: tmp719 << 718 720: OpFNegate: 6: tmp720 << 719 721: OpLoad: 6: tmp721 << 91 722: OpFMul: 6: tmp722 << 720, 721 724: OpLoad: 7: tmp724 << 673 725: OpVectorShuffle: 19: tmp725 << 724, 724, 0, 1 OpStore: : 725 >> 723 OpStore: : 722 >> 726 727: OpFunctionCall: 2: tmp727(723, 726) 728: OpLoad: 19: tmp728 << 723 729: OpLoad: 7: tmp729 << 673 730: OpVectorShuffle: 7: tmp730 << 729, 728, 3, 4, 2 OpStore: : 730 >> 673 731: OpAccessChain: 21: 692[198] 732: OpLoad: 6: tmp732 << 731 733: OpFNegate: 6: tmp733 << 732 734: OpLoad: 6: tmp734 << 91 735: OpFMul: 6: tmp735 << 733, 734 737: OpLoad: 7: tmp737 << 692 738: OpVectorShuffle: 19: tmp738 << 737, 737, 0, 1 OpStore: : 738 >> 736 OpStore: : 735 >> 739 740: OpFunctionCall: 2: tmp740(736, 739) 741: OpLoad: 19: tmp741 << 736 742: OpLoad: 7: tmp742 << 692 743: OpVectorShuffle: 7: tmp743 << 742, 741, 3, 4, 2 OpStore: : 743 >> 692 744: OpAccessChain: 21: 673[198] 745: OpLoad: 6: tmp745 << 744 746: OpFNegate: 6: tmp746 << 745 747: OpLoad: 6: tmp747 << 91 748: OpFMul: 6: tmp748 << 746, 747 750: OpLoad: 7: tmp750 << 683 751: OpVectorShuffle: 19: tmp751 << 750, 750, 0, 1 OpStore: : 751 >> 749 OpStore: : 748 >> 752 753: OpFunctionCall: 2: tmp753(749, 752) 754: OpLoad: 19: tmp754 << 749 755: OpLoad: 7: tmp755 << 683 756: OpVectorShuffle: 7: tmp756 << 755, 754, 3, 4, 2 OpStore: : 756 >> 683 760: OpLoad: 7: tmp760 << 673 OpStore: : 760 >> 759 762: OpLoad: 7: tmp762 << 683 OpStore: : 762 >> 761 OpStore: : 220 >> 763 765: OpFunctionCall: 6: tmp765(759, 761, 763, 764) 766: OpLoad: 6: tmp766 << 764 OpStore: : 766 >> 758 OpStore: : 765 >> 757 768: OpLoad: 7: tmp768 << 673 769: OpLoad: 7: tmp769 << 683 770: OpLoad: 6: tmp770 << 757 771: OpVectorTimesScalar: 7: tmp771 << 769, 770 772: OpFAdd: 7: tmp772 << 768, 771 OpStore: : 772 >> 767 775: OpLoad: 7: tmp775 << 767 OpStore: : 775 >> 774 776: OpFunctionCall: 7: tmp776(774) OpStore: : 776 >> 773 778: OpLoad: 7: tmp778 << 692 779: OpLoad: 7: tmp779 << 767 780: OpFSub: 7: tmp780 << 778, 779 781: OpExtInst(69): 7: tmp781 << 780 OpStore: : 781 >> 777 783: OpLoad: 7: tmp783 << 767 784: OpLoad: 7: tmp784 << 773 785: OpVectorTimesScalar: 7: tmp785 << 784, 467 786: OpVectorTimesScalar: 7: tmp786 << 785, 220 787: OpFAdd: 7: tmp787 << 783, 786 OpStore: : 787 >> 782 789: OpLoad: 7: tmp789 << 782 790: OpLoad: 7: tmp790 << 692 791: OpExtInst(67): 6: tmp791 << 789, 790 OpStore: : 791 >> 788 795: OpLoad: 7: tmp795 << 782 OpStore: : 795 >> 794 797: OpLoad: 7: tmp797 << 777 OpStore: : 797 >> 796 799: OpLoad: 6: tmp799 << 788 OpStore: : 799 >> 798 801: OpFunctionCall: 6: tmp801(794, 796, 798, 800) 802: OpLoad: 6: tmp802 << 800 OpStore: : 802 >> 793 803: OpLoad: 6: tmp803 << 788 804: OpFOrdGreaterThan: 75: tmp804 << 801, 803 805: OpSelect: 6: tmp805 << 804, 117, 92 OpStore: : 805 >> 792 806: OpLoad: 6: tmp806 << 793 808: OpFDiv: 6: tmp808 << 806, 807 809: OpExtInst(31): 6: tmp809 << 808 810: OpFSub: 6: tmp810 << 117, 809 811: OpLoad: 6: tmp811 << 792 812: OpFMul: 6: tmp812 << 811, 810 OpStore: : 812 >> 792 OpStore: : 363 >> 813 815: OpLoad: 7: tmp815 << 777 816: OpLoad: 7: tmp816 << 773 817: OpDot: 6: tmp817 << 815, 816 818: OpExtInst(40): 6: tmp818 << 92, 817 OpStore: : 818 >> 814 820: OpLoad: 7: tmp820 << 777 821: OpFNegate: 7: tmp821 << 820 822: OpLoad: 7: tmp822 << 773 823: OpExtInst(71): 7: tmp823 << 821, 822 824: OpLoad: 7: tmp824 << 683 825: OpFNegate: 7: tmp825 << 824 826: OpDot: 6: tmp826 << 823, 825 827: OpExtInst(40): 6: tmp827 << 92, 826 829: OpExtInst(26): 6: tmp829 << 827, 828 OpStore: : 829 >> 819 832: OpLoad: 7: tmp832 << 767 OpStore: : 832 >> 831 834: OpLoad: 7: tmp834 << 773 OpStore: : 834 >> 833 835: OpFunctionCall: 6: tmp835(831, 833) OpStore: : 835 >> 830 836: OpLoad: 6: tmp836 << 830 838: OpLoad: 7: tmp838 << 767 OpStore: : 838 >> 837 839: OpFunctionCall: 7: tmp839(837) 840: OpVectorTimesScalar: 7: tmp840 << 839, 836 841: OpLoad: 6: tmp841 << 813 842: OpLoad: 6: tmp842 << 819 843: OpLoad: 6: tmp843 << 814 844: OpFAdd: 6: tmp844 << 842, 843 845: OpLoad: 6: tmp845 << 792 846: OpFMul: 6: tmp846 << 844, 845 847: OpFAdd: 6: tmp847 << 841, 846 848: OpVectorTimesScalar: 7: tmp848 << 840, 847 849: OpLoad: 83: tmp849 << 86 850: OpVectorShuffle: 83: tmp850 << 849, 848, 4, 5, 6, 3 OpStore: : 850 >> 86 851: OpLoad: 6: tmp851 << 758 852: OpFDiv: 6: tmp852 << 851, 807 853: OpExtInst(31): 6: tmp853 << 852 854: OpLoad: 83: tmp854 << 86 855: OpVectorTimesScalar: 83: tmp855 << 854, 853 OpStore: : 855 >> 86 856: OpLoad: 83: tmp856 << 86 858: OpLoad: 6: tmp858 << 757 859: OpLoad: 6: tmp859 << 757 860: OpFMul: 6: tmp860 << 858, 859 862: OpFMul: 6: tmp862 << 860, 861 863: OpExtInst(43): 6: tmp863 << 862, 92, 117 864: OpCompositeConstruct: 83: tmp864 << 863, 863, 863, 863 865: OpExtInst(46): 83: tmp865 << 856, 857, 864 OpStore: : 865 >> 86 866: OpLoad: 83: tmp866 << 86 869: OpExtInst(26): 83: tmp869 << 866, 868 OpStore: : 869 >> 86 OpReturn: OpFunctionEnd: Linking the instructions Initial Disassembly: Module Info: OpSource: : ESSL ver 310 1: OpExtInstImport: : GLSL.std.450 OpMemoryModel: : addressing: Logical, memory: GLSL450 Capabilities: OpCapability: : Shader Inputs: 872: OpVariable: FloatVector4*: gl_FragCoord: storage class: Input Decorators: BuiltIn(FragCoord) Outputs: 880: OpVariable: FloatVector4*: finalColor: storage class: Output Uniform Constants: 649: OpVariable: FloatVector3*: iResolution: storage class: UniformConstant 667: OpVariable: Float*: iTime: storage class: UniformConstant 883: OpVariable: FloatVector4*: iMouse: storage class: UniformConstant 884: OpVariable: FloatVector4*: iDate: storage class: UniformConstant 885: OpVariable: Float*: iFrame: storage class: UniformConstant 889: OpVariable: FloatVector3[4]*: iChannelResolution: storage class: UniformConstant Textures: 893: OpVariable: SampledImage(Image(Float))*: iChannel0: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 894: OpVariable: SampledImage(Image(Float))*: iChannel1: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 895: OpVariable: SampledImage(Image(Float))*: iChannel2: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 896: OpVariable: SampledImage(Image(Float))*: iChannel3: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) Entry Points: 4: OpEntryPoint: : main, execution model: Fragment, Function: Void main(), OriginLowerLeft Constants: 92: OpConstant: Float const92 = 0 95: OpConstant: Float const95 = 0.0091239 96: OpConstant: Float const96 = 0.00231233 97: OpConstant: Float const97 = 0.00532234 98: OpConstantComposite: FloatVector3 const98 = {0.0091239, 0.00231233, 0.00532234} 101: OpConstant: Float const101 = 111112 112: OpConstantComposite: FloatVector3 const112 = {0, 0, 0} 117: OpConstant: Float const117 = 1 118: OpConstantComposite: FloatVector3 const118 = {0, 1, 0} 123: OpConstantComposite: FloatVector3 const123 = {1, 0, 0} 128: OpConstantComposite: FloatVector3 const128 = {1, 1, 0} 139: OpConstant: UInt const139 = 1 146: OpConstant: UInt const146 = 0 157: OpConstantComposite: FloatVector3 const157 = {0, 0, 1} 162: OpConstantComposite: FloatVector3 const162 = {0, 1, 1} 167: OpConstantComposite: FloatVector3 const167 = {1, 0, 1} 172: OpConstantComposite: FloatVector3 const172 = {1, 1, 1} 198: OpConstant: UInt const198 = 2 210: OpConstant: Int const210 = 0 217: OpConstant: Int const217 = 5 220: OpConstant: Float const220 = 10 227: OpConstant: Float const227 = 2 234: OpConstant: Int const234 = 1 275: OpConstant: Float const275 = 0.5 333: OpConstant: Float const333 = 0.7 334: OpConstantComposite: FloatVector2 const334 = {0.7, 1} 355: OpConstant: Float const355 = 0.15 360: OpConstant: Float const360 = 0.75 361: OpConstantComposite: FloatVector2 const361 = {0, 0.75} 363: OpConstant: Float const363 = 0.25 369: OpConstant: Float const369 = 0.375 370: OpConstantComposite: FloatVector2 const370 = {0, 0.375} 372: OpConstantComposite: FloatVector2 const372 = {0.25, 0.375} 386: OpConstant: Float const386 = 0.35 387: OpConstantComposite: FloatVector2 const387 = {0, 0.35} 389: OpConstant: Float const389 = 0.45 390: OpConstant: Float const390 = 0.3 391: OpConstantComposite: FloatVector2 const391 = {0.45, 0.3} 401: OpConstantComposite: FloatVector2 const401 = {0.35, 0} 403: OpConstant: Float const403 = 0.075 417: OpConstant: Float const417 = 0.6 418: OpConstantComposite: FloatVector2 const418 = {0.6, 0.5} 420: OpConstant: Float const420 = 0.4 421: OpConstantComposite: FloatVector2 const421 = {0.6, 0.4} 434: OpConstant: Float const434 = 0.8 451: OpConstant: Int const451 = 100 467: OpConstant: Float const467 = 1e-05 482: OpConstant: Float const482 = 0.0001 483: OpConstantComposite: FloatVector2 const483 = {0.0001, 0} 536: OpConstant: Float const536 = 5 606: OpConstant: Float const606 = 0.1 607: OpConstant: Float const607 = 0.9 617: OpConstant: Float const617 = 20 618: OpConstantComposite: FloatVector3 const618 = {5, 20, 5} 622: OpConstantComposite: FloatVector3 const622 = {1, 0.7, 0.4} 626: OpConstantComposite: FloatVector3 const626 = {2, 10, 2} 630: OpConstantComposite: FloatVector3 const630 = {1, 0.8, 0.5} 675: OpConstant: Float const675 = 3.14159 685: OpConstant: Float const685 = 1.5 807: OpConstant: Float const807 = 100 828: OpConstant: Float const828 = 8 857: OpConstantComposite: FloatVector4 const857 = {0.9, 0.8, 0.7, 1} 861: OpConstant: Float const861 = 0.03 867: OpConstant: Float const867 = 0.454545 868: OpConstantComposite: FloatVector4 const868 = {0.454545, 0.454545, 0.454545, 0.454545} 886: OpConstant: UInt const886 = 4 Private Global Variables: 91: OpVariable: Float*: _twist: storage class: Private Disassembled Code: 4: OpFunction: Void main() 870: OpVariable: FloatVector4*: color: storage class: Function 873: OpVariable: FloatVector4*: param873: storage class: Function 874: OpVariable: FloatVector2*: param874: storage class: Function 5: lb5: OpStore: : const92 >> _twist 875: OpLoad: FloatVector4: tmp875 << gl_FragCoord 876: OpVectorShuffle: FloatVector2: tmp876 << tmp875, tmp875, 0, 1 OpStore: : tmp876 >> param874 877: OpFunctionCall: Void: mainImage(vf4;vf2;(param873, param874) 878: OpLoad: FloatVector4: tmp878 << param873 OpStore: : tmp878 >> color 881: OpLoad: FloatVector4: tmp881 << color OpStore: : tmp881 >> finalColor OpReturn: 11: OpFunction: Float hash(vf3;(FloatVector3* uv) 93: OpVariable: Float*: f: storage class: Function 12: lb12: 94: OpLoad: FloatVector3: tmp94 << uv 99: OpDot: Float: tmp99 << tmp94, const98 100: OpExtInst(Sin): Float: tmp100 << tmp99 102: OpFMul: Float: tmp102 << tmp100, const101 103: OpExtInst(Fract): Float: tmp103 << tmp102 OpStore: : tmp103 >> f 104: OpLoad: Float: tmp104 << f OpReturnValue: : << tmp104 14: OpFunction: Float noise(vf3;(FloatVector3* uv) 107: OpVariable: FloatVector3*: fuv: storage class: Function 110: OpVariable: FloatVector4*: cell0: storage class: Function 114: OpVariable: FloatVector3*: param114: storage class: Function 120: OpVariable: FloatVector3*: param120: storage class: Function 125: OpVariable: FloatVector3*: param125: storage class: Function 130: OpVariable: FloatVector3*: param130: storage class: Function 133: OpVariable: FloatVector2*: axis0: storage class: Function 145: OpVariable: Float*: val0: storage class: Function 155: OpVariable: FloatVector4*: cell1: storage class: Function 159: OpVariable: FloatVector3*: param159: storage class: Function 164: OpVariable: FloatVector3*: param164: storage class: Function 169: OpVariable: FloatVector3*: param169: storage class: Function 174: OpVariable: FloatVector3*: param174: storage class: Function 177: OpVariable: FloatVector2*: axis1: storage class: Function 187: OpVariable: Float*: val1: storage class: Function 15: lb15: 108: OpLoad: FloatVector3: tmp108 << uv 109: OpExtInst(Floor): FloatVector3: tmp109 << tmp108 OpStore: : tmp109 >> fuv 111: OpLoad: FloatVector3: tmp111 << fuv 113: OpFAdd: FloatVector3: tmp113 << tmp111, const112 OpStore: : tmp113 >> param114 115: OpFunctionCall: Float: hash(vf3;(param114) 116: OpLoad: FloatVector3: tmp116 << fuv 119: OpFAdd: FloatVector3: tmp119 << tmp116, const118 OpStore: : tmp119 >> param120 121: OpFunctionCall: Float: hash(vf3;(param120) 122: OpLoad: FloatVector3: tmp122 << fuv 124: OpFAdd: FloatVector3: tmp124 << tmp122, const123 OpStore: : tmp124 >> param125 126: OpFunctionCall: Float: hash(vf3;(param125) 127: OpLoad: FloatVector3: tmp127 << fuv 129: OpFAdd: FloatVector3: tmp129 << tmp127, const128 OpStore: : tmp129 >> param130 131: OpFunctionCall: Float: hash(vf3;(param130) 132: OpCompositeConstruct: FloatVector4: tmp132 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; OpStore: : tmp132 >> cell0 134: OpLoad: FloatVector4: tmp134 << cell0 135: OpVectorShuffle: FloatVector2: tmp135 << tmp134, tmp134, 0, 2 136: OpLoad: FloatVector4: tmp136 << cell0 137: OpVectorShuffle: FloatVector2: tmp137 << tmp136, tmp136, 1, 3 140: OpAccessChain: Float*: uv[1] 141: OpLoad: Float: tmp141 << uv[1] 142: OpExtInst(Fract): Float: tmp142 << tmp141 143: OpCompositeConstruct: FloatVector2: tmp143 << tmp142, tmp142 144: OpExtInst(FMix): FloatVector2: tmp144 << tmp135, tmp137, tmp143 OpStore: : tmp144 >> axis0 147: OpAccessChain: Float*: axis0[0] 148: OpLoad: Float: tmp148 << axis0[0] 149: OpAccessChain: Float*: axis0[1] 150: OpLoad: Float: tmp150 << axis0[1] 151: OpAccessChain: Float*: uv[0] 152: OpLoad: Float: tmp152 << uv[0] 153: OpExtInst(Fract): Float: tmp153 << tmp152 154: OpExtInst(FMix): Float: tmp154 << tmp148, tmp150, tmp153 OpStore: : tmp154 >> val0 156: OpLoad: FloatVector3: tmp156 << fuv 158: OpFAdd: FloatVector3: tmp158 << tmp156, const157 OpStore: : tmp158 >> param159 160: OpFunctionCall: Float: hash(vf3;(param159) 161: OpLoad: FloatVector3: tmp161 << fuv 163: OpFAdd: FloatVector3: tmp163 << tmp161, const162 OpStore: : tmp163 >> param164 165: OpFunctionCall: Float: hash(vf3;(param164) 166: OpLoad: FloatVector3: tmp166 << fuv 168: OpFAdd: FloatVector3: tmp168 << tmp166, const167 OpStore: : tmp168 >> param169 170: OpFunctionCall: Float: hash(vf3;(param169) 171: OpLoad: FloatVector3: tmp171 << fuv 173: OpFAdd: FloatVector3: tmp173 << tmp171, const172 OpStore: : tmp173 >> param174 175: OpFunctionCall: Float: hash(vf3;(param174) 176: OpCompositeConstruct: FloatVector4: tmp176 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; OpStore: : tmp176 >> cell1 178: OpLoad: FloatVector4: tmp178 << cell1 179: OpVectorShuffle: FloatVector2: tmp179 << tmp178, tmp178, 0, 2 180: OpLoad: FloatVector4: tmp180 << cell1 181: OpVectorShuffle: FloatVector2: tmp181 << tmp180, tmp180, 1, 3 182: OpAccessChain: Float*: uv[1] 183: OpLoad: Float: tmp183 << uv[1] 184: OpExtInst(Fract): Float: tmp184 << tmp183 185: OpCompositeConstruct: FloatVector2: tmp185 << tmp184, tmp184 186: OpExtInst(FMix): FloatVector2: tmp186 << tmp179, tmp181, tmp185 OpStore: : tmp186 >> axis1 188: OpAccessChain: Float*: axis1[0] 189: OpLoad: Float: tmp189 << axis1[0] 190: OpAccessChain: Float*: axis1[1] 191: OpLoad: Float: tmp191 << axis1[1] 192: OpAccessChain: Float*: uv[0] 193: OpLoad: Float: tmp193 << uv[0] 194: OpExtInst(Fract): Float: tmp194 << tmp193 195: OpExtInst(FMix): Float: tmp195 << tmp189, tmp191, tmp194 OpStore: : tmp195 >> val1 196: OpLoad: Float: tmp196 << val0 197: OpLoad: Float: tmp197 << val1 199: OpAccessChain: Float*: uv[2] 200: OpLoad: Float: tmp200 << uv[2] 201: OpExtInst(Fract): Float: tmp201 << tmp200 202: OpExtInst(FMix): Float: tmp202 << tmp196, tmp197, tmp201 OpReturnValue: : << tmp202 17: OpFunction: Float fbm(vf3;(FloatVector3* uv) 205: OpVariable: Float*: f: storage class: Function 206: OpVariable: Float*: r: storage class: Function 209: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 225: OpVariable: FloatVector3*: param225: storage class: Function 18: lb18: OpStore: : const92 >> f OpStore: : const117 >> r OpStore: : const210 >> i OpBranch: to lb211 211: lb211: OpLoopMerge: (merge: lb213, continue: lb214) OpBranch: to lb215 215: lb215: 216: OpLoad: Int: tmp216 << i Decorators: RelaxedPrecision 218: OpSLessThan: Bool: tmp218 << tmp216, const217 OpBranchConditional: if(tmp218) then branch to lb212, else branch to lb213 212: lb212: 219: OpLoad: FloatVector3: tmp219 << uv 221: OpCompositeConstruct: FloatVector3: tmp221 << const220, const220, const220 222: OpFAdd: FloatVector3: tmp222 << tmp219, tmp221 223: OpLoad: Float: tmp223 << r 224: OpVectorTimesScalar: FloatVector3: tmp224 << tmp222, tmp223 OpStore: : tmp224 >> param225 226: OpFunctionCall: Float: noise(vf3;(param225) 228: OpLoad: Float: tmp228 << r 229: OpFMul: Float: tmp229 << tmp228, const227 OpStore: : tmp229 >> r 230: OpFDiv: Float: tmp230 << noise(vf3;, tmp229 231: OpLoad: Float: tmp231 << f 232: OpFAdd: Float: tmp232 << tmp231, tmp230 OpStore: : tmp232 >> f OpBranch: to lb214 214: lb214: 233: OpLoad: Int: tmp233 << i Decorators: RelaxedPrecision 235: OpIAdd: Int: tmp235 << tmp233, const234 Decorators: RelaxedPrecision OpStore: : tmp235 >> i OpBranch: to lb211 213: lb213: 236: OpLoad: Float: tmp236 << f 237: OpLoad: Float: tmp237 << r 238: OpFDiv: Float: tmp238 << const117, tmp237 239: OpFSub: Float: tmp239 << const117, tmp238 240: OpFDiv: Float: tmp240 << tmp236, tmp239 OpReturnValue: : << tmp240 25: OpFunction: Void tRotate(vf2;f1;(FloatVector2* p, Float* angel) 243: OpVariable: Float*: s: storage class: Function 246: OpVariable: Float*: c: storage class: Function 26: lb26: 244: OpLoad: Float: tmp244 << angel 245: OpExtInst(Sin): Float: tmp245 << tmp244 OpStore: : tmp245 >> s 247: OpLoad: Float: tmp247 << angel 248: OpExtInst(Cos): Float: tmp248 << tmp247 OpStore: : tmp248 >> c 249: OpLoad: Float: tmp249 << c 250: OpLoad: Float: tmp250 << s 251: OpFNegate: Float: tmp251 << tmp250 252: OpLoad: Float: tmp252 << s 253: OpLoad: Float: tmp253 << c 255: OpCompositeConstruct: FloatVector2: tmp255 << tmp249, tmp251 256: OpCompositeConstruct: FloatVector2: tmp256 << tmp252, tmp253 257: OpCompositeConstruct: FloatMatrix2x2: tmp257 << tmp255, tmp256 258: OpLoad: FloatVector2: tmp258 << p 259: OpVectorTimesMatrix: FloatVector2: tmp259 << tmp258, tmp257 OpStore: : tmp259 >> p OpReturn: 30: OpFunction: Void tTwist(vf3;f1;(FloatVector3* p, Float* a) 264: OpVariable: FloatVector2*: param264: storage class: Function 267: OpVariable: Float*: param267: storage class: Function 31: lb31: 260: OpAccessChain: Float*: p[2] 261: OpLoad: Float: tmp261 << p[2] 262: OpLoad: Float: tmp262 << a 263: OpFMul: Float: tmp263 << tmp261, tmp262 265: OpLoad: FloatVector3: tmp265 << p 266: OpVectorShuffle: FloatVector2: tmp266 << tmp265, tmp265, 0, 1 OpStore: : tmp266 >> param264 OpStore: : tmp263 >> param267 268: OpFunctionCall: Void: tRotate(vf2;f1;(param264, param267) 269: OpLoad: FloatVector2: tmp269 << param264 270: OpLoad: FloatVector3: tmp270 << p 271: OpVectorShuffle: FloatVector3: tmp271 << tmp270, tmp269, 3, 4, 2 OpStore: : tmp271 >> p OpReturn: 35: OpFunction: FloatVector2 tRepeat2(vf2;vf2;(FloatVector2* p, FloatVector2* r) 272: OpVariable: FloatVector2*: id: storage class: Function 36: lb36: 273: OpLoad: FloatVector2: tmp273 << p 274: OpLoad: FloatVector2: tmp274 << r 276: OpVectorTimesScalar: FloatVector2: tmp276 << tmp274, const275 277: OpFAdd: FloatVector2: tmp277 << tmp273, tmp276 278: OpLoad: FloatVector2: tmp278 << r 279: OpFDiv: FloatVector2: tmp279 << tmp277, tmp278 280: OpExtInst(Floor): FloatVector2: tmp280 << tmp279 OpStore: : tmp280 >> id 281: OpLoad: FloatVector2: tmp281 << p 282: OpLoad: FloatVector2: tmp282 << r 283: OpVectorTimesScalar: FloatVector2: tmp283 << tmp282, const275 284: OpFAdd: FloatVector2: tmp284 << tmp281, tmp283 285: OpLoad: FloatVector2: tmp285 << r 286: OpFMod: FloatVector2: tmp286 << tmp284, tmp285 287: OpLoad: FloatVector2: tmp287 << r 288: OpVectorTimesScalar: FloatVector2: tmp288 << tmp287, const275 289: OpFSub: FloatVector2: tmp289 << tmp286, tmp288 OpStore: : tmp289 >> p 290: OpLoad: FloatVector2: tmp290 << id OpReturnValue: : << tmp290 40: OpFunction: Float sdRect(vf2;vf2;(FloatVector2* p, FloatVector2* r) 41: lb41: 293: OpLoad: FloatVector2: tmp293 << p 294: OpExtInst(FAbs): FloatVector2: tmp294 << tmp293 295: OpLoad: FloatVector2: tmp295 << r 296: OpFSub: FloatVector2: tmp296 << tmp294, tmp295 OpStore: : tmp296 >> p 297: OpAccessChain: Float*: p[0] 298: OpLoad: Float: tmp298 << p[0] 299: OpAccessChain: Float*: p[1] 300: OpLoad: Float: tmp300 << p[1] 301: OpExtInst(FMax): Float: tmp301 << tmp298, tmp300 302: OpExtInst(FMin): Float: tmp302 << tmp301, const92 303: OpLoad: FloatVector2: tmp303 << p 304: OpCompositeConstruct: FloatVector2: tmp304 << const92, const92 305: OpExtInst(FMax): FloatVector2: tmp305 << tmp303, tmp304 306: OpExtInst(Length): Float: tmp306 << tmp305 307: OpFAdd: Float: tmp307 << tmp302, tmp306 OpReturnValue: : << tmp307 45: OpFunction: Float sdCircle(vf2;f1;(FloatVector2* p, Float* r) 46: lb46: 310: OpLoad: FloatVector2: tmp310 << p 311: OpExtInst(Length): Float: tmp311 << tmp310 312: OpLoad: Float: tmp312 << r 313: OpFSub: Float: tmp313 << tmp311, tmp312 OpReturnValue: : << tmp313 50: OpFunction: Float opU(f1;f1;(Float* a, Float* b) 51: lb51: 316: OpLoad: Float: tmp316 << a 317: OpLoad: Float: tmp317 << b 318: OpExtInst(FMin): Float: tmp318 << tmp316, tmp317 OpReturnValue: : << tmp318 54: OpFunction: Float opS(f1;f1;(Float* a, Float* b) 55: lb55: 321: OpLoad: Float: tmp321 << a 322: OpLoad: Float: tmp322 << b 323: OpFNegate: Float: tmp323 << tmp322 324: OpExtInst(FMax): Float: tmp324 << tmp321, tmp323 OpReturnValue: : << tmp324 57: OpFunction: Float map(vf3;(FloatVector3* p) 327: OpVariable: FloatVector3*: param327: storage class: Function 329: OpVariable: Float*: param329: storage class: Function 335: OpVariable: FloatVector2*: param335: storage class: Function 338: OpVariable: FloatVector2*: param338: storage class: Function 351: OpVariable: Float*: d: storage class: Function 357: OpVariable: Float*: w: storage class: Function 364: OpVariable: FloatVector2*: param364: storage class: Function 365: OpVariable: Float*: param365: storage class: Function 373: OpVariable: FloatVector2*: param373: storage class: Function 374: OpVariable: FloatVector2*: param374: storage class: Function 376: OpVariable: Float*: param376: storage class: Function 377: OpVariable: Float*: param377: storage class: Function 379: OpVariable: Float*: param379: storage class: Function 381: OpVariable: Float*: param381: storage class: Function 392: OpVariable: FloatVector2*: param392: storage class: Function 393: OpVariable: FloatVector2*: param393: storage class: Function 395: OpVariable: Float*: param395: storage class: Function 397: OpVariable: Float*: param397: storage class: Function 404: OpVariable: FloatVector2*: param404: storage class: Function 405: OpVariable: Float*: param405: storage class: Function 407: OpVariable: Float*: param407: storage class: Function 409: OpVariable: Float*: param409: storage class: Function 422: OpVariable: FloatVector2*: param422: storage class: Function 423: OpVariable: FloatVector2*: param423: storage class: Function 425: OpVariable: Float*: param425: storage class: Function 427: OpVariable: Float*: param427: storage class: Function 436: OpVariable: Float*: param436: storage class: Function 438: OpVariable: Float*: param438: storage class: Function 58: lb58: 328: OpLoad: FloatVector3: tmp328 << p OpStore: : tmp328 >> param327 330: OpLoad: Float: tmp330 << _twist OpStore: : tmp330 >> param329 331: OpFunctionCall: Void: tTwist(vf3;f1;(param327, param329) 332: OpLoad: FloatVector3: tmp332 << param327 OpStore: : tmp332 >> p 336: OpLoad: FloatVector3: tmp336 << p 337: OpVectorShuffle: FloatVector2: tmp337 << tmp336, tmp336, 0, 2 OpStore: : tmp337 >> param335 OpStore: : const334 >> param338 339: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param335, param338) 340: OpLoad: FloatVector2: tmp340 << param335 341: OpLoad: FloatVector3: tmp341 << p 342: OpVectorShuffle: FloatVector3: tmp342 << tmp341, tmp340, 3, 1, 4 OpStore: : tmp342 >> p 343: OpAccessChain: Float*: p[0] 344: OpLoad: Float: tmp344 << p[0] 345: OpExtInst(FAbs): Float: tmp345 << tmp344 346: OpAccessChain: Float*: p[0] OpStore: : tmp345 >> p[0] 347: OpAccessChain: Float*: p[1] 348: OpLoad: Float: tmp348 << p[1] 349: OpFAdd: Float: tmp349 << tmp348, const275 350: OpAccessChain: Float*: p[1] OpStore: : tmp349 >> p[1] 352: OpAccessChain: Float*: p[2] 353: OpLoad: Float: tmp353 << p[2] 354: OpExtInst(FAbs): Float: tmp354 << tmp353 356: OpFSub: Float: tmp356 << tmp354, const355 OpStore: : tmp356 >> d 358: OpLoad: FloatVector3: tmp358 << p 359: OpVectorShuffle: FloatVector2: tmp359 << tmp358, tmp358, 0, 1 362: OpFSub: FloatVector2: tmp362 << tmp359, const361 OpStore: : tmp362 >> param364 OpStore: : const363 >> param365 366: OpFunctionCall: Float: sdCircle(vf2;f1;(param364, param365) 367: OpLoad: FloatVector3: tmp367 << p 368: OpVectorShuffle: FloatVector2: tmp368 << tmp367, tmp367, 0, 1 371: OpFSub: FloatVector2: tmp371 << tmp368, const370 OpStore: : tmp371 >> param373 OpStore: : const372 >> param374 375: OpFunctionCall: Float: sdRect(vf2;vf2;(param373, param374) OpStore: : sdCircle(vf2;f1; >> param376 OpStore: : sdRect(vf2;vf2; >> param377 378: OpFunctionCall: Float: opU(f1;f1;(param376, param377) OpStore: : opU(f1;f1; >> w 380: OpLoad: Float: tmp380 << d OpStore: : tmp380 >> param379 382: OpLoad: Float: tmp382 << w OpStore: : tmp382 >> param381 383: OpFunctionCall: Float: opS(f1;f1;(param379, param381) OpStore: : opS(f1;f1; >> d 384: OpLoad: FloatVector3: tmp384 << p 385: OpVectorShuffle: FloatVector2: tmp385 << tmp384, tmp384, 0, 1 388: OpFSub: FloatVector2: tmp388 << tmp385, const387 OpStore: : tmp388 >> param392 OpStore: : const391 >> param393 394: OpFunctionCall: Float: sdRect(vf2;vf2;(param392, param393) 396: OpLoad: Float: tmp396 << d OpStore: : tmp396 >> param395 OpStore: : sdRect(vf2;vf2; >> param397 398: OpFunctionCall: Float: opS(f1;f1;(param395, param397) OpStore: : opS(f1;f1; >> d 399: OpLoad: FloatVector3: tmp399 << p 400: OpVectorShuffle: FloatVector2: tmp400 << tmp399, tmp399, 0, 2 402: OpFSub: FloatVector2: tmp402 << tmp400, const401 OpStore: : tmp402 >> param404 OpStore: : const403 >> param405 406: OpFunctionCall: Float: sdCircle(vf2;f1;(param404, param405) 408: OpLoad: Float: tmp408 << d OpStore: : tmp408 >> param407 OpStore: : sdCircle(vf2;f1; >> param409 410: OpFunctionCall: Float: opU(f1;f1;(param407, param409) OpStore: : opU(f1;f1; >> d 411: OpAccessChain: Float*: p[2] 412: OpLoad: Float: tmp412 << p[2] 413: OpExtInst(FAbs): Float: tmp413 << tmp412 414: OpAccessChain: Float*: p[2] OpStore: : tmp413 >> p[2] 415: OpLoad: FloatVector3: tmp415 << p 416: OpVectorShuffle: FloatVector2: tmp416 << tmp415, tmp415, 1, 2 419: OpFSub: FloatVector2: tmp419 << tmp416, const418 OpStore: : tmp419 >> param422 OpStore: : const421 >> param423 424: OpFunctionCall: Float: sdRect(vf2;vf2;(param422, param423) 426: OpLoad: Float: tmp426 << d OpStore: : tmp426 >> param425 OpStore: : sdRect(vf2;vf2; >> param427 428: OpFunctionCall: Float: opS(f1;f1;(param425, param427) OpStore: : opS(f1;f1; >> d 429: OpAccessChain: Float*: p[1] 430: OpLoad: Float: tmp430 << p[1] 431: OpFSub: Float: tmp431 << tmp430, const275 432: OpExtInst(FAbs): Float: tmp432 << tmp431 433: OpFNegate: Float: tmp433 << tmp432 435: OpFAdd: Float: tmp435 << tmp433, const434 437: OpLoad: Float: tmp437 << d OpStore: : tmp437 >> param436 OpStore: : tmp435 >> param438 439: OpFunctionCall: Float: opU(f1;f1;(param436, param438) OpStore: : opU(f1;f1; >> d 440: OpLoad: Float: tmp440 << d OpReturnValue: : << tmp440 64: OpFunction: Float trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* maxDist, Float* steps) 443: OpVariable: Float*: total: storage class: Function 444: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 455: OpVariable: Float*: d: storage class: Function 461: OpVariable: FloatVector3*: param461: storage class: Function 65: lb65: OpStore: : const92 >> total OpStore: : const92 >> steps OpStore: : const210 >> i OpBranch: to lb445 445: lb445: OpLoopMerge: (merge: lb447, continue: lb448) OpBranch: to lb449 449: lb449: 450: OpLoad: Int: tmp450 << i Decorators: RelaxedPrecision 452: OpSLessThan: Bool: tmp452 << tmp450, const451 OpBranchConditional: if(tmp452) then branch to lb446, else branch to lb447 446: lb446: 453: OpLoad: Float: tmp453 << steps 454: OpFAdd: Float: tmp454 << tmp453, const117 OpStore: : tmp454 >> steps 456: OpLoad: FloatVector3: tmp456 << ro 457: OpLoad: FloatVector3: tmp457 << rd 458: OpLoad: Float: tmp458 << total 459: OpVectorTimesScalar: FloatVector3: tmp459 << tmp457, tmp458 460: OpFAdd: FloatVector3: tmp460 << tmp456, tmp459 OpStore: : tmp460 >> param461 462: OpFunctionCall: Float: map(vf3;(param461) OpStore: : map(vf3; >> d 463: OpLoad: Float: tmp463 << d 464: OpLoad: Float: tmp464 << total 465: OpFAdd: Float: tmp465 << tmp464, tmp463 OpStore: : tmp465 >> total 466: OpLoad: Float: tmp466 << d 468: OpFOrdLessThan: Bool: tmp468 << tmp466, const467 469: OpLoad: Float: tmp469 << maxDist 470: OpLoad: Float: tmp470 << total 471: OpFOrdLessThan: Bool: tmp471 << tmp469, tmp470 472: OpLogicalOr: Bool: tmp472 << tmp468, tmp471 OpSelectionMerge: (merge: lb474) OpBranchConditional: if(tmp472) then branch to lb473, else branch to lb474 473: lb473: OpBranch: to lb447 474: lb474: OpBranch: to lb448 448: lb448: 476: OpLoad: Int: tmp476 << i Decorators: RelaxedPrecision 477: OpIAdd: Int: tmp477 << tmp476, const234 Decorators: RelaxedPrecision OpStore: : tmp477 >> i OpBranch: to lb445 447: lb447: 478: OpLoad: Float: tmp478 << total OpReturnValue: : << tmp478 68: OpFunction: FloatVector3 getNormal(vf3;(FloatVector3* p) 481: OpVariable: FloatVector2*: e: storage class: Function 488: OpVariable: FloatVector3*: param488: storage class: Function 494: OpVariable: FloatVector3*: param494: storage class: Function 501: OpVariable: FloatVector3*: param501: storage class: Function 507: OpVariable: FloatVector3*: param507: storage class: Function 514: OpVariable: FloatVector3*: param514: storage class: Function 520: OpVariable: FloatVector3*: param520: storage class: Function 69: lb69: OpStore: : const483 >> e 484: OpLoad: FloatVector3: tmp484 << p 485: OpLoad: FloatVector2: tmp485 << e 486: OpVectorShuffle: FloatVector3: tmp486 << tmp485, tmp485, 0, 1, 1 487: OpFAdd: FloatVector3: tmp487 << tmp484, tmp486 OpStore: : tmp487 >> param488 489: OpFunctionCall: Float: map(vf3;(param488) 490: OpLoad: FloatVector3: tmp490 << p 491: OpLoad: FloatVector2: tmp491 << e 492: OpVectorShuffle: FloatVector3: tmp492 << tmp491, tmp491, 0, 1, 1 493: OpFSub: FloatVector3: tmp493 << tmp490, tmp492 OpStore: : tmp493 >> param494 495: OpFunctionCall: Float: map(vf3;(param494) 496: OpFSub: Float: tmp496 << map(vf3;, map(vf3; 497: OpLoad: FloatVector3: tmp497 << p 498: OpLoad: FloatVector2: tmp498 << e 499: OpVectorShuffle: FloatVector3: tmp499 << tmp498, tmp498, 1, 0, 1 500: OpFAdd: FloatVector3: tmp500 << tmp497, tmp499 OpStore: : tmp500 >> param501 502: OpFunctionCall: Float: map(vf3;(param501) 503: OpLoad: FloatVector3: tmp503 << p 504: OpLoad: FloatVector2: tmp504 << e 505: OpVectorShuffle: FloatVector3: tmp505 << tmp504, tmp504, 1, 0, 1 506: OpFSub: FloatVector3: tmp506 << tmp503, tmp505 OpStore: : tmp506 >> param507 508: OpFunctionCall: Float: map(vf3;(param507) 509: OpFSub: Float: tmp509 << map(vf3;, map(vf3; 510: OpLoad: FloatVector3: tmp510 << p 511: OpLoad: FloatVector2: tmp511 << e 512: OpVectorShuffle: FloatVector3: tmp512 << tmp511, tmp511, 1, 1, 0 513: OpFAdd: FloatVector3: tmp513 << tmp510, tmp512 OpStore: : tmp513 >> param514 515: OpFunctionCall: Float: map(vf3;(param514) 516: OpLoad: FloatVector3: tmp516 << p 517: OpLoad: FloatVector2: tmp517 << e 518: OpVectorShuffle: FloatVector3: tmp518 << tmp517, tmp517, 1, 1, 0 519: OpFSub: FloatVector3: tmp519 << tmp516, tmp518 OpStore: : tmp519 >> param520 521: OpFunctionCall: Float: map(vf3;(param520) 522: OpFSub: Float: tmp522 << map(vf3;, map(vf3; 523: OpCompositeConstruct: FloatVector3: tmp523 << tmp496, tmp509, tmp522 524: OpExtInst(Normalize): FloatVector3: tmp524 << tmp523 OpReturnValue: : << tmp524 73: OpFunction: Float calculateAO(vf3;vf3;(FloatVector3* p, FloatVector3* n) 527: OpVariable: Float*: r: storage class: Function 528: OpVariable: Float*: w: storage class: Function 529: OpVariable: Float*: i: storage class: Function 538: OpVariable: Float*: d: storage class: Function 549: OpVariable: FloatVector3*: param549: storage class: Function 74: lb74: OpStore: : const92 >> r OpStore: : const117 >> w OpStore: : const117 >> i OpBranch: to lb530 530: lb530: OpLoopMerge: (merge: lb532, continue: lb533) OpBranch: to lb534 534: lb534: 535: OpLoad: Float: tmp535 << i 537: OpFOrdLessThanEqual: Bool: tmp537 << tmp535, const536 OpBranchConditional: if(tmp537) then branch to lb531, else branch to lb532 531: lb531: 539: OpLoad: Float: tmp539 << i 540: OpFDiv: Float: tmp540 << tmp539, const536 541: OpFDiv: Float: tmp541 << tmp540, const220 OpStore: : tmp541 >> d 542: OpLoad: Float: tmp542 << w 543: OpLoad: Float: tmp543 << d 544: OpLoad: FloatVector3: tmp544 << p 545: OpLoad: FloatVector3: tmp545 << n 546: OpLoad: Float: tmp546 << d 547: OpVectorTimesScalar: FloatVector3: tmp547 << tmp545, tmp546 548: OpFAdd: FloatVector3: tmp548 << tmp544, tmp547 OpStore: : tmp548 >> param549 550: OpFunctionCall: Float: map(vf3;(param549) 551: OpFSub: Float: tmp551 << tmp543, map(vf3; 552: OpFMul: Float: tmp552 << tmp542, tmp551 553: OpLoad: Float: tmp553 << r 554: OpFAdd: Float: tmp554 << tmp553, tmp552 OpStore: : tmp554 >> r 555: OpLoad: Float: tmp555 << w 556: OpFMul: Float: tmp556 << tmp555, const275 OpStore: : tmp556 >> w OpBranch: to lb533 533: lb533: 557: OpLoad: Float: tmp557 << i 558: OpFAdd: Float: tmp558 << tmp557, const117 OpStore: : tmp558 >> i OpBranch: to lb530 532: lb532: 559: OpLoad: Float: tmp559 << r 560: OpFMul: Float: tmp560 << tmp559, const220 561: OpExtInst(FClamp): Float: tmp561 << tmp560, const92, const117 562: OpFSub: Float: tmp562 << const117, tmp561 OpReturnValue: : << tmp562 78: OpFunction: Bool isWall(vf3;(FloatVector3* p) 569: OpVariable: FloatVector2*: param569: storage class: Function 572: OpVariable: FloatVector2*: param572: storage class: Function 79: lb79: 565: OpAccessChain: Float*: p[0] 566: OpLoad: Float: tmp566 << p[0] 567: OpFAdd: Float: tmp567 << tmp566, const386 568: OpAccessChain: Float*: p[0] OpStore: : tmp567 >> p[0] 570: OpLoad: FloatVector3: tmp570 << p 571: OpVectorShuffle: FloatVector2: tmp571 << tmp570, tmp570, 0, 2 OpStore: : tmp571 >> param569 OpStore: : const334 >> param572 573: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param569, param572) 574: OpLoad: FloatVector2: tmp574 << param569 575: OpLoad: FloatVector3: tmp575 << p 576: OpVectorShuffle: FloatVector3: tmp576 << tmp575, tmp574, 3, 1, 4 OpStore: : tmp576 >> p 577: OpAccessChain: Float*: p[1] 578: OpLoad: Float: tmp578 << p[1] 579: OpFAdd: Float: tmp579 << tmp578, const355 580: OpExtInst(FAbs): Float: tmp580 << tmp579 581: OpLoad: FloatVector3: tmp581 << p 582: OpVectorShuffle: FloatVector2: tmp582 << tmp581, tmp581, 0, 2 583: OpExtInst(Length): Float: tmp583 << tmp582 584: OpFAdd: Float: tmp584 << tmp580, tmp583 585: OpFOrdLessThan: Bool: tmp585 << const369, tmp584 OpReturnValue: : << tmp585 81: OpFunction: FloatVector3 _texture(vf3;(FloatVector3* p) 588: OpVariable: FloatVector3*: param588: storage class: Function 590: OpVariable: Float*: param590: storage class: Function 595: OpVariable: Bool*: wall: storage class: Function 596: OpVariable: FloatVector3*: param596: storage class: Function 599: OpVariable: FloatVector3*: t: storage class: Function 601: OpVariable: Float*: var601: storage class: Function 610: OpVariable: FloatVector3*: param610: storage class: Function 620: OpVariable: FloatVector3*: param620: storage class: Function 628: OpVariable: FloatVector3*: param628: storage class: Function 82: lb82: 589: OpLoad: FloatVector3: tmp589 << p OpStore: : tmp589 >> param588 591: OpLoad: Float: tmp591 << _twist OpStore: : tmp591 >> param590 592: OpFunctionCall: Void: tTwist(vf3;f1;(param588, param590) 593: OpLoad: FloatVector3: tmp593 << param588 OpStore: : tmp593 >> p 597: OpLoad: FloatVector3: tmp597 << p OpStore: : tmp597 >> param596 598: OpFunctionCall: Bool: isWall(vf3;(param596) OpStore: : isWall(vf3; >> wall 600: OpLoad: FloatVector3: tmp600 << p 602: OpLoad: Bool: tmp602 << wall OpSelectionMerge: (merge: lb604) OpBranchConditional: if(tmp602) then branch to lb603, else branch to lb605 603: lb603: OpStore: : const92 >> var601 OpBranch: to lb604 605: lb605: 608: OpLoad: FloatVector3: tmp608 << p 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp608, const536 OpStore: : tmp609 >> param610 611: OpFunctionCall: Float: fbm(vf3;(param610) 612: OpFMul: Float: tmp612 << const607, fbm(vf3; 613: OpFAdd: Float: tmp613 << const606, tmp612 OpStore: : tmp613 >> var601 OpBranch: to lb604 604: lb604: 614: OpLoad: Float: tmp614 << var601 615: OpCompositeConstruct: FloatVector3: tmp615 << tmp614, tmp614, tmp614 616: OpFAdd: FloatVector3: tmp616 << tmp600, tmp615 619: OpFMul: FloatVector3: tmp619 << tmp616, const618 OpStore: : tmp619 >> param620 621: OpFunctionCall: Float: fbm(vf3;(param620) 623: OpVectorTimesScalar: FloatVector3: tmp623 << const622, fbm(vf3; 624: OpVectorTimesScalar: FloatVector3: tmp624 << tmp623, const360 625: OpLoad: FloatVector3: tmp625 << p 627: OpFMul: FloatVector3: tmp627 << tmp625, const626 OpStore: : tmp627 >> param628 629: OpFunctionCall: Float: fbm(vf3;(param628) 631: OpVectorTimesScalar: FloatVector3: tmp631 << const630, fbm(vf3; 632: OpVectorTimesScalar: FloatVector3: tmp632 << tmp631, const363 633: OpFAdd: FloatVector3: tmp633 << tmp624, tmp632 OpStore: : tmp633 >> t 634: OpLoad: Bool: tmp634 << wall OpSelectionMerge: (merge: lb636) OpBranchConditional: if(tmp634) then branch to lb635, else branch to lb636 635: lb635: 637: OpLoad: FloatVector3: tmp637 << t 638: OpCompositeConstruct: FloatVector3: tmp638 << const275, const275, const275 639: OpExtInst(FMix): FloatVector3: tmp639 << tmp637, const172, tmp638 OpStore: : tmp639 >> t OpBranch: to lb636 636: lb636: 640: OpLoad: FloatVector3: tmp640 << t 641: OpCompositeConstruct: FloatVector3: tmp641 << const92, const92, const92 642: OpCompositeConstruct: FloatVector3: tmp642 << const117, const117, const117 643: OpExtInst(FClamp): FloatVector3: tmp643 << tmp640, tmp641, tmp642 OpReturnValue: : << tmp643 88: OpFunction: Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) 646: OpVariable: FloatVector2*: uv: storage class: Function 666: OpVariable: Float*: time: storage class: Function 673: OpVariable: FloatVector3*: ro: storage class: Function 683: OpVariable: FloatVector3*: rd: storage class: Function 692: OpVariable: FloatVector3*: light: storage class: Function 710: OpVariable: FloatVector2*: param710: storage class: Function 713: OpVariable: Float*: param713: storage class: Function 723: OpVariable: FloatVector2*: param723: storage class: Function 726: OpVariable: Float*: param726: storage class: Function 736: OpVariable: FloatVector2*: param736: storage class: Function 739: OpVariable: Float*: param739: storage class: Function 749: OpVariable: FloatVector2*: param749: storage class: Function 752: OpVariable: Float*: param752: storage class: Function 757: OpVariable: Float*: dist: storage class: Function 758: OpVariable: Float*: steps: storage class: Function 759: OpVariable: FloatVector3*: param759: storage class: Function 761: OpVariable: FloatVector3*: param761: storage class: Function 763: OpVariable: Float*: param763: storage class: Function 764: OpVariable: Float*: param764: storage class: Function 767: OpVariable: FloatVector3*: p: storage class: Function 773: OpVariable: FloatVector3*: normal: storage class: Function 774: OpVariable: FloatVector3*: param774: storage class: Function 777: OpVariable: FloatVector3*: l: storage class: Function 782: OpVariable: FloatVector3*: shadowStart: storage class: Function 788: OpVariable: Float*: shadowDistance: storage class: Function 792: OpVariable: Float*: shadow: storage class: Function 793: OpVariable: Float*: shadowSteps: storage class: Function 794: OpVariable: FloatVector3*: param794: storage class: Function 796: OpVariable: FloatVector3*: param796: storage class: Function 798: OpVariable: Float*: param798: storage class: Function 800: OpVariable: Float*: param800: storage class: Function 813: OpVariable: Float*: ambient: storage class: Function 814: OpVariable: Float*: diffuse: storage class: Function 819: OpVariable: Float*: specular: storage class: Function 830: OpVariable: Float*: ao: storage class: Function 831: OpVariable: FloatVector3*: param831: storage class: Function 833: OpVariable: FloatVector3*: param833: storage class: Function 837: OpVariable: FloatVector3*: param837: storage class: Function 89: lb89: 647: OpLoad: FloatVector2: tmp647 << fragCoord 650: OpLoad: FloatVector3: tmp650 << iResolution 651: OpVectorShuffle: FloatVector2: tmp651 << tmp650, tmp650, 0, 1 652: OpFDiv: FloatVector2: tmp652 << tmp647, tmp651 653: OpVectorTimesScalar: FloatVector2: tmp653 << tmp652, const227 654: OpCompositeConstruct: FloatVector2: tmp654 << const117, const117 655: OpFSub: FloatVector2: tmp655 << tmp653, tmp654 OpStore: : tmp655 >> uv 657: OpAccessChain: Float*: iResolution[0] 658: OpLoad: Float: tmp658 << iResolution[0] 659: OpAccessChain: Float*: iResolution[1] 660: OpLoad: Float: tmp660 << iResolution[1] 661: OpFDiv: Float: tmp661 << tmp658, tmp660 662: OpAccessChain: Float*: uv[0] 663: OpLoad: Float: tmp663 << uv[0] 664: OpFMul: Float: tmp664 << tmp663, tmp661 665: OpAccessChain: Float*: uv[0] OpStore: : tmp664 >> uv[0] 668: OpLoad: Float: tmp668 << iTime 669: OpFMul: Float: tmp669 << tmp668, const275 OpStore: : tmp669 >> time 670: OpLoad: Float: tmp670 << time 671: OpExtInst(Sin): Float: tmp671 << tmp670 672: OpFMul: Float: tmp672 << tmp671, const420 OpStore: : tmp672 >> _twist 674: OpLoad: Float: tmp674 << time 676: OpFMul: Float: tmp676 << tmp674, const675 677: OpFDiv: Float: tmp677 << tmp676, const227 678: OpFAdd: Float: tmp678 << tmp677, const117 679: OpExtInst(Sin): Float: tmp679 << tmp678 680: OpFMul: Float: tmp680 << tmp679, const117 681: OpLoad: Float: tmp681 << time 682: OpCompositeConstruct: FloatVector3: tmp682 << tmp680, const92, tmp681 OpStore: : tmp682 >> ro 684: OpLoad: FloatVector2: tmp684 << uv 686: OpCompositeExtract: Float: tmp686 << tmp684, 0 687: OpCompositeExtract: Float: tmp687 << tmp684, 1 688: OpCompositeConstruct: FloatVector3: tmp688 << tmp686, tmp687, const685 689: OpExtInst(Normalize): FloatVector3: tmp689 << tmp688 OpStore: : tmp689 >> rd 690: OpLoad: Float: tmp690 << time 691: OpFAdd: Float: tmp691 << tmp690, const227 OpStore: : tmp691 >> time 693: OpLoad: Float: tmp693 << time 694: OpFMul: Float: tmp694 << tmp693, const675 695: OpFDiv: Float: tmp695 << tmp694, const227 696: OpFAdd: Float: tmp696 << tmp695, const117 697: OpExtInst(Sin): Float: tmp697 << tmp696 698: OpFMul: Float: tmp698 << tmp697, const117 699: OpLoad: Float: tmp699 << time 700: OpCompositeConstruct: FloatVector3: tmp700 << tmp698, const92, tmp699 OpStore: : tmp700 >> light 701: OpLoad: Float: tmp701 << time 702: OpFSub: Float: tmp702 << tmp701, const227 OpStore: : tmp702 >> time 703: OpLoad: Float: tmp703 << time 704: OpFMul: Float: tmp704 << tmp703, const675 705: OpFDiv: Float: tmp705 << tmp704, const227 706: OpFAdd: Float: tmp706 << tmp705, const117 707: OpExtInst(Cos): Float: tmp707 << tmp706 708: OpFNegate: Float: tmp708 << tmp707 709: OpFMul: Float: tmp709 << tmp708, const275 711: OpLoad: FloatVector3: tmp711 << rd 712: OpVectorShuffle: FloatVector2: tmp712 << tmp711, tmp711, 0, 2 OpStore: : tmp712 >> param710 OpStore: : tmp709 >> param713 714: OpFunctionCall: Void: tRotate(vf2;f1;(param710, param713) 715: OpLoad: FloatVector2: tmp715 << param710 716: OpLoad: FloatVector3: tmp716 << rd 717: OpVectorShuffle: FloatVector3: tmp717 << tmp716, tmp715, 3, 1, 4 OpStore: : tmp717 >> rd 718: OpAccessChain: Float*: ro[2] 719: OpLoad: Float: tmp719 << ro[2] 720: OpFNegate: Float: tmp720 << tmp719 721: OpLoad: Float: tmp721 << _twist 722: OpFMul: Float: tmp722 << tmp720, tmp721 724: OpLoad: FloatVector3: tmp724 << ro 725: OpVectorShuffle: FloatVector2: tmp725 << tmp724, tmp724, 0, 1 OpStore: : tmp725 >> param723 OpStore: : tmp722 >> param726 727: OpFunctionCall: Void: tRotate(vf2;f1;(param723, param726) 728: OpLoad: FloatVector2: tmp728 << param723 729: OpLoad: FloatVector3: tmp729 << ro 730: OpVectorShuffle: FloatVector3: tmp730 << tmp729, tmp728, 3, 4, 2 OpStore: : tmp730 >> ro 731: OpAccessChain: Float*: light[2] 732: OpLoad: Float: tmp732 << light[2] 733: OpFNegate: Float: tmp733 << tmp732 734: OpLoad: Float: tmp734 << _twist 735: OpFMul: Float: tmp735 << tmp733, tmp734 737: OpLoad: FloatVector3: tmp737 << light 738: OpVectorShuffle: FloatVector2: tmp738 << tmp737, tmp737, 0, 1 OpStore: : tmp738 >> param736 OpStore: : tmp735 >> param739 740: OpFunctionCall: Void: tRotate(vf2;f1;(param736, param739) 741: OpLoad: FloatVector2: tmp741 << param736 742: OpLoad: FloatVector3: tmp742 << light 743: OpVectorShuffle: FloatVector3: tmp743 << tmp742, tmp741, 3, 4, 2 OpStore: : tmp743 >> light 744: OpAccessChain: Float*: ro[2] 745: OpLoad: Float: tmp745 << ro[2] 746: OpFNegate: Float: tmp746 << tmp745 747: OpLoad: Float: tmp747 << _twist 748: OpFMul: Float: tmp748 << tmp746, tmp747 750: OpLoad: FloatVector3: tmp750 << rd 751: OpVectorShuffle: FloatVector2: tmp751 << tmp750, tmp750, 0, 1 OpStore: : tmp751 >> param749 OpStore: : tmp748 >> param752 753: OpFunctionCall: Void: tRotate(vf2;f1;(param749, param752) 754: OpLoad: FloatVector2: tmp754 << param749 755: OpLoad: FloatVector3: tmp755 << rd 756: OpVectorShuffle: FloatVector3: tmp756 << tmp755, tmp754, 3, 4, 2 OpStore: : tmp756 >> rd 760: OpLoad: FloatVector3: tmp760 << ro OpStore: : tmp760 >> param759 762: OpLoad: FloatVector3: tmp762 << rd OpStore: : tmp762 >> param761 OpStore: : const220 >> param763 765: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param759, param761, param763, param764) 766: OpLoad: Float: tmp766 << param764 OpStore: : tmp766 >> steps OpStore: : trace(vf3;vf3;f1;f1; >> dist 768: OpLoad: FloatVector3: tmp768 << ro 769: OpLoad: FloatVector3: tmp769 << rd 770: OpLoad: Float: tmp770 << dist 771: OpVectorTimesScalar: FloatVector3: tmp771 << tmp769, tmp770 772: OpFAdd: FloatVector3: tmp772 << tmp768, tmp771 OpStore: : tmp772 >> p 775: OpLoad: FloatVector3: tmp775 << p OpStore: : tmp775 >> param774 776: OpFunctionCall: FloatVector3: getNormal(vf3;(param774) OpStore: : getNormal(vf3; >> normal 778: OpLoad: FloatVector3: tmp778 << light 779: OpLoad: FloatVector3: tmp779 << p 780: OpFSub: FloatVector3: tmp780 << tmp778, tmp779 781: OpExtInst(Normalize): FloatVector3: tmp781 << tmp780 OpStore: : tmp781 >> l 783: OpLoad: FloatVector3: tmp783 << p 784: OpLoad: FloatVector3: tmp784 << normal 785: OpVectorTimesScalar: FloatVector3: tmp785 << tmp784, const467 786: OpVectorTimesScalar: FloatVector3: tmp786 << tmp785, const220 787: OpFAdd: FloatVector3: tmp787 << tmp783, tmp786 OpStore: : tmp787 >> shadowStart 789: OpLoad: FloatVector3: tmp789 << shadowStart 790: OpLoad: FloatVector3: tmp790 << light 791: OpExtInst(Distance): Float: tmp791 << tmp789, tmp790 OpStore: : tmp791 >> shadowDistance 795: OpLoad: FloatVector3: tmp795 << shadowStart OpStore: : tmp795 >> param794 797: OpLoad: FloatVector3: tmp797 << l OpStore: : tmp797 >> param796 799: OpLoad: Float: tmp799 << shadowDistance OpStore: : tmp799 >> param798 801: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param794, param796, param798, param800) 802: OpLoad: Float: tmp802 << param800 OpStore: : tmp802 >> shadowSteps 803: OpLoad: Float: tmp803 << shadowDistance 804: OpFOrdGreaterThan: Bool: tmp804 << trace(vf3;vf3;f1;f1;, tmp803 805: OpSelect: Float: tmp805 << tmp804, const117, const92 OpStore: : tmp805 >> shadow 806: OpLoad: Float: tmp806 << shadowSteps 808: OpFDiv: Float: tmp808 << tmp806, const807 809: OpExtInst(Sqrt): Float: tmp809 << tmp808 810: OpFSub: Float: tmp810 << const117, tmp809 811: OpLoad: Float: tmp811 << shadow 812: OpFMul: Float: tmp812 << tmp811, tmp810 OpStore: : tmp812 >> shadow OpStore: : const363 >> ambient 815: OpLoad: FloatVector3: tmp815 << l 816: OpLoad: FloatVector3: tmp816 << normal 817: OpDot: Float: tmp817 << tmp815, tmp816 818: OpExtInst(FMax): Float: tmp818 << const92, tmp817 OpStore: : tmp818 >> diffuse 820: OpLoad: FloatVector3: tmp820 << l 821: OpFNegate: FloatVector3: tmp821 << tmp820 822: OpLoad: FloatVector3: tmp822 << normal 823: OpExtInst(Reflect): FloatVector3: tmp823 << tmp821, tmp822 824: OpLoad: FloatVector3: tmp824 << rd 825: OpFNegate: FloatVector3: tmp825 << tmp824 826: OpDot: Float: tmp826 << tmp823, tmp825 827: OpExtInst(FMax): Float: tmp827 << const92, tmp826 829: OpExtInst(Pow): Float: tmp829 << tmp827, const828 OpStore: : tmp829 >> specular 832: OpLoad: FloatVector3: tmp832 << p OpStore: : tmp832 >> param831 834: OpLoad: FloatVector3: tmp834 << normal OpStore: : tmp834 >> param833 835: OpFunctionCall: Float: calculateAO(vf3;vf3;(param831, param833) OpStore: : calculateAO(vf3;vf3; >> ao 836: OpLoad: Float: tmp836 << ao 838: OpLoad: FloatVector3: tmp838 << p OpStore: : tmp838 >> param837 839: OpFunctionCall: FloatVector3: _texture(vf3;(param837) 840: OpVectorTimesScalar: FloatVector3: tmp840 << _texture(vf3;, tmp836 841: OpLoad: Float: tmp841 << ambient 842: OpLoad: Float: tmp842 << specular 843: OpLoad: Float: tmp843 << diffuse 844: OpFAdd: Float: tmp844 << tmp842, tmp843 845: OpLoad: Float: tmp845 << shadow 846: OpFMul: Float: tmp846 << tmp844, tmp845 847: OpFAdd: Float: tmp847 << tmp841, tmp846 848: OpVectorTimesScalar: FloatVector3: tmp848 << tmp840, tmp847 849: OpLoad: FloatVector4: tmp849 << fragColor 850: OpVectorShuffle: FloatVector4: tmp850 << tmp849, tmp848, 4, 5, 6, 3 OpStore: : tmp850 >> fragColor 851: OpLoad: Float: tmp851 << steps 852: OpFDiv: Float: tmp852 << tmp851, const807 853: OpExtInst(Sqrt): Float: tmp853 << tmp852 854: OpLoad: FloatVector4: tmp854 << fragColor 855: OpVectorTimesScalar: FloatVector4: tmp855 << tmp854, tmp853 OpStore: : tmp855 >> fragColor 856: OpLoad: FloatVector4: tmp856 << fragColor 858: OpLoad: Float: tmp858 << dist 859: OpLoad: Float: tmp859 << dist 860: OpFMul: Float: tmp860 << tmp858, tmp859 862: OpFMul: Float: tmp862 << tmp860, const861 863: OpExtInst(FClamp): Float: tmp863 << tmp862, const92, const117 864: OpCompositeConstruct: FloatVector4: tmp864 << tmp863, tmp863, tmp863, tmp863 865: OpExtInst(FMix): FloatVector4: tmp865 << tmp856, const857, tmp864 OpStore: : tmp865 >> fragColor 866: OpLoad: FloatVector4: tmp866 << fragColor 869: OpExtInst(Pow): FloatVector4: tmp869 << tmp866, const868 OpStore: : tmp869 >> fragColor OpReturn: Performing hardware-independent optimization... Variable color Variable color is redundant. Removing both it and related Load/Store instructions. Variable param873 Variable param874 Removed 1 redundant local variables from function main Variable f Variable f is redundant. Removing both it and related Load/Store instructions. Removed 1 redundant local variables from function hash(vf3; Variable fuv Variable fuv is redundant. Removing both it and related Load/Store instructions. Variable cell0 Variable cell0 is redundant. Removing both it and related Load/Store instructions. Variable param114 Variable param120 Variable param125 Variable param130 Variable axis0 Variable axis0 is redundant. Removing both it and related Load/Store instructions. Variable val0 Variable val0 is redundant. Removing both it and related Load/Store instructions. Variable cell1 Variable cell1 is redundant. Removing both it and related Load/Store instructions. Variable param159 Variable param164 Variable param169 Variable param174 Variable axis1 Variable axis1 is redundant. Removing both it and related Load/Store instructions. Variable val1 Variable val1 is redundant. Removing both it and related Load/Store instructions. Removed 7 redundant local variables from function noise(vf3; Variable f Variable r Variable i Variable param225 Variable s Variable s is redundant. Removing both it and related Load/Store instructions. Variable c Variable c is redundant. Removing both it and related Load/Store instructions. Removed 2 redundant local variables from function tRotate(vf2;f1; Variable param264 Variable param267 Variable id Variable id is redundant. Removing both it and related Load/Store instructions. Removed 1 redundant local variables from function tRepeat2(vf2;vf2; Variable param327 Variable param329 Variable param335 Variable param338 Variable d Variable w Variable w is redundant. Removing both it and related Load/Store instructions. Variable param364 Variable param365 Variable param373 Variable param374 Variable param376 Variable param377 Variable param379 Variable param381 Variable param392 Variable param393 Variable param395 Variable param397 Variable param404 Variable param405 Variable param407 Variable param409 Variable param422 Variable param423 Variable param425 Variable param427 Variable param436 Variable param438 Removed 1 redundant local variables from function map(vf3; Variable total Variable i Variable d Variable d is redundant. Removing both it and related Load/Store instructions. Variable param461 Removed 1 redundant local variables from function trace(vf3;vf3;f1;f1; Variable e Variable e is redundant. Removing both it and related Load/Store instructions. Variable param488 Variable param494 Variable param501 Variable param507 Variable param514 Variable param520 Removed 1 redundant local variables from function getNormal(vf3; Variable r Variable w Variable i Variable d Variable d is redundant. Removing both it and related Load/Store instructions. Variable param549 Removed 1 redundant local variables from function calculateAO(vf3;vf3; Variable param569 Variable param572 Variable param588 Variable param590 Variable wall Variable wall is redundant. Removing both it and related Load/Store instructions. Variable param596 Variable t Variable var601 Variable param610 Variable param620 Variable param628 Removed 1 redundant local variables from function _texture(vf3; Variable uv Variable time Variable ro Variable rd Variable light Variable param710 Variable param713 Variable param723 Variable param726 Variable param736 Variable param739 Variable param749 Variable param752 Variable dist Variable dist is redundant. Removing both it and related Load/Store instructions. Variable steps Variable steps is redundant. Removing both it and related Load/Store instructions. Variable param759 Variable param761 Variable param763 Variable param764 Variable p Variable p is redundant. Removing both it and related Load/Store instructions. Variable normal Variable normal is redundant. Removing both it and related Load/Store instructions. Variable param774 Variable l Variable l is redundant. Removing both it and related Load/Store instructions. Variable shadowStart Variable shadowStart is redundant. Removing both it and related Load/Store instructions. Variable shadowDistance Variable shadowDistance is redundant. Removing both it and related Load/Store instructions. Variable shadow Variable shadowSteps Variable shadowSteps is redundant. Removing both it and related Load/Store instructions. Variable param794 Variable param796 Variable param798 Variable param800 Variable ambient Variable ambient is redundant. Removing both it and related Load/Store instructions. Variable diffuse Variable diffuse is redundant. Removing both it and related Load/Store instructions. Variable specular Variable specular is redundant. Removing both it and related Load/Store instructions. Variable ao Variable ao is redundant. Removing both it and related Load/Store instructions. Variable param831 Variable param833 Variable param837 Removed 12 redundant local variables from function mainImage(vf4;vf2; Optimization done. Optimized Disassembly: Module Info: OpSource: : ESSL ver 310 1: OpExtInstImport: : GLSL.std.450 OpMemoryModel: : addressing: Logical, memory: GLSL450 Capabilities: OpCapability: : Shader Inputs: 872: OpVariable: FloatVector4*: gl_FragCoord: storage class: Input Decorators: BuiltIn(FragCoord) Outputs: 880: OpVariable: FloatVector4*: finalColor: storage class: Output Uniform Constants: 649: OpVariable: FloatVector3*: iResolution: storage class: UniformConstant 667: OpVariable: Float*: iTime: storage class: UniformConstant 883: OpVariable: FloatVector4*: iMouse: storage class: UniformConstant 884: OpVariable: FloatVector4*: iDate: storage class: UniformConstant 885: OpVariable: Float*: iFrame: storage class: UniformConstant 889: OpVariable: FloatVector3[4]*: iChannelResolution: storage class: UniformConstant Textures: 893: OpVariable: SampledImage(Image(Float))*: iChannel0: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 894: OpVariable: SampledImage(Image(Float))*: iChannel1: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 895: OpVariable: SampledImage(Image(Float))*: iChannel2: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) 896: OpVariable: SampledImage(Image(Float))*: iChannel3: storage class: UniformConstant Decorators: RelaxedPrecision, DescriptorSet(0) Entry Points: 4: OpEntryPoint: : main, execution model: Fragment, Function: Void main(), OriginLowerLeft Constants: 92: OpConstant: Float const92 = 0 95: OpConstant: Float const95 = 0.0091239 96: OpConstant: Float const96 = 0.00231233 97: OpConstant: Float const97 = 0.00532234 98: OpConstantComposite: FloatVector3 const98 = {0.0091239, 0.00231233, 0.00532234} 101: OpConstant: Float const101 = 111112 112: OpConstantComposite: FloatVector3 const112 = {0, 0, 0} 117: OpConstant: Float const117 = 1 118: OpConstantComposite: FloatVector3 const118 = {0, 1, 0} 123: OpConstantComposite: FloatVector3 const123 = {1, 0, 0} 128: OpConstantComposite: FloatVector3 const128 = {1, 1, 0} 139: OpConstant: UInt const139 = 1 146: OpConstant: UInt const146 = 0 157: OpConstantComposite: FloatVector3 const157 = {0, 0, 1} 162: OpConstantComposite: FloatVector3 const162 = {0, 1, 1} 167: OpConstantComposite: FloatVector3 const167 = {1, 0, 1} 172: OpConstantComposite: FloatVector3 const172 = {1, 1, 1} 198: OpConstant: UInt const198 = 2 210: OpConstant: Int const210 = 0 217: OpConstant: Int const217 = 5 220: OpConstant: Float const220 = 10 227: OpConstant: Float const227 = 2 234: OpConstant: Int const234 = 1 275: OpConstant: Float const275 = 0.5 333: OpConstant: Float const333 = 0.7 334: OpConstantComposite: FloatVector2 const334 = {0.7, 1} 355: OpConstant: Float const355 = 0.15 360: OpConstant: Float const360 = 0.75 361: OpConstantComposite: FloatVector2 const361 = {0, 0.75} 363: OpConstant: Float const363 = 0.25 369: OpConstant: Float const369 = 0.375 370: OpConstantComposite: FloatVector2 const370 = {0, 0.375} 372: OpConstantComposite: FloatVector2 const372 = {0.25, 0.375} 386: OpConstant: Float const386 = 0.35 387: OpConstantComposite: FloatVector2 const387 = {0, 0.35} 389: OpConstant: Float const389 = 0.45 390: OpConstant: Float const390 = 0.3 391: OpConstantComposite: FloatVector2 const391 = {0.45, 0.3} 401: OpConstantComposite: FloatVector2 const401 = {0.35, 0} 403: OpConstant: Float const403 = 0.075 417: OpConstant: Float const417 = 0.6 418: OpConstantComposite: FloatVector2 const418 = {0.6, 0.5} 420: OpConstant: Float const420 = 0.4 421: OpConstantComposite: FloatVector2 const421 = {0.6, 0.4} 434: OpConstant: Float const434 = 0.8 451: OpConstant: Int const451 = 100 467: OpConstant: Float const467 = 1e-05 482: OpConstant: Float const482 = 0.0001 483: OpConstantComposite: FloatVector2 const483 = {0.0001, 0} 536: OpConstant: Float const536 = 5 606: OpConstant: Float const606 = 0.1 607: OpConstant: Float const607 = 0.9 617: OpConstant: Float const617 = 20 618: OpConstantComposite: FloatVector3 const618 = {5, 20, 5} 622: OpConstantComposite: FloatVector3 const622 = {1, 0.7, 0.4} 626: OpConstantComposite: FloatVector3 const626 = {2, 10, 2} 630: OpConstantComposite: FloatVector3 const630 = {1, 0.8, 0.5} 675: OpConstant: Float const675 = 3.14159 685: OpConstant: Float const685 = 1.5 807: OpConstant: Float const807 = 100 828: OpConstant: Float const828 = 8 857: OpConstantComposite: FloatVector4 const857 = {0.9, 0.8, 0.7, 1} 861: OpConstant: Float const861 = 0.03 867: OpConstant: Float const867 = 0.454545 868: OpConstantComposite: FloatVector4 const868 = {0.454545, 0.454545, 0.454545, 0.454545} 886: OpConstant: UInt const886 = 4 Private Global Variables: 91: OpVariable: Float*: _twist: storage class: Private Disassembled Code: 4: OpFunction: Void main() 873: OpVariable: FloatVector4*: param873: storage class: Function 874: OpVariable: FloatVector2*: param874: storage class: Function 5: lb5: OpStore: : const92 >> _twist 875: OpLoad: FloatVector4: tmp875 << gl_FragCoord 876: OpVectorShuffle: FloatVector2: tmp876 << tmp875, tmp875, 0, 1 OpStore: : tmp876 >> param874 877: OpFunctionCall: Void: mainImage(vf4;vf2;(param873, param874) 878: OpLoad: FloatVector4: tmp878 << param873 OpStore: : tmp878 >> finalColor OpReturn: 11: OpFunction: Float hash(vf3;(FloatVector3* uv) 12: lb12: 94: OpLoad: FloatVector3: tmp94 << uv 99: OpDot: Float: tmp99 << tmp94, const98 100: OpExtInst(Sin): Float: tmp100 << tmp99 102: OpFMul: Float: tmp102 << tmp100, const101 103: OpExtInst(Fract): Float: tmp103 << tmp102 OpReturnValue: : << tmp103 14: OpFunction: Float noise(vf3;(FloatVector3* uv) 114: OpVariable: FloatVector3*: param114: storage class: Function 120: OpVariable: FloatVector3*: param120: storage class: Function 125: OpVariable: FloatVector3*: param125: storage class: Function 130: OpVariable: FloatVector3*: param130: storage class: Function 159: OpVariable: FloatVector3*: param159: storage class: Function 164: OpVariable: FloatVector3*: param164: storage class: Function 169: OpVariable: FloatVector3*: param169: storage class: Function 174: OpVariable: FloatVector3*: param174: storage class: Function 15: lb15: 108: OpLoad: FloatVector3: tmp108 << uv 109: OpExtInst(Floor): FloatVector3: tmp109 << tmp108 113: OpFAdd: FloatVector3: tmp113 << tmp109, const112 OpStore: : tmp113 >> param114 115: OpFunctionCall: Float: hash(vf3;(param114) 119: OpFAdd: FloatVector3: tmp119 << tmp109, const118 OpStore: : tmp119 >> param120 121: OpFunctionCall: Float: hash(vf3;(param120) 124: OpFAdd: FloatVector3: tmp124 << tmp109, const123 OpStore: : tmp124 >> param125 126: OpFunctionCall: Float: hash(vf3;(param125) 129: OpFAdd: FloatVector3: tmp129 << tmp109, const128 OpStore: : tmp129 >> param130 131: OpFunctionCall: Float: hash(vf3;(param130) 132: OpCompositeConstruct: FloatVector4: tmp132 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; 135: OpVectorShuffle: FloatVector2: tmp135 << tmp132, tmp132, 0, 2 137: OpVectorShuffle: FloatVector2: tmp137 << tmp132, tmp132, 1, 3 140: OpAccessChain: Float*: uv[1] 141: OpLoad: Float: tmp141 << uv[1] 142: OpExtInst(Fract): Float: tmp142 << tmp141 143: OpCompositeConstruct: FloatVector2: tmp143 << tmp142, tmp142 144: OpExtInst(FMix): FloatVector2: tmp144 << tmp135, tmp137, tmp143 147: OpAccessChain: Float*: axis0[0] 148: OpCompositeExtract: Float: tmp148 << tmp144, 0 149: OpAccessChain: Float*: axis0[1] 150: OpCompositeExtract: Float: tmp150 << tmp144, 1 151: OpAccessChain: Float*: uv[0] 152: OpLoad: Float: tmp152 << uv[0] 153: OpExtInst(Fract): Float: tmp153 << tmp152 154: OpExtInst(FMix): Float: tmp154 << tmp148, tmp150, tmp153 158: OpFAdd: FloatVector3: tmp158 << tmp109, const157 OpStore: : tmp158 >> param159 160: OpFunctionCall: Float: hash(vf3;(param159) 163: OpFAdd: FloatVector3: tmp163 << tmp109, const162 OpStore: : tmp163 >> param164 165: OpFunctionCall: Float: hash(vf3;(param164) 168: OpFAdd: FloatVector3: tmp168 << tmp109, const167 OpStore: : tmp168 >> param169 170: OpFunctionCall: Float: hash(vf3;(param169) 173: OpFAdd: FloatVector3: tmp173 << tmp109, const172 OpStore: : tmp173 >> param174 175: OpFunctionCall: Float: hash(vf3;(param174) 176: OpCompositeConstruct: FloatVector4: tmp176 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; 179: OpVectorShuffle: FloatVector2: tmp179 << tmp176, tmp176, 0, 2 181: OpVectorShuffle: FloatVector2: tmp181 << tmp176, tmp176, 1, 3 182: OpAccessChain: Float*: uv[1] 183: OpLoad: Float: tmp183 << uv[1] 184: OpExtInst(Fract): Float: tmp184 << tmp183 185: OpCompositeConstruct: FloatVector2: tmp185 << tmp184, tmp184 186: OpExtInst(FMix): FloatVector2: tmp186 << tmp179, tmp181, tmp185 188: OpAccessChain: Float*: axis1[0] 189: OpCompositeExtract: Float: tmp189 << tmp186, 0 190: OpAccessChain: Float*: axis1[1] 191: OpCompositeExtract: Float: tmp191 << tmp186, 1 192: OpAccessChain: Float*: uv[0] 193: OpLoad: Float: tmp193 << uv[0] 194: OpExtInst(Fract): Float: tmp194 << tmp193 195: OpExtInst(FMix): Float: tmp195 << tmp189, tmp191, tmp194 199: OpAccessChain: Float*: uv[2] 200: OpLoad: Float: tmp200 << uv[2] 201: OpExtInst(Fract): Float: tmp201 << tmp200 202: OpExtInst(FMix): Float: tmp202 << tmp154, tmp195, tmp201 OpReturnValue: : << tmp202 17: OpFunction: Float fbm(vf3;(FloatVector3* uv) 205: OpVariable: Float*: f: storage class: Function 206: OpVariable: Float*: r: storage class: Function 209: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 225: OpVariable: FloatVector3*: param225: storage class: Function 18: lb18: OpStore: : const92 >> f OpStore: : const117 >> r OpStore: : const210 >> i OpBranch: to lb211 211: lb211: OpLoopMerge: (merge: lb213, continue: lb214) OpBranch: to lb215 215: lb215: 216: OpLoad: Int: tmp216 << i Decorators: RelaxedPrecision 218: OpSLessThan: Bool: tmp218 << tmp216, const217 OpBranchConditional: if(tmp218) then branch to lb212, else branch to lb213 212: lb212: 219: OpLoad: FloatVector3: tmp219 << uv 221: OpCompositeConstruct: FloatVector3: tmp221 << const220, const220, const220 222: OpFAdd: FloatVector3: tmp222 << tmp219, tmp221 223: OpLoad: Float: tmp223 << r 224: OpVectorTimesScalar: FloatVector3: tmp224 << tmp222, tmp223 OpStore: : tmp224 >> param225 226: OpFunctionCall: Float: noise(vf3;(param225) 228: OpLoad: Float: tmp228 << r 229: OpFMul: Float: tmp229 << tmp228, const227 OpStore: : tmp229 >> r 230: OpFDiv: Float: tmp230 << noise(vf3;, tmp229 231: OpLoad: Float: tmp231 << f 232: OpFAdd: Float: tmp232 << tmp231, tmp230 OpStore: : tmp232 >> f OpBranch: to lb214 214: lb214: 233: OpLoad: Int: tmp233 << i Decorators: RelaxedPrecision 235: OpIAdd: Int: tmp235 << tmp233, const234 Decorators: RelaxedPrecision OpStore: : tmp235 >> i OpBranch: to lb211 213: lb213: 236: OpLoad: Float: tmp236 << f 237: OpLoad: Float: tmp237 << r 238: OpFDiv: Float: tmp238 << const117, tmp237 239: OpFSub: Float: tmp239 << const117, tmp238 240: OpFDiv: Float: tmp240 << tmp236, tmp239 OpReturnValue: : << tmp240 25: OpFunction: Void tRotate(vf2;f1;(FloatVector2* p, Float* angel) 26: lb26: 244: OpLoad: Float: tmp244 << angel 245: OpExtInst(Sin): Float: tmp245 << tmp244 247: OpLoad: Float: tmp247 << angel 248: OpExtInst(Cos): Float: tmp248 << tmp247 251: OpFNegate: Float: tmp251 << tmp245 255: OpCompositeConstruct: FloatVector2: tmp255 << tmp248, tmp251 256: OpCompositeConstruct: FloatVector2: tmp256 << tmp245, tmp248 257: OpCompositeConstruct: FloatMatrix2x2: tmp257 << tmp255, tmp256 258: OpLoad: FloatVector2: tmp258 << p 259: OpVectorTimesMatrix: FloatVector2: tmp259 << tmp258, tmp257 OpStore: : tmp259 >> p OpReturn: 30: OpFunction: Void tTwist(vf3;f1;(FloatVector3* p, Float* a) 264: OpVariable: FloatVector2*: param264: storage class: Function 267: OpVariable: Float*: param267: storage class: Function 31: lb31: 260: OpAccessChain: Float*: p[2] 261: OpLoad: Float: tmp261 << p[2] 262: OpLoad: Float: tmp262 << a 263: OpFMul: Float: tmp263 << tmp261, tmp262 265: OpLoad: FloatVector3: tmp265 << p 266: OpVectorShuffle: FloatVector2: tmp266 << tmp265, tmp265, 0, 1 OpStore: : tmp266 >> param264 OpStore: : tmp263 >> param267 268: OpFunctionCall: Void: tRotate(vf2;f1;(param264, param267) 269: OpLoad: FloatVector2: tmp269 << param264 270: OpLoad: FloatVector3: tmp270 << p 271: OpVectorShuffle: FloatVector3: tmp271 << tmp270, tmp269, 3, 4, 2 OpStore: : tmp271 >> p OpReturn: 35: OpFunction: FloatVector2 tRepeat2(vf2;vf2;(FloatVector2* p, FloatVector2* r) 36: lb36: 273: OpLoad: FloatVector2: tmp273 << p 274: OpLoad: FloatVector2: tmp274 << r 276: OpVectorTimesScalar: FloatVector2: tmp276 << tmp274, const275 277: OpFAdd: FloatVector2: tmp277 << tmp273, tmp276 278: OpLoad: FloatVector2: tmp278 << r 279: OpFDiv: FloatVector2: tmp279 << tmp277, tmp278 280: OpExtInst(Floor): FloatVector2: tmp280 << tmp279 281: OpLoad: FloatVector2: tmp281 << p 282: OpLoad: FloatVector2: tmp282 << r 283: OpVectorTimesScalar: FloatVector2: tmp283 << tmp282, const275 284: OpFAdd: FloatVector2: tmp284 << tmp281, tmp283 285: OpLoad: FloatVector2: tmp285 << r 286: OpFMod: FloatVector2: tmp286 << tmp284, tmp285 287: OpLoad: FloatVector2: tmp287 << r 288: OpVectorTimesScalar: FloatVector2: tmp288 << tmp287, const275 289: OpFSub: FloatVector2: tmp289 << tmp286, tmp288 OpStore: : tmp289 >> p OpReturnValue: : << tmp280 40: OpFunction: Float sdRect(vf2;vf2;(FloatVector2* p, FloatVector2* r) 41: lb41: 293: OpLoad: FloatVector2: tmp293 << p 294: OpExtInst(FAbs): FloatVector2: tmp294 << tmp293 295: OpLoad: FloatVector2: tmp295 << r 296: OpFSub: FloatVector2: tmp296 << tmp294, tmp295 OpStore: : tmp296 >> p 297: OpAccessChain: Float*: p[0] 298: OpLoad: Float: tmp298 << p[0] 299: OpAccessChain: Float*: p[1] 300: OpLoad: Float: tmp300 << p[1] 301: OpExtInst(FMax): Float: tmp301 << tmp298, tmp300 302: OpExtInst(FMin): Float: tmp302 << tmp301, const92 303: OpLoad: FloatVector2: tmp303 << p 304: OpCompositeConstruct: FloatVector2: tmp304 << const92, const92 305: OpExtInst(FMax): FloatVector2: tmp305 << tmp303, tmp304 306: OpExtInst(Length): Float: tmp306 << tmp305 307: OpFAdd: Float: tmp307 << tmp302, tmp306 OpReturnValue: : << tmp307 45: OpFunction: Float sdCircle(vf2;f1;(FloatVector2* p, Float* r) 46: lb46: 310: OpLoad: FloatVector2: tmp310 << p 311: OpExtInst(Length): Float: tmp311 << tmp310 312: OpLoad: Float: tmp312 << r 313: OpFSub: Float: tmp313 << tmp311, tmp312 OpReturnValue: : << tmp313 50: OpFunction: Float opU(f1;f1;(Float* a, Float* b) 51: lb51: 316: OpLoad: Float: tmp316 << a 317: OpLoad: Float: tmp317 << b 318: OpExtInst(FMin): Float: tmp318 << tmp316, tmp317 OpReturnValue: : << tmp318 54: OpFunction: Float opS(f1;f1;(Float* a, Float* b) 55: lb55: 321: OpLoad: Float: tmp321 << a 322: OpLoad: Float: tmp322 << b 323: OpFNegate: Float: tmp323 << tmp322 324: OpExtInst(FMax): Float: tmp324 << tmp321, tmp323 OpReturnValue: : << tmp324 57: OpFunction: Float map(vf3;(FloatVector3* p) 327: OpVariable: FloatVector3*: param327: storage class: Function 329: OpVariable: Float*: param329: storage class: Function 335: OpVariable: FloatVector2*: param335: storage class: Function 338: OpVariable: FloatVector2*: param338: storage class: Function 351: OpVariable: Float*: d: storage class: Function 364: OpVariable: FloatVector2*: param364: storage class: Function 365: OpVariable: Float*: param365: storage class: Function 373: OpVariable: FloatVector2*: param373: storage class: Function 374: OpVariable: FloatVector2*: param374: storage class: Function 376: OpVariable: Float*: param376: storage class: Function 377: OpVariable: Float*: param377: storage class: Function 379: OpVariable: Float*: param379: storage class: Function 381: OpVariable: Float*: param381: storage class: Function 392: OpVariable: FloatVector2*: param392: storage class: Function 393: OpVariable: FloatVector2*: param393: storage class: Function 395: OpVariable: Float*: param395: storage class: Function 397: OpVariable: Float*: param397: storage class: Function 404: OpVariable: FloatVector2*: param404: storage class: Function 405: OpVariable: Float*: param405: storage class: Function 407: OpVariable: Float*: param407: storage class: Function 409: OpVariable: Float*: param409: storage class: Function 422: OpVariable: FloatVector2*: param422: storage class: Function 423: OpVariable: FloatVector2*: param423: storage class: Function 425: OpVariable: Float*: param425: storage class: Function 427: OpVariable: Float*: param427: storage class: Function 436: OpVariable: Float*: param436: storage class: Function 438: OpVariable: Float*: param438: storage class: Function 58: lb58: 328: OpLoad: FloatVector3: tmp328 << p OpStore: : tmp328 >> param327 330: OpLoad: Float: tmp330 << _twist OpStore: : tmp330 >> param329 331: OpFunctionCall: Void: tTwist(vf3;f1;(param327, param329) 332: OpLoad: FloatVector3: tmp332 << param327 OpStore: : tmp332 >> p 336: OpLoad: FloatVector3: tmp336 << p 337: OpVectorShuffle: FloatVector2: tmp337 << tmp336, tmp336, 0, 2 OpStore: : tmp337 >> param335 OpStore: : const334 >> param338 339: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param335, param338) 340: OpLoad: FloatVector2: tmp340 << param335 341: OpLoad: FloatVector3: tmp341 << p 342: OpVectorShuffle: FloatVector3: tmp342 << tmp341, tmp340, 3, 1, 4 OpStore: : tmp342 >> p 343: OpAccessChain: Float*: p[0] 344: OpLoad: Float: tmp344 << p[0] 345: OpExtInst(FAbs): Float: tmp345 << tmp344 346: OpAccessChain: Float*: p[0] OpStore: : tmp345 >> p[0] 347: OpAccessChain: Float*: p[1] 348: OpLoad: Float: tmp348 << p[1] 349: OpFAdd: Float: tmp349 << tmp348, const275 350: OpAccessChain: Float*: p[1] OpStore: : tmp349 >> p[1] 352: OpAccessChain: Float*: p[2] 353: OpLoad: Float: tmp353 << p[2] 354: OpExtInst(FAbs): Float: tmp354 << tmp353 356: OpFSub: Float: tmp356 << tmp354, const355 OpStore: : tmp356 >> d 358: OpLoad: FloatVector3: tmp358 << p 359: OpVectorShuffle: FloatVector2: tmp359 << tmp358, tmp358, 0, 1 362: OpFSub: FloatVector2: tmp362 << tmp359, const361 OpStore: : tmp362 >> param364 OpStore: : const363 >> param365 366: OpFunctionCall: Float: sdCircle(vf2;f1;(param364, param365) 367: OpLoad: FloatVector3: tmp367 << p 368: OpVectorShuffle: FloatVector2: tmp368 << tmp367, tmp367, 0, 1 371: OpFSub: FloatVector2: tmp371 << tmp368, const370 OpStore: : tmp371 >> param373 OpStore: : const372 >> param374 375: OpFunctionCall: Float: sdRect(vf2;vf2;(param373, param374) OpStore: : sdCircle(vf2;f1; >> param376 OpStore: : sdRect(vf2;vf2; >> param377 378: OpFunctionCall: Float: opU(f1;f1;(param376, param377) 380: OpLoad: Float: tmp380 << d OpStore: : tmp380 >> param379 OpStore: : opU(f1;f1; >> param381 383: OpFunctionCall: Float: opS(f1;f1;(param379, param381) OpStore: : opS(f1;f1; >> d 384: OpLoad: FloatVector3: tmp384 << p 385: OpVectorShuffle: FloatVector2: tmp385 << tmp384, tmp384, 0, 1 388: OpFSub: FloatVector2: tmp388 << tmp385, const387 OpStore: : tmp388 >> param392 OpStore: : const391 >> param393 394: OpFunctionCall: Float: sdRect(vf2;vf2;(param392, param393) 396: OpLoad: Float: tmp396 << d OpStore: : tmp396 >> param395 OpStore: : sdRect(vf2;vf2; >> param397 398: OpFunctionCall: Float: opS(f1;f1;(param395, param397) OpStore: : opS(f1;f1; >> d 399: OpLoad: FloatVector3: tmp399 << p 400: OpVectorShuffle: FloatVector2: tmp400 << tmp399, tmp399, 0, 2 402: OpFSub: FloatVector2: tmp402 << tmp400, const401 OpStore: : tmp402 >> param404 OpStore: : const403 >> param405 406: OpFunctionCall: Float: sdCircle(vf2;f1;(param404, param405) 408: OpLoad: Float: tmp408 << d OpStore: : tmp408 >> param407 OpStore: : sdCircle(vf2;f1; >> param409 410: OpFunctionCall: Float: opU(f1;f1;(param407, param409) OpStore: : opU(f1;f1; >> d 411: OpAccessChain: Float*: p[2] 412: OpLoad: Float: tmp412 << p[2] 413: OpExtInst(FAbs): Float: tmp413 << tmp412 414: OpAccessChain: Float*: p[2] OpStore: : tmp413 >> p[2] 415: OpLoad: FloatVector3: tmp415 << p 416: OpVectorShuffle: FloatVector2: tmp416 << tmp415, tmp415, 1, 2 419: OpFSub: FloatVector2: tmp419 << tmp416, const418 OpStore: : tmp419 >> param422 OpStore: : const421 >> param423 424: OpFunctionCall: Float: sdRect(vf2;vf2;(param422, param423) 426: OpLoad: Float: tmp426 << d OpStore: : tmp426 >> param425 OpStore: : sdRect(vf2;vf2; >> param427 428: OpFunctionCall: Float: opS(f1;f1;(param425, param427) OpStore: : opS(f1;f1; >> d 429: OpAccessChain: Float*: p[1] 430: OpLoad: Float: tmp430 << p[1] 431: OpFSub: Float: tmp431 << tmp430, const275 432: OpExtInst(FAbs): Float: tmp432 << tmp431 433: OpFNegate: Float: tmp433 << tmp432 435: OpFAdd: Float: tmp435 << tmp433, const434 437: OpLoad: Float: tmp437 << d OpStore: : tmp437 >> param436 OpStore: : tmp435 >> param438 439: OpFunctionCall: Float: opU(f1;f1;(param436, param438) OpStore: : opU(f1;f1; >> d 440: OpLoad: Float: tmp440 << d OpReturnValue: : << tmp440 64: OpFunction: Float trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* maxDist, Float* steps) 443: OpVariable: Float*: total: storage class: Function 444: OpVariable: Int*: i: storage class: Function Decorators: RelaxedPrecision 461: OpVariable: FloatVector3*: param461: storage class: Function 65: lb65: OpStore: : const92 >> total OpStore: : const92 >> steps OpStore: : const210 >> i OpBranch: to lb445 445: lb445: OpLoopMerge: (merge: lb447, continue: lb448) OpBranch: to lb449 449: lb449: 450: OpLoad: Int: tmp450 << i Decorators: RelaxedPrecision 452: OpSLessThan: Bool: tmp452 << tmp450, const451 OpBranchConditional: if(tmp452) then branch to lb446, else branch to lb447 446: lb446: 453: OpLoad: Float: tmp453 << steps 454: OpFAdd: Float: tmp454 << tmp453, const117 OpStore: : tmp454 >> steps 456: OpLoad: FloatVector3: tmp456 << ro 457: OpLoad: FloatVector3: tmp457 << rd 458: OpLoad: Float: tmp458 << total 459: OpVectorTimesScalar: FloatVector3: tmp459 << tmp457, tmp458 460: OpFAdd: FloatVector3: tmp460 << tmp456, tmp459 OpStore: : tmp460 >> param461 462: OpFunctionCall: Float: map(vf3;(param461) 464: OpLoad: Float: tmp464 << total 465: OpFAdd: Float: tmp465 << tmp464, map(vf3; OpStore: : tmp465 >> total 468: OpFOrdLessThan: Bool: tmp468 << map(vf3;, const467 469: OpLoad: Float: tmp469 << maxDist 470: OpLoad: Float: tmp470 << total 471: OpFOrdLessThan: Bool: tmp471 << tmp469, tmp470 472: OpLogicalOr: Bool: tmp472 << tmp468, tmp471 OpSelectionMerge: (merge: lb474) OpBranchConditional: if(tmp472) then branch to lb473, else branch to lb474 473: lb473: OpBranch: to lb447 474: lb474: OpBranch: to lb448 448: lb448: 476: OpLoad: Int: tmp476 << i Decorators: RelaxedPrecision 477: OpIAdd: Int: tmp477 << tmp476, const234 Decorators: RelaxedPrecision OpStore: : tmp477 >> i OpBranch: to lb445 447: lb447: 478: OpLoad: Float: tmp478 << total OpReturnValue: : << tmp478 68: OpFunction: FloatVector3 getNormal(vf3;(FloatVector3* p) 488: OpVariable: FloatVector3*: param488: storage class: Function 494: OpVariable: FloatVector3*: param494: storage class: Function 501: OpVariable: FloatVector3*: param501: storage class: Function 507: OpVariable: FloatVector3*: param507: storage class: Function 514: OpVariable: FloatVector3*: param514: storage class: Function 520: OpVariable: FloatVector3*: param520: storage class: Function 69: lb69: 484: OpLoad: FloatVector3: tmp484 << p 486: OpVectorShuffle: FloatVector3: tmp486 << const483, const483, 0, 1, 1 487: OpFAdd: FloatVector3: tmp487 << tmp484, tmp486 OpStore: : tmp487 >> param488 489: OpFunctionCall: Float: map(vf3;(param488) 490: OpLoad: FloatVector3: tmp490 << p 492: OpVectorShuffle: FloatVector3: tmp492 << const483, const483, 0, 1, 1 493: OpFSub: FloatVector3: tmp493 << tmp490, tmp492 OpStore: : tmp493 >> param494 495: OpFunctionCall: Float: map(vf3;(param494) 496: OpFSub: Float: tmp496 << map(vf3;, map(vf3; 497: OpLoad: FloatVector3: tmp497 << p 499: OpVectorShuffle: FloatVector3: tmp499 << const483, const483, 1, 0, 1 500: OpFAdd: FloatVector3: tmp500 << tmp497, tmp499 OpStore: : tmp500 >> param501 502: OpFunctionCall: Float: map(vf3;(param501) 503: OpLoad: FloatVector3: tmp503 << p 505: OpVectorShuffle: FloatVector3: tmp505 << const483, const483, 1, 0, 1 506: OpFSub: FloatVector3: tmp506 << tmp503, tmp505 OpStore: : tmp506 >> param507 508: OpFunctionCall: Float: map(vf3;(param507) 509: OpFSub: Float: tmp509 << map(vf3;, map(vf3; 510: OpLoad: FloatVector3: tmp510 << p 512: OpVectorShuffle: FloatVector3: tmp512 << const483, const483, 1, 1, 0 513: OpFAdd: FloatVector3: tmp513 << tmp510, tmp512 OpStore: : tmp513 >> param514 515: OpFunctionCall: Float: map(vf3;(param514) 516: OpLoad: FloatVector3: tmp516 << p 518: OpVectorShuffle: FloatVector3: tmp518 << const483, const483, 1, 1, 0 519: OpFSub: FloatVector3: tmp519 << tmp516, tmp518 OpStore: : tmp519 >> param520 521: OpFunctionCall: Float: map(vf3;(param520) 522: OpFSub: Float: tmp522 << map(vf3;, map(vf3; 523: OpCompositeConstruct: FloatVector3: tmp523 << tmp496, tmp509, tmp522 524: OpExtInst(Normalize): FloatVector3: tmp524 << tmp523 OpReturnValue: : << tmp524 73: OpFunction: Float calculateAO(vf3;vf3;(FloatVector3* p, FloatVector3* n) 527: OpVariable: Float*: r: storage class: Function 528: OpVariable: Float*: w: storage class: Function 529: OpVariable: Float*: i: storage class: Function 549: OpVariable: FloatVector3*: param549: storage class: Function 74: lb74: OpStore: : const92 >> r OpStore: : const117 >> w OpStore: : const117 >> i OpBranch: to lb530 530: lb530: OpLoopMerge: (merge: lb532, continue: lb533) OpBranch: to lb534 534: lb534: 535: OpLoad: Float: tmp535 << i 537: OpFOrdLessThanEqual: Bool: tmp537 << tmp535, const536 OpBranchConditional: if(tmp537) then branch to lb531, else branch to lb532 531: lb531: 539: OpLoad: Float: tmp539 << i 540: OpFDiv: Float: tmp540 << tmp539, const536 541: OpFDiv: Float: tmp541 << tmp540, const220 542: OpLoad: Float: tmp542 << w 544: OpLoad: FloatVector3: tmp544 << p 545: OpLoad: FloatVector3: tmp545 << n 547: OpVectorTimesScalar: FloatVector3: tmp547 << tmp545, tmp541 548: OpFAdd: FloatVector3: tmp548 << tmp544, tmp547 OpStore: : tmp548 >> param549 550: OpFunctionCall: Float: map(vf3;(param549) 551: OpFSub: Float: tmp551 << tmp541, map(vf3; 552: OpFMul: Float: tmp552 << tmp542, tmp551 553: OpLoad: Float: tmp553 << r 554: OpFAdd: Float: tmp554 << tmp553, tmp552 OpStore: : tmp554 >> r 555: OpLoad: Float: tmp555 << w 556: OpFMul: Float: tmp556 << tmp555, const275 OpStore: : tmp556 >> w OpBranch: to lb533 533: lb533: 557: OpLoad: Float: tmp557 << i 558: OpFAdd: Float: tmp558 << tmp557, const117 OpStore: : tmp558 >> i OpBranch: to lb530 532: lb532: 559: OpLoad: Float: tmp559 << r 560: OpFMul: Float: tmp560 << tmp559, const220 561: OpExtInst(FClamp): Float: tmp561 << tmp560, const92, const117 562: OpFSub: Float: tmp562 << const117, tmp561 OpReturnValue: : << tmp562 78: OpFunction: Bool isWall(vf3;(FloatVector3* p) 569: OpVariable: FloatVector2*: param569: storage class: Function 572: OpVariable: FloatVector2*: param572: storage class: Function 79: lb79: 565: OpAccessChain: Float*: p[0] 566: OpLoad: Float: tmp566 << p[0] 567: OpFAdd: Float: tmp567 << tmp566, const386 568: OpAccessChain: Float*: p[0] OpStore: : tmp567 >> p[0] 570: OpLoad: FloatVector3: tmp570 << p 571: OpVectorShuffle: FloatVector2: tmp571 << tmp570, tmp570, 0, 2 OpStore: : tmp571 >> param569 OpStore: : const334 >> param572 573: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param569, param572) 574: OpLoad: FloatVector2: tmp574 << param569 575: OpLoad: FloatVector3: tmp575 << p 576: OpVectorShuffle: FloatVector3: tmp576 << tmp575, tmp574, 3, 1, 4 OpStore: : tmp576 >> p 577: OpAccessChain: Float*: p[1] 578: OpLoad: Float: tmp578 << p[1] 579: OpFAdd: Float: tmp579 << tmp578, const355 580: OpExtInst(FAbs): Float: tmp580 << tmp579 581: OpLoad: FloatVector3: tmp581 << p 582: OpVectorShuffle: FloatVector2: tmp582 << tmp581, tmp581, 0, 2 583: OpExtInst(Length): Float: tmp583 << tmp582 584: OpFAdd: Float: tmp584 << tmp580, tmp583 585: OpFOrdLessThan: Bool: tmp585 << const369, tmp584 OpReturnValue: : << tmp585 81: OpFunction: FloatVector3 _texture(vf3;(FloatVector3* p) 588: OpVariable: FloatVector3*: param588: storage class: Function 590: OpVariable: Float*: param590: storage class: Function 596: OpVariable: FloatVector3*: param596: storage class: Function 599: OpVariable: FloatVector3*: t: storage class: Function 601: OpVariable: Float*: var601: storage class: Function 610: OpVariable: FloatVector3*: param610: storage class: Function 620: OpVariable: FloatVector3*: param620: storage class: Function 628: OpVariable: FloatVector3*: param628: storage class: Function 82: lb82: 589: OpLoad: FloatVector3: tmp589 << p OpStore: : tmp589 >> param588 591: OpLoad: Float: tmp591 << _twist OpStore: : tmp591 >> param590 592: OpFunctionCall: Void: tTwist(vf3;f1;(param588, param590) 593: OpLoad: FloatVector3: tmp593 << param588 OpStore: : tmp593 >> p 597: OpLoad: FloatVector3: tmp597 << p OpStore: : tmp597 >> param596 598: OpFunctionCall: Bool: isWall(vf3;(param596) 600: OpLoad: FloatVector3: tmp600 << p OpSelectionMerge: (merge: lb604) OpBranchConditional: if(isWall(vf3;) then branch to lb603, else branch to lb605 603: lb603: OpStore: : const92 >> var601 OpBranch: to lb604 605: lb605: 608: OpLoad: FloatVector3: tmp608 << p 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp608, const536 OpStore: : tmp609 >> param610 611: OpFunctionCall: Float: fbm(vf3;(param610) 612: OpFMul: Float: tmp612 << const607, fbm(vf3; 613: OpFAdd: Float: tmp613 << const606, tmp612 OpStore: : tmp613 >> var601 OpBranch: to lb604 604: lb604: 614: OpLoad: Float: tmp614 << var601 615: OpCompositeConstruct: FloatVector3: tmp615 << tmp614, tmp614, tmp614 616: OpFAdd: FloatVector3: tmp616 << tmp600, tmp615 619: OpFMul: FloatVector3: tmp619 << tmp616, const618 OpStore: : tmp619 >> param620 621: OpFunctionCall: Float: fbm(vf3;(param620) 623: OpVectorTimesScalar: FloatVector3: tmp623 << const622, fbm(vf3; 624: OpVectorTimesScalar: FloatVector3: tmp624 << tmp623, const360 625: OpLoad: FloatVector3: tmp625 << p 627: OpFMul: FloatVector3: tmp627 << tmp625, const626 OpStore: : tmp627 >> param628 629: OpFunctionCall: Float: fbm(vf3;(param628) 631: OpVectorTimesScalar: FloatVector3: tmp631 << const630, fbm(vf3; 632: OpVectorTimesScalar: FloatVector3: tmp632 << tmp631, const363 633: OpFAdd: FloatVector3: tmp633 << tmp624, tmp632 OpStore: : tmp633 >> t OpSelectionMerge: (merge: lb636) OpBranchConditional: if(isWall(vf3;) then branch to lb635, else branch to lb636 635: lb635: 637: OpLoad: FloatVector3: tmp637 << t 638: OpCompositeConstruct: FloatVector3: tmp638 << const275, const275, const275 639: OpExtInst(FMix): FloatVector3: tmp639 << tmp637, const172, tmp638 OpStore: : tmp639 >> t OpBranch: to lb636 636: lb636: 640: OpLoad: FloatVector3: tmp640 << t 641: OpCompositeConstruct: FloatVector3: tmp641 << const92, const92, const92 642: OpCompositeConstruct: FloatVector3: tmp642 << const117, const117, const117 643: OpExtInst(FClamp): FloatVector3: tmp643 << tmp640, tmp641, tmp642 OpReturnValue: : << tmp643 88: OpFunction: Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) 646: OpVariable: FloatVector2*: uv: storage class: Function 666: OpVariable: Float*: time: storage class: Function 673: OpVariable: FloatVector3*: ro: storage class: Function 683: OpVariable: FloatVector3*: rd: storage class: Function 692: OpVariable: FloatVector3*: light: storage class: Function 710: OpVariable: FloatVector2*: param710: storage class: Function 713: OpVariable: Float*: param713: storage class: Function 723: OpVariable: FloatVector2*: param723: storage class: Function 726: OpVariable: Float*: param726: storage class: Function 736: OpVariable: FloatVector2*: param736: storage class: Function 739: OpVariable: Float*: param739: storage class: Function 749: OpVariable: FloatVector2*: param749: storage class: Function 752: OpVariable: Float*: param752: storage class: Function 759: OpVariable: FloatVector3*: param759: storage class: Function 761: OpVariable: FloatVector3*: param761: storage class: Function 763: OpVariable: Float*: param763: storage class: Function 764: OpVariable: Float*: param764: storage class: Function 774: OpVariable: FloatVector3*: param774: storage class: Function 792: OpVariable: Float*: shadow: storage class: Function 794: OpVariable: FloatVector3*: param794: storage class: Function 796: OpVariable: FloatVector3*: param796: storage class: Function 798: OpVariable: Float*: param798: storage class: Function 800: OpVariable: Float*: param800: storage class: Function 831: OpVariable: FloatVector3*: param831: storage class: Function 833: OpVariable: FloatVector3*: param833: storage class: Function 837: OpVariable: FloatVector3*: param837: storage class: Function 89: lb89: 647: OpLoad: FloatVector2: tmp647 << fragCoord 650: OpLoad: FloatVector3: tmp650 << iResolution 651: OpVectorShuffle: FloatVector2: tmp651 << tmp650, tmp650, 0, 1 652: OpFDiv: FloatVector2: tmp652 << tmp647, tmp651 653: OpVectorTimesScalar: FloatVector2: tmp653 << tmp652, const227 654: OpCompositeConstruct: FloatVector2: tmp654 << const117, const117 655: OpFSub: FloatVector2: tmp655 << tmp653, tmp654 OpStore: : tmp655 >> uv 657: OpAccessChain: Float*: iResolution[0] 658: OpLoad: Float: tmp658 << iResolution[0] 659: OpAccessChain: Float*: iResolution[1] 660: OpLoad: Float: tmp660 << iResolution[1] 661: OpFDiv: Float: tmp661 << tmp658, tmp660 662: OpAccessChain: Float*: uv[0] 663: OpLoad: Float: tmp663 << uv[0] 664: OpFMul: Float: tmp664 << tmp663, tmp661 665: OpAccessChain: Float*: uv[0] OpStore: : tmp664 >> uv[0] 668: OpLoad: Float: tmp668 << iTime 669: OpFMul: Float: tmp669 << tmp668, const275 OpStore: : tmp669 >> time 670: OpLoad: Float: tmp670 << time 671: OpExtInst(Sin): Float: tmp671 << tmp670 672: OpFMul: Float: tmp672 << tmp671, const420 OpStore: : tmp672 >> _twist 674: OpLoad: Float: tmp674 << time 676: OpFMul: Float: tmp676 << tmp674, const675 677: OpFDiv: Float: tmp677 << tmp676, const227 678: OpFAdd: Float: tmp678 << tmp677, const117 679: OpExtInst(Sin): Float: tmp679 << tmp678 680: OpFMul: Float: tmp680 << tmp679, const117 681: OpLoad: Float: tmp681 << time 682: OpCompositeConstruct: FloatVector3: tmp682 << tmp680, const92, tmp681 OpStore: : tmp682 >> ro 684: OpLoad: FloatVector2: tmp684 << uv 686: OpCompositeExtract: Float: tmp686 << tmp684, 0 687: OpCompositeExtract: Float: tmp687 << tmp684, 1 688: OpCompositeConstruct: FloatVector3: tmp688 << tmp686, tmp687, const685 689: OpExtInst(Normalize): FloatVector3: tmp689 << tmp688 OpStore: : tmp689 >> rd 690: OpLoad: Float: tmp690 << time 691: OpFAdd: Float: tmp691 << tmp690, const227 OpStore: : tmp691 >> time 693: OpLoad: Float: tmp693 << time 694: OpFMul: Float: tmp694 << tmp693, const675 695: OpFDiv: Float: tmp695 << tmp694, const227 696: OpFAdd: Float: tmp696 << tmp695, const117 697: OpExtInst(Sin): Float: tmp697 << tmp696 698: OpFMul: Float: tmp698 << tmp697, const117 699: OpLoad: Float: tmp699 << time 700: OpCompositeConstruct: FloatVector3: tmp700 << tmp698, const92, tmp699 OpStore: : tmp700 >> light 701: OpLoad: Float: tmp701 << time 702: OpFSub: Float: tmp702 << tmp701, const227 OpStore: : tmp702 >> time 703: OpLoad: Float: tmp703 << time 704: OpFMul: Float: tmp704 << tmp703, const675 705: OpFDiv: Float: tmp705 << tmp704, const227 706: OpFAdd: Float: tmp706 << tmp705, const117 707: OpExtInst(Cos): Float: tmp707 << tmp706 708: OpFNegate: Float: tmp708 << tmp707 709: OpFMul: Float: tmp709 << tmp708, const275 711: OpLoad: FloatVector3: tmp711 << rd 712: OpVectorShuffle: FloatVector2: tmp712 << tmp711, tmp711, 0, 2 OpStore: : tmp712 >> param710 OpStore: : tmp709 >> param713 714: OpFunctionCall: Void: tRotate(vf2;f1;(param710, param713) 715: OpLoad: FloatVector2: tmp715 << param710 716: OpLoad: FloatVector3: tmp716 << rd 717: OpVectorShuffle: FloatVector3: tmp717 << tmp716, tmp715, 3, 1, 4 OpStore: : tmp717 >> rd 718: OpAccessChain: Float*: ro[2] 719: OpLoad: Float: tmp719 << ro[2] 720: OpFNegate: Float: tmp720 << tmp719 721: OpLoad: Float: tmp721 << _twist 722: OpFMul: Float: tmp722 << tmp720, tmp721 724: OpLoad: FloatVector3: tmp724 << ro 725: OpVectorShuffle: FloatVector2: tmp725 << tmp724, tmp724, 0, 1 OpStore: : tmp725 >> param723 OpStore: : tmp722 >> param726 727: OpFunctionCall: Void: tRotate(vf2;f1;(param723, param726) 728: OpLoad: FloatVector2: tmp728 << param723 729: OpLoad: FloatVector3: tmp729 << ro 730: OpVectorShuffle: FloatVector3: tmp730 << tmp729, tmp728, 3, 4, 2 OpStore: : tmp730 >> ro 731: OpAccessChain: Float*: light[2] 732: OpLoad: Float: tmp732 << light[2] 733: OpFNegate: Float: tmp733 << tmp732 734: OpLoad: Float: tmp734 << _twist 735: OpFMul: Float: tmp735 << tmp733, tmp734 737: OpLoad: FloatVector3: tmp737 << light 738: OpVectorShuffle: FloatVector2: tmp738 << tmp737, tmp737, 0, 1 OpStore: : tmp738 >> param736 OpStore: : tmp735 >> param739 740: OpFunctionCall: Void: tRotate(vf2;f1;(param736, param739) 741: OpLoad: FloatVector2: tmp741 << param736 742: OpLoad: FloatVector3: tmp742 << light 743: OpVectorShuffle: FloatVector3: tmp743 << tmp742, tmp741, 3, 4, 2 OpStore: : tmp743 >> light 744: OpAccessChain: Float*: ro[2] 745: OpLoad: Float: tmp745 << ro[2] 746: OpFNegate: Float: tmp746 << tmp745 747: OpLoad: Float: tmp747 << _twist 748: OpFMul: Float: tmp748 << tmp746, tmp747 750: OpLoad: FloatVector3: tmp750 << rd 751: OpVectorShuffle: FloatVector2: tmp751 << tmp750, tmp750, 0, 1 OpStore: : tmp751 >> param749 OpStore: : tmp748 >> param752 753: OpFunctionCall: Void: tRotate(vf2;f1;(param749, param752) 754: OpLoad: FloatVector2: tmp754 << param749 755: OpLoad: FloatVector3: tmp755 << rd 756: OpVectorShuffle: FloatVector3: tmp756 << tmp755, tmp754, 3, 4, 2 OpStore: : tmp756 >> rd 760: OpLoad: FloatVector3: tmp760 << ro OpStore: : tmp760 >> param759 762: OpLoad: FloatVector3: tmp762 << rd OpStore: : tmp762 >> param761 OpStore: : const220 >> param763 765: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param759, param761, param763, param764) 766: OpLoad: Float: tmp766 << param764 768: OpLoad: FloatVector3: tmp768 << ro 769: OpLoad: FloatVector3: tmp769 << rd 771: OpVectorTimesScalar: FloatVector3: tmp771 << tmp769, trace(vf3;vf3;f1;f1; 772: OpFAdd: FloatVector3: tmp772 << tmp768, tmp771 OpStore: : tmp772 >> param774 776: OpFunctionCall: FloatVector3: getNormal(vf3;(param774) 778: OpLoad: FloatVector3: tmp778 << light 780: OpFSub: FloatVector3: tmp780 << tmp778, tmp772 781: OpExtInst(Normalize): FloatVector3: tmp781 << tmp780 785: OpVectorTimesScalar: FloatVector3: tmp785 << getNormal(vf3;, const467 786: OpVectorTimesScalar: FloatVector3: tmp786 << tmp785, const220 787: OpFAdd: FloatVector3: tmp787 << tmp772, tmp786 790: OpLoad: FloatVector3: tmp790 << light 791: OpExtInst(Distance): Float: tmp791 << tmp787, tmp790 OpStore: : tmp787 >> param794 OpStore: : tmp781 >> param796 OpStore: : tmp791 >> param798 801: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param794, param796, param798, param800) 802: OpLoad: Float: tmp802 << param800 804: OpFOrdGreaterThan: Bool: tmp804 << trace(vf3;vf3;f1;f1;, tmp791 805: OpSelect: Float: tmp805 << tmp804, const117, const92 OpStore: : tmp805 >> shadow 808: OpFDiv: Float: tmp808 << tmp802, const807 809: OpExtInst(Sqrt): Float: tmp809 << tmp808 810: OpFSub: Float: tmp810 << const117, tmp809 811: OpLoad: Float: tmp811 << shadow 812: OpFMul: Float: tmp812 << tmp811, tmp810 OpStore: : tmp812 >> shadow 817: OpDot: Float: tmp817 << tmp781, getNormal(vf3; 818: OpExtInst(FMax): Float: tmp818 << const92, tmp817 821: OpFNegate: FloatVector3: tmp821 << tmp781 823: OpExtInst(Reflect): FloatVector3: tmp823 << tmp821, getNormal(vf3; 824: OpLoad: FloatVector3: tmp824 << rd 825: OpFNegate: FloatVector3: tmp825 << tmp824 826: OpDot: Float: tmp826 << tmp823, tmp825 827: OpExtInst(FMax): Float: tmp827 << const92, tmp826 829: OpExtInst(Pow): Float: tmp829 << tmp827, const828 OpStore: : tmp772 >> param831 OpStore: : getNormal(vf3; >> param833 835: OpFunctionCall: Float: calculateAO(vf3;vf3;(param831, param833) OpStore: : tmp772 >> param837 839: OpFunctionCall: FloatVector3: _texture(vf3;(param837) 840: OpVectorTimesScalar: FloatVector3: tmp840 << _texture(vf3;, calculateAO(vf3;vf3; 844: OpFAdd: Float: tmp844 << tmp829, tmp818 845: OpLoad: Float: tmp845 << shadow 846: OpFMul: Float: tmp846 << tmp844, tmp845 847: OpFAdd: Float: tmp847 << const363, tmp846 848: OpVectorTimesScalar: FloatVector3: tmp848 << tmp840, tmp847 849: OpLoad: FloatVector4: tmp849 << fragColor 850: OpVectorShuffle: FloatVector4: tmp850 << tmp849, tmp848, 4, 5, 6, 3 OpStore: : tmp850 >> fragColor 852: OpFDiv: Float: tmp852 << tmp766, const807 853: OpExtInst(Sqrt): Float: tmp853 << tmp852 854: OpLoad: FloatVector4: tmp854 << fragColor 855: OpVectorTimesScalar: FloatVector4: tmp855 << tmp854, tmp853 OpStore: : tmp855 >> fragColor 856: OpLoad: FloatVector4: tmp856 << fragColor 860: OpFMul: Float: tmp860 << trace(vf3;vf3;f1;f1;, trace(vf3;vf3;f1;f1; 862: OpFMul: Float: tmp862 << tmp860, const861 863: OpExtInst(FClamp): Float: tmp863 << tmp862, const92, const117 864: OpCompositeConstruct: FloatVector4: tmp864 << tmp863, tmp863, tmp863, tmp863 865: OpExtInst(FMix): FloatVector4: tmp865 << tmp856, const857, tmp864 OpStore: : tmp865 >> fragColor 866: OpLoad: FloatVector4: tmp866 << fragColor 869: OpExtInst(Pow): FloatVector4: tmp869 << tmp866, const868 OpStore: : tmp869 >> fragColor OpReturn: Generating the compiled code... Intermediate disassembly (pre optimization): Program Type: Fragment Special Input Variables: offset: unset, size: 16, FloatVector4 gl_FragCoord BuiltIn(FragCoord) Textures: offset: 0, size: 4, Float iChannel0 offset: 1, size: 4, Float iChannel1 offset: 2, size: 4, Float iChannel2 offset: 3, size: 4, Float iChannel3 Output Variables: offset: 0, size: 16, FloatVector4 finalColor Uniform Constants: offset: 0, size: 12, FloatVector3 iResolution offset: 12, size: 4, Float iTime offset: 16, size: 16, FloatVector4 iMouse offset: 32, size: 16, FloatVector4 iDate offset: 48, size: 4, Float iFrame offset: 52, size: 48, FloatVector3 iChannelResolution[4] Private Global Variables: offset: unset, size: 4, Float _twist Constants: Float const92: 0 Float const95: 0.0091239 Float const96: 0.00231233 Float const97: 0.00532234 FloatVector3 const98: {0.0091239, 0.00231233, 0.00532234} Float const101: 111112 FloatVector3 const112: {0, 0, 0} Float const117: 1 FloatVector3 const118: {0, 1, 0} FloatVector3 const123: {1, 0, 0} FloatVector3 const128: {1, 1, 0} UInt32 const139: 1 UInt32 const146: 0 FloatVector3 const157: {0, 0, 1} FloatVector3 const162: {0, 1, 1} FloatVector3 const167: {1, 0, 1} FloatVector3 const172: {1, 1, 1} UInt32 const198: 2 Int32 const210: 0 Int32 const217: 5 Float const220: 10 Float const227: 2 Int32 const234: 1 Float const275: 0.5 Float const333: 0.7 FloatVector2 const334: {0.7, 1} Float const355: 0.15 Float const360: 0.75 FloatVector2 const361: {0, 0.75} Float const363: 0.25 Float const369: 0.375 FloatVector2 const370: {0, 0.375} FloatVector2 const372: {0.25, 0.375} Float const386: 0.35 FloatVector2 const387: {0, 0.35} Float const389: 0.45 Float const390: 0.3 FloatVector2 const391: {0.45, 0.3} FloatVector2 const401: {0.35, 0} Float const403: 0.075 Float const417: 0.6 FloatVector2 const418: {0.6, 0.5} Float const420: 0.4 FloatVector2 const421: {0.6, 0.4} Float const434: 0.8 Int32 const451: 100 Float const467: 1e-05 Float const482: 0.0001 FloatVector2 const483: {0.0001, 0} Float const536: 5 Float const606: 0.1 Float const607: 0.9 Float const617: 20 FloatVector3 const618: {5, 20, 5} FloatVector3 const622: {1, 0.7, 0.4} FloatVector3 const626: {2, 10, 2} FloatVector3 const630: {1, 0.8, 0.5} Float const675: 3.14159 Float const685: 1.5 Float const807: 100 Float const828: 8 FloatVector4 const857: {0.9, 0.8, 0.7, 1} Float const861: 0.03 Float const867: 0.454545 FloatVector4 const868: {0.454545, 0.454545, 0.454545, 0.454545} UInt32 const886: 4 Function Local Variables: offset: unset, size: 16, FloatVector4 main.param873 offset: unset, size: 8, FloatVector2 main.param874 offset: unset, size: 16, FloatVector4 main.fragColor offset: unset, size: 8, FloatVector2 main.fragCoord offset: unset, size: 12, FloatVector3 main.uv offset: unset, size: 12, FloatVector3 hash(vf3;.uv offset: unset, size: 12, FloatVector3 noise(vf3;.param114 offset: unset, size: 12, FloatVector3 noise(vf3;.param120 offset: unset, size: 12, FloatVector3 noise(vf3;.param125 offset: unset, size: 12, FloatVector3 noise(vf3;.param130 offset: unset, size: 12, FloatVector3 noise(vf3;.param159 offset: unset, size: 12, FloatVector3 noise(vf3;.param164 offset: unset, size: 12, FloatVector3 noise(vf3;.param169 offset: unset, size: 12, FloatVector3 noise(vf3;.param174 offset: unset, size: 12, FloatVector3 noise(vf3;.uv offset: unset, size: 4, Float fbm(vf3;.f offset: unset, size: 4, Float fbm(vf3;.r offset: unset, size: 4, Int32 fbm(vf3;.i offset: unset, size: 12, FloatVector3 fbm(vf3;.param225 offset: unset, size: 8, FloatVector2 fbm(vf3;.p offset: unset, size: 4, Float fbm(vf3;.angel offset: unset, size: 12, FloatVector3 tRotate(vf2;f1;.p offset: unset, size: 4, Float tRotate(vf2;f1;.a offset: unset, size: 8, FloatVector2 tTwist(vf3;f1;.param264 offset: unset, size: 4, Float tTwist(vf3;f1;.param267 offset: unset, size: 8, FloatVector2 tTwist(vf3;f1;.p offset: unset, size: 8, FloatVector2 tTwist(vf3;f1;.r offset: unset, size: 8, FloatVector2 tRepeat2(vf2;vf2;.p offset: unset, size: 8, FloatVector2 tRepeat2(vf2;vf2;.r offset: unset, size: 8, FloatVector2 sdRect(vf2;vf2;.p offset: unset, size: 4, Float sdRect(vf2;vf2;.r offset: unset, size: 4, Float sdCircle(vf2;f1;.a offset: unset, size: 4, Float sdCircle(vf2;f1;.b offset: unset, size: 4, Float opU(f1;f1;.a offset: unset, size: 4, Float opU(f1;f1;.b offset: unset, size: 12, FloatVector3 opS(f1;f1;.p offset: unset, size: 12, FloatVector3 map(vf3;.param327 offset: unset, size: 4, Float map(vf3;.param329 offset: unset, size: 8, FloatVector2 map(vf3;.param335 offset: unset, size: 8, FloatVector2 map(vf3;.param338 offset: unset, size: 4, Float map(vf3;.d offset: unset, size: 8, FloatVector2 map(vf3;.param364 offset: unset, size: 4, Float map(vf3;.param365 offset: unset, size: 8, FloatVector2 map(vf3;.param373 offset: unset, size: 8, FloatVector2 map(vf3;.param374 offset: unset, size: 4, Float map(vf3;.param376 offset: unset, size: 4, Float map(vf3;.param377 offset: unset, size: 4, Float map(vf3;.param379 offset: unset, size: 4, Float map(vf3;.param381 offset: unset, size: 8, FloatVector2 map(vf3;.param392 offset: unset, size: 8, FloatVector2 map(vf3;.param393 offset: unset, size: 4, Float map(vf3;.param395 offset: unset, size: 4, Float map(vf3;.param397 offset: unset, size: 8, FloatVector2 map(vf3;.param404 offset: unset, size: 4, Float map(vf3;.param405 offset: unset, size: 4, Float map(vf3;.param407 offset: unset, size: 4, Float map(vf3;.param409 offset: unset, size: 8, FloatVector2 map(vf3;.param422 offset: unset, size: 8, FloatVector2 map(vf3;.param423 offset: unset, size: 4, Float map(vf3;.param425 offset: unset, size: 4, Float map(vf3;.param427 offset: unset, size: 4, Float map(vf3;.param436 offset: unset, size: 4, Float map(vf3;.param438 offset: unset, size: 12, FloatVector3 map(vf3;.ro offset: unset, size: 12, FloatVector3 map(vf3;.rd offset: unset, size: 4, Float map(vf3;.maxDist offset: unset, size: 4, Float map(vf3;.steps offset: unset, size: 4, Float trace(vf3;vf3;f1;f1;.total offset: unset, size: 4, Int32 trace(vf3;vf3;f1;f1;.i offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param461 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.p offset: unset, size: 12, FloatVector3 getNormal(vf3;.param488 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param494 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param501 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param507 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param514 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param520 offset: unset, size: 12, FloatVector3 getNormal(vf3;.p offset: unset, size: 12, FloatVector3 getNormal(vf3;.n offset: unset, size: 4, Float calculateAO(vf3;vf3;.r offset: unset, size: 4, Float calculateAO(vf3;vf3;.w offset: unset, size: 4, Float calculateAO(vf3;vf3;.i offset: unset, size: 12, FloatVector3 calculateAO(vf3;vf3;.param549 offset: unset, size: 12, FloatVector3 calculateAO(vf3;vf3;.p offset: unset, size: 8, FloatVector2 isWall(vf3;.param569 offset: unset, size: 8, FloatVector2 isWall(vf3;.param572 offset: unset, size: 12, FloatVector3 isWall(vf3;.p offset: unset, size: 12, FloatVector3 _texture(vf3;.param588 offset: unset, size: 4, Float _texture(vf3;.param590 offset: unset, size: 12, FloatVector3 _texture(vf3;.param596 offset: unset, size: 12, FloatVector3 _texture(vf3;.t offset: unset, size: 4, Float _texture(vf3;.var601 offset: unset, size: 12, FloatVector3 _texture(vf3;.param610 offset: unset, size: 12, FloatVector3 _texture(vf3;.param620 offset: unset, size: 12, FloatVector3 _texture(vf3;.param628 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.uv offset: unset, size: 4, Float mainImage(vf4;vf2;.time offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.ro offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.rd offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.light offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param710 offset: unset, size: 4, Float mainImage(vf4;vf2;.param713 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param723 offset: unset, size: 4, Float mainImage(vf4;vf2;.param726 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param736 offset: unset, size: 4, Float mainImage(vf4;vf2;.param739 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param749 offset: unset, size: 4, Float mainImage(vf4;vf2;.param752 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param759 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param761 offset: unset, size: 4, Float mainImage(vf4;vf2;.param763 offset: unset, size: 4, Float mainImage(vf4;vf2;.param764 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param774 offset: unset, size: 4, Float mainImage(vf4;vf2;.shadow offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param794 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param796 offset: unset, size: 4, Float mainImage(vf4;vf2;.param798 offset: unset, size: 4, Float mainImage(vf4;vf2;.param800 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param831 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param833 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param837 Instructions: V_SUB_F32 vDst(VGPR14) src0(SGPR2) src1(VGPR14) // VOP2 # Void main() Function: Void main() # lb5 Label: lb5 # OpStore: : const92 >> _twist V_MOV_B32 vDst(VGPR25) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR24) src0(VGPR25) # 875: OpLoad: FloatVector4: tmp875 << gl_FragCoord V_MOV_B32 vDst(VGPR26) src0(VGPR13) V_MOV_B32 vDst(VGPR27) src0(VGPR14) V_MOV_B32 vDst(VGPR28) src0(VGPR15) V_MOV_B32 vDst(VGPR29) src0(VGPR16) # 876: OpVectorShuffle: FloatVector2: tmp876 << tmp875, tmp875, 0, 1 V_MOV_B32 vDst(VGPR30) src0(VGPR26) V_MOV_B32 vDst(VGPR31) src0(VGPR27) # OpStore: : tmp876 >> param874 V_MOV_B32 vDst(VGPR22) src0(VGPR30) V_MOV_B32 vDst(VGPR23) src0(VGPR31) # 877: OpFunctionCall: Void: mainImage(vf4;vf2;(param873, param874) S_ADD_U32 sDst(SGPR12) src0(LITERAL_CONST) src1(0) const: 0x12 # VGPR[18:21] S_ADD_U32 sDst(SGPR13) src0(LITERAL_CONST) src1(0) const: 0x16 # VGPR[22:23] S_MOV_B64 sDst(SGPR14) src0(EXEC) # Indirect branch to mainImage(vf4;vf2;: ??? S_GETPC_B64 sDst(SGPR10) src0(SGPR10) S_ADD_U32 sDst(SGPR10) src0(SGPR10) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR11) src0(SGPR11) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR10) src0(SGPR10) S_MOV_B64 sDst(EXEC) src0(SGPR14) # .lbl0 # 878: OpLoad: FloatVector4: tmp878 << param873 # OpStore: : tmp878 >> finalColor V_MOV_B32 vDst(VGPR32) src0(VGPR18) V_MOV_B32 vDst(VGPR33) src0(VGPR19) V_MOV_B32 vDst(VGPR34) src0(VGPR20) V_MOV_B32 vDst(VGPR35) src0(VGPR21) # OpReturn: S_ENDPGM 0 # Float hash(vf3;(FloatVector3* uv) Function: Float hash(vf3;() S_MOV_B64 sDst(SGPR20) src0(EXEC) # lb12 Label: lb12 # 94: OpLoad: FloatVector3: tmp94 << uv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR36) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR37) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR38) src0(VGPR2) # 99: OpDot: Float: tmp99 << tmp94, const98 V_MOV_B32 vDst(VGPR39) src0(LITERAL_CONST) const: 0x3c157c67 V_MOV_B32 vDst(VGPR40) src0(LITERAL_CONST) const: 0x3b178a76 V_MOV_B32 vDst(VGPR41) src0(LITERAL_CONST) const: 0x3bae6706 V_MUL_F32 vDst(VGPR42) src0(VGPR36) src1(VGPR39) // VOP2 V_MAC_F32 vDst(VGPR42) src0(VGPR37) src1(VGPR40) // VOP2 V_MAC_F32 vDst(VGPR42) src0(VGPR38) src1(VGPR41) // VOP2 # 100: OpExtInst(Sin): Float: tmp100 << tmp99 V_MUL_F32 vDst(VGPR43) src0(LITERAL_CONST) src1(VGPR42) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR43) src0(VGPR43) V_SIN_F32 vDst(VGPR43) src0(VGPR43) # 102: OpFMul: Float: tmp102 << tmp100, const101 V_MOV_B32 vDst(VGPR44) src0(LITERAL_CONST) const: 0x47d903c6 V_MUL_F32 vDst(VGPR45) src0(VGPR43) src1(VGPR44) // VOP2 # 103: OpExtInst(Fract): Float: tmp103 << tmp102 V_FRACT_F32 vDst(VGPR46) src0(VGPR45) # OpReturnValue: : << tmp103 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR46) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # Float noise(vf3;(FloatVector3* uv) Function: Float noise(vf3;() S_MOV_B64 sDst(SGPR26) src0(EXEC) # lb15 Label: lb15 # 108: OpLoad: FloatVector3: tmp108 << uv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR71) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR72) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR73) src0(VGPR2) # 109: OpExtInst(Floor): FloatVector3: tmp109 << tmp108 V_FLOOR_F32 vDst(VGPR74) src0(VGPR71) V_FLOOR_F32 vDst(VGPR75) src0(VGPR72) V_FLOOR_F32 vDst(VGPR76) src0(VGPR73) # 113: OpFAdd: FloatVector3: tmp113 << tmp109, const112 V_MOV_B32 vDst(VGPR77) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR78) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR79) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR80) src0(VGPR74) src1(VGPR77) // VOP2 V_ADD_F32 vDst(VGPR81) src0(VGPR75) src1(VGPR78) // VOP2 V_ADD_F32 vDst(VGPR82) src0(VGPR76) src1(VGPR79) // VOP2 # OpStore: : tmp113 >> param114 V_MOV_B32 vDst(VGPR47) src0(VGPR80) V_MOV_B32 vDst(VGPR48) src0(VGPR81) V_MOV_B32 vDst(VGPR49) src0(VGPR82) # 115: OpFunctionCall: Float: hash(vf3;(param114) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x2f # VGPR[47:49] S_MOV_B64 sDst(SGPR28) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x53 # VGPR83 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR28) # .lbl1 # 119: OpFAdd: FloatVector3: tmp119 << tmp109, const118 V_MOV_B32 vDst(VGPR84) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR85) src0(1_0_F) V_MOV_B32 vDst(VGPR86) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR87) src0(VGPR74) src1(VGPR84) // VOP2 V_ADD_F32 vDst(VGPR88) src0(VGPR75) src1(VGPR85) // VOP2 V_ADD_F32 vDst(VGPR89) src0(VGPR76) src1(VGPR86) // VOP2 # OpStore: : tmp119 >> param120 V_MOV_B32 vDst(VGPR50) src0(VGPR87) V_MOV_B32 vDst(VGPR51) src0(VGPR88) V_MOV_B32 vDst(VGPR52) src0(VGPR89) # 121: OpFunctionCall: Float: hash(vf3;(param120) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x32 # VGPR[50:52] S_MOV_B64 sDst(SGPR30) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x5a # VGPR90 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR30) # .lbl2 # 124: OpFAdd: FloatVector3: tmp124 << tmp109, const123 V_MOV_B32 vDst(VGPR91) src0(1_0_F) V_MOV_B32 vDst(VGPR92) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR93) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR94) src0(VGPR74) src1(VGPR91) // VOP2 V_ADD_F32 vDst(VGPR95) src0(VGPR75) src1(VGPR92) // VOP2 V_ADD_F32 vDst(VGPR96) src0(VGPR76) src1(VGPR93) // VOP2 # OpStore: : tmp124 >> param125 V_MOV_B32 vDst(VGPR53) src0(VGPR94) V_MOV_B32 vDst(VGPR54) src0(VGPR95) V_MOV_B32 vDst(VGPR55) src0(VGPR96) # 126: OpFunctionCall: Float: hash(vf3;(param125) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x35 # VGPR[53:55] S_MOV_B64 sDst(SGPR32) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x61 # VGPR97 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR32) # .lbl3 # 129: OpFAdd: FloatVector3: tmp129 << tmp109, const128 V_MOV_B32 vDst(VGPR98) src0(1_0_F) V_MOV_B32 vDst(VGPR99) src0(1_0_F) V_MOV_B32 vDst(VGPR100) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR101) src0(VGPR74) src1(VGPR98) // VOP2 V_ADD_F32 vDst(VGPR102) src0(VGPR75) src1(VGPR99) // VOP2 V_ADD_F32 vDst(VGPR103) src0(VGPR76) src1(VGPR100) // VOP2 # OpStore: : tmp129 >> param130 V_MOV_B32 vDst(VGPR56) src0(VGPR101) V_MOV_B32 vDst(VGPR57) src0(VGPR102) V_MOV_B32 vDst(VGPR58) src0(VGPR103) # 131: OpFunctionCall: Float: hash(vf3;(param130) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x38 # VGPR[56:58] S_MOV_B64 sDst(SGPR34) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x68 # VGPR104 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR34) # .lbl4 # 132: OpCompositeConstruct: FloatVector4: tmp132 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; V_MOV_B32 vDst(VGPR105) src0(VGPR83) V_MOV_B32 vDst(VGPR106) src0(VGPR90) V_MOV_B32 vDst(VGPR107) src0(VGPR97) V_MOV_B32 vDst(VGPR108) src0(VGPR104) # 135: OpVectorShuffle: FloatVector2: tmp135 << tmp132, tmp132, 0, 2 V_MOV_B32 vDst(VGPR109) src0(VGPR105) V_MOV_B32 vDst(VGPR110) src0(VGPR107) # 137: OpVectorShuffle: FloatVector2: tmp137 << tmp132, tmp132, 1, 3 V_MOV_B32 vDst(VGPR111) src0(VGPR106) V_MOV_B32 vDst(VGPR112) src0(VGPR108) # 140: OpAccessChain: Float*: uv[1] # 141: OpLoad: Float: tmp141 << uv[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR113) src0(VGPR1) # 142: OpExtInst(Fract): Float: tmp142 << tmp141 V_FRACT_F32 vDst(VGPR114) src0(VGPR113) # 143: OpCompositeConstruct: FloatVector2: tmp143 << tmp142, tmp142 V_MOV_B32 vDst(VGPR115) src0(VGPR114) V_MOV_B32 vDst(VGPR116) src0(VGPR114) # 144: OpExtInst(FMix): FloatVector2: tmp144 << tmp135, tmp137, tmp143 V_SUBREV_F32 vDst(VGPR117) src0(VGPR115) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR117) src0(VGPR109) src1(VGPR117) // VOP2 V_MAD_F32 vDst(VGPR117) src0(VGPR111) src1(VGPR115) src2(VGPR117) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR118) src0(VGPR116) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR118) src0(VGPR110) src1(VGPR118) // VOP2 V_MAD_F32 vDst(VGPR118) src0(VGPR112) src1(VGPR116) src2(VGPR118) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 147: OpAccessChain: Float*: axis0[0] # 148: OpCompositeExtract: Float: tmp148 << tmp144, 0 V_MOV_B32 vDst(VGPR119) src0(VGPR117) # 149: OpAccessChain: Float*: axis0[1] # 150: OpCompositeExtract: Float: tmp150 << tmp144, 1 V_MOV_B32 vDst(VGPR120) src0(VGPR118) # 151: OpAccessChain: Float*: uv[0] # 152: OpLoad: Float: tmp152 << uv[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR121) src0(VGPR0) # 153: OpExtInst(Fract): Float: tmp153 << tmp152 V_FRACT_F32 vDst(VGPR122) src0(VGPR121) # 154: OpExtInst(FMix): Float: tmp154 << tmp148, tmp150, tmp153 V_SUBREV_F32 vDst(VGPR123) src0(VGPR122) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR123) src0(VGPR119) src1(VGPR123) // VOP2 V_MAD_F32 vDst(VGPR123) src0(VGPR120) src1(VGPR122) src2(VGPR123) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 158: OpFAdd: FloatVector3: tmp158 << tmp109, const157 V_MOV_B32 vDst(VGPR124) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR125) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR126) src0(1_0_F) V_ADD_F32 vDst(VGPR127) src0(VGPR74) src1(VGPR124) // VOP2 V_ADD_F32 vDst(VGPR128) src0(VGPR75) src1(VGPR125) // VOP2 V_ADD_F32 vDst(VGPR129) src0(VGPR76) src1(VGPR126) // VOP2 # OpStore: : tmp158 >> param159 V_MOV_B32 vDst(VGPR59) src0(VGPR127) V_MOV_B32 vDst(VGPR60) src0(VGPR128) V_MOV_B32 vDst(VGPR61) src0(VGPR129) # 160: OpFunctionCall: Float: hash(vf3;(param159) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x3b # VGPR[59:61] S_MOV_B64 sDst(SGPR36) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x82 # VGPR130 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR36) # .lbl5 # 163: OpFAdd: FloatVector3: tmp163 << tmp109, const162 V_MOV_B32 vDst(VGPR131) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR132) src0(1_0_F) V_MOV_B32 vDst(VGPR133) src0(1_0_F) V_ADD_F32 vDst(VGPR134) src0(VGPR74) src1(VGPR131) // VOP2 V_ADD_F32 vDst(VGPR135) src0(VGPR75) src1(VGPR132) // VOP2 V_ADD_F32 vDst(VGPR136) src0(VGPR76) src1(VGPR133) // VOP2 # OpStore: : tmp163 >> param164 V_MOV_B32 vDst(VGPR62) src0(VGPR134) V_MOV_B32 vDst(VGPR63) src0(VGPR135) V_MOV_B32 vDst(VGPR64) src0(VGPR136) # 165: OpFunctionCall: Float: hash(vf3;(param164) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x3e # VGPR[62:64] S_MOV_B64 sDst(SGPR38) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x89 # VGPR137 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR38) # .lbl6 # 168: OpFAdd: FloatVector3: tmp168 << tmp109, const167 V_MOV_B32 vDst(VGPR138) src0(1_0_F) V_MOV_B32 vDst(VGPR139) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR140) src0(1_0_F) V_ADD_F32 vDst(VGPR141) src0(VGPR74) src1(VGPR138) // VOP2 V_ADD_F32 vDst(VGPR142) src0(VGPR75) src1(VGPR139) // VOP2 V_ADD_F32 vDst(VGPR143) src0(VGPR76) src1(VGPR140) // VOP2 # OpStore: : tmp168 >> param169 V_MOV_B32 vDst(VGPR65) src0(VGPR141) V_MOV_B32 vDst(VGPR66) src0(VGPR142) V_MOV_B32 vDst(VGPR67) src0(VGPR143) # 170: OpFunctionCall: Float: hash(vf3;(param169) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x41 # VGPR[65:67] S_MOV_B64 sDst(SGPR40) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x90 # VGPR144 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR40) # .lbl7 # 173: OpFAdd: FloatVector3: tmp173 << tmp109, const172 V_MOV_B32 vDst(VGPR145) src0(1_0_F) V_MOV_B32 vDst(VGPR146) src0(1_0_F) V_MOV_B32 vDst(VGPR147) src0(1_0_F) V_ADD_F32 vDst(VGPR148) src0(VGPR74) src1(VGPR145) // VOP2 V_ADD_F32 vDst(VGPR149) src0(VGPR75) src1(VGPR146) // VOP2 V_ADD_F32 vDst(VGPR150) src0(VGPR76) src1(VGPR147) // VOP2 # OpStore: : tmp173 >> param174 V_MOV_B32 vDst(VGPR68) src0(VGPR148) V_MOV_B32 vDst(VGPR69) src0(VGPR149) V_MOV_B32 vDst(VGPR70) src0(VGPR150) # 175: OpFunctionCall: Float: hash(vf3;(param174) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x44 # VGPR[68:70] S_MOV_B64 sDst(SGPR42) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x97 # VGPR151 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR42) # .lbl8 # 176: OpCompositeConstruct: FloatVector4: tmp176 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; V_MOV_B32 vDst(VGPR152) src0(VGPR130) V_MOV_B32 vDst(VGPR153) src0(VGPR137) V_MOV_B32 vDst(VGPR154) src0(VGPR144) V_MOV_B32 vDst(VGPR155) src0(VGPR151) # 179: OpVectorShuffle: FloatVector2: tmp179 << tmp176, tmp176, 0, 2 V_MOV_B32 vDst(VGPR156) src0(VGPR152) V_MOV_B32 vDst(VGPR157) src0(VGPR154) # 181: OpVectorShuffle: FloatVector2: tmp181 << tmp176, tmp176, 1, 3 V_MOV_B32 vDst(VGPR158) src0(VGPR153) V_MOV_B32 vDst(VGPR159) src0(VGPR155) # 182: OpAccessChain: Float*: uv[1] # 183: OpLoad: Float: tmp183 << uv[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR160) src0(VGPR1) # 184: OpExtInst(Fract): Float: tmp184 << tmp183 V_FRACT_F32 vDst(VGPR161) src0(VGPR160) # 185: OpCompositeConstruct: FloatVector2: tmp185 << tmp184, tmp184 V_MOV_B32 vDst(VGPR162) src0(VGPR161) V_MOV_B32 vDst(VGPR163) src0(VGPR161) # 186: OpExtInst(FMix): FloatVector2: tmp186 << tmp179, tmp181, tmp185 V_SUBREV_F32 vDst(VGPR164) src0(VGPR162) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR164) src0(VGPR156) src1(VGPR164) // VOP2 V_MAD_F32 vDst(VGPR164) src0(VGPR158) src1(VGPR162) src2(VGPR164) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR165) src0(VGPR163) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR165) src0(VGPR157) src1(VGPR165) // VOP2 V_MAD_F32 vDst(VGPR165) src0(VGPR159) src1(VGPR163) src2(VGPR165) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 188: OpAccessChain: Float*: axis1[0] # 189: OpCompositeExtract: Float: tmp189 << tmp186, 0 V_MOV_B32 vDst(VGPR166) src0(VGPR164) # 190: OpAccessChain: Float*: axis1[1] # 191: OpCompositeExtract: Float: tmp191 << tmp186, 1 V_MOV_B32 vDst(VGPR167) src0(VGPR165) # 192: OpAccessChain: Float*: uv[0] # 193: OpLoad: Float: tmp193 << uv[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR168) src0(VGPR0) # 194: OpExtInst(Fract): Float: tmp194 << tmp193 V_FRACT_F32 vDst(VGPR169) src0(VGPR168) # 195: OpExtInst(FMix): Float: tmp195 << tmp189, tmp191, tmp194 V_SUBREV_F32 vDst(VGPR170) src0(VGPR169) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR170) src0(VGPR166) src1(VGPR170) // VOP2 V_MAD_F32 vDst(VGPR170) src0(VGPR167) src1(VGPR169) src2(VGPR170) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 199: OpAccessChain: Float*: uv[2] # 200: OpLoad: Float: tmp200 << uv[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR2) # 201: OpExtInst(Fract): Float: tmp201 << tmp200 V_FRACT_F32 vDst(VGPR172) src0(VGPR171) # 202: OpExtInst(FMix): Float: tmp202 << tmp154, tmp195, tmp201 V_SUBREV_F32 vDst(VGPR173) src0(VGPR172) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR173) src0(VGPR123) src1(VGPR173) // VOP2 V_MAD_F32 vDst(VGPR173) src0(VGPR170) src1(VGPR172) src2(VGPR173) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp202 S_MOV_B32 sDst(M0) src0(SGPR24) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR173) S_SETPC_B64 sDst(SGPR22) src0(SGPR22) # Float fbm(vf3;(FloatVector3* uv) Function: Float fbm(vf3;() S_MOV_B64 sDst(SGPR48) src0(EXEC) # lb18 Label: lb18 # OpStore: : const92 >> f V_MOV_B32 vDst(VGPR180) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR174) src0(VGPR180) # OpStore: : const117 >> r V_MOV_B32 vDst(VGPR175) src0(1_0_F) # OpStore: : const210 >> i V_MOV_B32 vDst(VGPR176) src0(0) # OpBranch: to lb211 S_BRANCH ??? lb211 # lb211 Label: lb211 # OpLoopMerge: (merge: lb213, continue: lb214) # CF Block: Merge: lb213, Continue: lb214 S_MOV_B64 sDst(SGPR50) src0(EXEC) S_MOV_B64 sDst(SGPR52) src0(EXEC) S_MOV_B64 sDst(SGPR54) src0(EXEC) Label: lb211Loop # OpBranch: to lb215 S_BRANCH ??? lb215 # lb215 Label: lb215 # 216: OpLoad: Int: tmp216 << i Decorators: RelaxedPrecision # 218: OpSLessThan: Bool: tmp218 << tmp216, const217 V_MOV_B32 vDst(VGPR181) src0(5_INT) V_CMP_LT_I32 dst(SGPR56) src0(VGPR176) src1(VGPR181) // VOP3a # OpBranchConditional: if(tmp218) then branch to lb212, else branch to lb213 # CF Block: Cond Branch: true: lb212, false: lb213 S_AND_B64 sDst(EXEC) src0(SGPR56) src1(EXEC) S_CBRANCH_EXECZ ??? lb213 S_BRANCH ??? lb212 # lb212 Label: lb212 # 219: OpLoad: FloatVector3: tmp219 << uv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR47) const: 0x0 V_MOVRELS_B32 vDst(VGPR182) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR183) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR184) src0(VGPR2) # 221: OpCompositeConstruct: FloatVector3: tmp221 << const220, const220, const220 V_MOV_B32 vDst(VGPR188) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR185) src0(VGPR188) V_MOV_B32 vDst(VGPR189) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR186) src0(VGPR189) V_MOV_B32 vDst(VGPR190) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR187) src0(VGPR190) # 222: OpFAdd: FloatVector3: tmp222 << tmp219, tmp221 V_ADD_F32 vDst(VGPR191) src0(VGPR182) src1(VGPR185) // VOP2 V_ADD_F32 vDst(VGPR192) src0(VGPR183) src1(VGPR186) // VOP2 V_ADD_F32 vDst(VGPR193) src0(VGPR184) src1(VGPR187) // VOP2 # 223: OpLoad: Float: tmp223 << r # 224: OpVectorTimesScalar: FloatVector3: tmp224 << tmp222, tmp223 V_MUL_F32 vDst(VGPR194) src0(VGPR175) src1(VGPR191) // VOP2 V_MUL_F32 vDst(VGPR195) src0(VGPR175) src1(VGPR192) // VOP2 V_MUL_F32 vDst(VGPR196) src0(VGPR175) src1(VGPR193) // VOP2 # OpStore: : tmp224 >> param225 V_MOV_B32 vDst(VGPR177) src0(VGPR194) V_MOV_B32 vDst(VGPR178) src0(VGPR195) V_MOV_B32 vDst(VGPR179) src0(VGPR196) # 226: OpFunctionCall: Float: noise(vf3;(param225) S_ADD_U32 sDst(SGPR25) src0(LITERAL_CONST) src1(0) const: 0xb1 # VGPR[177:179] S_MOV_B64 sDst(SGPR58) src0(EXEC) S_MOV_B32 sDst(SGPR24) src0(LITERAL_CONST) const: 0xc5 # VGPR197 # Indirect branch to noise(vf3;: ??? S_GETPC_B64 sDst(SGPR22) src0(SGPR22) S_ADD_U32 sDst(SGPR22) src0(SGPR22) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR23) src0(SGPR23) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR22) src0(SGPR22) S_MOV_B64 sDst(EXEC) src0(SGPR58) # .lbl9 # 228: OpLoad: Float: tmp228 << r # 229: OpFMul: Float: tmp229 << tmp228, const227 V_MOV_B32 vDst(VGPR198) src0(2_0_F) V_MUL_F32 vDst(VGPR199) src0(VGPR175) src1(VGPR198) // VOP2 # OpStore: : tmp229 >> r V_MOV_B32 vDst(VGPR175) src0(VGPR199) # 230: OpFDiv: Float: tmp230 << noise(vf3;, tmp229 V_RCP_F32 vDst(VGPR200) src0(VGPR199) V_MUL_F32 vDst(VGPR200) src0(VGPR197) src1(VGPR200) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR200) src0(VGPR200) src1(VGPR199) src2(VGPR197) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 231: OpLoad: Float: tmp231 << f # 232: OpFAdd: Float: tmp232 << tmp231, tmp230 V_ADD_F32 vDst(VGPR201) src0(VGPR174) src1(VGPR200) // VOP2 # OpStore: : tmp232 >> f V_MOV_B32 vDst(VGPR174) src0(VGPR201) # OpBranch: to lb214 S_BRANCH ??? lb214 # lb214 Label: lb214 # 233: OpLoad: Int: tmp233 << i Decorators: RelaxedPrecision # 235: OpIAdd: Int: tmp235 << tmp233, const234 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR202) src0(1_INT) V_ADD_I32 vDst(VGPR203) src0(VGPR176) src1(VGPR202) // VOP2 # OpStore: : tmp235 >> i V_MOV_B32 vDst(VGPR176) src0(VGPR203) # OpBranch: to lb211 S_BRANCH ??? lb211 # lb213 Label: lb213 # 236: OpLoad: Float: tmp236 << f # 237: OpLoad: Float: tmp237 << r # 238: OpFDiv: Float: tmp238 << const117, tmp237 V_RCP_F32 vDst(VGPR204) src0(VGPR175) V_MUL_F32 vDst(VGPR204) src0(1_0_F) src1(VGPR204) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR204) src0(VGPR204) src1(VGPR175) src2(1_0_F) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 239: OpFSub: Float: tmp239 << const117, tmp238 V_SUB_F32 vDst(VGPR205) src0(1_0_F) src1(VGPR204) // VOP2 # 240: OpFDiv: Float: tmp240 << tmp236, tmp239 V_RCP_F32 vDst(VGPR206) src0(VGPR205) V_MUL_F32 vDst(VGPR206) src0(VGPR174) src1(VGPR206) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR206) src0(VGPR206) src1(VGPR205) src2(VGPR174) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp240 S_MOV_B32 sDst(M0) src0(SGPR46) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR206) S_SETPC_B64 sDst(SGPR44) src0(SGPR44) # Void tRotate(vf2;f1;(FloatVector2* p, Float* angel) Function: Void tRotate(vf2;f1;(, Float fbm(vf3;.angel) S_MOV_B64 sDst(SGPR64) src0(EXEC) # lb26 Label: lb26 # 244: OpLoad: Float: tmp244 << angel S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR63) const: 0x0 V_MOVRELS_B32 vDst(VGPR207) src0(VGPR0) # 245: OpExtInst(Sin): Float: tmp245 << tmp244 V_MUL_F32 vDst(VGPR208) src0(LITERAL_CONST) src1(VGPR207) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR208) src0(VGPR208) V_SIN_F32 vDst(VGPR208) src0(VGPR208) # 247: OpLoad: Float: tmp247 << angel S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR63) const: 0x0 V_MOVRELS_B32 vDst(VGPR209) src0(VGPR0) # 248: OpExtInst(Cos): Float: tmp248 << tmp247 V_MUL_F32 vDst(VGPR210) src0(LITERAL_CONST) src1(VGPR209) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR210) src0(VGPR210) V_COS_F32 vDst(VGPR210) src0(VGPR210) # 251: OpFNegate: Float: tmp251 << tmp245 V_MUL_F32 vDst(VGPR211) src0(M1_0_F) src1(VGPR208) // VOP2 # 255: OpCompositeConstruct: FloatVector2: tmp255 << tmp248, tmp251 V_MOV_B32 vDst(VGPR212) src0(VGPR210) V_MOV_B32 vDst(VGPR213) src0(VGPR211) # 256: OpCompositeConstruct: FloatVector2: tmp256 << tmp245, tmp248 V_MOV_B32 vDst(VGPR214) src0(VGPR208) V_MOV_B32 vDst(VGPR215) src0(VGPR210) # 257: OpCompositeConstruct: FloatMatrix2x2: tmp257 << tmp255, tmp256 V_MOV_B32 vDst(VGPR216) src0(VGPR212) V_MOV_B32 vDst(VGPR217) src0(VGPR213) V_MOV_B32 vDst(VGPR218) src0(VGPR214) V_MOV_B32 vDst(VGPR219) src0(VGPR215) # 258: OpLoad: FloatVector2: tmp258 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR62) const: 0x0 V_MOVRELS_B32 vDst(VGPR220) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR221) src0(VGPR1) # 259: OpVectorTimesMatrix: FloatVector2: tmp259 << tmp258, tmp257 V_MUL_F32 vDst(VGPR222) src0(VGPR220) src1(VGPR216) // VOP2 V_MUL_F32 vDst(VGPR223) src0(VGPR220) src1(VGPR218) // VOP2 V_MAC_F32 vDst(VGPR222) src0(VGPR221) src1(VGPR217) // VOP2 V_MAC_F32 vDst(VGPR223) src0(VGPR221) src1(VGPR219) // VOP2 # OpStore: : tmp259 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR62) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR222) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR223) # OpReturn: S_SETPC_B64 sDst(SGPR60) src0(SGPR60) # Void tTwist(vf3;f1;(FloatVector3* p, Float* a) Function: Void tTwist(vf3;f1;(, Float tRotate(vf2;f1;.a) S_MOV_B64 sDst(SGPR70) src0(EXEC) # lb31 Label: lb31 # 260: OpAccessChain: Float*: p[2] # 261: OpLoad: Float: tmp261 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR68) const: 0x0 V_MOVRELS_B32 vDst(VGPR227) src0(VGPR2) # 262: OpLoad: Float: tmp262 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR69) const: 0x0 V_MOVRELS_B32 vDst(VGPR228) src0(VGPR0) # 263: OpFMul: Float: tmp263 << tmp261, tmp262 V_MUL_F32 vDst(VGPR229) src0(VGPR227) src1(VGPR228) // VOP2 # 265: OpLoad: FloatVector3: tmp265 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR68) const: 0x0 V_MOVRELS_B32 vDst(VGPR230) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR231) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR232) src0(VGPR2) # 266: OpVectorShuffle: FloatVector2: tmp266 << tmp265, tmp265, 0, 1 V_MOV_B32 vDst(VGPR233) src0(VGPR230) V_MOV_B32 vDst(VGPR234) src0(VGPR231) # OpStore: : tmp266 >> param264 V_MOV_B32 vDst(VGPR224) src0(VGPR233) V_MOV_B32 vDst(VGPR225) src0(VGPR234) # OpStore: : tmp263 >> param267 V_MOV_B32 vDst(VGPR226) src0(VGPR229) # 268: OpFunctionCall: Void: tRotate(vf2;f1;(param264, param267) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0xe0 # VGPR[224:225] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0xe2 # VGPR226 S_MOV_B64 sDst(SGPR72) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR72) # .lbl10 # 269: OpLoad: FloatVector2: tmp269 << param264 # 270: OpLoad: FloatVector3: tmp270 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR68) const: 0x0 V_MOVRELS_B32 vDst(VGPR235) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR236) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR237) src0(VGPR2) # 271: OpVectorShuffle: FloatVector3: tmp271 << tmp270, tmp269, 3, 4, 2 V_MOV_B32 vDst(VGPR238) src0(VGPR224) V_MOV_B32 vDst(VGPR239) src0(VGPR225) V_MOV_B32 vDst(VGPR240) src0(VGPR237) # OpStore: : tmp271 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR68) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR238) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR239) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR240) # OpReturn: S_SETPC_B64 sDst(SGPR66) src0(SGPR66) # FloatVector2 tRepeat2(vf2;vf2;(FloatVector2* p, FloatVector2* r) Function: FloatVector2 tRepeat2(vf2;vf2;(, FloatVector2 tTwist(vf3;f1;.r) S_MOV_B64 sDst(SGPR80) src0(EXEC) # lb36 Label: lb36 # 273: OpLoad: FloatVector2: tmp273 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELS_B32 vDst(VGPR241) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR242) src0(VGPR1) # 274: OpLoad: FloatVector2: tmp274 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR243) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR244) src0(VGPR1) # 276: OpVectorTimesScalar: FloatVector2: tmp276 << tmp274, const275 V_MOV_B32 vDst(VGPR247) src0(0_5_F) V_MUL_F32 vDst(VGPR245) src0(VGPR247) src1(VGPR243) // VOP2 V_MUL_F32 vDst(VGPR246) src0(VGPR247) src1(VGPR244) // VOP2 # 277: OpFAdd: FloatVector2: tmp277 << tmp273, tmp276 V_ADD_F32 vDst(VGPR248) src0(VGPR241) src1(VGPR245) // VOP2 V_ADD_F32 vDst(VGPR249) src0(VGPR242) src1(VGPR246) // VOP2 # 278: OpLoad: FloatVector2: tmp278 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR250) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR251) src0(VGPR1) # 279: OpFDiv: FloatVector2: tmp279 << tmp277, tmp278 V_RCP_F32 vDst(VGPR252) src0(VGPR250) V_RCP_F32 vDst(VGPR253) src0(VGPR251) V_MUL_F32 vDst(VGPR252) src0(VGPR248) src1(VGPR252) // VOP2 V_MUL_F32 vDst(VGPR253) src0(VGPR249) src1(VGPR253) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR252) src0(VGPR252) src1(VGPR250) src2(VGPR248) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR253) src0(VGPR253) src1(VGPR251) src2(VGPR249) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 280: OpExtInst(Floor): FloatVector2: tmp280 << tmp279 V_FLOOR_F32 vDst(VGPR254) src0(VGPR252) V_FLOOR_F32 vDst(VGPR255) src0(VGPR253) # 281: OpLoad: FloatVector2: tmp281 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) # 282: OpLoad: FloatVector2: tmp282 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR258) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR259) src0(VGPR1) # 283: OpVectorTimesScalar: FloatVector2: tmp283 << tmp282, const275 V_MOV_B32 vDst(VGPR262) src0(0_5_F) V_MUL_F32 vDst(VGPR260) src0(VGPR262) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR261) src0(VGPR262) src1(VGPR259) // VOP2 # 284: OpFAdd: FloatVector2: tmp284 << tmp281, tmp283 V_ADD_F32 vDst(VGPR263) src0(VGPR256) src1(VGPR260) // VOP2 V_ADD_F32 vDst(VGPR264) src0(VGPR257) src1(VGPR261) // VOP2 # 285: OpLoad: FloatVector2: tmp285 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR265) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR266) src0(VGPR1) # 286: OpFMod: FloatVector2: tmp286 << tmp284, tmp285 V_RCP_F32 vDst(VGPR267) src0(VGPR265) V_MUL_F32 vDst(VGPR267) src0(VGPR263) src1(VGPR267) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR267) src0(VGPR267) src1(VGPR265) src2(VGPR263) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR267) src0(VGPR267) V_RCP_F32 vDst(VGPR268) src0(VGPR266) V_MUL_F32 vDst(VGPR268) src0(VGPR264) src1(VGPR268) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR268) src0(VGPR268) src1(VGPR266) src2(VGPR264) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR268) src0(VGPR268) V_MAD_F32 vDst(VGPR267) src0(VGPR265) src1(VGPR267) src2(VGPR263) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR268) src0(VGPR266) src1(VGPR268) src2(VGPR264) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 287: OpLoad: FloatVector2: tmp287 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR269) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR270) src0(VGPR1) # 288: OpVectorTimesScalar: FloatVector2: tmp288 << tmp287, const275 V_MOV_B32 vDst(VGPR273) src0(0_5_F) V_MUL_F32 vDst(VGPR271) src0(VGPR273) src1(VGPR269) // VOP2 V_MUL_F32 vDst(VGPR272) src0(VGPR273) src1(VGPR270) // VOP2 # 289: OpFSub: FloatVector2: tmp289 << tmp286, tmp288 V_SUB_F32 vDst(VGPR274) src0(VGPR267) src1(VGPR271) // VOP2 V_SUB_F32 vDst(VGPR275) src0(VGPR268) src1(VGPR272) // VOP2 # OpStore: : tmp289 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR274) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR275) # OpReturnValue: : << tmp280 S_MOV_B32 sDst(M0) src0(SGPR76) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR254) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR255) S_SETPC_B64 sDst(SGPR74) src0(SGPR74) # Float sdRect(vf2;vf2;(FloatVector2* p, FloatVector2* r) Function: Float sdRect(vf2;vf2;(, FloatVector2 tRepeat2(vf2;vf2;.r) S_MOV_B64 sDst(SGPR88) src0(EXEC) # lb41 Label: lb41 # 293: OpLoad: FloatVector2: tmp293 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR276) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR277) src0(VGPR1) # 294: OpExtInst(FAbs): FloatVector2: tmp294 << tmp293 V_ADD_F32 vDst(VGPR278) src0(VGPR276) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR279) src0(VGPR277) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 295: OpLoad: FloatVector2: tmp295 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR86) const: 0x0 V_MOVRELS_B32 vDst(VGPR280) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR281) src0(VGPR1) # 296: OpFSub: FloatVector2: tmp296 << tmp294, tmp295 V_SUB_F32 vDst(VGPR282) src0(VGPR278) src1(VGPR280) // VOP2 V_SUB_F32 vDst(VGPR283) src0(VGPR279) src1(VGPR281) // VOP2 # OpStore: : tmp296 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR282) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR283) # 297: OpAccessChain: Float*: p[0] # 298: OpLoad: Float: tmp298 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR284) src0(VGPR0) # 299: OpAccessChain: Float*: p[1] # 300: OpLoad: Float: tmp300 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR285) src0(VGPR1) # 301: OpExtInst(FMax): Float: tmp301 << tmp298, tmp300 V_MAX_F32 vDst(VGPR286) src0(VGPR284) src1(VGPR285) // VOP2 # 302: OpExtInst(FMin): Float: tmp302 << tmp301, const92 V_MOV_B32 vDst(VGPR287) src0(LITERAL_CONST) const: 0x00000000 V_MIN_F32 vDst(VGPR288) src0(VGPR286) src1(VGPR287) // VOP2 # 303: OpLoad: FloatVector2: tmp303 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR289) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR290) src0(VGPR1) # 304: OpCompositeConstruct: FloatVector2: tmp304 << const92, const92 V_MOV_B32 vDst(VGPR293) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR291) src0(VGPR293) V_MOV_B32 vDst(VGPR294) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR292) src0(VGPR294) # 305: OpExtInst(FMax): FloatVector2: tmp305 << tmp303, tmp304 V_MAX_F32 vDst(VGPR295) src0(VGPR289) src1(VGPR291) // VOP2 V_MAX_F32 vDst(VGPR296) src0(VGPR290) src1(VGPR292) // VOP2 # 306: OpExtInst(Length): Float: tmp306 << tmp305 V_MUL_F32 vDst(VGPR297) src0(VGPR295) src1(VGPR295) // VOP2 V_MAC_F32 vDst(VGPR297) src0(VGPR296) src1(VGPR296) // VOP2 V_SQRT_F32 vDst(VGPR297) src0(VGPR297) # 307: OpFAdd: Float: tmp307 << tmp302, tmp306 V_ADD_F32 vDst(VGPR298) src0(VGPR288) src1(VGPR297) // VOP2 # OpReturnValue: : << tmp307 S_MOV_B32 sDst(M0) src0(SGPR84) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR298) S_SETPC_B64 sDst(SGPR82) src0(SGPR82) # Float sdCircle(vf2;f1;(FloatVector2* p, Float* r) Function: Float sdCircle(vf2;f1;(, Float sdRect(vf2;vf2;.r) S_MOV_B64 sDst(SGPR96) src0(EXEC) # lb46 Label: lb46 # 310: OpLoad: FloatVector2: tmp310 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR93) const: 0x0 V_MOVRELS_B32 vDst(VGPR299) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR300) src0(VGPR1) # 311: OpExtInst(Length): Float: tmp311 << tmp310 V_MUL_F32 vDst(VGPR301) src0(VGPR299) src1(VGPR299) // VOP2 V_MAC_F32 vDst(VGPR301) src0(VGPR300) src1(VGPR300) // VOP2 V_SQRT_F32 vDst(VGPR301) src0(VGPR301) # 312: OpLoad: Float: tmp312 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR94) const: 0x0 V_MOVRELS_B32 vDst(VGPR302) src0(VGPR0) # 313: OpFSub: Float: tmp313 << tmp311, tmp312 V_SUB_F32 vDst(VGPR303) src0(VGPR301) src1(VGPR302) // VOP2 # OpReturnValue: : << tmp313 S_MOV_B32 sDst(M0) src0(SGPR92) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR303) S_SETPC_B64 sDst(SGPR90) src0(SGPR90) # Float opU(f1;f1;(Float* a, Float* b) Function: Float opU(f1;f1;(, Float sdCircle(vf2;f1;.b) S_MOV_B64 sDst(SGPR104) src0(EXEC) # lb51 Label: lb51 # 316: OpLoad: Float: tmp316 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR101) const: 0x0 V_MOVRELS_B32 vDst(VGPR304) src0(VGPR0) # 317: OpLoad: Float: tmp317 << b S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR102) const: 0x0 V_MOVRELS_B32 vDst(VGPR305) src0(VGPR0) # 318: OpExtInst(FMin): Float: tmp318 << tmp316, tmp317 V_MIN_F32 vDst(VGPR306) src0(VGPR304) src1(VGPR305) // VOP2 # OpReturnValue: : << tmp318 S_MOV_B32 sDst(M0) src0(SGPR100) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR306) S_SETPC_B64 sDst(SGPR98) src0(SGPR98) # Float opS(f1;f1;(Float* a, Float* b) Function: Float opS(f1;f1;(, Float opU(f1;f1;.b) S_MOV_B64 sDst(SGPR112) src0(EXEC) # lb55 Label: lb55 # 321: OpLoad: Float: tmp321 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR109) const: 0x0 V_MOVRELS_B32 vDst(VGPR307) src0(VGPR0) # 322: OpLoad: Float: tmp322 << b S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR110) const: 0x0 V_MOVRELS_B32 vDst(VGPR308) src0(VGPR0) # 323: OpFNegate: Float: tmp323 << tmp322 V_MUL_F32 vDst(VGPR309) src0(M1_0_F) src1(VGPR308) // VOP2 # 324: OpExtInst(FMax): Float: tmp324 << tmp321, tmp323 V_MAX_F32 vDst(VGPR310) src0(VGPR307) src1(VGPR309) // VOP2 # OpReturnValue: : << tmp324 S_MOV_B32 sDst(M0) src0(SGPR108) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR310) S_SETPC_B64 sDst(SGPR106) src0(SGPR106) # Float map(vf3;(FloatVector3* p) Function: Float map(vf3;() S_MOV_B64 sDst(SGPR118) src0(EXEC) # lb58 Label: lb58 # 328: OpLoad: FloatVector3: tmp328 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR350) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR351) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR352) src0(VGPR2) # OpStore: : tmp328 >> param327 V_MOV_B32 vDst(VGPR311) src0(VGPR350) V_MOV_B32 vDst(VGPR312) src0(VGPR351) V_MOV_B32 vDst(VGPR313) src0(VGPR352) # 330: OpLoad: Float: tmp330 << _twist # OpStore: : tmp330 >> param329 V_MOV_B32 vDst(VGPR314) src0(VGPR24) # 331: OpFunctionCall: Void: tTwist(vf3;f1;(param327, param329) S_ADD_U32 sDst(SGPR68) src0(LITERAL_CONST) src1(0) const: 0x137 # VGPR[311:313] S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0x13a # VGPR314 S_MOV_B64 sDst(SGPR120) src0(EXEC) # Indirect branch to tTwist(vf3;f1;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR120) # .lbl11 # 332: OpLoad: FloatVector3: tmp332 << param327 # OpStore: : tmp332 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR311) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR312) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR313) # 336: OpLoad: FloatVector3: tmp336 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR353) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR354) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR355) src0(VGPR2) # 337: OpVectorShuffle: FloatVector2: tmp337 << tmp336, tmp336, 0, 2 V_MOV_B32 vDst(VGPR356) src0(VGPR353) V_MOV_B32 vDst(VGPR357) src0(VGPR355) # OpStore: : tmp337 >> param335 V_MOV_B32 vDst(VGPR315) src0(VGPR356) V_MOV_B32 vDst(VGPR316) src0(VGPR357) # OpStore: : const334 >> param338 V_MOV_B32 vDst(VGPR358) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR359) src0(1_0_F) V_MOV_B32 vDst(VGPR317) src0(VGPR358) V_MOV_B32 vDst(VGPR318) src0(VGPR359) # 339: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param335, param338) S_ADD_U32 sDst(SGPR77) src0(LITERAL_CONST) src1(0) const: 0x13b # VGPR[315:316] S_ADD_U32 sDst(SGPR78) src0(LITERAL_CONST) src1(0) const: 0x13d # VGPR[317:318] S_MOV_B64 sDst(SGPR122) src0(EXEC) S_MOV_B32 sDst(SGPR76) src0(LITERAL_CONST) const: 0x168 # VGPR[360:361] # Indirect branch to tRepeat2(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR74) src0(SGPR74) S_ADD_U32 sDst(SGPR74) src0(SGPR74) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR75) src0(SGPR75) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR74) src0(SGPR74) S_MOV_B64 sDst(EXEC) src0(SGPR122) # .lbl12 # 340: OpLoad: FloatVector2: tmp340 << param335 # 341: OpLoad: FloatVector3: tmp341 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR362) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR363) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR364) src0(VGPR2) # 342: OpVectorShuffle: FloatVector3: tmp342 << tmp341, tmp340, 3, 1, 4 V_MOV_B32 vDst(VGPR365) src0(VGPR315) V_MOV_B32 vDst(VGPR366) src0(VGPR363) V_MOV_B32 vDst(VGPR367) src0(VGPR316) # OpStore: : tmp342 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR365) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR366) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR367) # 343: OpAccessChain: Float*: p[0] # 344: OpLoad: Float: tmp344 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR368) src0(VGPR0) # 345: OpExtInst(FAbs): Float: tmp345 << tmp344 V_ADD_F32 vDst(VGPR369) src0(VGPR368) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 346: OpAccessChain: Float*: p[0] # OpStore: : tmp345 >> p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR369) # 347: OpAccessChain: Float*: p[1] # 348: OpLoad: Float: tmp348 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR370) src0(VGPR1) # 349: OpFAdd: Float: tmp349 << tmp348, const275 V_MOV_B32 vDst(VGPR371) src0(0_5_F) V_ADD_F32 vDst(VGPR372) src0(VGPR370) src1(VGPR371) // VOP2 # 350: OpAccessChain: Float*: p[1] # OpStore: : tmp349 >> p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR1) src0(VGPR372) # 352: OpAccessChain: Float*: p[2] # 353: OpLoad: Float: tmp353 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR373) src0(VGPR2) # 354: OpExtInst(FAbs): Float: tmp354 << tmp353 V_ADD_F32 vDst(VGPR374) src0(VGPR373) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 356: OpFSub: Float: tmp356 << tmp354, const355 V_MOV_B32 vDst(VGPR375) src0(LITERAL_CONST) const: 0x3e19999a V_SUB_F32 vDst(VGPR376) src0(VGPR374) src1(VGPR375) // VOP2 # OpStore: : tmp356 >> d V_MOV_B32 vDst(VGPR319) src0(VGPR376) # 358: OpLoad: FloatVector3: tmp358 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR377) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR378) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR379) src0(VGPR2) # 359: OpVectorShuffle: FloatVector2: tmp359 << tmp358, tmp358, 0, 1 V_MOV_B32 vDst(VGPR380) src0(VGPR377) V_MOV_B32 vDst(VGPR381) src0(VGPR378) # 362: OpFSub: FloatVector2: tmp362 << tmp359, const361 V_MOV_B32 vDst(VGPR382) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR383) src0(LITERAL_CONST) const: 0x3f400000 V_SUB_F32 vDst(VGPR384) src0(VGPR380) src1(VGPR382) // VOP2 V_SUB_F32 vDst(VGPR385) src0(VGPR381) src1(VGPR383) // VOP2 # OpStore: : tmp362 >> param364 V_MOV_B32 vDst(VGPR320) src0(VGPR384) V_MOV_B32 vDst(VGPR321) src0(VGPR385) # OpStore: : const363 >> param365 V_MOV_B32 vDst(VGPR386) src0(LITERAL_CONST) const: 0x3e800000 V_MOV_B32 vDst(VGPR322) src0(VGPR386) # 366: OpFunctionCall: Float: sdCircle(vf2;f1;(param364, param365) S_ADD_U32 sDst(SGPR93) src0(LITERAL_CONST) src1(0) const: 0x140 # VGPR[320:321] S_ADD_U32 sDst(SGPR94) src0(LITERAL_CONST) src1(0) const: 0x142 # VGPR322 S_MOV_B64 sDst(SGPR124) src0(EXEC) S_MOV_B32 sDst(SGPR92) src0(LITERAL_CONST) const: 0x183 # VGPR387 # Indirect branch to sdCircle(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR90) src0(SGPR90) S_ADD_U32 sDst(SGPR90) src0(SGPR90) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR91) src0(SGPR91) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR90) src0(SGPR90) S_MOV_B64 sDst(EXEC) src0(SGPR124) # .lbl13 # 367: OpLoad: FloatVector3: tmp367 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR388) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR389) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR390) src0(VGPR2) # 368: OpVectorShuffle: FloatVector2: tmp368 << tmp367, tmp367, 0, 1 V_MOV_B32 vDst(VGPR391) src0(VGPR388) V_MOV_B32 vDst(VGPR392) src0(VGPR389) # 371: OpFSub: FloatVector2: tmp371 << tmp368, const370 V_MOV_B32 vDst(VGPR393) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR394) src0(LITERAL_CONST) const: 0x3ec00000 V_SUB_F32 vDst(VGPR395) src0(VGPR391) src1(VGPR393) // VOP2 V_SUB_F32 vDst(VGPR396) src0(VGPR392) src1(VGPR394) // VOP2 # OpStore: : tmp371 >> param373 V_MOV_B32 vDst(VGPR323) src0(VGPR395) V_MOV_B32 vDst(VGPR324) src0(VGPR396) # OpStore: : const372 >> param374 V_MOV_B32 vDst(VGPR397) src0(LITERAL_CONST) const: 0x3e800000 V_MOV_B32 vDst(VGPR398) src0(LITERAL_CONST) const: 0x3ec00000 V_MOV_B32 vDst(VGPR325) src0(VGPR397) V_MOV_B32 vDst(VGPR326) src0(VGPR398) # 375: OpFunctionCall: Float: sdRect(vf2;vf2;(param373, param374) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x143 # VGPR[323:324] S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x145 # VGPR[325:326] S_MOV_B64 sDst(SGPR126) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x18f # VGPR399 # Indirect branch to sdRect(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR126) # .lbl14 # OpStore: : sdCircle(vf2;f1; >> param376 V_MOV_B32 vDst(VGPR327) src0(VGPR387) # OpStore: : sdRect(vf2;vf2; >> param377 V_MOV_B32 vDst(VGPR328) src0(VGPR399) # 378: OpFunctionCall: Float: opU(f1;f1;(param376, param377) S_ADD_U32 sDst(SGPR101) src0(LITERAL_CONST) src1(0) const: 0x147 # VGPR327 S_ADD_U32 sDst(SGPR102) src0(LITERAL_CONST) src1(0) const: 0x148 # VGPR328 S_MOV_B64 sDst(SGPR128) src0(EXEC) S_MOV_B32 sDst(SGPR100) src0(LITERAL_CONST) const: 0x190 # VGPR400 # Indirect branch to opU(f1;f1;: ??? S_GETPC_B64 sDst(SGPR98) src0(SGPR98) S_ADD_U32 sDst(SGPR98) src0(SGPR98) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR99) src0(SGPR99) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR98) src0(SGPR98) S_MOV_B64 sDst(EXEC) src0(SGPR128) # .lbl15 # 380: OpLoad: Float: tmp380 << d # OpStore: : tmp380 >> param379 V_MOV_B32 vDst(VGPR329) src0(VGPR319) # OpStore: : opU(f1;f1; >> param381 V_MOV_B32 vDst(VGPR330) src0(VGPR400) # 383: OpFunctionCall: Float: opS(f1;f1;(param379, param381) S_ADD_U32 sDst(SGPR109) src0(LITERAL_CONST) src1(0) const: 0x149 # VGPR329 S_ADD_U32 sDst(SGPR110) src0(LITERAL_CONST) src1(0) const: 0x14a # VGPR330 S_MOV_B64 sDst(SGPR130) src0(EXEC) S_MOV_B32 sDst(SGPR108) src0(LITERAL_CONST) const: 0x191 # VGPR401 # Indirect branch to opS(f1;f1;: ??? S_GETPC_B64 sDst(SGPR106) src0(SGPR106) S_ADD_U32 sDst(SGPR106) src0(SGPR106) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR107) src0(SGPR107) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR106) src0(SGPR106) S_MOV_B64 sDst(EXEC) src0(SGPR130) # .lbl16 # OpStore: : opS(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR401) # 384: OpLoad: FloatVector3: tmp384 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR402) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR403) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR404) src0(VGPR2) # 385: OpVectorShuffle: FloatVector2: tmp385 << tmp384, tmp384, 0, 1 V_MOV_B32 vDst(VGPR405) src0(VGPR402) V_MOV_B32 vDst(VGPR406) src0(VGPR403) # 388: OpFSub: FloatVector2: tmp388 << tmp385, const387 V_MOV_B32 vDst(VGPR407) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR408) src0(LITERAL_CONST) const: 0x3eb33333 V_SUB_F32 vDst(VGPR409) src0(VGPR405) src1(VGPR407) // VOP2 V_SUB_F32 vDst(VGPR410) src0(VGPR406) src1(VGPR408) // VOP2 # OpStore: : tmp388 >> param392 V_MOV_B32 vDst(VGPR331) src0(VGPR409) V_MOV_B32 vDst(VGPR332) src0(VGPR410) # OpStore: : const391 >> param393 V_MOV_B32 vDst(VGPR411) src0(LITERAL_CONST) const: 0x3ee66666 V_MOV_B32 vDst(VGPR412) src0(LITERAL_CONST) const: 0x3e99999a V_MOV_B32 vDst(VGPR333) src0(VGPR411) V_MOV_B32 vDst(VGPR334) src0(VGPR412) # 394: OpFunctionCall: Float: sdRect(vf2;vf2;(param392, param393) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x14b # VGPR[331:332] S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x14d # VGPR[333:334] S_MOV_B64 sDst(SGPR132) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x19d # VGPR413 # Indirect branch to sdRect(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR132) # .lbl17 # 396: OpLoad: Float: tmp396 << d # OpStore: : tmp396 >> param395 V_MOV_B32 vDst(VGPR335) src0(VGPR319) # OpStore: : sdRect(vf2;vf2; >> param397 V_MOV_B32 vDst(VGPR336) src0(VGPR413) # 398: OpFunctionCall: Float: opS(f1;f1;(param395, param397) S_ADD_U32 sDst(SGPR109) src0(LITERAL_CONST) src1(0) const: 0x14f # VGPR335 S_ADD_U32 sDst(SGPR110) src0(LITERAL_CONST) src1(0) const: 0x150 # VGPR336 S_MOV_B64 sDst(SGPR134) src0(EXEC) S_MOV_B32 sDst(SGPR108) src0(LITERAL_CONST) const: 0x19e # VGPR414 # Indirect branch to opS(f1;f1;: ??? S_GETPC_B64 sDst(SGPR106) src0(SGPR106) S_ADD_U32 sDst(SGPR106) src0(SGPR106) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR107) src0(SGPR107) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR106) src0(SGPR106) S_MOV_B64 sDst(EXEC) src0(SGPR134) # .lbl18 # OpStore: : opS(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR414) # 399: OpLoad: FloatVector3: tmp399 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR415) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR416) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR417) src0(VGPR2) # 400: OpVectorShuffle: FloatVector2: tmp400 << tmp399, tmp399, 0, 2 V_MOV_B32 vDst(VGPR418) src0(VGPR415) V_MOV_B32 vDst(VGPR419) src0(VGPR417) # 402: OpFSub: FloatVector2: tmp402 << tmp400, const401 V_MOV_B32 vDst(VGPR420) src0(LITERAL_CONST) const: 0x3eb33333 V_MOV_B32 vDst(VGPR421) src0(LITERAL_CONST) const: 0x00000000 V_SUB_F32 vDst(VGPR422) src0(VGPR418) src1(VGPR420) // VOP2 V_SUB_F32 vDst(VGPR423) src0(VGPR419) src1(VGPR421) // VOP2 # OpStore: : tmp402 >> param404 V_MOV_B32 vDst(VGPR337) src0(VGPR422) V_MOV_B32 vDst(VGPR338) src0(VGPR423) # OpStore: : const403 >> param405 V_MOV_B32 vDst(VGPR424) src0(LITERAL_CONST) const: 0x3d99999a V_MOV_B32 vDst(VGPR339) src0(VGPR424) # 406: OpFunctionCall: Float: sdCircle(vf2;f1;(param404, param405) S_ADD_U32 sDst(SGPR93) src0(LITERAL_CONST) src1(0) const: 0x151 # VGPR[337:338] S_ADD_U32 sDst(SGPR94) src0(LITERAL_CONST) src1(0) const: 0x153 # VGPR339 S_MOV_B64 sDst(SGPR136) src0(EXEC) S_MOV_B32 sDst(SGPR92) src0(LITERAL_CONST) const: 0x1a9 # VGPR425 # Indirect branch to sdCircle(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR90) src0(SGPR90) S_ADD_U32 sDst(SGPR90) src0(SGPR90) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR91) src0(SGPR91) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR90) src0(SGPR90) S_MOV_B64 sDst(EXEC) src0(SGPR136) # .lbl19 # 408: OpLoad: Float: tmp408 << d # OpStore: : tmp408 >> param407 V_MOV_B32 vDst(VGPR340) src0(VGPR319) # OpStore: : sdCircle(vf2;f1; >> param409 V_MOV_B32 vDst(VGPR341) src0(VGPR425) # 410: OpFunctionCall: Float: opU(f1;f1;(param407, param409) S_ADD_U32 sDst(SGPR101) src0(LITERAL_CONST) src1(0) const: 0x154 # VGPR340 S_ADD_U32 sDst(SGPR102) src0(LITERAL_CONST) src1(0) const: 0x155 # VGPR341 S_MOV_B64 sDst(SGPR138) src0(EXEC) S_MOV_B32 sDst(SGPR100) src0(LITERAL_CONST) const: 0x1aa # VGPR426 # Indirect branch to opU(f1;f1;: ??? S_GETPC_B64 sDst(SGPR98) src0(SGPR98) S_ADD_U32 sDst(SGPR98) src0(SGPR98) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR99) src0(SGPR99) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR98) src0(SGPR98) S_MOV_B64 sDst(EXEC) src0(SGPR138) # .lbl20 # OpStore: : opU(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR426) # 411: OpAccessChain: Float*: p[2] # 412: OpLoad: Float: tmp412 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR427) src0(VGPR2) # 413: OpExtInst(FAbs): Float: tmp413 << tmp412 V_ADD_F32 vDst(VGPR428) src0(VGPR427) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 414: OpAccessChain: Float*: p[2] # OpStore: : tmp413 >> p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR2) src0(VGPR428) # 415: OpLoad: FloatVector3: tmp415 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR429) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR430) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR431) src0(VGPR2) # 416: OpVectorShuffle: FloatVector2: tmp416 << tmp415, tmp415, 1, 2 V_MOV_B32 vDst(VGPR432) src0(VGPR430) V_MOV_B32 vDst(VGPR433) src0(VGPR431) # 419: OpFSub: FloatVector2: tmp419 << tmp416, const418 V_MOV_B32 vDst(VGPR434) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR435) src0(0_5_F) V_SUB_F32 vDst(VGPR436) src0(VGPR432) src1(VGPR434) // VOP2 V_SUB_F32 vDst(VGPR437) src0(VGPR433) src1(VGPR435) // VOP2 # OpStore: : tmp419 >> param422 V_MOV_B32 vDst(VGPR342) src0(VGPR436) V_MOV_B32 vDst(VGPR343) src0(VGPR437) # OpStore: : const421 >> param423 V_MOV_B32 vDst(VGPR438) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR439) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR344) src0(VGPR438) V_MOV_B32 vDst(VGPR345) src0(VGPR439) # 424: OpFunctionCall: Float: sdRect(vf2;vf2;(param422, param423) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x156 # VGPR[342:343] S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x158 # VGPR[344:345] S_MOV_B64 sDst(SGPR140) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x1b8 # VGPR440 # Indirect branch to sdRect(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR140) # .lbl21 # 426: OpLoad: Float: tmp426 << d # OpStore: : tmp426 >> param425 V_MOV_B32 vDst(VGPR346) src0(VGPR319) # OpStore: : sdRect(vf2;vf2; >> param427 V_MOV_B32 vDst(VGPR347) src0(VGPR440) # 428: OpFunctionCall: Float: opS(f1;f1;(param425, param427) S_ADD_U32 sDst(SGPR109) src0(LITERAL_CONST) src1(0) const: 0x15a # VGPR346 S_ADD_U32 sDst(SGPR110) src0(LITERAL_CONST) src1(0) const: 0x15b # VGPR347 S_MOV_B64 sDst(SGPR142) src0(EXEC) S_MOV_B32 sDst(SGPR108) src0(LITERAL_CONST) const: 0x1b9 # VGPR441 # Indirect branch to opS(f1;f1;: ??? S_GETPC_B64 sDst(SGPR106) src0(SGPR106) S_ADD_U32 sDst(SGPR106) src0(SGPR106) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR107) src0(SGPR107) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR106) src0(SGPR106) S_MOV_B64 sDst(EXEC) src0(SGPR142) # .lbl22 # OpStore: : opS(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR441) # 429: OpAccessChain: Float*: p[1] # 430: OpLoad: Float: tmp430 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR442) src0(VGPR1) # 431: OpFSub: Float: tmp431 << tmp430, const275 V_MOV_B32 vDst(VGPR443) src0(0_5_F) V_SUB_F32 vDst(VGPR444) src0(VGPR442) src1(VGPR443) // VOP2 # 432: OpExtInst(FAbs): Float: tmp432 << tmp431 V_ADD_F32 vDst(VGPR445) src0(VGPR444) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 433: OpFNegate: Float: tmp433 << tmp432 V_MUL_F32 vDst(VGPR446) src0(M1_0_F) src1(VGPR445) // VOP2 # 435: OpFAdd: Float: tmp435 << tmp433, const434 V_MOV_B32 vDst(VGPR447) src0(LITERAL_CONST) const: 0x3f4ccccd V_ADD_F32 vDst(VGPR448) src0(VGPR446) src1(VGPR447) // VOP2 # 437: OpLoad: Float: tmp437 << d # OpStore: : tmp437 >> param436 V_MOV_B32 vDst(VGPR348) src0(VGPR319) # OpStore: : tmp435 >> param438 V_MOV_B32 vDst(VGPR349) src0(VGPR448) # 439: OpFunctionCall: Float: opU(f1;f1;(param436, param438) S_ADD_U32 sDst(SGPR101) src0(LITERAL_CONST) src1(0) const: 0x15c # VGPR348 S_ADD_U32 sDst(SGPR102) src0(LITERAL_CONST) src1(0) const: 0x15d # VGPR349 S_MOV_B64 sDst(SGPR144) src0(EXEC) S_MOV_B32 sDst(SGPR100) src0(LITERAL_CONST) const: 0x1c1 # VGPR449 # Indirect branch to opU(f1;f1;: ??? S_GETPC_B64 sDst(SGPR98) src0(SGPR98) S_ADD_U32 sDst(SGPR98) src0(SGPR98) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR99) src0(SGPR99) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR98) src0(SGPR98) S_MOV_B64 sDst(EXEC) src0(SGPR144) # .lbl23 # OpStore: : opU(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR449) # 440: OpLoad: Float: tmp440 << d # OpReturnValue: : << tmp440 S_MOV_B32 sDst(M0) src0(SGPR116) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR319) S_SETPC_B64 sDst(SGPR114) src0(SGPR114) # Float trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* maxDist, Float* steps) Function: Float trace(vf3;vf3;f1;f1;(, FloatVector3 map(vf3;.rd, Float map(vf3;.maxDist, Float map(vf3;.steps) S_MOV_B64 sDst(SGPR154) src0(EXEC) # lb65 Label: lb65 # OpStore: : const92 >> total V_MOV_B32 vDst(VGPR455) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR450) src0(VGPR455) # OpStore: : const92 >> steps S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR152) const: 0x0 V_MOV_B32 vDst(VGPR456) src0(LITERAL_CONST) const: 0x00000000 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR456) # OpStore: : const210 >> i V_MOV_B32 vDst(VGPR451) src0(0) # OpBranch: to lb445 S_BRANCH ??? lb445 # lb445 Label: lb445 # OpLoopMerge: (merge: lb447, continue: lb448) # CF Block: Merge: lb447, Continue: lb448 S_MOV_B64 sDst(SGPR156) src0(EXEC) S_MOV_B64 sDst(SGPR158) src0(EXEC) S_MOV_B64 sDst(SGPR160) src0(EXEC) Label: lb445Loop # OpBranch: to lb449 S_BRANCH ??? lb449 # lb449 Label: lb449 # 450: OpLoad: Int: tmp450 << i Decorators: RelaxedPrecision # 452: OpSLessThan: Bool: tmp452 << tmp450, const451 V_MOV_B32 vDst(VGPR457) src0(LITERAL_CONST) const: 0x00000064 V_CMP_LT_I32 dst(SGPR162) src0(VGPR451) src1(VGPR457) // VOP3a # OpBranchConditional: if(tmp452) then branch to lb446, else branch to lb447 # CF Block: Cond Branch: true: lb446, false: lb447 S_AND_B64 sDst(EXEC) src0(SGPR162) src1(EXEC) S_CBRANCH_EXECZ ??? lb447 S_BRANCH ??? lb446 # lb446 Label: lb446 # 453: OpLoad: Float: tmp453 << steps S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR152) const: 0x0 V_MOVRELS_B32 vDst(VGPR458) src0(VGPR0) # 454: OpFAdd: Float: tmp454 << tmp453, const117 V_MOV_B32 vDst(VGPR459) src0(1_0_F) V_ADD_F32 vDst(VGPR460) src0(VGPR458) src1(VGPR459) // VOP2 # OpStore: : tmp454 >> steps S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR152) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR460) # 456: OpLoad: FloatVector3: tmp456 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR149) const: 0x0 V_MOVRELS_B32 vDst(VGPR461) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR462) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR463) src0(VGPR2) # 457: OpLoad: FloatVector3: tmp457 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR150) const: 0x0 V_MOVRELS_B32 vDst(VGPR464) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR465) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR466) src0(VGPR2) # 458: OpLoad: Float: tmp458 << total # 459: OpVectorTimesScalar: FloatVector3: tmp459 << tmp457, tmp458 V_MUL_F32 vDst(VGPR467) src0(VGPR450) src1(VGPR464) // VOP2 V_MUL_F32 vDst(VGPR468) src0(VGPR450) src1(VGPR465) // VOP2 V_MUL_F32 vDst(VGPR469) src0(VGPR450) src1(VGPR466) // VOP2 # 460: OpFAdd: FloatVector3: tmp460 << tmp456, tmp459 V_ADD_F32 vDst(VGPR470) src0(VGPR461) src1(VGPR467) // VOP2 V_ADD_F32 vDst(VGPR471) src0(VGPR462) src1(VGPR468) // VOP2 V_ADD_F32 vDst(VGPR472) src0(VGPR463) src1(VGPR469) // VOP2 # OpStore: : tmp460 >> param461 V_MOV_B32 vDst(VGPR452) src0(VGPR470) V_MOV_B32 vDst(VGPR453) src0(VGPR471) V_MOV_B32 vDst(VGPR454) src0(VGPR472) # 462: OpFunctionCall: Float: map(vf3;(param461) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1c4 # VGPR[452:454] S_MOV_B64 sDst(SGPR164) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x1d9 # VGPR473 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR164) # .lbl24 # 464: OpLoad: Float: tmp464 << total # 465: OpFAdd: Float: tmp465 << tmp464, map(vf3; V_ADD_F32 vDst(VGPR474) src0(VGPR450) src1(VGPR473) // VOP2 # OpStore: : tmp465 >> total V_MOV_B32 vDst(VGPR450) src0(VGPR474) # 468: OpFOrdLessThan: Bool: tmp468 << map(vf3;, const467 V_MOV_B32 vDst(VGPR475) src0(LITERAL_CONST) const: 0x3727c5ac V_CMP_LT_F32 dst(SGPR166) src0(VGPR473) src1(VGPR475) // VOP3a # 469: OpLoad: Float: tmp469 << maxDist S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR151) const: 0x0 V_MOVRELS_B32 vDst(VGPR476) src0(VGPR0) # 470: OpLoad: Float: tmp470 << total # 471: OpFOrdLessThan: Bool: tmp471 << tmp469, tmp470 V_CMP_LT_F32 dst(SGPR168) src0(VGPR476) src1(VGPR450) // VOP3a # 472: OpLogicalOr: Bool: tmp472 << tmp468, tmp471 S_OR_B64 sDst(SGPR170) src0(SGPR166) src1(SGPR168) # OpSelectionMerge: (merge: lb474) # CF Block: Merge: lb474 S_MOV_B64 sDst(SGPR172) src0(EXEC) # OpBranchConditional: if(tmp472) then branch to lb473, else branch to lb474 # CF Block: Cond Branch: true: lb473, false: lb474 S_AND_B64 sDst(EXEC) src0(SGPR170) src1(EXEC) S_CBRANCH_EXECZ ??? lb474 S_BRANCH ??? lb473 # lb473 Label: lb473 # OpBranch: to lb447 S_BRANCH ??? lb447 # lb474 Label: lb474 # OpBranch: to lb448 S_BRANCH ??? lb448 # lb448 Label: lb448 # 476: OpLoad: Int: tmp476 << i Decorators: RelaxedPrecision # 477: OpIAdd: Int: tmp477 << tmp476, const234 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR477) src0(1_INT) V_ADD_I32 vDst(VGPR478) src0(VGPR451) src1(VGPR477) // VOP2 # OpStore: : tmp477 >> i V_MOV_B32 vDst(VGPR451) src0(VGPR478) # OpBranch: to lb445 S_BRANCH ??? lb445 # lb447 Label: lb447 # 478: OpLoad: Float: tmp478 << total # OpReturnValue: : << tmp478 S_MOV_B32 sDst(M0) src0(SGPR148) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR450) S_SETPC_B64 sDst(SGPR146) src0(SGPR146) # FloatVector3 getNormal(vf3;(FloatVector3* p) Function: FloatVector3 getNormal(vf3;() S_MOV_B64 sDst(SGPR178) src0(EXEC) # lb69 Label: lb69 # 484: OpLoad: FloatVector3: tmp484 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR497) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR498) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR499) src0(VGPR2) # 486: OpVectorShuffle: FloatVector3: tmp486 << const483, const483, 0, 1, 1 V_MOV_B32 vDst(VGPR500) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR501) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR502) src0(VGPR500) V_MOV_B32 vDst(VGPR503) src0(VGPR501) V_MOV_B32 vDst(VGPR504) src0(VGPR501) # 487: OpFAdd: FloatVector3: tmp487 << tmp484, tmp486 V_ADD_F32 vDst(VGPR505) src0(VGPR497) src1(VGPR502) // VOP2 V_ADD_F32 vDst(VGPR506) src0(VGPR498) src1(VGPR503) // VOP2 V_ADD_F32 vDst(VGPR507) src0(VGPR499) src1(VGPR504) // VOP2 # OpStore: : tmp487 >> param488 V_MOV_B32 vDst(VGPR479) src0(VGPR505) V_MOV_B32 vDst(VGPR480) src0(VGPR506) V_MOV_B32 vDst(VGPR481) src0(VGPR507) # 489: OpFunctionCall: Float: map(vf3;(param488) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1df # VGPR[479:481] S_MOV_B64 sDst(SGPR180) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x1fc # VGPR508 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR180) # .lbl25 # 490: OpLoad: FloatVector3: tmp490 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR509) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR510) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR511) src0(VGPR2) # 492: OpVectorShuffle: FloatVector3: tmp492 << const483, const483, 0, 1, 1 V_MOV_B32 vDst(VGPR512) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR513) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR514) src0(VGPR512) V_MOV_B32 vDst(VGPR515) src0(VGPR513) V_MOV_B32 vDst(VGPR516) src0(VGPR513) # 493: OpFSub: FloatVector3: tmp493 << tmp490, tmp492 V_SUB_F32 vDst(VGPR517) src0(VGPR509) src1(VGPR514) // VOP2 V_SUB_F32 vDst(VGPR518) src0(VGPR510) src1(VGPR515) // VOP2 V_SUB_F32 vDst(VGPR519) src0(VGPR511) src1(VGPR516) // VOP2 # OpStore: : tmp493 >> param494 V_MOV_B32 vDst(VGPR482) src0(VGPR517) V_MOV_B32 vDst(VGPR483) src0(VGPR518) V_MOV_B32 vDst(VGPR484) src0(VGPR519) # 495: OpFunctionCall: Float: map(vf3;(param494) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1e2 # VGPR[482:484] S_MOV_B64 sDst(SGPR182) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x208 # VGPR520 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR182) # .lbl26 # 496: OpFSub: Float: tmp496 << map(vf3;, map(vf3; V_SUB_F32 vDst(VGPR521) src0(VGPR508) src1(VGPR520) // VOP2 # 497: OpLoad: FloatVector3: tmp497 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR522) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR523) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR524) src0(VGPR2) # 499: OpVectorShuffle: FloatVector3: tmp499 << const483, const483, 1, 0, 1 V_MOV_B32 vDst(VGPR525) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR526) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR527) src0(VGPR526) V_MOV_B32 vDst(VGPR528) src0(VGPR525) V_MOV_B32 vDst(VGPR529) src0(VGPR526) # 500: OpFAdd: FloatVector3: tmp500 << tmp497, tmp499 V_ADD_F32 vDst(VGPR530) src0(VGPR522) src1(VGPR527) // VOP2 V_ADD_F32 vDst(VGPR531) src0(VGPR523) src1(VGPR528) // VOP2 V_ADD_F32 vDst(VGPR532) src0(VGPR524) src1(VGPR529) // VOP2 # OpStore: : tmp500 >> param501 V_MOV_B32 vDst(VGPR485) src0(VGPR530) V_MOV_B32 vDst(VGPR486) src0(VGPR531) V_MOV_B32 vDst(VGPR487) src0(VGPR532) # 502: OpFunctionCall: Float: map(vf3;(param501) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1e5 # VGPR[485:487] S_MOV_B64 sDst(SGPR184) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x215 # VGPR533 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR184) # .lbl27 # 503: OpLoad: FloatVector3: tmp503 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR534) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR535) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR536) src0(VGPR2) # 505: OpVectorShuffle: FloatVector3: tmp505 << const483, const483, 1, 0, 1 V_MOV_B32 vDst(VGPR537) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR538) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR539) src0(VGPR538) V_MOV_B32 vDst(VGPR540) src0(VGPR537) V_MOV_B32 vDst(VGPR541) src0(VGPR538) # 506: OpFSub: FloatVector3: tmp506 << tmp503, tmp505 V_SUB_F32 vDst(VGPR542) src0(VGPR534) src1(VGPR539) // VOP2 V_SUB_F32 vDst(VGPR543) src0(VGPR535) src1(VGPR540) // VOP2 V_SUB_F32 vDst(VGPR544) src0(VGPR536) src1(VGPR541) // VOP2 # OpStore: : tmp506 >> param507 V_MOV_B32 vDst(VGPR488) src0(VGPR542) V_MOV_B32 vDst(VGPR489) src0(VGPR543) V_MOV_B32 vDst(VGPR490) src0(VGPR544) # 508: OpFunctionCall: Float: map(vf3;(param507) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1e8 # VGPR[488:490] S_MOV_B64 sDst(SGPR186) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x221 # VGPR545 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR186) # .lbl28 # 509: OpFSub: Float: tmp509 << map(vf3;, map(vf3; V_SUB_F32 vDst(VGPR546) src0(VGPR533) src1(VGPR545) // VOP2 # 510: OpLoad: FloatVector3: tmp510 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR547) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR548) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR549) src0(VGPR2) # 512: OpVectorShuffle: FloatVector3: tmp512 << const483, const483, 1, 1, 0 V_MOV_B32 vDst(VGPR550) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR551) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR552) src0(VGPR551) V_MOV_B32 vDst(VGPR553) src0(VGPR551) V_MOV_B32 vDst(VGPR554) src0(VGPR550) # 513: OpFAdd: FloatVector3: tmp513 << tmp510, tmp512 V_ADD_F32 vDst(VGPR555) src0(VGPR547) src1(VGPR552) // VOP2 V_ADD_F32 vDst(VGPR556) src0(VGPR548) src1(VGPR553) // VOP2 V_ADD_F32 vDst(VGPR557) src0(VGPR549) src1(VGPR554) // VOP2 # OpStore: : tmp513 >> param514 V_MOV_B32 vDst(VGPR491) src0(VGPR555) V_MOV_B32 vDst(VGPR492) src0(VGPR556) V_MOV_B32 vDst(VGPR493) src0(VGPR557) # 515: OpFunctionCall: Float: map(vf3;(param514) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1eb # VGPR[491:493] S_MOV_B64 sDst(SGPR188) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x22e # VGPR558 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR188) # .lbl29 # 516: OpLoad: FloatVector3: tmp516 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR559) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR560) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR561) src0(VGPR2) # 518: OpVectorShuffle: FloatVector3: tmp518 << const483, const483, 1, 1, 0 V_MOV_B32 vDst(VGPR562) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR563) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR564) src0(VGPR563) V_MOV_B32 vDst(VGPR565) src0(VGPR563) V_MOV_B32 vDst(VGPR566) src0(VGPR562) # 519: OpFSub: FloatVector3: tmp519 << tmp516, tmp518 V_SUB_F32 vDst(VGPR567) src0(VGPR559) src1(VGPR564) // VOP2 V_SUB_F32 vDst(VGPR568) src0(VGPR560) src1(VGPR565) // VOP2 V_SUB_F32 vDst(VGPR569) src0(VGPR561) src1(VGPR566) // VOP2 # OpStore: : tmp519 >> param520 V_MOV_B32 vDst(VGPR494) src0(VGPR567) V_MOV_B32 vDst(VGPR495) src0(VGPR568) V_MOV_B32 vDst(VGPR496) src0(VGPR569) # 521: OpFunctionCall: Float: map(vf3;(param520) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1ee # VGPR[494:496] S_MOV_B64 sDst(SGPR190) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x23a # VGPR570 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR190) # .lbl30 # 522: OpFSub: Float: tmp522 << map(vf3;, map(vf3; V_SUB_F32 vDst(VGPR571) src0(VGPR558) src1(VGPR570) // VOP2 # 523: OpCompositeConstruct: FloatVector3: tmp523 << tmp496, tmp509, tmp522 V_MOV_B32 vDst(VGPR572) src0(VGPR521) V_MOV_B32 vDst(VGPR573) src0(VGPR546) V_MOV_B32 vDst(VGPR574) src0(VGPR571) # 524: OpExtInst(Normalize): FloatVector3: tmp524 << tmp523 V_MUL_F32 vDst(VGPR575) src0(VGPR572) src1(VGPR572) // VOP2 V_MAC_F32 vDst(VGPR575) src0(VGPR573) src1(VGPR573) // VOP2 V_MAC_F32 vDst(VGPR575) src0(VGPR574) src1(VGPR574) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR575) src0(VGPR575) V_MUL_F32 vDst(VGPR576) src0(VGPR572) src1(VGPR575) // VOP2 V_MUL_F32 vDst(VGPR577) src0(VGPR573) src1(VGPR575) // VOP2 V_MUL_F32 vDst(VGPR578) src0(VGPR574) src1(VGPR575) // VOP2 # OpReturnValue: : << tmp524 S_MOV_B32 sDst(M0) src0(SGPR176) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR576) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR577) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR578) S_SETPC_B64 sDst(SGPR174) src0(SGPR174) # Float calculateAO(vf3;vf3;(FloatVector3* p, FloatVector3* n) Function: Float calculateAO(vf3;vf3;(, FloatVector3 getNormal(vf3;.n) S_MOV_B64 sDst(SGPR198) src0(EXEC) # lb74 Label: lb74 # OpStore: : const92 >> r V_MOV_B32 vDst(VGPR585) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR579) src0(VGPR585) # OpStore: : const117 >> w V_MOV_B32 vDst(VGPR580) src0(1_0_F) # OpStore: : const117 >> i V_MOV_B32 vDst(VGPR581) src0(1_0_F) # OpBranch: to lb530 S_BRANCH ??? lb530 # lb530 Label: lb530 # OpLoopMerge: (merge: lb532, continue: lb533) # CF Block: Merge: lb532, Continue: lb533 S_MOV_B64 sDst(SGPR200) src0(EXEC) S_MOV_B64 sDst(SGPR202) src0(EXEC) S_MOV_B64 sDst(SGPR204) src0(EXEC) Label: lb530Loop # OpBranch: to lb534 S_BRANCH ??? lb534 # lb534 Label: lb534 # 535: OpLoad: Float: tmp535 << i # 537: OpFOrdLessThanEqual: Bool: tmp537 << tmp535, const536 V_MOV_B32 vDst(VGPR586) src0(LITERAL_CONST) const: 0x40a00000 V_CMP_LE_F32 dst(SGPR206) src0(VGPR581) src1(VGPR586) // VOP3a # OpBranchConditional: if(tmp537) then branch to lb531, else branch to lb532 # CF Block: Cond Branch: true: lb531, false: lb532 S_AND_B64 sDst(EXEC) src0(SGPR206) src1(EXEC) S_CBRANCH_EXECZ ??? lb532 S_BRANCH ??? lb531 # lb531 Label: lb531 # 539: OpLoad: Float: tmp539 << i # 540: OpFDiv: Float: tmp540 << tmp539, const536 V_MOV_B32 vDst(VGPR587) src0(LITERAL_CONST) const: 0x40a00000 V_RCP_F32 vDst(VGPR588) src0(VGPR587) V_MUL_F32 vDst(VGPR588) src0(VGPR581) src1(VGPR588) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR588) src0(VGPR588) src1(VGPR587) src2(VGPR581) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 541: OpFDiv: Float: tmp541 << tmp540, const220 V_MOV_B32 vDst(VGPR589) src0(LITERAL_CONST) const: 0x41200000 V_RCP_F32 vDst(VGPR590) src0(VGPR589) V_MUL_F32 vDst(VGPR590) src0(VGPR588) src1(VGPR590) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR590) src0(VGPR590) src1(VGPR589) src2(VGPR588) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 542: OpLoad: Float: tmp542 << w # 544: OpLoad: FloatVector3: tmp544 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR195) const: 0x0 V_MOVRELS_B32 vDst(VGPR591) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR592) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR593) src0(VGPR2) # 545: OpLoad: FloatVector3: tmp545 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR196) const: 0x0 V_MOVRELS_B32 vDst(VGPR594) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR595) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR596) src0(VGPR2) # 547: OpVectorTimesScalar: FloatVector3: tmp547 << tmp545, tmp541 V_MUL_F32 vDst(VGPR597) src0(VGPR590) src1(VGPR594) // VOP2 V_MUL_F32 vDst(VGPR598) src0(VGPR590) src1(VGPR595) // VOP2 V_MUL_F32 vDst(VGPR599) src0(VGPR590) src1(VGPR596) // VOP2 # 548: OpFAdd: FloatVector3: tmp548 << tmp544, tmp547 V_ADD_F32 vDst(VGPR600) src0(VGPR591) src1(VGPR597) // VOP2 V_ADD_F32 vDst(VGPR601) src0(VGPR592) src1(VGPR598) // VOP2 V_ADD_F32 vDst(VGPR602) src0(VGPR593) src1(VGPR599) // VOP2 # OpStore: : tmp548 >> param549 V_MOV_B32 vDst(VGPR582) src0(VGPR600) V_MOV_B32 vDst(VGPR583) src0(VGPR601) V_MOV_B32 vDst(VGPR584) src0(VGPR602) # 550: OpFunctionCall: Float: map(vf3;(param549) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x246 # VGPR[582:584] S_MOV_B64 sDst(SGPR208) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x25b # VGPR603 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR208) # .lbl31 # 551: OpFSub: Float: tmp551 << tmp541, map(vf3; V_SUB_F32 vDst(VGPR604) src0(VGPR590) src1(VGPR603) // VOP2 # 552: OpFMul: Float: tmp552 << tmp542, tmp551 V_MUL_F32 vDst(VGPR605) src0(VGPR580) src1(VGPR604) // VOP2 # 553: OpLoad: Float: tmp553 << r # 554: OpFAdd: Float: tmp554 << tmp553, tmp552 V_ADD_F32 vDst(VGPR606) src0(VGPR579) src1(VGPR605) // VOP2 # OpStore: : tmp554 >> r V_MOV_B32 vDst(VGPR579) src0(VGPR606) # 555: OpLoad: Float: tmp555 << w # 556: OpFMul: Float: tmp556 << tmp555, const275 V_MOV_B32 vDst(VGPR607) src0(0_5_F) V_MUL_F32 vDst(VGPR608) src0(VGPR580) src1(VGPR607) // VOP2 # OpStore: : tmp556 >> w V_MOV_B32 vDst(VGPR580) src0(VGPR608) # OpBranch: to lb533 S_BRANCH ??? lb533 # lb533 Label: lb533 # 557: OpLoad: Float: tmp557 << i # 558: OpFAdd: Float: tmp558 << tmp557, const117 V_MOV_B32 vDst(VGPR609) src0(1_0_F) V_ADD_F32 vDst(VGPR610) src0(VGPR581) src1(VGPR609) // VOP2 # OpStore: : tmp558 >> i V_MOV_B32 vDst(VGPR581) src0(VGPR610) # OpBranch: to lb530 S_BRANCH ??? lb530 # lb532 Label: lb532 # 559: OpLoad: Float: tmp559 << r # 560: OpFMul: Float: tmp560 << tmp559, const220 V_MOV_B32 vDst(VGPR611) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR612) src0(VGPR579) src1(VGPR611) // VOP2 # 561: OpExtInst(FClamp): Float: tmp561 << tmp560, const92, const117 V_MOV_B32 vDst(VGPR613) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR614) src0(1_0_F) V_MAX_F32 vDst(VGPR615) src0(VGPR612) src1(VGPR613) // VOP2 V_MIN_F32 vDst(VGPR615) src0(VGPR615) src1(VGPR614) // VOP2 # 562: OpFSub: Float: tmp562 << const117, tmp561 V_SUB_F32 vDst(VGPR616) src0(1_0_F) src1(VGPR615) // VOP2 # OpReturnValue: : << tmp562 S_MOV_B32 sDst(M0) src0(SGPR194) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR616) S_SETPC_B64 sDst(SGPR192) src0(SGPR192) # Bool isWall(vf3;(FloatVector3* p) Function: Bool isWall(vf3;() S_MOV_B64 sDst(SGPR214) src0(EXEC) # lb79 Label: lb79 # 565: OpAccessChain: Float*: p[0] # 566: OpLoad: Float: tmp566 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR621) src0(VGPR0) # 567: OpFAdd: Float: tmp567 << tmp566, const386 V_MOV_B32 vDst(VGPR622) src0(LITERAL_CONST) const: 0x3eb33333 V_ADD_F32 vDst(VGPR623) src0(VGPR621) src1(VGPR622) // VOP2 # 568: OpAccessChain: Float*: p[0] # OpStore: : tmp567 >> p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR623) # 570: OpLoad: FloatVector3: tmp570 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR624) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR625) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR626) src0(VGPR2) # 571: OpVectorShuffle: FloatVector2: tmp571 << tmp570, tmp570, 0, 2 V_MOV_B32 vDst(VGPR627) src0(VGPR624) V_MOV_B32 vDst(VGPR628) src0(VGPR626) # OpStore: : tmp571 >> param569 V_MOV_B32 vDst(VGPR617) src0(VGPR627) V_MOV_B32 vDst(VGPR618) src0(VGPR628) # OpStore: : const334 >> param572 V_MOV_B32 vDst(VGPR629) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR630) src0(1_0_F) V_MOV_B32 vDst(VGPR619) src0(VGPR629) V_MOV_B32 vDst(VGPR620) src0(VGPR630) # 573: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param569, param572) S_ADD_U32 sDst(SGPR77) src0(LITERAL_CONST) src1(0) const: 0x269 # VGPR[617:618] S_ADD_U32 sDst(SGPR78) src0(LITERAL_CONST) src1(0) const: 0x26b # VGPR[619:620] S_MOV_B64 sDst(SGPR216) src0(EXEC) S_MOV_B32 sDst(SGPR76) src0(LITERAL_CONST) const: 0x277 # VGPR[631:632] # Indirect branch to tRepeat2(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR74) src0(SGPR74) S_ADD_U32 sDst(SGPR74) src0(SGPR74) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR75) src0(SGPR75) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR74) src0(SGPR74) S_MOV_B64 sDst(EXEC) src0(SGPR216) # .lbl32 # 574: OpLoad: FloatVector2: tmp574 << param569 # 575: OpLoad: FloatVector3: tmp575 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR633) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR634) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR635) src0(VGPR2) # 576: OpVectorShuffle: FloatVector3: tmp576 << tmp575, tmp574, 3, 1, 4 V_MOV_B32 vDst(VGPR636) src0(VGPR617) V_MOV_B32 vDst(VGPR637) src0(VGPR634) V_MOV_B32 vDst(VGPR638) src0(VGPR618) # OpStore: : tmp576 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR636) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR637) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR638) # 577: OpAccessChain: Float*: p[1] # 578: OpLoad: Float: tmp578 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR639) src0(VGPR1) # 579: OpFAdd: Float: tmp579 << tmp578, const355 V_MOV_B32 vDst(VGPR640) src0(LITERAL_CONST) const: 0x3e19999a V_ADD_F32 vDst(VGPR641) src0(VGPR639) src1(VGPR640) // VOP2 # 580: OpExtInst(FAbs): Float: tmp580 << tmp579 V_ADD_F32 vDst(VGPR642) src0(VGPR641) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 581: OpLoad: FloatVector3: tmp581 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR643) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR644) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR645) src0(VGPR2) # 582: OpVectorShuffle: FloatVector2: tmp582 << tmp581, tmp581, 0, 2 V_MOV_B32 vDst(VGPR646) src0(VGPR643) V_MOV_B32 vDst(VGPR647) src0(VGPR645) # 583: OpExtInst(Length): Float: tmp583 << tmp582 V_MUL_F32 vDst(VGPR648) src0(VGPR646) src1(VGPR646) // VOP2 V_MAC_F32 vDst(VGPR648) src0(VGPR647) src1(VGPR647) // VOP2 V_SQRT_F32 vDst(VGPR648) src0(VGPR648) # 584: OpFAdd: Float: tmp584 << tmp580, tmp583 V_ADD_F32 vDst(VGPR649) src0(VGPR642) src1(VGPR648) // VOP2 # 585: OpFOrdLessThan: Bool: tmp585 << const369, tmp584 V_MOV_B32 vDst(VGPR650) src0(LITERAL_CONST) const: 0x3ec00000 V_CMP_LT_F32 dst(SGPR218) src0(VGPR650) src1(VGPR649) // VOP3a # OpReturnValue: : << tmp585 S_MOV_B32 sDst(M0) src0(SGPR212) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR218) S_SETPC_B64 sDst(SGPR210) src0(SGPR210) # FloatVector3 _texture(vf3;(FloatVector3* p) Function: FloatVector3 _texture(vf3;() S_MOV_B64 sDst(SGPR224) src0(EXEC) # lb82 Label: lb82 # 589: OpLoad: FloatVector3: tmp589 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR671) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR672) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR673) src0(VGPR2) # OpStore: : tmp589 >> param588 V_MOV_B32 vDst(VGPR651) src0(VGPR671) V_MOV_B32 vDst(VGPR652) src0(VGPR672) V_MOV_B32 vDst(VGPR653) src0(VGPR673) # 591: OpLoad: Float: tmp591 << _twist # OpStore: : tmp591 >> param590 V_MOV_B32 vDst(VGPR654) src0(VGPR24) # 592: OpFunctionCall: Void: tTwist(vf3;f1;(param588, param590) S_ADD_U32 sDst(SGPR68) src0(LITERAL_CONST) src1(0) const: 0x28b # VGPR[651:653] S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0x28e # VGPR654 S_MOV_B64 sDst(SGPR226) src0(EXEC) # Indirect branch to tTwist(vf3;f1;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR226) # .lbl33 # 593: OpLoad: FloatVector3: tmp593 << param588 # OpStore: : tmp593 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR651) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR652) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR653) # 597: OpLoad: FloatVector3: tmp597 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR674) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR675) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR676) src0(VGPR2) # OpStore: : tmp597 >> param596 V_MOV_B32 vDst(VGPR655) src0(VGPR674) V_MOV_B32 vDst(VGPR656) src0(VGPR675) V_MOV_B32 vDst(VGPR657) src0(VGPR676) # 598: OpFunctionCall: Bool: isWall(vf3;(param596) S_ADD_U32 sDst(SGPR213) src0(LITERAL_CONST) src1(0) const: 0x28f # VGPR[655:657] S_MOV_B64 sDst(SGPR228) src0(EXEC) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x2a5 # VGPR677 # Indirect branch to isWall(vf3;: ??? S_GETPC_B64 sDst(SGPR210) src0(SGPR210) S_ADD_U32 sDst(SGPR210) src0(SGPR210) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR211) src0(SGPR211) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR210) src0(SGPR210) S_MOV_B64 sDst(EXEC) src0(SGPR228) # .lbl34 # 600: OpLoad: FloatVector3: tmp600 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR678) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR679) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR680) src0(VGPR2) # OpSelectionMerge: (merge: lb604) # CF Block: Merge: lb604 S_MOV_B64 sDst(SGPR230) src0(EXEC) # OpBranchConditional: if(isWall(vf3;) then branch to lb603, else branch to lb605 # CF Block: Cond Branch: true: lb603, false: lb605 S_AND_B64 sDst(EXEC) src0(VGPR677) src1(EXEC) S_CBRANCH_EXECZ ??? lb605 S_BRANCH ??? lb603 # lb603 Label: lb603 # OpStore: : const92 >> var601 V_MOV_B32 vDst(VGPR681) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR661) src0(VGPR681) # OpBranch: to lb604 S_BRANCH ??? lb604 # lb605 Label: lb605 # 608: OpLoad: FloatVector3: tmp608 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR682) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR683) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR684) src0(VGPR2) # 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp608, const536 V_MOV_B32 vDst(VGPR688) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR685) src0(VGPR688) src1(VGPR682) // VOP2 V_MUL_F32 vDst(VGPR686) src0(VGPR688) src1(VGPR683) // VOP2 V_MUL_F32 vDst(VGPR687) src0(VGPR688) src1(VGPR684) // VOP2 # OpStore: : tmp609 >> param610 V_MOV_B32 vDst(VGPR662) src0(VGPR685) V_MOV_B32 vDst(VGPR663) src0(VGPR686) V_MOV_B32 vDst(VGPR664) src0(VGPR687) # 611: OpFunctionCall: Float: fbm(vf3;(param610) S_ADD_U32 sDst(SGPR47) src0(LITERAL_CONST) src1(0) const: 0x296 # VGPR[662:664] S_MOV_B64 sDst(SGPR232) src0(EXEC) S_MOV_B32 sDst(SGPR46) src0(LITERAL_CONST) const: 0x2b1 # VGPR689 # Indirect branch to fbm(vf3;: ??? S_GETPC_B64 sDst(SGPR44) src0(SGPR44) S_ADD_U32 sDst(SGPR44) src0(SGPR44) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR45) src0(SGPR45) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR44) src0(SGPR44) S_MOV_B64 sDst(EXEC) src0(SGPR232) # .lbl35 # 612: OpFMul: Float: tmp612 << const607, fbm(vf3; V_MOV_B32 vDst(VGPR690) src0(LITERAL_CONST) const: 0x3f666666 V_MUL_F32 vDst(VGPR691) src0(VGPR690) src1(VGPR689) // VOP2 # 613: OpFAdd: Float: tmp613 << const606, tmp612 V_MOV_B32 vDst(VGPR692) src0(LITERAL_CONST) const: 0x3dcccccd V_ADD_F32 vDst(VGPR693) src0(VGPR692) src1(VGPR691) // VOP2 # OpStore: : tmp613 >> var601 V_MOV_B32 vDst(VGPR661) src0(VGPR693) # OpBranch: to lb604 S_BRANCH ??? lb604 # lb604 Label: lb604 # 614: OpLoad: Float: tmp614 << var601 # 615: OpCompositeConstruct: FloatVector3: tmp615 << tmp614, tmp614, tmp614 V_MOV_B32 vDst(VGPR694) src0(VGPR661) V_MOV_B32 vDst(VGPR695) src0(VGPR661) V_MOV_B32 vDst(VGPR696) src0(VGPR661) # 616: OpFAdd: FloatVector3: tmp616 << tmp600, tmp615 V_ADD_F32 vDst(VGPR697) src0(VGPR678) src1(VGPR694) // VOP2 V_ADD_F32 vDst(VGPR698) src0(VGPR679) src1(VGPR695) // VOP2 V_ADD_F32 vDst(VGPR699) src0(VGPR680) src1(VGPR696) // VOP2 # 619: OpFMul: FloatVector3: tmp619 << tmp616, const618 V_MOV_B32 vDst(VGPR700) src0(LITERAL_CONST) const: 0x40a00000 V_MOV_B32 vDst(VGPR701) src0(LITERAL_CONST) const: 0x41a00000 V_MOV_B32 vDst(VGPR702) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR703) src0(VGPR697) src1(VGPR700) // VOP2 V_MUL_F32 vDst(VGPR704) src0(VGPR698) src1(VGPR701) // VOP2 V_MUL_F32 vDst(VGPR705) src0(VGPR699) src1(VGPR702) // VOP2 # OpStore: : tmp619 >> param620 V_MOV_B32 vDst(VGPR665) src0(VGPR703) V_MOV_B32 vDst(VGPR666) src0(VGPR704) V_MOV_B32 vDst(VGPR667) src0(VGPR705) # 621: OpFunctionCall: Float: fbm(vf3;(param620) S_ADD_U32 sDst(SGPR47) src0(LITERAL_CONST) src1(0) const: 0x299 # VGPR[665:667] S_MOV_B64 sDst(SGPR234) src0(EXEC) S_MOV_B32 sDst(SGPR46) src0(LITERAL_CONST) const: 0x2c2 # VGPR706 # Indirect branch to fbm(vf3;: ??? S_GETPC_B64 sDst(SGPR44) src0(SGPR44) S_ADD_U32 sDst(SGPR44) src0(SGPR44) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR45) src0(SGPR45) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR44) src0(SGPR44) S_MOV_B64 sDst(EXEC) src0(SGPR234) # .lbl36 # 623: OpVectorTimesScalar: FloatVector3: tmp623 << const622, fbm(vf3; V_MOV_B32 vDst(VGPR710) src0(1_0_F) V_MOV_B32 vDst(VGPR711) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR712) src0(LITERAL_CONST) const: 0x3ecccccd V_MUL_F32 vDst(VGPR707) src0(VGPR706) src1(VGPR710) // VOP2 V_MUL_F32 vDst(VGPR708) src0(VGPR706) src1(VGPR711) // VOP2 V_MUL_F32 vDst(VGPR709) src0(VGPR706) src1(VGPR712) // VOP2 # 624: OpVectorTimesScalar: FloatVector3: tmp624 << tmp623, const360 V_MOV_B32 vDst(VGPR716) src0(LITERAL_CONST) const: 0x3f400000 V_MUL_F32 vDst(VGPR713) src0(VGPR716) src1(VGPR707) // VOP2 V_MUL_F32 vDst(VGPR714) src0(VGPR716) src1(VGPR708) // VOP2 V_MUL_F32 vDst(VGPR715) src0(VGPR716) src1(VGPR709) // VOP2 # 625: OpLoad: FloatVector3: tmp625 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR717) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR718) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR719) src0(VGPR2) # 627: OpFMul: FloatVector3: tmp627 << tmp625, const626 V_MOV_B32 vDst(VGPR720) src0(2_0_F) V_MOV_B32 vDst(VGPR721) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR722) src0(2_0_F) V_MUL_F32 vDst(VGPR723) src0(VGPR717) src1(VGPR720) // VOP2 V_MUL_F32 vDst(VGPR724) src0(VGPR718) src1(VGPR721) // VOP2 V_MUL_F32 vDst(VGPR725) src0(VGPR719) src1(VGPR722) // VOP2 # OpStore: : tmp627 >> param628 V_MOV_B32 vDst(VGPR668) src0(VGPR723) V_MOV_B32 vDst(VGPR669) src0(VGPR724) V_MOV_B32 vDst(VGPR670) src0(VGPR725) # 629: OpFunctionCall: Float: fbm(vf3;(param628) S_ADD_U32 sDst(SGPR47) src0(LITERAL_CONST) src1(0) const: 0x29c # VGPR[668:670] S_MOV_B64 sDst(SGPR236) src0(EXEC) S_MOV_B32 sDst(SGPR46) src0(LITERAL_CONST) const: 0x2d6 # VGPR726 # Indirect branch to fbm(vf3;: ??? S_GETPC_B64 sDst(SGPR44) src0(SGPR44) S_ADD_U32 sDst(SGPR44) src0(SGPR44) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR45) src0(SGPR45) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR44) src0(SGPR44) S_MOV_B64 sDst(EXEC) src0(SGPR236) # .lbl37 # 631: OpVectorTimesScalar: FloatVector3: tmp631 << const630, fbm(vf3; V_MOV_B32 vDst(VGPR730) src0(1_0_F) V_MOV_B32 vDst(VGPR731) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR732) src0(0_5_F) V_MUL_F32 vDst(VGPR727) src0(VGPR726) src1(VGPR730) // VOP2 V_MUL_F32 vDst(VGPR728) src0(VGPR726) src1(VGPR731) // VOP2 V_MUL_F32 vDst(VGPR729) src0(VGPR726) src1(VGPR732) // VOP2 # 632: OpVectorTimesScalar: FloatVector3: tmp632 << tmp631, const363 V_MOV_B32 vDst(VGPR736) src0(LITERAL_CONST) const: 0x3e800000 V_MUL_F32 vDst(VGPR733) src0(VGPR736) src1(VGPR727) // VOP2 V_MUL_F32 vDst(VGPR734) src0(VGPR736) src1(VGPR728) // VOP2 V_MUL_F32 vDst(VGPR735) src0(VGPR736) src1(VGPR729) // VOP2 # 633: OpFAdd: FloatVector3: tmp633 << tmp624, tmp632 V_ADD_F32 vDst(VGPR737) src0(VGPR713) src1(VGPR733) // VOP2 V_ADD_F32 vDst(VGPR738) src0(VGPR714) src1(VGPR734) // VOP2 V_ADD_F32 vDst(VGPR739) src0(VGPR715) src1(VGPR735) // VOP2 # OpStore: : tmp633 >> t V_MOV_B32 vDst(VGPR658) src0(VGPR737) V_MOV_B32 vDst(VGPR659) src0(VGPR738) V_MOV_B32 vDst(VGPR660) src0(VGPR739) # OpSelectionMerge: (merge: lb636) # CF Block: Merge: lb636 S_MOV_B64 sDst(SGPR238) src0(EXEC) # OpBranchConditional: if(isWall(vf3;) then branch to lb635, else branch to lb636 # CF Block: Cond Branch: true: lb635, false: lb636 S_AND_B64 sDst(EXEC) src0(VGPR677) src1(EXEC) S_CBRANCH_EXECZ ??? lb636 S_BRANCH ??? lb635 # lb635 Label: lb635 # 637: OpLoad: FloatVector3: tmp637 << t # 638: OpCompositeConstruct: FloatVector3: tmp638 << const275, const275, const275 V_MOV_B32 vDst(VGPR740) src0(0_5_F) V_MOV_B32 vDst(VGPR741) src0(0_5_F) V_MOV_B32 vDst(VGPR742) src0(0_5_F) # 639: OpExtInst(FMix): FloatVector3: tmp639 << tmp637, const172, tmp638 V_MOV_B32 vDst(VGPR743) src0(1_0_F) V_MOV_B32 vDst(VGPR744) src0(1_0_F) V_MOV_B32 vDst(VGPR745) src0(1_0_F) V_SUBREV_F32 vDst(VGPR746) src0(VGPR740) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR746) src0(VGPR658) src1(VGPR746) // VOP2 V_MAD_F32 vDst(VGPR746) src0(VGPR743) src1(VGPR740) src2(VGPR746) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR747) src0(VGPR741) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR747) src0(VGPR659) src1(VGPR747) // VOP2 V_MAD_F32 vDst(VGPR747) src0(VGPR744) src1(VGPR741) src2(VGPR747) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR748) src0(VGPR742) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR748) src0(VGPR660) src1(VGPR748) // VOP2 V_MAD_F32 vDst(VGPR748) src0(VGPR745) src1(VGPR742) src2(VGPR748) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp639 >> t V_MOV_B32 vDst(VGPR658) src0(VGPR746) V_MOV_B32 vDst(VGPR659) src0(VGPR747) V_MOV_B32 vDst(VGPR660) src0(VGPR748) # OpBranch: to lb636 S_BRANCH ??? lb636 # lb636 Label: lb636 # 640: OpLoad: FloatVector3: tmp640 << t # 641: OpCompositeConstruct: FloatVector3: tmp641 << const92, const92, const92 V_MOV_B32 vDst(VGPR752) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR749) src0(VGPR752) V_MOV_B32 vDst(VGPR753) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR750) src0(VGPR753) V_MOV_B32 vDst(VGPR754) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR751) src0(VGPR754) # 642: OpCompositeConstruct: FloatVector3: tmp642 << const117, const117, const117 V_MOV_B32 vDst(VGPR755) src0(1_0_F) V_MOV_B32 vDst(VGPR756) src0(1_0_F) V_MOV_B32 vDst(VGPR757) src0(1_0_F) # 643: OpExtInst(FClamp): FloatVector3: tmp643 << tmp640, tmp641, tmp642 V_MAX_F32 vDst(VGPR758) src0(VGPR658) src1(VGPR749) // VOP2 V_MAX_F32 vDst(VGPR759) src0(VGPR659) src1(VGPR750) // VOP2 V_MAX_F32 vDst(VGPR760) src0(VGPR660) src1(VGPR751) // VOP2 V_MIN_F32 vDst(VGPR758) src0(VGPR758) src1(VGPR755) // VOP2 V_MIN_F32 vDst(VGPR759) src0(VGPR759) src1(VGPR756) // VOP2 V_MIN_F32 vDst(VGPR760) src0(VGPR760) src1(VGPR757) // VOP2 # OpReturnValue: : << tmp643 S_MOV_B32 sDst(M0) src0(SGPR222) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR758) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR759) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR760) S_SETPC_B64 sDst(SGPR220) src0(SGPR220) # Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) Function: Void mainImage(vf4;vf2;(, FloatVector2 main.fragCoord) S_MOV_B64 sDst(SGPR240) src0(EXEC) # lb89 Label: lb89 # 647: OpLoad: FloatVector2: tmp647 << fragCoord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR13) const: 0x0 V_MOVRELS_B32 vDst(VGPR814) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR815) src0(VGPR1) # 650: OpLoad: FloatVector3: tmp650 << iResolution S_LOAD_DWORDX2_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR[242:243]) S_WAITCNT 0 S_LOAD_DWORD_IMM offset(8) sBase(SGPR[0:1]) sDst(SGPR244) S_WAITCNT 0 # 651: OpVectorShuffle: FloatVector2: tmp651 << tmp650, tmp650, 0, 1 V_MOV_B32 vDst(VGPR816) src0(SGPR242) V_MOV_B32 vDst(VGPR817) src0(SGPR243) # 652: OpFDiv: FloatVector2: tmp652 << tmp647, tmp651 V_RCP_F32 vDst(VGPR818) src0(VGPR816) V_RCP_F32 vDst(VGPR819) src0(VGPR817) V_MUL_F32 vDst(VGPR818) src0(VGPR814) src1(VGPR818) // VOP2 V_MUL_F32 vDst(VGPR819) src0(VGPR815) src1(VGPR819) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR818) src0(VGPR818) src1(VGPR816) src2(VGPR814) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR819) src0(VGPR819) src1(VGPR817) src2(VGPR815) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 653: OpVectorTimesScalar: FloatVector2: tmp653 << tmp652, const227 V_MOV_B32 vDst(VGPR822) src0(2_0_F) V_MUL_F32 vDst(VGPR820) src0(VGPR822) src1(VGPR818) // VOP2 V_MUL_F32 vDst(VGPR821) src0(VGPR822) src1(VGPR819) // VOP2 # 654: OpCompositeConstruct: FloatVector2: tmp654 << const117, const117 V_MOV_B32 vDst(VGPR823) src0(1_0_F) V_MOV_B32 vDst(VGPR824) src0(1_0_F) # 655: OpFSub: FloatVector2: tmp655 << tmp653, tmp654 V_SUB_F32 vDst(VGPR825) src0(VGPR820) src1(VGPR823) // VOP2 V_SUB_F32 vDst(VGPR826) src0(VGPR821) src1(VGPR824) // VOP2 # OpStore: : tmp655 >> uv V_MOV_B32 vDst(VGPR761) src0(VGPR825) V_MOV_B32 vDst(VGPR762) src0(VGPR826) # 657: OpAccessChain: Float*: iResolution[0] # 658: OpLoad: Float: tmp658 << iResolution[0] S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR245) S_WAITCNT 0 # 659: OpAccessChain: Float*: iResolution[1] # 660: OpLoad: Float: tmp660 << iResolution[1] S_LOAD_DWORD_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR246) S_WAITCNT 0 # 661: OpFDiv: Float: tmp661 << tmp658, tmp660 V_MOV_B32 vDst(VGPR827) src0(SGPR246) V_RCP_F32 vDst(VGPR828) src0(VGPR827) V_MUL_F32 vDst(VGPR828) src0(SGPR245) src1(VGPR828) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR828) src0(VGPR828) src1(VGPR827) src2(SGPR245) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 662: OpAccessChain: Float*: uv[0] # 663: OpLoad: Float: tmp663 << uv[0] V_MOV_B32 vDst(VGPR829) src0(VGPR761) # 664: OpFMul: Float: tmp664 << tmp663, tmp661 V_MUL_F32 vDst(VGPR830) src0(VGPR829) src1(VGPR828) // VOP2 # 665: OpAccessChain: Float*: uv[0] # OpStore: : tmp664 >> uv[0] V_MOV_B32 vDst(VGPR761) src0(VGPR830) # 668: OpLoad: Float: tmp668 << iTime S_LOAD_DWORD_IMM offset(12) sBase(SGPR[0:1]) sDst(SGPR247) S_WAITCNT 0 # 669: OpFMul: Float: tmp669 << tmp668, const275 V_MOV_B32 vDst(VGPR831) src0(0_5_F) V_MUL_F32 vDst(VGPR832) src0(SGPR247) src1(VGPR831) // VOP2 # OpStore: : tmp669 >> time V_MOV_B32 vDst(VGPR763) src0(VGPR832) # 670: OpLoad: Float: tmp670 << time # 671: OpExtInst(Sin): Float: tmp671 << tmp670 V_MUL_F32 vDst(VGPR833) src0(LITERAL_CONST) src1(VGPR763) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR833) src0(VGPR833) V_SIN_F32 vDst(VGPR833) src0(VGPR833) # 672: OpFMul: Float: tmp672 << tmp671, const420 V_MOV_B32 vDst(VGPR834) src0(LITERAL_CONST) const: 0x3ecccccd V_MUL_F32 vDst(VGPR835) src0(VGPR833) src1(VGPR834) // VOP2 # OpStore: : tmp672 >> _twist V_MOV_B32 vDst(VGPR24) src0(VGPR835) # 674: OpLoad: Float: tmp674 << time # 676: OpFMul: Float: tmp676 << tmp674, const675 V_MOV_B32 vDst(VGPR836) src0(LITERAL_CONST) const: 0x40490fdb V_MUL_F32 vDst(VGPR837) src0(VGPR763) src1(VGPR836) // VOP2 # 677: OpFDiv: Float: tmp677 << tmp676, const227 V_MOV_B32 vDst(VGPR838) src0(2_0_F) V_RCP_F32 vDst(VGPR839) src0(VGPR838) V_MUL_F32 vDst(VGPR839) src0(VGPR837) src1(VGPR839) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR839) src0(VGPR839) src1(VGPR838) src2(VGPR837) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 678: OpFAdd: Float: tmp678 << tmp677, const117 V_MOV_B32 vDst(VGPR840) src0(1_0_F) V_ADD_F32 vDst(VGPR841) src0(VGPR839) src1(VGPR840) // VOP2 # 679: OpExtInst(Sin): Float: tmp679 << tmp678 V_MUL_F32 vDst(VGPR842) src0(LITERAL_CONST) src1(VGPR841) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR842) src0(VGPR842) V_SIN_F32 vDst(VGPR842) src0(VGPR842) # 680: OpFMul: Float: tmp680 << tmp679, const117 V_MOV_B32 vDst(VGPR843) src0(1_0_F) V_MUL_F32 vDst(VGPR844) src0(VGPR842) src1(VGPR843) // VOP2 # 681: OpLoad: Float: tmp681 << time # 682: OpCompositeConstruct: FloatVector3: tmp682 << tmp680, const92, tmp681 V_MOV_B32 vDst(VGPR845) src0(VGPR844) V_MOV_B32 vDst(VGPR848) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR846) src0(VGPR848) V_MOV_B32 vDst(VGPR847) src0(VGPR763) # OpStore: : tmp682 >> ro V_MOV_B32 vDst(VGPR764) src0(VGPR845) V_MOV_B32 vDst(VGPR765) src0(VGPR846) V_MOV_B32 vDst(VGPR766) src0(VGPR847) # 684: OpLoad: FloatVector2: tmp684 << uv # 686: OpCompositeExtract: Float: tmp686 << tmp684, 0 V_MOV_B32 vDst(VGPR849) src0(VGPR761) # 687: OpCompositeExtract: Float: tmp687 << tmp684, 1 V_MOV_B32 vDst(VGPR850) src0(VGPR762) # 688: OpCompositeConstruct: FloatVector3: tmp688 << tmp686, tmp687, const685 V_MOV_B32 vDst(VGPR851) src0(VGPR849) V_MOV_B32 vDst(VGPR852) src0(VGPR850) V_MOV_B32 vDst(VGPR854) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR853) src0(VGPR854) # 689: OpExtInst(Normalize): FloatVector3: tmp689 << tmp688 V_MUL_F32 vDst(VGPR855) src0(VGPR851) src1(VGPR851) // VOP2 V_MAC_F32 vDst(VGPR855) src0(VGPR852) src1(VGPR852) // VOP2 V_MAC_F32 vDst(VGPR855) src0(VGPR853) src1(VGPR853) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR855) src0(VGPR855) V_MUL_F32 vDst(VGPR856) src0(VGPR851) src1(VGPR855) // VOP2 V_MUL_F32 vDst(VGPR857) src0(VGPR852) src1(VGPR855) // VOP2 V_MUL_F32 vDst(VGPR858) src0(VGPR853) src1(VGPR855) // VOP2 # OpStore: : tmp689 >> rd V_MOV_B32 vDst(VGPR767) src0(VGPR856) V_MOV_B32 vDst(VGPR768) src0(VGPR857) V_MOV_B32 vDst(VGPR769) src0(VGPR858) # 690: OpLoad: Float: tmp690 << time # 691: OpFAdd: Float: tmp691 << tmp690, const227 V_MOV_B32 vDst(VGPR859) src0(2_0_F) V_ADD_F32 vDst(VGPR860) src0(VGPR763) src1(VGPR859) // VOP2 # OpStore: : tmp691 >> time V_MOV_B32 vDst(VGPR763) src0(VGPR860) # 693: OpLoad: Float: tmp693 << time # 694: OpFMul: Float: tmp694 << tmp693, const675 V_MOV_B32 vDst(VGPR861) src0(LITERAL_CONST) const: 0x40490fdb V_MUL_F32 vDst(VGPR862) src0(VGPR763) src1(VGPR861) // VOP2 # 695: OpFDiv: Float: tmp695 << tmp694, const227 V_MOV_B32 vDst(VGPR863) src0(2_0_F) V_RCP_F32 vDst(VGPR864) src0(VGPR863) V_MUL_F32 vDst(VGPR864) src0(VGPR862) src1(VGPR864) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR864) src0(VGPR864) src1(VGPR863) src2(VGPR862) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 696: OpFAdd: Float: tmp696 << tmp695, const117 V_MOV_B32 vDst(VGPR865) src0(1_0_F) V_ADD_F32 vDst(VGPR866) src0(VGPR864) src1(VGPR865) // VOP2 # 697: OpExtInst(Sin): Float: tmp697 << tmp696 V_MUL_F32 vDst(VGPR867) src0(LITERAL_CONST) src1(VGPR866) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR867) src0(VGPR867) V_SIN_F32 vDst(VGPR867) src0(VGPR867) # 698: OpFMul: Float: tmp698 << tmp697, const117 V_MOV_B32 vDst(VGPR868) src0(1_0_F) V_MUL_F32 vDst(VGPR869) src0(VGPR867) src1(VGPR868) // VOP2 # 699: OpLoad: Float: tmp699 << time # 700: OpCompositeConstruct: FloatVector3: tmp700 << tmp698, const92, tmp699 V_MOV_B32 vDst(VGPR870) src0(VGPR869) V_MOV_B32 vDst(VGPR873) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR871) src0(VGPR873) V_MOV_B32 vDst(VGPR872) src0(VGPR763) # OpStore: : tmp700 >> light V_MOV_B32 vDst(VGPR770) src0(VGPR870) V_MOV_B32 vDst(VGPR771) src0(VGPR871) V_MOV_B32 vDst(VGPR772) src0(VGPR872) # 701: OpLoad: Float: tmp701 << time # 702: OpFSub: Float: tmp702 << tmp701, const227 V_MOV_B32 vDst(VGPR874) src0(2_0_F) V_SUB_F32 vDst(VGPR875) src0(VGPR763) src1(VGPR874) // VOP2 # OpStore: : tmp702 >> time V_MOV_B32 vDst(VGPR763) src0(VGPR875) # 703: OpLoad: Float: tmp703 << time # 704: OpFMul: Float: tmp704 << tmp703, const675 V_MOV_B32 vDst(VGPR876) src0(LITERAL_CONST) const: 0x40490fdb V_MUL_F32 vDst(VGPR877) src0(VGPR763) src1(VGPR876) // VOP2 # 705: OpFDiv: Float: tmp705 << tmp704, const227 V_MOV_B32 vDst(VGPR878) src0(2_0_F) V_RCP_F32 vDst(VGPR879) src0(VGPR878) V_MUL_F32 vDst(VGPR879) src0(VGPR877) src1(VGPR879) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR879) src0(VGPR879) src1(VGPR878) src2(VGPR877) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 706: OpFAdd: Float: tmp706 << tmp705, const117 V_MOV_B32 vDst(VGPR880) src0(1_0_F) V_ADD_F32 vDst(VGPR881) src0(VGPR879) src1(VGPR880) // VOP2 # 707: OpExtInst(Cos): Float: tmp707 << tmp706 V_MUL_F32 vDst(VGPR882) src0(LITERAL_CONST) src1(VGPR881) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR882) src0(VGPR882) V_COS_F32 vDst(VGPR882) src0(VGPR882) # 708: OpFNegate: Float: tmp708 << tmp707 V_MUL_F32 vDst(VGPR883) src0(M1_0_F) src1(VGPR882) // VOP2 # 709: OpFMul: Float: tmp709 << tmp708, const275 V_MOV_B32 vDst(VGPR884) src0(0_5_F) V_MUL_F32 vDst(VGPR885) src0(VGPR883) src1(VGPR884) // VOP2 # 711: OpLoad: FloatVector3: tmp711 << rd # 712: OpVectorShuffle: FloatVector2: tmp712 << tmp711, tmp711, 0, 2 V_MOV_B32 vDst(VGPR886) src0(VGPR767) V_MOV_B32 vDst(VGPR887) src0(VGPR769) # OpStore: : tmp712 >> param710 V_MOV_B32 vDst(VGPR773) src0(VGPR886) V_MOV_B32 vDst(VGPR774) src0(VGPR887) # OpStore: : tmp709 >> param713 V_MOV_B32 vDst(VGPR775) src0(VGPR885) # 714: OpFunctionCall: Void: tRotate(vf2;f1;(param710, param713) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x305 # VGPR[773:774] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x307 # VGPR775 S_MOV_B64 sDst(SGPR248) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR248) # .lbl38 # 715: OpLoad: FloatVector2: tmp715 << param710 # 716: OpLoad: FloatVector3: tmp716 << rd # 717: OpVectorShuffle: FloatVector3: tmp717 << tmp716, tmp715, 3, 1, 4 V_MOV_B32 vDst(VGPR888) src0(VGPR773) V_MOV_B32 vDst(VGPR889) src0(VGPR768) V_MOV_B32 vDst(VGPR890) src0(VGPR774) # OpStore: : tmp717 >> rd V_MOV_B32 vDst(VGPR767) src0(VGPR888) V_MOV_B32 vDst(VGPR768) src0(VGPR889) V_MOV_B32 vDst(VGPR769) src0(VGPR890) # 718: OpAccessChain: Float*: ro[2] # 719: OpLoad: Float: tmp719 << ro[2] V_MOV_B32 vDst(VGPR891) src0(VGPR766) # 720: OpFNegate: Float: tmp720 << tmp719 V_MUL_F32 vDst(VGPR892) src0(M1_0_F) src1(VGPR891) // VOP2 # 721: OpLoad: Float: tmp721 << _twist # 722: OpFMul: Float: tmp722 << tmp720, tmp721 V_MUL_F32 vDst(VGPR893) src0(VGPR892) src1(VGPR24) // VOP2 # 724: OpLoad: FloatVector3: tmp724 << ro # 725: OpVectorShuffle: FloatVector2: tmp725 << tmp724, tmp724, 0, 1 V_MOV_B32 vDst(VGPR894) src0(VGPR764) V_MOV_B32 vDst(VGPR895) src0(VGPR765) # OpStore: : tmp725 >> param723 V_MOV_B32 vDst(VGPR776) src0(VGPR894) V_MOV_B32 vDst(VGPR777) src0(VGPR895) # OpStore: : tmp722 >> param726 V_MOV_B32 vDst(VGPR778) src0(VGPR893) # 727: OpFunctionCall: Void: tRotate(vf2;f1;(param723, param726) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x308 # VGPR[776:777] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x30a # VGPR778 S_MOV_B64 sDst(SGPR250) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR250) # .lbl39 # 728: OpLoad: FloatVector2: tmp728 << param723 # 729: OpLoad: FloatVector3: tmp729 << ro # 730: OpVectorShuffle: FloatVector3: tmp730 << tmp729, tmp728, 3, 4, 2 V_MOV_B32 vDst(VGPR896) src0(VGPR776) V_MOV_B32 vDst(VGPR897) src0(VGPR777) V_MOV_B32 vDst(VGPR898) src0(VGPR766) # OpStore: : tmp730 >> ro V_MOV_B32 vDst(VGPR764) src0(VGPR896) V_MOV_B32 vDst(VGPR765) src0(VGPR897) V_MOV_B32 vDst(VGPR766) src0(VGPR898) # 731: OpAccessChain: Float*: light[2] # 732: OpLoad: Float: tmp732 << light[2] V_MOV_B32 vDst(VGPR899) src0(VGPR772) # 733: OpFNegate: Float: tmp733 << tmp732 V_MUL_F32 vDst(VGPR900) src0(M1_0_F) src1(VGPR899) // VOP2 # 734: OpLoad: Float: tmp734 << _twist # 735: OpFMul: Float: tmp735 << tmp733, tmp734 V_MUL_F32 vDst(VGPR901) src0(VGPR900) src1(VGPR24) // VOP2 # 737: OpLoad: FloatVector3: tmp737 << light # 738: OpVectorShuffle: FloatVector2: tmp738 << tmp737, tmp737, 0, 1 V_MOV_B32 vDst(VGPR902) src0(VGPR770) V_MOV_B32 vDst(VGPR903) src0(VGPR771) # OpStore: : tmp738 >> param736 V_MOV_B32 vDst(VGPR779) src0(VGPR902) V_MOV_B32 vDst(VGPR780) src0(VGPR903) # OpStore: : tmp735 >> param739 V_MOV_B32 vDst(VGPR781) src0(VGPR901) # 740: OpFunctionCall: Void: tRotate(vf2;f1;(param736, param739) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x30b # VGPR[779:780] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x30d # VGPR781 S_MOV_B64 sDst(SGPR252) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR252) # .lbl40 # 741: OpLoad: FloatVector2: tmp741 << param736 # 742: OpLoad: FloatVector3: tmp742 << light # 743: OpVectorShuffle: FloatVector3: tmp743 << tmp742, tmp741, 3, 4, 2 V_MOV_B32 vDst(VGPR904) src0(VGPR779) V_MOV_B32 vDst(VGPR905) src0(VGPR780) V_MOV_B32 vDst(VGPR906) src0(VGPR772) # OpStore: : tmp743 >> light V_MOV_B32 vDst(VGPR770) src0(VGPR904) V_MOV_B32 vDst(VGPR771) src0(VGPR905) V_MOV_B32 vDst(VGPR772) src0(VGPR906) # 744: OpAccessChain: Float*: ro[2] # 745: OpLoad: Float: tmp745 << ro[2] V_MOV_B32 vDst(VGPR907) src0(VGPR766) # 746: OpFNegate: Float: tmp746 << tmp745 V_MUL_F32 vDst(VGPR908) src0(M1_0_F) src1(VGPR907) // VOP2 # 747: OpLoad: Float: tmp747 << _twist # 748: OpFMul: Float: tmp748 << tmp746, tmp747 V_MUL_F32 vDst(VGPR909) src0(VGPR908) src1(VGPR24) // VOP2 # 750: OpLoad: FloatVector3: tmp750 << rd # 751: OpVectorShuffle: FloatVector2: tmp751 << tmp750, tmp750, 0, 1 V_MOV_B32 vDst(VGPR910) src0(VGPR767) V_MOV_B32 vDst(VGPR911) src0(VGPR768) # OpStore: : tmp751 >> param749 V_MOV_B32 vDst(VGPR782) src0(VGPR910) V_MOV_B32 vDst(VGPR783) src0(VGPR911) # OpStore: : tmp748 >> param752 V_MOV_B32 vDst(VGPR784) src0(VGPR909) # 753: OpFunctionCall: Void: tRotate(vf2;f1;(param749, param752) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x30e # VGPR[782:783] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x310 # VGPR784 S_MOV_B64 sDst(SGPR254) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR254) # .lbl41 # 754: OpLoad: FloatVector2: tmp754 << param749 # 755: OpLoad: FloatVector3: tmp755 << rd # 756: OpVectorShuffle: FloatVector3: tmp756 << tmp755, tmp754, 3, 4, 2 V_MOV_B32 vDst(VGPR912) src0(VGPR782) V_MOV_B32 vDst(VGPR913) src0(VGPR783) V_MOV_B32 vDst(VGPR914) src0(VGPR769) # OpStore: : tmp756 >> rd V_MOV_B32 vDst(VGPR767) src0(VGPR912) V_MOV_B32 vDst(VGPR768) src0(VGPR913) V_MOV_B32 vDst(VGPR769) src0(VGPR914) # 760: OpLoad: FloatVector3: tmp760 << ro # OpStore: : tmp760 >> param759 V_MOV_B32 vDst(VGPR785) src0(VGPR764) V_MOV_B32 vDst(VGPR786) src0(VGPR765) V_MOV_B32 vDst(VGPR787) src0(VGPR766) # 762: OpLoad: FloatVector3: tmp762 << rd # OpStore: : tmp762 >> param761 V_MOV_B32 vDst(VGPR788) src0(VGPR767) V_MOV_B32 vDst(VGPR789) src0(VGPR768) V_MOV_B32 vDst(VGPR790) src0(VGPR769) # OpStore: : const220 >> param763 V_MOV_B32 vDst(VGPR915) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR791) src0(VGPR915) # 765: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param759, param761, param763, param764) S_ADD_U32 sDst(SGPR149) src0(LITERAL_CONST) src1(0) const: 0x311 # VGPR[785:787] S_ADD_U32 sDst(SGPR150) src0(LITERAL_CONST) src1(0) const: 0x314 # VGPR[788:790] S_ADD_U32 sDst(SGPR151) src0(LITERAL_CONST) src1(0) const: 0x317 # VGPR791 S_ADD_U32 sDst(SGPR152) src0(LITERAL_CONST) src1(0) const: 0x318 # VGPR792 S_MOV_B64 sDst(SGPR256) src0(EXEC) S_MOV_B32 sDst(SGPR148) src0(LITERAL_CONST) const: 0x394 # VGPR916 # Indirect branch to trace(vf3;vf3;f1;f1;: ??? S_GETPC_B64 sDst(SGPR146) src0(SGPR146) S_ADD_U32 sDst(SGPR146) src0(SGPR146) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR147) src0(SGPR147) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR146) src0(SGPR146) S_MOV_B64 sDst(EXEC) src0(SGPR256) # .lbl42 # 766: OpLoad: Float: tmp766 << param764 # 768: OpLoad: FloatVector3: tmp768 << ro # 769: OpLoad: FloatVector3: tmp769 << rd # 771: OpVectorTimesScalar: FloatVector3: tmp771 << tmp769, trace(vf3;vf3;f1;f1; V_MUL_F32 vDst(VGPR917) src0(VGPR916) src1(VGPR767) // VOP2 V_MUL_F32 vDst(VGPR918) src0(VGPR916) src1(VGPR768) // VOP2 V_MUL_F32 vDst(VGPR919) src0(VGPR916) src1(VGPR769) // VOP2 # 772: OpFAdd: FloatVector3: tmp772 << tmp768, tmp771 V_ADD_F32 vDst(VGPR920) src0(VGPR764) src1(VGPR917) // VOP2 V_ADD_F32 vDst(VGPR921) src0(VGPR765) src1(VGPR918) // VOP2 V_ADD_F32 vDst(VGPR922) src0(VGPR766) src1(VGPR919) // VOP2 # OpStore: : tmp772 >> param774 V_MOV_B32 vDst(VGPR793) src0(VGPR920) V_MOV_B32 vDst(VGPR794) src0(VGPR921) V_MOV_B32 vDst(VGPR795) src0(VGPR922) # 776: OpFunctionCall: FloatVector3: getNormal(vf3;(param774) S_ADD_U32 sDst(SGPR177) src0(LITERAL_CONST) src1(0) const: 0x319 # VGPR[793:795] S_MOV_B64 sDst(SGPR258) src0(EXEC) S_MOV_B32 sDst(SGPR176) src0(LITERAL_CONST) const: 0x39b # VGPR[923:925] # Indirect branch to getNormal(vf3;: ??? S_GETPC_B64 sDst(SGPR174) src0(SGPR174) S_ADD_U32 sDst(SGPR174) src0(SGPR174) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR175) src0(SGPR175) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR174) src0(SGPR174) S_MOV_B64 sDst(EXEC) src0(SGPR258) # .lbl43 # 778: OpLoad: FloatVector3: tmp778 << light # 780: OpFSub: FloatVector3: tmp780 << tmp778, tmp772 V_SUB_F32 vDst(VGPR926) src0(VGPR770) src1(VGPR920) // VOP2 V_SUB_F32 vDst(VGPR927) src0(VGPR771) src1(VGPR921) // VOP2 V_SUB_F32 vDst(VGPR928) src0(VGPR772) src1(VGPR922) // VOP2 # 781: OpExtInst(Normalize): FloatVector3: tmp781 << tmp780 V_MUL_F32 vDst(VGPR929) src0(VGPR926) src1(VGPR926) // VOP2 V_MAC_F32 vDst(VGPR929) src0(VGPR927) src1(VGPR927) // VOP2 V_MAC_F32 vDst(VGPR929) src0(VGPR928) src1(VGPR928) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR929) src0(VGPR929) V_MUL_F32 vDst(VGPR930) src0(VGPR926) src1(VGPR929) // VOP2 V_MUL_F32 vDst(VGPR931) src0(VGPR927) src1(VGPR929) // VOP2 V_MUL_F32 vDst(VGPR932) src0(VGPR928) src1(VGPR929) // VOP2 # 785: OpVectorTimesScalar: FloatVector3: tmp785 << getNormal(vf3;, const467 V_MOV_B32 vDst(VGPR936) src0(LITERAL_CONST) const: 0x3727c5ac V_MUL_F32 vDst(VGPR933) src0(VGPR936) src1(VGPR923) // VOP2 V_MUL_F32 vDst(VGPR934) src0(VGPR936) src1(VGPR924) // VOP2 V_MUL_F32 vDst(VGPR935) src0(VGPR936) src1(VGPR925) // VOP2 # 786: OpVectorTimesScalar: FloatVector3: tmp786 << tmp785, const220 V_MOV_B32 vDst(VGPR940) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR937) src0(VGPR940) src1(VGPR933) // VOP2 V_MUL_F32 vDst(VGPR938) src0(VGPR940) src1(VGPR934) // VOP2 V_MUL_F32 vDst(VGPR939) src0(VGPR940) src1(VGPR935) // VOP2 # 787: OpFAdd: FloatVector3: tmp787 << tmp772, tmp786 V_ADD_F32 vDst(VGPR941) src0(VGPR920) src1(VGPR937) // VOP2 V_ADD_F32 vDst(VGPR942) src0(VGPR921) src1(VGPR938) // VOP2 V_ADD_F32 vDst(VGPR943) src0(VGPR922) src1(VGPR939) // VOP2 # 790: OpLoad: FloatVector3: tmp790 << light # 791: OpExtInst(Distance): Float: tmp791 << tmp787, tmp790 V_SUB_F32 vDst(VGPR944) src0(VGPR941) src1(VGPR770) // VOP2 V_SUB_F32 vDst(VGPR945) src0(VGPR942) src1(VGPR771) // VOP2 V_SUB_F32 vDst(VGPR946) src0(VGPR943) src1(VGPR772) // VOP2 V_MUL_F32 vDst(VGPR947) src0(VGPR944) src1(VGPR944) // VOP2 V_MAC_F32 vDst(VGPR947) src0(VGPR945) src1(VGPR945) // VOP2 V_MAC_F32 vDst(VGPR947) src0(VGPR946) src1(VGPR946) // VOP2 V_SQRT_F32 vDst(VGPR947) src0(VGPR947) # OpStore: : tmp787 >> param794 V_MOV_B32 vDst(VGPR797) src0(VGPR941) V_MOV_B32 vDst(VGPR798) src0(VGPR942) V_MOV_B32 vDst(VGPR799) src0(VGPR943) # OpStore: : tmp781 >> param796 V_MOV_B32 vDst(VGPR800) src0(VGPR930) V_MOV_B32 vDst(VGPR801) src0(VGPR931) V_MOV_B32 vDst(VGPR802) src0(VGPR932) # OpStore: : tmp791 >> param798 V_MOV_B32 vDst(VGPR803) src0(VGPR947) # 801: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param794, param796, param798, param800) S_ADD_U32 sDst(SGPR149) src0(LITERAL_CONST) src1(0) const: 0x31d # VGPR[797:799] S_ADD_U32 sDst(SGPR150) src0(LITERAL_CONST) src1(0) const: 0x320 # VGPR[800:802] S_ADD_U32 sDst(SGPR151) src0(LITERAL_CONST) src1(0) const: 0x323 # VGPR803 S_ADD_U32 sDst(SGPR152) src0(LITERAL_CONST) src1(0) const: 0x324 # VGPR804 S_MOV_B64 sDst(SGPR260) src0(EXEC) S_MOV_B32 sDst(SGPR148) src0(LITERAL_CONST) const: 0x3b4 # VGPR948 # Indirect branch to trace(vf3;vf3;f1;f1;: ??? S_GETPC_B64 sDst(SGPR146) src0(SGPR146) S_ADD_U32 sDst(SGPR146) src0(SGPR146) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR147) src0(SGPR147) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR146) src0(SGPR146) S_MOV_B64 sDst(EXEC) src0(SGPR260) # .lbl44 # 802: OpLoad: Float: tmp802 << param800 # 804: OpFOrdGreaterThan: Bool: tmp804 << trace(vf3;vf3;f1;f1;, tmp791 V_CMP_GT_F32 dst(SGPR262) src0(VGPR948) src1(VGPR947) // VOP3a # 805: OpSelect: Float: tmp805 << tmp804, const117, const92 # CF Block: Merge: .lbl46 S_MOV_B64 sDst(SGPR264) src0(EXEC) # CF Block: Cond Branch: true: .lbl47, false: .lbl45 S_AND_B64 sDst(EXEC) src0(SGPR262) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl45 S_BRANCH ??? .lbl47 Label: .lbl47 V_MOV_B32 vDst(VGPR949) src0(1_0_F) S_BRANCH ??? .lbl46 Label: .lbl45 V_MOV_B32 vDst(VGPR950) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR949) src0(VGPR950) S_BRANCH ??? .lbl46 Label: .lbl46 # OpStore: : tmp805 >> shadow V_MOV_B32 vDst(VGPR796) src0(VGPR949) # 808: OpFDiv: Float: tmp808 << tmp802, const807 V_MOV_B32 vDst(VGPR951) src0(LITERAL_CONST) const: 0x42c80000 V_RCP_F32 vDst(VGPR952) src0(VGPR951) V_MUL_F32 vDst(VGPR952) src0(VGPR804) src1(VGPR952) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR952) src0(VGPR952) src1(VGPR951) src2(VGPR804) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 809: OpExtInst(Sqrt): Float: tmp809 << tmp808 V_SQRT_F32 vDst(VGPR953) src0(VGPR952) # 810: OpFSub: Float: tmp810 << const117, tmp809 V_SUB_F32 vDst(VGPR954) src0(1_0_F) src1(VGPR953) // VOP2 # 811: OpLoad: Float: tmp811 << shadow # 812: OpFMul: Float: tmp812 << tmp811, tmp810 V_MUL_F32 vDst(VGPR955) src0(VGPR796) src1(VGPR954) // VOP2 # OpStore: : tmp812 >> shadow V_MOV_B32 vDst(VGPR796) src0(VGPR955) # 817: OpDot: Float: tmp817 << tmp781, getNormal(vf3; V_MUL_F32 vDst(VGPR956) src0(VGPR930) src1(VGPR923) // VOP2 V_MAC_F32 vDst(VGPR956) src0(VGPR931) src1(VGPR924) // VOP2 V_MAC_F32 vDst(VGPR956) src0(VGPR932) src1(VGPR925) // VOP2 # 818: OpExtInst(FMax): Float: tmp818 << const92, tmp817 V_MOV_B32 vDst(VGPR957) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR958) src0(VGPR957) src1(VGPR956) // VOP2 # 821: OpFNegate: FloatVector3: tmp821 << tmp781 V_MUL_F32 vDst(VGPR959) src0(M1_0_F) src1(VGPR930) // VOP2 V_MUL_F32 vDst(VGPR960) src0(M1_0_F) src1(VGPR931) // VOP2 V_MUL_F32 vDst(VGPR961) src0(M1_0_F) src1(VGPR932) // VOP2 # 823: OpExtInst(Reflect): FloatVector3: tmp823 << tmp821, getNormal(vf3; V_MUL_F32 vDst(VGPR965) src0(VGPR959) src1(VGPR923) // VOP2 V_MAC_F32 vDst(VGPR965) src0(VGPR960) src1(VGPR924) // VOP2 V_MAC_F32 vDst(VGPR965) src0(VGPR961) src1(VGPR925) // VOP2 V_MUL_F32 vDst(VGPR965) src0(2_0_F) src1(VGPR965) // VOP2 V_MUL_F32 vDst(VGPR962) src0(VGPR923) src1(VGPR965) // VOP2 V_MUL_F32 vDst(VGPR963) src0(VGPR924) src1(VGPR965) // VOP2 V_MUL_F32 vDst(VGPR964) src0(VGPR925) src1(VGPR965) // VOP2 V_SUB_F32 vDst(VGPR962) src0(VGPR959) src1(VGPR962) // VOP2 V_SUB_F32 vDst(VGPR963) src0(VGPR960) src1(VGPR963) // VOP2 V_SUB_F32 vDst(VGPR964) src0(VGPR961) src1(VGPR964) // VOP2 # 824: OpLoad: FloatVector3: tmp824 << rd # 825: OpFNegate: FloatVector3: tmp825 << tmp824 V_MUL_F32 vDst(VGPR966) src0(M1_0_F) src1(VGPR767) // VOP2 V_MUL_F32 vDst(VGPR967) src0(M1_0_F) src1(VGPR768) // VOP2 V_MUL_F32 vDst(VGPR968) src0(M1_0_F) src1(VGPR769) // VOP2 # 826: OpDot: Float: tmp826 << tmp823, tmp825 V_MUL_F32 vDst(VGPR969) src0(VGPR962) src1(VGPR966) // VOP2 V_MAC_F32 vDst(VGPR969) src0(VGPR963) src1(VGPR967) // VOP2 V_MAC_F32 vDst(VGPR969) src0(VGPR964) src1(VGPR968) // VOP2 # 827: OpExtInst(FMax): Float: tmp827 << const92, tmp826 V_MOV_B32 vDst(VGPR970) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR971) src0(VGPR970) src1(VGPR969) // VOP2 # 829: OpExtInst(Pow): Float: tmp829 << tmp827, const828 V_MOV_B32 vDst(VGPR972) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR973) src0(VGPR971) V_MUL_F32 vDst(VGPR973) src0(VGPR972) src1(VGPR973) // VOP2 V_EXP_F32 vDst(VGPR973) src0(VGPR973) # OpStore: : tmp772 >> param831 V_MOV_B32 vDst(VGPR805) src0(VGPR920) V_MOV_B32 vDst(VGPR806) src0(VGPR921) V_MOV_B32 vDst(VGPR807) src0(VGPR922) # OpStore: : getNormal(vf3; >> param833 V_MOV_B32 vDst(VGPR808) src0(VGPR923) V_MOV_B32 vDst(VGPR809) src0(VGPR924) V_MOV_B32 vDst(VGPR810) src0(VGPR925) # 835: OpFunctionCall: Float: calculateAO(vf3;vf3;(param831, param833) S_ADD_U32 sDst(SGPR195) src0(LITERAL_CONST) src1(0) const: 0x325 # VGPR[805:807] S_ADD_U32 sDst(SGPR196) src0(LITERAL_CONST) src1(0) const: 0x328 # VGPR[808:810] S_MOV_B64 sDst(SGPR266) src0(EXEC) S_MOV_B32 sDst(SGPR194) src0(LITERAL_CONST) const: 0x3ce # VGPR974 # Indirect branch to calculateAO(vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR192) src0(SGPR192) S_ADD_U32 sDst(SGPR192) src0(SGPR192) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR193) src0(SGPR193) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR192) src0(SGPR192) S_MOV_B64 sDst(EXEC) src0(SGPR266) # .lbl48 # OpStore: : tmp772 >> param837 V_MOV_B32 vDst(VGPR811) src0(VGPR920) V_MOV_B32 vDst(VGPR812) src0(VGPR921) V_MOV_B32 vDst(VGPR813) src0(VGPR922) # 839: OpFunctionCall: FloatVector3: _texture(vf3;(param837) S_ADD_U32 sDst(SGPR223) src0(LITERAL_CONST) src1(0) const: 0x32b # VGPR[811:813] S_MOV_B64 sDst(SGPR268) src0(EXEC) S_MOV_B32 sDst(SGPR222) src0(LITERAL_CONST) const: 0x3cf # VGPR[975:977] # Indirect branch to _texture(vf3;: ??? S_GETPC_B64 sDst(SGPR220) src0(SGPR220) S_ADD_U32 sDst(SGPR220) src0(SGPR220) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR221) src0(SGPR221) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR220) src0(SGPR220) S_MOV_B64 sDst(EXEC) src0(SGPR268) # .lbl49 # 840: OpVectorTimesScalar: FloatVector3: tmp840 << _texture(vf3;, calculateAO(vf3;vf3; V_MUL_F32 vDst(VGPR978) src0(VGPR974) src1(VGPR975) // VOP2 V_MUL_F32 vDst(VGPR979) src0(VGPR974) src1(VGPR976) // VOP2 V_MUL_F32 vDst(VGPR980) src0(VGPR974) src1(VGPR977) // VOP2 # 844: OpFAdd: Float: tmp844 << tmp829, tmp818 V_ADD_F32 vDst(VGPR981) src0(VGPR973) src1(VGPR958) // VOP2 # 845: OpLoad: Float: tmp845 << shadow # 846: OpFMul: Float: tmp846 << tmp844, tmp845 V_MUL_F32 vDst(VGPR982) src0(VGPR981) src1(VGPR796) // VOP2 # 847: OpFAdd: Float: tmp847 << const363, tmp846 V_MOV_B32 vDst(VGPR983) src0(LITERAL_CONST) const: 0x3e800000 V_ADD_F32 vDst(VGPR984) src0(VGPR983) src1(VGPR982) // VOP2 # 848: OpVectorTimesScalar: FloatVector3: tmp848 << tmp840, tmp847 V_MUL_F32 vDst(VGPR985) src0(VGPR984) src1(VGPR978) // VOP2 V_MUL_F32 vDst(VGPR986) src0(VGPR984) src1(VGPR979) // VOP2 V_MUL_F32 vDst(VGPR987) src0(VGPR984) src1(VGPR980) // VOP2 # 849: OpLoad: FloatVector4: tmp849 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR988) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR989) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR990) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR991) src0(VGPR3) # 850: OpVectorShuffle: FloatVector4: tmp850 << tmp849, tmp848, 4, 5, 6, 3 V_MOV_B32 vDst(VGPR992) src0(VGPR985) V_MOV_B32 vDst(VGPR993) src0(VGPR986) V_MOV_B32 vDst(VGPR994) src0(VGPR987) V_MOV_B32 vDst(VGPR995) src0(VGPR991) # OpStore: : tmp850 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR992) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR993) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR994) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR995) # 852: OpFDiv: Float: tmp852 << tmp766, const807 V_MOV_B32 vDst(VGPR996) src0(LITERAL_CONST) const: 0x42c80000 V_RCP_F32 vDst(VGPR997) src0(VGPR996) V_MUL_F32 vDst(VGPR997) src0(VGPR792) src1(VGPR997) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR997) src0(VGPR997) src1(VGPR996) src2(VGPR792) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 853: OpExtInst(Sqrt): Float: tmp853 << tmp852 V_SQRT_F32 vDst(VGPR998) src0(VGPR997) # 854: OpLoad: FloatVector4: tmp854 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR999) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1000) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1001) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1002) src0(VGPR3) # 855: OpVectorTimesScalar: FloatVector4: tmp855 << tmp854, tmp853 V_MUL_F32 vDst(VGPR1003) src0(VGPR998) src1(VGPR999) // VOP2 V_MUL_F32 vDst(VGPR1004) src0(VGPR998) src1(VGPR1000) // VOP2 V_MUL_F32 vDst(VGPR1005) src0(VGPR998) src1(VGPR1001) // VOP2 V_MUL_F32 vDst(VGPR1006) src0(VGPR998) src1(VGPR1002) // VOP2 # OpStore: : tmp855 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1003) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1004) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1005) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1006) # 856: OpLoad: FloatVector4: tmp856 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1007) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1008) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1009) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1010) src0(VGPR3) # 860: OpFMul: Float: tmp860 << trace(vf3;vf3;f1;f1;, trace(vf3;vf3;f1;f1; V_MUL_F32 vDst(VGPR1011) src0(VGPR916) src1(VGPR916) // VOP2 # 862: OpFMul: Float: tmp862 << tmp860, const861 V_MOV_B32 vDst(VGPR1012) src0(LITERAL_CONST) const: 0x3cf5c28f V_MUL_F32 vDst(VGPR1013) src0(VGPR1011) src1(VGPR1012) // VOP2 # 863: OpExtInst(FClamp): Float: tmp863 << tmp862, const92, const117 V_MOV_B32 vDst(VGPR1014) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1015) src0(1_0_F) V_MAX_F32 vDst(VGPR1016) src0(VGPR1013) src1(VGPR1014) // VOP2 V_MIN_F32 vDst(VGPR1016) src0(VGPR1016) src1(VGPR1015) // VOP2 # 864: OpCompositeConstruct: FloatVector4: tmp864 << tmp863, tmp863, tmp863, tmp863 V_MOV_B32 vDst(VGPR1017) src0(VGPR1016) V_MOV_B32 vDst(VGPR1018) src0(VGPR1016) V_MOV_B32 vDst(VGPR1019) src0(VGPR1016) V_MOV_B32 vDst(VGPR1020) src0(VGPR1016) # 865: OpExtInst(FMix): FloatVector4: tmp865 << tmp856, const857, tmp864 V_MOV_B32 vDst(VGPR1021) src0(LITERAL_CONST) const: 0x3f666666 V_MOV_B32 vDst(VGPR1022) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR1023) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR1024) src0(1_0_F) V_SUBREV_F32 vDst(VGPR1025) src0(VGPR1017) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1025) src0(VGPR1007) src1(VGPR1025) // VOP2 V_MAD_F32 vDst(VGPR1025) src0(VGPR1021) src1(VGPR1017) src2(VGPR1025) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1026) src0(VGPR1018) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1026) src0(VGPR1008) src1(VGPR1026) // VOP2 V_MAD_F32 vDst(VGPR1026) src0(VGPR1022) src1(VGPR1018) src2(VGPR1026) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1027) src0(VGPR1019) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1027) src0(VGPR1009) src1(VGPR1027) // VOP2 V_MAD_F32 vDst(VGPR1027) src0(VGPR1023) src1(VGPR1019) src2(VGPR1027) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1028) src0(VGPR1020) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1028) src0(VGPR1010) src1(VGPR1028) // VOP2 V_MAD_F32 vDst(VGPR1028) src0(VGPR1024) src1(VGPR1020) src2(VGPR1028) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp865 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1025) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1026) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1027) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1028) # 866: OpLoad: FloatVector4: tmp866 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1029) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1030) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1031) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1032) src0(VGPR3) # 869: OpExtInst(Pow): FloatVector4: tmp869 << tmp866, const868 V_MOV_B32 vDst(VGPR1033) src0(LITERAL_CONST) const: 0x3ee8ba2f V_MOV_B32 vDst(VGPR1034) src0(LITERAL_CONST) const: 0x3ee8ba2f V_MOV_B32 vDst(VGPR1035) src0(LITERAL_CONST) const: 0x3ee8ba2f V_MOV_B32 vDst(VGPR1036) src0(LITERAL_CONST) const: 0x3ee8ba2f V_LOG_F32 vDst(VGPR1037) src0(VGPR1029) V_LOG_F32 vDst(VGPR1038) src0(VGPR1030) V_LOG_F32 vDst(VGPR1039) src0(VGPR1031) V_LOG_F32 vDst(VGPR1040) src0(VGPR1032) V_MUL_F32 vDst(VGPR1037) src0(VGPR1033) src1(VGPR1037) // VOP2 V_MUL_F32 vDst(VGPR1038) src0(VGPR1034) src1(VGPR1038) // VOP2 V_MUL_F32 vDst(VGPR1039) src0(VGPR1035) src1(VGPR1039) // VOP2 V_MUL_F32 vDst(VGPR1040) src0(VGPR1036) src1(VGPR1040) // VOP2 V_EXP_F32 vDst(VGPR1037) src0(VGPR1037) V_EXP_F32 vDst(VGPR1038) src0(VGPR1038) V_EXP_F32 vDst(VGPR1039) src0(VGPR1039) V_EXP_F32 vDst(VGPR1040) src0(VGPR1040) # OpStore: : tmp869 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1037) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1038) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1039) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1040) # OpReturn: S_SETPC_B64 sDst(SGPR10) src0(SGPR10) Performing GPU-specific optimization... Pre register allocation control-flow processing... Intermediate disassembly (pre register allocation): Program Type: Fragment Special Input Variables: offset: unset, size: 16, FloatVector4 gl_FragCoord BuiltIn(FragCoord) Textures: offset: 0, size: 4, Float iChannel0 offset: 1, size: 4, Float iChannel1 offset: 2, size: 4, Float iChannel2 offset: 3, size: 4, Float iChannel3 Output Variables: offset: 0, size: 16, FloatVector4 finalColor Uniform Constants: offset: 0, size: 12, FloatVector3 iResolution offset: 12, size: 4, Float iTime offset: 16, size: 16, FloatVector4 iMouse offset: 32, size: 16, FloatVector4 iDate offset: 48, size: 4, Float iFrame offset: 52, size: 48, FloatVector3 iChannelResolution[4] Private Global Variables: offset: unset, size: 4, Float _twist Constants: Float const92: 0 Float const95: 0.0091239 Float const96: 0.00231233 Float const97: 0.00532234 FloatVector3 const98: {0.0091239, 0.00231233, 0.00532234} Float const101: 111112 FloatVector3 const112: {0, 0, 0} Float const117: 1 FloatVector3 const118: {0, 1, 0} FloatVector3 const123: {1, 0, 0} FloatVector3 const128: {1, 1, 0} UInt32 const139: 1 UInt32 const146: 0 FloatVector3 const157: {0, 0, 1} FloatVector3 const162: {0, 1, 1} FloatVector3 const167: {1, 0, 1} FloatVector3 const172: {1, 1, 1} UInt32 const198: 2 Int32 const210: 0 Int32 const217: 5 Float const220: 10 Float const227: 2 Int32 const234: 1 Float const275: 0.5 Float const333: 0.7 FloatVector2 const334: {0.7, 1} Float const355: 0.15 Float const360: 0.75 FloatVector2 const361: {0, 0.75} Float const363: 0.25 Float const369: 0.375 FloatVector2 const370: {0, 0.375} FloatVector2 const372: {0.25, 0.375} Float const386: 0.35 FloatVector2 const387: {0, 0.35} Float const389: 0.45 Float const390: 0.3 FloatVector2 const391: {0.45, 0.3} FloatVector2 const401: {0.35, 0} Float const403: 0.075 Float const417: 0.6 FloatVector2 const418: {0.6, 0.5} Float const420: 0.4 FloatVector2 const421: {0.6, 0.4} Float const434: 0.8 Int32 const451: 100 Float const467: 1e-05 Float const482: 0.0001 FloatVector2 const483: {0.0001, 0} Float const536: 5 Float const606: 0.1 Float const607: 0.9 Float const617: 20 FloatVector3 const618: {5, 20, 5} FloatVector3 const622: {1, 0.7, 0.4} FloatVector3 const626: {2, 10, 2} FloatVector3 const630: {1, 0.8, 0.5} Float const675: 3.14159 Float const685: 1.5 Float const807: 100 Float const828: 8 FloatVector4 const857: {0.9, 0.8, 0.7, 1} Float const861: 0.03 Float const867: 0.454545 FloatVector4 const868: {0.454545, 0.454545, 0.454545, 0.454545} UInt32 const886: 4 Function Local Variables: offset: unset, size: 16, FloatVector4 main.param873 offset: unset, size: 8, FloatVector2 main.param874 offset: unset, size: 16, FloatVector4 main.fragColor offset: unset, size: 8, FloatVector2 main.fragCoord offset: unset, size: 12, FloatVector3 main.uv offset: unset, size: 12, FloatVector3 hash(vf3;.uv offset: unset, size: 12, FloatVector3 noise(vf3;.param114 offset: unset, size: 12, FloatVector3 noise(vf3;.param120 offset: unset, size: 12, FloatVector3 noise(vf3;.param125 offset: unset, size: 12, FloatVector3 noise(vf3;.param130 offset: unset, size: 12, FloatVector3 noise(vf3;.param159 offset: unset, size: 12, FloatVector3 noise(vf3;.param164 offset: unset, size: 12, FloatVector3 noise(vf3;.param169 offset: unset, size: 12, FloatVector3 noise(vf3;.param174 offset: unset, size: 12, FloatVector3 noise(vf3;.uv offset: unset, size: 4, Float fbm(vf3;.f offset: unset, size: 4, Float fbm(vf3;.r offset: unset, size: 4, Int32 fbm(vf3;.i offset: unset, size: 12, FloatVector3 fbm(vf3;.param225 offset: unset, size: 8, FloatVector2 fbm(vf3;.p offset: unset, size: 4, Float fbm(vf3;.angel offset: unset, size: 12, FloatVector3 tRotate(vf2;f1;.p offset: unset, size: 4, Float tRotate(vf2;f1;.a offset: unset, size: 8, FloatVector2 tTwist(vf3;f1;.param264 offset: unset, size: 4, Float tTwist(vf3;f1;.param267 offset: unset, size: 8, FloatVector2 tTwist(vf3;f1;.p offset: unset, size: 8, FloatVector2 tTwist(vf3;f1;.r offset: unset, size: 8, FloatVector2 tRepeat2(vf2;vf2;.p offset: unset, size: 8, FloatVector2 tRepeat2(vf2;vf2;.r offset: unset, size: 8, FloatVector2 sdRect(vf2;vf2;.p offset: unset, size: 4, Float sdRect(vf2;vf2;.r offset: unset, size: 4, Float sdCircle(vf2;f1;.a offset: unset, size: 4, Float sdCircle(vf2;f1;.b offset: unset, size: 4, Float opU(f1;f1;.a offset: unset, size: 4, Float opU(f1;f1;.b offset: unset, size: 12, FloatVector3 opS(f1;f1;.p offset: unset, size: 12, FloatVector3 map(vf3;.param327 offset: unset, size: 4, Float map(vf3;.param329 offset: unset, size: 8, FloatVector2 map(vf3;.param335 offset: unset, size: 8, FloatVector2 map(vf3;.param338 offset: unset, size: 4, Float map(vf3;.d offset: unset, size: 8, FloatVector2 map(vf3;.param364 offset: unset, size: 4, Float map(vf3;.param365 offset: unset, size: 8, FloatVector2 map(vf3;.param373 offset: unset, size: 8, FloatVector2 map(vf3;.param374 offset: unset, size: 4, Float map(vf3;.param376 offset: unset, size: 4, Float map(vf3;.param377 offset: unset, size: 4, Float map(vf3;.param379 offset: unset, size: 4, Float map(vf3;.param381 offset: unset, size: 8, FloatVector2 map(vf3;.param392 offset: unset, size: 8, FloatVector2 map(vf3;.param393 offset: unset, size: 4, Float map(vf3;.param395 offset: unset, size: 4, Float map(vf3;.param397 offset: unset, size: 8, FloatVector2 map(vf3;.param404 offset: unset, size: 4, Float map(vf3;.param405 offset: unset, size: 4, Float map(vf3;.param407 offset: unset, size: 4, Float map(vf3;.param409 offset: unset, size: 8, FloatVector2 map(vf3;.param422 offset: unset, size: 8, FloatVector2 map(vf3;.param423 offset: unset, size: 4, Float map(vf3;.param425 offset: unset, size: 4, Float map(vf3;.param427 offset: unset, size: 4, Float map(vf3;.param436 offset: unset, size: 4, Float map(vf3;.param438 offset: unset, size: 12, FloatVector3 map(vf3;.ro offset: unset, size: 12, FloatVector3 map(vf3;.rd offset: unset, size: 4, Float map(vf3;.maxDist offset: unset, size: 4, Float map(vf3;.steps offset: unset, size: 4, Float trace(vf3;vf3;f1;f1;.total offset: unset, size: 4, Int32 trace(vf3;vf3;f1;f1;.i offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param461 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.p offset: unset, size: 12, FloatVector3 getNormal(vf3;.param488 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param494 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param501 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param507 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param514 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param520 offset: unset, size: 12, FloatVector3 getNormal(vf3;.p offset: unset, size: 12, FloatVector3 getNormal(vf3;.n offset: unset, size: 4, Float calculateAO(vf3;vf3;.r offset: unset, size: 4, Float calculateAO(vf3;vf3;.w offset: unset, size: 4, Float calculateAO(vf3;vf3;.i offset: unset, size: 12, FloatVector3 calculateAO(vf3;vf3;.param549 offset: unset, size: 12, FloatVector3 calculateAO(vf3;vf3;.p offset: unset, size: 8, FloatVector2 isWall(vf3;.param569 offset: unset, size: 8, FloatVector2 isWall(vf3;.param572 offset: unset, size: 12, FloatVector3 isWall(vf3;.p offset: unset, size: 12, FloatVector3 _texture(vf3;.param588 offset: unset, size: 4, Float _texture(vf3;.param590 offset: unset, size: 12, FloatVector3 _texture(vf3;.param596 offset: unset, size: 12, FloatVector3 _texture(vf3;.t offset: unset, size: 4, Float _texture(vf3;.var601 offset: unset, size: 12, FloatVector3 _texture(vf3;.param610 offset: unset, size: 12, FloatVector3 _texture(vf3;.param620 offset: unset, size: 12, FloatVector3 _texture(vf3;.param628 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.uv offset: unset, size: 4, Float mainImage(vf4;vf2;.time offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.ro offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.rd offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.light offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param710 offset: unset, size: 4, Float mainImage(vf4;vf2;.param713 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param723 offset: unset, size: 4, Float mainImage(vf4;vf2;.param726 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param736 offset: unset, size: 4, Float mainImage(vf4;vf2;.param739 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param749 offset: unset, size: 4, Float mainImage(vf4;vf2;.param752 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param759 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param761 offset: unset, size: 4, Float mainImage(vf4;vf2;.param763 offset: unset, size: 4, Float mainImage(vf4;vf2;.param764 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param774 offset: unset, size: 4, Float mainImage(vf4;vf2;.shadow offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param794 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param796 offset: unset, size: 4, Float mainImage(vf4;vf2;.param798 offset: unset, size: 4, Float mainImage(vf4;vf2;.param800 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param831 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param833 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param837 Instructions: V_SUB_F32 vDst(VGPR14) src0(SGPR2) src1(VGPR14) // VOP2 # Void main() Function: Void main() # lb5 Label: lb5 # OpStore: : const92 >> _twist V_MOV_B32 vDst(VGPR25) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR24) src0(VGPR25) # 875: OpLoad: FloatVector4: tmp875 << gl_FragCoord V_MOV_B32 vDst(VGPR26) src0(VGPR13) V_MOV_B32 vDst(VGPR27) src0(VGPR14) V_MOV_B32 vDst(VGPR28) src0(VGPR15) V_MOV_B32 vDst(VGPR29) src0(VGPR16) # 876: OpVectorShuffle: FloatVector2: tmp876 << tmp875, tmp875, 0, 1 V_MOV_B32 vDst(VGPR30) src0(VGPR26) V_MOV_B32 vDst(VGPR31) src0(VGPR27) # OpStore: : tmp876 >> param874 V_MOV_B32 vDst(VGPR22) src0(VGPR30) V_MOV_B32 vDst(VGPR23) src0(VGPR31) # 877: OpFunctionCall: Void: mainImage(vf4;vf2;(param873, param874) S_ADD_U32 sDst(SGPR12) src0(LITERAL_CONST) src1(0) const: 0x12 # VGPR[18:21] S_ADD_U32 sDst(SGPR13) src0(LITERAL_CONST) src1(0) const: 0x16 # VGPR[22:23] S_MOV_B64 sDst(SGPR14) src0(EXEC) # Indirect branch to mainImage(vf4;vf2;: ??? S_GETPC_B64 sDst(SGPR10) src0(SGPR10) S_ADD_U32 sDst(SGPR10) src0(SGPR10) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR11) src0(SGPR11) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR10) src0(SGPR10) S_MOV_B64 sDst(EXEC) src0(SGPR14) # .lbl0 # 878: OpLoad: FloatVector4: tmp878 << param873 # OpStore: : tmp878 >> finalColor V_MOV_B32 vDst(VGPR32) src0(VGPR18) V_MOV_B32 vDst(VGPR33) src0(VGPR19) V_MOV_B32 vDst(VGPR34) src0(VGPR20) V_MOV_B32 vDst(VGPR35) src0(VGPR21) # OpReturn: V_CVT_PKRTZ_F16_F32 vDst(VGPR32) src0(VGPR32) src1(VGPR33) // VOP2 V_CVT_PKRTZ_F16_F32 vDst(VGPR33) src0(VGPR34) src1(VGPR35) // VOP2 EXP en(0xf) tgt(0) compr(1) done(1) vm(1) vsrc0(VGPR32) vsrc1(VGPR33) vsrc2(VGPR34) vsrc3(VGPR35) S_WAITCNT 0 S_ENDPGM 0 # Float hash(vf3;(FloatVector3* uv) Function: Float hash(vf3;() S_MOV_B64 sDst(SGPR20) src0(EXEC) # lb12 Label: lb12 # 94: OpLoad: FloatVector3: tmp94 << uv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR19) const: 0x0 V_MOVRELS_B32 vDst(VGPR36) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR37) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR38) src0(VGPR2) # 99: OpDot: Float: tmp99 << tmp94, const98 V_MOV_B32 vDst(VGPR39) src0(LITERAL_CONST) const: 0x3c157c67 V_MOV_B32 vDst(VGPR40) src0(LITERAL_CONST) const: 0x3b178a76 V_MOV_B32 vDst(VGPR41) src0(LITERAL_CONST) const: 0x3bae6706 V_MUL_F32 vDst(VGPR42) src0(VGPR36) src1(VGPR39) // VOP2 V_MAC_F32 vDst(VGPR42) src0(VGPR37) src1(VGPR40) // VOP2 V_MAC_F32 vDst(VGPR42) src0(VGPR38) src1(VGPR41) // VOP2 # 100: OpExtInst(Sin): Float: tmp100 << tmp99 V_MUL_F32 vDst(VGPR43) src0(LITERAL_CONST) src1(VGPR42) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR43) src0(VGPR43) V_SIN_F32 vDst(VGPR43) src0(VGPR43) # 102: OpFMul: Float: tmp102 << tmp100, const101 V_MOV_B32 vDst(VGPR44) src0(LITERAL_CONST) const: 0x47d903c6 V_MUL_F32 vDst(VGPR45) src0(VGPR43) src1(VGPR44) // VOP2 # 103: OpExtInst(Fract): Float: tmp103 << tmp102 V_FRACT_F32 vDst(VGPR46) src0(VGPR45) # OpReturnValue: : << tmp103 S_MOV_B32 sDst(M0) src0(SGPR18) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR46) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # Float noise(vf3;(FloatVector3* uv) Function: Float noise(vf3;() S_MOV_B64 sDst(SGPR26) src0(EXEC) # lb15 Label: lb15 # 108: OpLoad: FloatVector3: tmp108 << uv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR71) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR72) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR73) src0(VGPR2) # 109: OpExtInst(Floor): FloatVector3: tmp109 << tmp108 V_FLOOR_F32 vDst(VGPR74) src0(VGPR71) V_FLOOR_F32 vDst(VGPR75) src0(VGPR72) V_FLOOR_F32 vDst(VGPR76) src0(VGPR73) # 113: OpFAdd: FloatVector3: tmp113 << tmp109, const112 V_MOV_B32 vDst(VGPR77) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR78) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR79) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR80) src0(VGPR74) src1(VGPR77) // VOP2 V_ADD_F32 vDst(VGPR81) src0(VGPR75) src1(VGPR78) // VOP2 V_ADD_F32 vDst(VGPR82) src0(VGPR76) src1(VGPR79) // VOP2 # OpStore: : tmp113 >> param114 V_MOV_B32 vDst(VGPR47) src0(VGPR80) V_MOV_B32 vDst(VGPR48) src0(VGPR81) V_MOV_B32 vDst(VGPR49) src0(VGPR82) # 115: OpFunctionCall: Float: hash(vf3;(param114) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x2f # VGPR[47:49] S_MOV_B64 sDst(SGPR28) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x53 # VGPR83 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR28) # .lbl1 # 119: OpFAdd: FloatVector3: tmp119 << tmp109, const118 V_MOV_B32 vDst(VGPR84) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR85) src0(1_0_F) V_MOV_B32 vDst(VGPR86) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR87) src0(VGPR74) src1(VGPR84) // VOP2 V_ADD_F32 vDst(VGPR88) src0(VGPR75) src1(VGPR85) // VOP2 V_ADD_F32 vDst(VGPR89) src0(VGPR76) src1(VGPR86) // VOP2 # OpStore: : tmp119 >> param120 V_MOV_B32 vDst(VGPR50) src0(VGPR87) V_MOV_B32 vDst(VGPR51) src0(VGPR88) V_MOV_B32 vDst(VGPR52) src0(VGPR89) # 121: OpFunctionCall: Float: hash(vf3;(param120) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x32 # VGPR[50:52] S_MOV_B64 sDst(SGPR30) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x5a # VGPR90 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR30) # .lbl2 # 124: OpFAdd: FloatVector3: tmp124 << tmp109, const123 V_MOV_B32 vDst(VGPR91) src0(1_0_F) V_MOV_B32 vDst(VGPR92) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR93) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR94) src0(VGPR74) src1(VGPR91) // VOP2 V_ADD_F32 vDst(VGPR95) src0(VGPR75) src1(VGPR92) // VOP2 V_ADD_F32 vDst(VGPR96) src0(VGPR76) src1(VGPR93) // VOP2 # OpStore: : tmp124 >> param125 V_MOV_B32 vDst(VGPR53) src0(VGPR94) V_MOV_B32 vDst(VGPR54) src0(VGPR95) V_MOV_B32 vDst(VGPR55) src0(VGPR96) # 126: OpFunctionCall: Float: hash(vf3;(param125) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x35 # VGPR[53:55] S_MOV_B64 sDst(SGPR32) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x61 # VGPR97 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR32) # .lbl3 # 129: OpFAdd: FloatVector3: tmp129 << tmp109, const128 V_MOV_B32 vDst(VGPR98) src0(1_0_F) V_MOV_B32 vDst(VGPR99) src0(1_0_F) V_MOV_B32 vDst(VGPR100) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR101) src0(VGPR74) src1(VGPR98) // VOP2 V_ADD_F32 vDst(VGPR102) src0(VGPR75) src1(VGPR99) // VOP2 V_ADD_F32 vDst(VGPR103) src0(VGPR76) src1(VGPR100) // VOP2 # OpStore: : tmp129 >> param130 V_MOV_B32 vDst(VGPR56) src0(VGPR101) V_MOV_B32 vDst(VGPR57) src0(VGPR102) V_MOV_B32 vDst(VGPR58) src0(VGPR103) # 131: OpFunctionCall: Float: hash(vf3;(param130) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x38 # VGPR[56:58] S_MOV_B64 sDst(SGPR34) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x68 # VGPR104 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR34) # .lbl4 # 132: OpCompositeConstruct: FloatVector4: tmp132 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; V_MOV_B32 vDst(VGPR105) src0(VGPR83) V_MOV_B32 vDst(VGPR106) src0(VGPR90) V_MOV_B32 vDst(VGPR107) src0(VGPR97) V_MOV_B32 vDst(VGPR108) src0(VGPR104) # 135: OpVectorShuffle: FloatVector2: tmp135 << tmp132, tmp132, 0, 2 V_MOV_B32 vDst(VGPR109) src0(VGPR105) V_MOV_B32 vDst(VGPR110) src0(VGPR107) # 137: OpVectorShuffle: FloatVector2: tmp137 << tmp132, tmp132, 1, 3 V_MOV_B32 vDst(VGPR111) src0(VGPR106) V_MOV_B32 vDst(VGPR112) src0(VGPR108) # 140: OpAccessChain: Float*: uv[1] # 141: OpLoad: Float: tmp141 << uv[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR113) src0(VGPR1) # 142: OpExtInst(Fract): Float: tmp142 << tmp141 V_FRACT_F32 vDst(VGPR114) src0(VGPR113) # 143: OpCompositeConstruct: FloatVector2: tmp143 << tmp142, tmp142 V_MOV_B32 vDst(VGPR115) src0(VGPR114) V_MOV_B32 vDst(VGPR116) src0(VGPR114) # 144: OpExtInst(FMix): FloatVector2: tmp144 << tmp135, tmp137, tmp143 V_SUBREV_F32 vDst(VGPR117) src0(VGPR115) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR117) src0(VGPR109) src1(VGPR117) // VOP2 V_MAD_F32 vDst(VGPR117) src0(VGPR111) src1(VGPR115) src2(VGPR117) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR118) src0(VGPR116) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR118) src0(VGPR110) src1(VGPR118) // VOP2 V_MAD_F32 vDst(VGPR118) src0(VGPR112) src1(VGPR116) src2(VGPR118) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 147: OpAccessChain: Float*: axis0[0] # 148: OpCompositeExtract: Float: tmp148 << tmp144, 0 V_MOV_B32 vDst(VGPR119) src0(VGPR117) # 149: OpAccessChain: Float*: axis0[1] # 150: OpCompositeExtract: Float: tmp150 << tmp144, 1 V_MOV_B32 vDst(VGPR120) src0(VGPR118) # 151: OpAccessChain: Float*: uv[0] # 152: OpLoad: Float: tmp152 << uv[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR121) src0(VGPR0) # 153: OpExtInst(Fract): Float: tmp153 << tmp152 V_FRACT_F32 vDst(VGPR122) src0(VGPR121) # 154: OpExtInst(FMix): Float: tmp154 << tmp148, tmp150, tmp153 V_SUBREV_F32 vDst(VGPR123) src0(VGPR122) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR123) src0(VGPR119) src1(VGPR123) // VOP2 V_MAD_F32 vDst(VGPR123) src0(VGPR120) src1(VGPR122) src2(VGPR123) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 158: OpFAdd: FloatVector3: tmp158 << tmp109, const157 V_MOV_B32 vDst(VGPR124) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR125) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR126) src0(1_0_F) V_ADD_F32 vDst(VGPR127) src0(VGPR74) src1(VGPR124) // VOP2 V_ADD_F32 vDst(VGPR128) src0(VGPR75) src1(VGPR125) // VOP2 V_ADD_F32 vDst(VGPR129) src0(VGPR76) src1(VGPR126) // VOP2 # OpStore: : tmp158 >> param159 V_MOV_B32 vDst(VGPR59) src0(VGPR127) V_MOV_B32 vDst(VGPR60) src0(VGPR128) V_MOV_B32 vDst(VGPR61) src0(VGPR129) # 160: OpFunctionCall: Float: hash(vf3;(param159) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x3b # VGPR[59:61] S_MOV_B64 sDst(SGPR36) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x82 # VGPR130 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR36) # .lbl5 # 163: OpFAdd: FloatVector3: tmp163 << tmp109, const162 V_MOV_B32 vDst(VGPR131) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR132) src0(1_0_F) V_MOV_B32 vDst(VGPR133) src0(1_0_F) V_ADD_F32 vDst(VGPR134) src0(VGPR74) src1(VGPR131) // VOP2 V_ADD_F32 vDst(VGPR135) src0(VGPR75) src1(VGPR132) // VOP2 V_ADD_F32 vDst(VGPR136) src0(VGPR76) src1(VGPR133) // VOP2 # OpStore: : tmp163 >> param164 V_MOV_B32 vDst(VGPR62) src0(VGPR134) V_MOV_B32 vDst(VGPR63) src0(VGPR135) V_MOV_B32 vDst(VGPR64) src0(VGPR136) # 165: OpFunctionCall: Float: hash(vf3;(param164) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x3e # VGPR[62:64] S_MOV_B64 sDst(SGPR38) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x89 # VGPR137 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR38) # .lbl6 # 168: OpFAdd: FloatVector3: tmp168 << tmp109, const167 V_MOV_B32 vDst(VGPR138) src0(1_0_F) V_MOV_B32 vDst(VGPR139) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR140) src0(1_0_F) V_ADD_F32 vDst(VGPR141) src0(VGPR74) src1(VGPR138) // VOP2 V_ADD_F32 vDst(VGPR142) src0(VGPR75) src1(VGPR139) // VOP2 V_ADD_F32 vDst(VGPR143) src0(VGPR76) src1(VGPR140) // VOP2 # OpStore: : tmp168 >> param169 V_MOV_B32 vDst(VGPR65) src0(VGPR141) V_MOV_B32 vDst(VGPR66) src0(VGPR142) V_MOV_B32 vDst(VGPR67) src0(VGPR143) # 170: OpFunctionCall: Float: hash(vf3;(param169) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x41 # VGPR[65:67] S_MOV_B64 sDst(SGPR40) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x90 # VGPR144 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR40) # .lbl7 # 173: OpFAdd: FloatVector3: tmp173 << tmp109, const172 V_MOV_B32 vDst(VGPR145) src0(1_0_F) V_MOV_B32 vDst(VGPR146) src0(1_0_F) V_MOV_B32 vDst(VGPR147) src0(1_0_F) V_ADD_F32 vDst(VGPR148) src0(VGPR74) src1(VGPR145) // VOP2 V_ADD_F32 vDst(VGPR149) src0(VGPR75) src1(VGPR146) // VOP2 V_ADD_F32 vDst(VGPR150) src0(VGPR76) src1(VGPR147) // VOP2 # OpStore: : tmp173 >> param174 V_MOV_B32 vDst(VGPR68) src0(VGPR148) V_MOV_B32 vDst(VGPR69) src0(VGPR149) V_MOV_B32 vDst(VGPR70) src0(VGPR150) # 175: OpFunctionCall: Float: hash(vf3;(param174) S_ADD_U32 sDst(SGPR19) src0(LITERAL_CONST) src1(0) const: 0x44 # VGPR[68:70] S_MOV_B64 sDst(SGPR42) src0(EXEC) S_MOV_B32 sDst(SGPR18) src0(LITERAL_CONST) const: 0x97 # VGPR151 # Indirect branch to hash(vf3;: ??? S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_ADD_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR42) # .lbl8 # 176: OpCompositeConstruct: FloatVector4: tmp176 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; V_MOV_B32 vDst(VGPR152) src0(VGPR130) V_MOV_B32 vDst(VGPR153) src0(VGPR137) V_MOV_B32 vDst(VGPR154) src0(VGPR144) V_MOV_B32 vDst(VGPR155) src0(VGPR151) # 179: OpVectorShuffle: FloatVector2: tmp179 << tmp176, tmp176, 0, 2 V_MOV_B32 vDst(VGPR156) src0(VGPR152) V_MOV_B32 vDst(VGPR157) src0(VGPR154) # 181: OpVectorShuffle: FloatVector2: tmp181 << tmp176, tmp176, 1, 3 V_MOV_B32 vDst(VGPR158) src0(VGPR153) V_MOV_B32 vDst(VGPR159) src0(VGPR155) # 182: OpAccessChain: Float*: uv[1] # 183: OpLoad: Float: tmp183 << uv[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR160) src0(VGPR1) # 184: OpExtInst(Fract): Float: tmp184 << tmp183 V_FRACT_F32 vDst(VGPR161) src0(VGPR160) # 185: OpCompositeConstruct: FloatVector2: tmp185 << tmp184, tmp184 V_MOV_B32 vDst(VGPR162) src0(VGPR161) V_MOV_B32 vDst(VGPR163) src0(VGPR161) # 186: OpExtInst(FMix): FloatVector2: tmp186 << tmp179, tmp181, tmp185 V_SUBREV_F32 vDst(VGPR164) src0(VGPR162) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR164) src0(VGPR156) src1(VGPR164) // VOP2 V_MAD_F32 vDst(VGPR164) src0(VGPR158) src1(VGPR162) src2(VGPR164) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR165) src0(VGPR163) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR165) src0(VGPR157) src1(VGPR165) // VOP2 V_MAD_F32 vDst(VGPR165) src0(VGPR159) src1(VGPR163) src2(VGPR165) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 188: OpAccessChain: Float*: axis1[0] # 189: OpCompositeExtract: Float: tmp189 << tmp186, 0 V_MOV_B32 vDst(VGPR166) src0(VGPR164) # 190: OpAccessChain: Float*: axis1[1] # 191: OpCompositeExtract: Float: tmp191 << tmp186, 1 V_MOV_B32 vDst(VGPR167) src0(VGPR165) # 192: OpAccessChain: Float*: uv[0] # 193: OpLoad: Float: tmp193 << uv[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR168) src0(VGPR0) # 194: OpExtInst(Fract): Float: tmp194 << tmp193 V_FRACT_F32 vDst(VGPR169) src0(VGPR168) # 195: OpExtInst(FMix): Float: tmp195 << tmp189, tmp191, tmp194 V_SUBREV_F32 vDst(VGPR170) src0(VGPR169) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR170) src0(VGPR166) src1(VGPR170) // VOP2 V_MAD_F32 vDst(VGPR170) src0(VGPR167) src1(VGPR169) src2(VGPR170) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 199: OpAccessChain: Float*: uv[2] # 200: OpLoad: Float: tmp200 << uv[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR25) const: 0x0 V_MOVRELS_B32 vDst(VGPR171) src0(VGPR2) # 201: OpExtInst(Fract): Float: tmp201 << tmp200 V_FRACT_F32 vDst(VGPR172) src0(VGPR171) # 202: OpExtInst(FMix): Float: tmp202 << tmp154, tmp195, tmp201 V_SUBREV_F32 vDst(VGPR173) src0(VGPR172) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR173) src0(VGPR123) src1(VGPR173) // VOP2 V_MAD_F32 vDst(VGPR173) src0(VGPR170) src1(VGPR172) src2(VGPR173) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp202 S_MOV_B32 sDst(M0) src0(SGPR24) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR173) S_SETPC_B64 sDst(SGPR22) src0(SGPR22) # Float fbm(vf3;(FloatVector3* uv) Function: Float fbm(vf3;() S_MOV_B64 sDst(SGPR48) src0(EXEC) # lb18 Label: lb18 # OpStore: : const92 >> f V_MOV_B32 vDst(VGPR180) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR174) src0(VGPR180) # OpStore: : const117 >> r V_MOV_B32 vDst(VGPR175) src0(1_0_F) # OpStore: : const210 >> i V_MOV_B32 vDst(VGPR176) src0(0) # OpBranch: to lb211 # lb211 Label: lb211 # OpLoopMerge: (merge: lb213, continue: lb214) # CF Block: Merge: lb213, Continue: lb214 S_MOV_B64 sDst(SGPR50) src0(EXEC) S_MOV_B64 sDst(SGPR52) src0(EXEC) S_MOV_B64 sDst(SGPR54) src0(EXEC) Label: lb211Loop # OpBranch: to lb215 # lb215 Label: lb215 # 216: OpLoad: Int: tmp216 << i Decorators: RelaxedPrecision # 218: OpSLessThan: Bool: tmp218 << tmp216, const217 V_MOV_B32 vDst(VGPR181) src0(5_INT) V_CMP_LT_I32 dst(SGPR56) src0(VGPR176) src1(VGPR181) // VOP3a # OpBranchConditional: if(tmp218) then branch to lb212, else branch to lb213 # CF Block: Cond Branch: true: lb212, false: lb213 S_AND_B64 sDst(EXEC) src0(SGPR56) src1(EXEC) S_CBRANCH_EXECZ ??? lb213 # lb212 Label: lb212 S_MOV_B64 sDst(SGPR52) src0(EXEC) S_MOV_B64 sDst(SGPR54) src0(EXEC) # 219: OpLoad: FloatVector3: tmp219 << uv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR47) const: 0x0 V_MOVRELS_B32 vDst(VGPR182) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR183) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR184) src0(VGPR2) # 221: OpCompositeConstruct: FloatVector3: tmp221 << const220, const220, const220 V_MOV_B32 vDst(VGPR188) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR185) src0(VGPR188) V_MOV_B32 vDst(VGPR189) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR186) src0(VGPR189) V_MOV_B32 vDst(VGPR190) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR187) src0(VGPR190) # 222: OpFAdd: FloatVector3: tmp222 << tmp219, tmp221 V_ADD_F32 vDst(VGPR191) src0(VGPR182) src1(VGPR185) // VOP2 V_ADD_F32 vDst(VGPR192) src0(VGPR183) src1(VGPR186) // VOP2 V_ADD_F32 vDst(VGPR193) src0(VGPR184) src1(VGPR187) // VOP2 # 223: OpLoad: Float: tmp223 << r # 224: OpVectorTimesScalar: FloatVector3: tmp224 << tmp222, tmp223 V_MUL_F32 vDst(VGPR194) src0(VGPR175) src1(VGPR191) // VOP2 V_MUL_F32 vDst(VGPR195) src0(VGPR175) src1(VGPR192) // VOP2 V_MUL_F32 vDst(VGPR196) src0(VGPR175) src1(VGPR193) // VOP2 # OpStore: : tmp224 >> param225 V_MOV_B32 vDst(VGPR177) src0(VGPR194) V_MOV_B32 vDst(VGPR178) src0(VGPR195) V_MOV_B32 vDst(VGPR179) src0(VGPR196) # 226: OpFunctionCall: Float: noise(vf3;(param225) S_ADD_U32 sDst(SGPR25) src0(LITERAL_CONST) src1(0) const: 0xb1 # VGPR[177:179] S_MOV_B64 sDst(SGPR58) src0(EXEC) S_MOV_B32 sDst(SGPR24) src0(LITERAL_CONST) const: 0xc5 # VGPR197 # Indirect branch to noise(vf3;: ??? S_GETPC_B64 sDst(SGPR22) src0(SGPR22) S_ADD_U32 sDst(SGPR22) src0(SGPR22) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR23) src0(SGPR23) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR22) src0(SGPR22) S_MOV_B64 sDst(EXEC) src0(SGPR58) # .lbl9 # 228: OpLoad: Float: tmp228 << r # 229: OpFMul: Float: tmp229 << tmp228, const227 V_MOV_B32 vDst(VGPR198) src0(2_0_F) V_MUL_F32 vDst(VGPR199) src0(VGPR175) src1(VGPR198) // VOP2 # OpStore: : tmp229 >> r V_MOV_B32 vDst(VGPR175) src0(VGPR199) # 230: OpFDiv: Float: tmp230 << noise(vf3;, tmp229 V_RCP_F32 vDst(VGPR200) src0(VGPR199) V_MUL_F32 vDst(VGPR200) src0(VGPR197) src1(VGPR200) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR200) src0(VGPR200) src1(VGPR199) src2(VGPR197) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 231: OpLoad: Float: tmp231 << f # 232: OpFAdd: Float: tmp232 << tmp231, tmp230 V_ADD_F32 vDst(VGPR201) src0(VGPR174) src1(VGPR200) // VOP2 # OpStore: : tmp232 >> f V_MOV_B32 vDst(VGPR174) src0(VGPR201) # OpBranch: to lb214 # lb214 Label: lb214 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR52) # 233: OpLoad: Int: tmp233 << i Decorators: RelaxedPrecision # 235: OpIAdd: Int: tmp235 << tmp233, const234 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR202) src0(1_INT) V_ADD_I32 vDst(VGPR203) src0(VGPR176) src1(VGPR202) // VOP2 # OpStore: : tmp235 >> i V_MOV_B32 vDst(VGPR176) src0(VGPR203) # OpBranch: to lb211 S_BRANCH ??? lb211Loop # lb213 Label: lb213 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR50) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR48) # 236: OpLoad: Float: tmp236 << f # 237: OpLoad: Float: tmp237 << r # 238: OpFDiv: Float: tmp238 << const117, tmp237 V_RCP_F32 vDst(VGPR204) src0(VGPR175) V_MUL_F32 vDst(VGPR204) src0(1_0_F) src1(VGPR204) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR204) src0(VGPR204) src1(VGPR175) src2(1_0_F) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 239: OpFSub: Float: tmp239 << const117, tmp238 V_SUB_F32 vDst(VGPR205) src0(1_0_F) src1(VGPR204) // VOP2 # 240: OpFDiv: Float: tmp240 << tmp236, tmp239 V_RCP_F32 vDst(VGPR206) src0(VGPR205) V_MUL_F32 vDst(VGPR206) src0(VGPR174) src1(VGPR206) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR206) src0(VGPR206) src1(VGPR205) src2(VGPR174) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp240 S_MOV_B32 sDst(M0) src0(SGPR46) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR206) S_SETPC_B64 sDst(SGPR44) src0(SGPR44) # Void tRotate(vf2;f1;(FloatVector2* p, Float* angel) Function: Void tRotate(vf2;f1;(, Float fbm(vf3;.angel) S_MOV_B64 sDst(SGPR64) src0(EXEC) # lb26 Label: lb26 # 244: OpLoad: Float: tmp244 << angel S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR63) const: 0x0 V_MOVRELS_B32 vDst(VGPR207) src0(VGPR0) # 245: OpExtInst(Sin): Float: tmp245 << tmp244 V_MUL_F32 vDst(VGPR208) src0(LITERAL_CONST) src1(VGPR207) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR208) src0(VGPR208) V_SIN_F32 vDst(VGPR208) src0(VGPR208) # 247: OpLoad: Float: tmp247 << angel S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR63) const: 0x0 V_MOVRELS_B32 vDst(VGPR209) src0(VGPR0) # 248: OpExtInst(Cos): Float: tmp248 << tmp247 V_MUL_F32 vDst(VGPR210) src0(LITERAL_CONST) src1(VGPR209) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR210) src0(VGPR210) V_COS_F32 vDst(VGPR210) src0(VGPR210) # 251: OpFNegate: Float: tmp251 << tmp245 V_MUL_F32 vDst(VGPR211) src0(M1_0_F) src1(VGPR208) // VOP2 # 255: OpCompositeConstruct: FloatVector2: tmp255 << tmp248, tmp251 V_MOV_B32 vDst(VGPR212) src0(VGPR210) V_MOV_B32 vDst(VGPR213) src0(VGPR211) # 256: OpCompositeConstruct: FloatVector2: tmp256 << tmp245, tmp248 V_MOV_B32 vDst(VGPR214) src0(VGPR208) V_MOV_B32 vDst(VGPR215) src0(VGPR210) # 257: OpCompositeConstruct: FloatMatrix2x2: tmp257 << tmp255, tmp256 V_MOV_B32 vDst(VGPR216) src0(VGPR212) V_MOV_B32 vDst(VGPR217) src0(VGPR213) V_MOV_B32 vDst(VGPR218) src0(VGPR214) V_MOV_B32 vDst(VGPR219) src0(VGPR215) # 258: OpLoad: FloatVector2: tmp258 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR62) const: 0x0 V_MOVRELS_B32 vDst(VGPR220) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR221) src0(VGPR1) # 259: OpVectorTimesMatrix: FloatVector2: tmp259 << tmp258, tmp257 V_MUL_F32 vDst(VGPR222) src0(VGPR220) src1(VGPR216) // VOP2 V_MUL_F32 vDst(VGPR223) src0(VGPR220) src1(VGPR218) // VOP2 V_MAC_F32 vDst(VGPR222) src0(VGPR221) src1(VGPR217) // VOP2 V_MAC_F32 vDst(VGPR223) src0(VGPR221) src1(VGPR219) // VOP2 # OpStore: : tmp259 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR62) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR222) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR223) # OpReturn: S_SETPC_B64 sDst(SGPR60) src0(SGPR60) # Void tTwist(vf3;f1;(FloatVector3* p, Float* a) Function: Void tTwist(vf3;f1;(, Float tRotate(vf2;f1;.a) S_MOV_B64 sDst(SGPR70) src0(EXEC) # lb31 Label: lb31 # 260: OpAccessChain: Float*: p[2] # 261: OpLoad: Float: tmp261 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR68) const: 0x0 V_MOVRELS_B32 vDst(VGPR227) src0(VGPR2) # 262: OpLoad: Float: tmp262 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR69) const: 0x0 V_MOVRELS_B32 vDst(VGPR228) src0(VGPR0) # 263: OpFMul: Float: tmp263 << tmp261, tmp262 V_MUL_F32 vDst(VGPR229) src0(VGPR227) src1(VGPR228) // VOP2 # 265: OpLoad: FloatVector3: tmp265 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR68) const: 0x0 V_MOVRELS_B32 vDst(VGPR230) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR231) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR232) src0(VGPR2) # 266: OpVectorShuffle: FloatVector2: tmp266 << tmp265, tmp265, 0, 1 V_MOV_B32 vDst(VGPR233) src0(VGPR230) V_MOV_B32 vDst(VGPR234) src0(VGPR231) # OpStore: : tmp266 >> param264 V_MOV_B32 vDst(VGPR224) src0(VGPR233) V_MOV_B32 vDst(VGPR225) src0(VGPR234) # OpStore: : tmp263 >> param267 V_MOV_B32 vDst(VGPR226) src0(VGPR229) # 268: OpFunctionCall: Void: tRotate(vf2;f1;(param264, param267) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0xe0 # VGPR[224:225] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0xe2 # VGPR226 S_MOV_B64 sDst(SGPR72) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR72) # .lbl10 # 269: OpLoad: FloatVector2: tmp269 << param264 # 270: OpLoad: FloatVector3: tmp270 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR68) const: 0x0 V_MOVRELS_B32 vDst(VGPR235) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR236) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR237) src0(VGPR2) # 271: OpVectorShuffle: FloatVector3: tmp271 << tmp270, tmp269, 3, 4, 2 V_MOV_B32 vDst(VGPR238) src0(VGPR224) V_MOV_B32 vDst(VGPR239) src0(VGPR225) V_MOV_B32 vDst(VGPR240) src0(VGPR237) # OpStore: : tmp271 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR68) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR238) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR239) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR240) # OpReturn: S_SETPC_B64 sDst(SGPR66) src0(SGPR66) # FloatVector2 tRepeat2(vf2;vf2;(FloatVector2* p, FloatVector2* r) Function: FloatVector2 tRepeat2(vf2;vf2;(, FloatVector2 tTwist(vf3;f1;.r) S_MOV_B64 sDst(SGPR80) src0(EXEC) # lb36 Label: lb36 # 273: OpLoad: FloatVector2: tmp273 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELS_B32 vDst(VGPR241) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR242) src0(VGPR1) # 274: OpLoad: FloatVector2: tmp274 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR243) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR244) src0(VGPR1) # 276: OpVectorTimesScalar: FloatVector2: tmp276 << tmp274, const275 V_MOV_B32 vDst(VGPR247) src0(0_5_F) V_MUL_F32 vDst(VGPR245) src0(VGPR247) src1(VGPR243) // VOP2 V_MUL_F32 vDst(VGPR246) src0(VGPR247) src1(VGPR244) // VOP2 # 277: OpFAdd: FloatVector2: tmp277 << tmp273, tmp276 V_ADD_F32 vDst(VGPR248) src0(VGPR241) src1(VGPR245) // VOP2 V_ADD_F32 vDst(VGPR249) src0(VGPR242) src1(VGPR246) // VOP2 # 278: OpLoad: FloatVector2: tmp278 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR250) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR251) src0(VGPR1) # 279: OpFDiv: FloatVector2: tmp279 << tmp277, tmp278 V_RCP_F32 vDst(VGPR252) src0(VGPR250) V_RCP_F32 vDst(VGPR253) src0(VGPR251) V_MUL_F32 vDst(VGPR252) src0(VGPR248) src1(VGPR252) // VOP2 V_MUL_F32 vDst(VGPR253) src0(VGPR249) src1(VGPR253) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR252) src0(VGPR252) src1(VGPR250) src2(VGPR248) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR253) src0(VGPR253) src1(VGPR251) src2(VGPR249) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 280: OpExtInst(Floor): FloatVector2: tmp280 << tmp279 V_FLOOR_F32 vDst(VGPR254) src0(VGPR252) V_FLOOR_F32 vDst(VGPR255) src0(VGPR253) # 281: OpLoad: FloatVector2: tmp281 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) # 282: OpLoad: FloatVector2: tmp282 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR258) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR259) src0(VGPR1) # 283: OpVectorTimesScalar: FloatVector2: tmp283 << tmp282, const275 V_MOV_B32 vDst(VGPR262) src0(0_5_F) V_MUL_F32 vDst(VGPR260) src0(VGPR262) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR261) src0(VGPR262) src1(VGPR259) // VOP2 # 284: OpFAdd: FloatVector2: tmp284 << tmp281, tmp283 V_ADD_F32 vDst(VGPR263) src0(VGPR256) src1(VGPR260) // VOP2 V_ADD_F32 vDst(VGPR264) src0(VGPR257) src1(VGPR261) // VOP2 # 285: OpLoad: FloatVector2: tmp285 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR265) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR266) src0(VGPR1) # 286: OpFMod: FloatVector2: tmp286 << tmp284, tmp285 V_RCP_F32 vDst(VGPR267) src0(VGPR265) V_MUL_F32 vDst(VGPR267) src0(VGPR263) src1(VGPR267) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR267) src0(VGPR267) src1(VGPR265) src2(VGPR263) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR267) src0(VGPR267) V_RCP_F32 vDst(VGPR268) src0(VGPR266) V_MUL_F32 vDst(VGPR268) src0(VGPR264) src1(VGPR268) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR268) src0(VGPR268) src1(VGPR266) src2(VGPR264) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR268) src0(VGPR268) V_MAD_F32 vDst(VGPR267) src0(VGPR265) src1(VGPR267) src2(VGPR263) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR268) src0(VGPR266) src1(VGPR268) src2(VGPR264) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 287: OpLoad: FloatVector2: tmp287 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR78) const: 0x0 V_MOVRELS_B32 vDst(VGPR269) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR270) src0(VGPR1) # 288: OpVectorTimesScalar: FloatVector2: tmp288 << tmp287, const275 V_MOV_B32 vDst(VGPR273) src0(0_5_F) V_MUL_F32 vDst(VGPR271) src0(VGPR273) src1(VGPR269) // VOP2 V_MUL_F32 vDst(VGPR272) src0(VGPR273) src1(VGPR270) // VOP2 # 289: OpFSub: FloatVector2: tmp289 << tmp286, tmp288 V_SUB_F32 vDst(VGPR274) src0(VGPR267) src1(VGPR271) // VOP2 V_SUB_F32 vDst(VGPR275) src0(VGPR268) src1(VGPR272) // VOP2 # OpStore: : tmp289 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR274) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR275) # OpReturnValue: : << tmp280 S_MOV_B32 sDst(M0) src0(SGPR76) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR254) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR255) S_SETPC_B64 sDst(SGPR74) src0(SGPR74) # Float sdRect(vf2;vf2;(FloatVector2* p, FloatVector2* r) Function: Float sdRect(vf2;vf2;(, FloatVector2 tRepeat2(vf2;vf2;.r) S_MOV_B64 sDst(SGPR88) src0(EXEC) # lb41 Label: lb41 # 293: OpLoad: FloatVector2: tmp293 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR276) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR277) src0(VGPR1) # 294: OpExtInst(FAbs): FloatVector2: tmp294 << tmp293 V_ADD_F32 vDst(VGPR278) src0(VGPR276) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR279) src0(VGPR277) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 295: OpLoad: FloatVector2: tmp295 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR86) const: 0x0 V_MOVRELS_B32 vDst(VGPR280) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR281) src0(VGPR1) # 296: OpFSub: FloatVector2: tmp296 << tmp294, tmp295 V_SUB_F32 vDst(VGPR282) src0(VGPR278) src1(VGPR280) // VOP2 V_SUB_F32 vDst(VGPR283) src0(VGPR279) src1(VGPR281) // VOP2 # OpStore: : tmp296 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR282) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR283) # 297: OpAccessChain: Float*: p[0] # 298: OpLoad: Float: tmp298 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR284) src0(VGPR0) # 299: OpAccessChain: Float*: p[1] # 300: OpLoad: Float: tmp300 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR285) src0(VGPR1) # 301: OpExtInst(FMax): Float: tmp301 << tmp298, tmp300 V_MAX_F32 vDst(VGPR286) src0(VGPR284) src1(VGPR285) // VOP2 # 302: OpExtInst(FMin): Float: tmp302 << tmp301, const92 V_MOV_B32 vDst(VGPR287) src0(LITERAL_CONST) const: 0x00000000 V_MIN_F32 vDst(VGPR288) src0(VGPR286) src1(VGPR287) // VOP2 # 303: OpLoad: FloatVector2: tmp303 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR85) const: 0x0 V_MOVRELS_B32 vDst(VGPR289) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR290) src0(VGPR1) # 304: OpCompositeConstruct: FloatVector2: tmp304 << const92, const92 V_MOV_B32 vDst(VGPR293) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR291) src0(VGPR293) V_MOV_B32 vDst(VGPR294) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR292) src0(VGPR294) # 305: OpExtInst(FMax): FloatVector2: tmp305 << tmp303, tmp304 V_MAX_F32 vDst(VGPR295) src0(VGPR289) src1(VGPR291) // VOP2 V_MAX_F32 vDst(VGPR296) src0(VGPR290) src1(VGPR292) // VOP2 # 306: OpExtInst(Length): Float: tmp306 << tmp305 V_MUL_F32 vDst(VGPR297) src0(VGPR295) src1(VGPR295) // VOP2 V_MAC_F32 vDst(VGPR297) src0(VGPR296) src1(VGPR296) // VOP2 V_SQRT_F32 vDst(VGPR297) src0(VGPR297) # 307: OpFAdd: Float: tmp307 << tmp302, tmp306 V_ADD_F32 vDst(VGPR298) src0(VGPR288) src1(VGPR297) // VOP2 # OpReturnValue: : << tmp307 S_MOV_B32 sDst(M0) src0(SGPR84) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR298) S_SETPC_B64 sDst(SGPR82) src0(SGPR82) # Float sdCircle(vf2;f1;(FloatVector2* p, Float* r) Function: Float sdCircle(vf2;f1;(, Float sdRect(vf2;vf2;.r) S_MOV_B64 sDst(SGPR96) src0(EXEC) # lb46 Label: lb46 # 310: OpLoad: FloatVector2: tmp310 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR93) const: 0x0 V_MOVRELS_B32 vDst(VGPR299) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR300) src0(VGPR1) # 311: OpExtInst(Length): Float: tmp311 << tmp310 V_MUL_F32 vDst(VGPR301) src0(VGPR299) src1(VGPR299) // VOP2 V_MAC_F32 vDst(VGPR301) src0(VGPR300) src1(VGPR300) // VOP2 V_SQRT_F32 vDst(VGPR301) src0(VGPR301) # 312: OpLoad: Float: tmp312 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR94) const: 0x0 V_MOVRELS_B32 vDst(VGPR302) src0(VGPR0) # 313: OpFSub: Float: tmp313 << tmp311, tmp312 V_SUB_F32 vDst(VGPR303) src0(VGPR301) src1(VGPR302) // VOP2 # OpReturnValue: : << tmp313 S_MOV_B32 sDst(M0) src0(SGPR92) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR303) S_SETPC_B64 sDst(SGPR90) src0(SGPR90) # Float opU(f1;f1;(Float* a, Float* b) Function: Float opU(f1;f1;(, Float sdCircle(vf2;f1;.b) S_MOV_B64 sDst(SGPR104) src0(EXEC) # lb51 Label: lb51 # 316: OpLoad: Float: tmp316 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR101) const: 0x0 V_MOVRELS_B32 vDst(VGPR304) src0(VGPR0) # 317: OpLoad: Float: tmp317 << b S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR102) const: 0x0 V_MOVRELS_B32 vDst(VGPR305) src0(VGPR0) # 318: OpExtInst(FMin): Float: tmp318 << tmp316, tmp317 V_MIN_F32 vDst(VGPR306) src0(VGPR304) src1(VGPR305) // VOP2 # OpReturnValue: : << tmp318 S_MOV_B32 sDst(M0) src0(SGPR100) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR306) S_SETPC_B64 sDst(SGPR98) src0(SGPR98) # Float opS(f1;f1;(Float* a, Float* b) Function: Float opS(f1;f1;(, Float opU(f1;f1;.b) S_MOV_B64 sDst(SGPR112) src0(EXEC) # lb55 Label: lb55 # 321: OpLoad: Float: tmp321 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR109) const: 0x0 V_MOVRELS_B32 vDst(VGPR307) src0(VGPR0) # 322: OpLoad: Float: tmp322 << b S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR110) const: 0x0 V_MOVRELS_B32 vDst(VGPR308) src0(VGPR0) # 323: OpFNegate: Float: tmp323 << tmp322 V_MUL_F32 vDst(VGPR309) src0(M1_0_F) src1(VGPR308) // VOP2 # 324: OpExtInst(FMax): Float: tmp324 << tmp321, tmp323 V_MAX_F32 vDst(VGPR310) src0(VGPR307) src1(VGPR309) // VOP2 # OpReturnValue: : << tmp324 S_MOV_B32 sDst(M0) src0(SGPR108) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR310) S_SETPC_B64 sDst(SGPR106) src0(SGPR106) # Float map(vf3;(FloatVector3* p) Function: Float map(vf3;() S_MOV_B64 sDst(SGPR118) src0(EXEC) # lb58 Label: lb58 # 328: OpLoad: FloatVector3: tmp328 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR350) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR351) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR352) src0(VGPR2) # OpStore: : tmp328 >> param327 V_MOV_B32 vDst(VGPR311) src0(VGPR350) V_MOV_B32 vDst(VGPR312) src0(VGPR351) V_MOV_B32 vDst(VGPR313) src0(VGPR352) # 330: OpLoad: Float: tmp330 << _twist # OpStore: : tmp330 >> param329 V_MOV_B32 vDst(VGPR314) src0(VGPR24) # 331: OpFunctionCall: Void: tTwist(vf3;f1;(param327, param329) S_ADD_U32 sDst(SGPR68) src0(LITERAL_CONST) src1(0) const: 0x137 # VGPR[311:313] S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0x13a # VGPR314 S_MOV_B64 sDst(SGPR120) src0(EXEC) # Indirect branch to tTwist(vf3;f1;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR120) # .lbl11 # 332: OpLoad: FloatVector3: tmp332 << param327 # OpStore: : tmp332 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR311) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR312) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR313) # 336: OpLoad: FloatVector3: tmp336 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR353) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR354) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR355) src0(VGPR2) # 337: OpVectorShuffle: FloatVector2: tmp337 << tmp336, tmp336, 0, 2 V_MOV_B32 vDst(VGPR356) src0(VGPR353) V_MOV_B32 vDst(VGPR357) src0(VGPR355) # OpStore: : tmp337 >> param335 V_MOV_B32 vDst(VGPR315) src0(VGPR356) V_MOV_B32 vDst(VGPR316) src0(VGPR357) # OpStore: : const334 >> param338 V_MOV_B32 vDst(VGPR358) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR359) src0(1_0_F) V_MOV_B32 vDst(VGPR317) src0(VGPR358) V_MOV_B32 vDst(VGPR318) src0(VGPR359) # 339: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param335, param338) S_ADD_U32 sDst(SGPR77) src0(LITERAL_CONST) src1(0) const: 0x13b # VGPR[315:316] S_ADD_U32 sDst(SGPR78) src0(LITERAL_CONST) src1(0) const: 0x13d # VGPR[317:318] S_MOV_B64 sDst(SGPR122) src0(EXEC) S_MOV_B32 sDst(SGPR76) src0(LITERAL_CONST) const: 0x168 # VGPR[360:361] # Indirect branch to tRepeat2(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR74) src0(SGPR74) S_ADD_U32 sDst(SGPR74) src0(SGPR74) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR75) src0(SGPR75) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR74) src0(SGPR74) S_MOV_B64 sDst(EXEC) src0(SGPR122) # .lbl12 # 340: OpLoad: FloatVector2: tmp340 << param335 # 341: OpLoad: FloatVector3: tmp341 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR362) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR363) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR364) src0(VGPR2) # 342: OpVectorShuffle: FloatVector3: tmp342 << tmp341, tmp340, 3, 1, 4 V_MOV_B32 vDst(VGPR365) src0(VGPR315) V_MOV_B32 vDst(VGPR366) src0(VGPR363) V_MOV_B32 vDst(VGPR367) src0(VGPR316) # OpStore: : tmp342 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR365) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR366) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR367) # 343: OpAccessChain: Float*: p[0] # 344: OpLoad: Float: tmp344 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR368) src0(VGPR0) # 345: OpExtInst(FAbs): Float: tmp345 << tmp344 V_ADD_F32 vDst(VGPR369) src0(VGPR368) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 346: OpAccessChain: Float*: p[0] # OpStore: : tmp345 >> p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR369) # 347: OpAccessChain: Float*: p[1] # 348: OpLoad: Float: tmp348 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR370) src0(VGPR1) # 349: OpFAdd: Float: tmp349 << tmp348, const275 V_MOV_B32 vDst(VGPR371) src0(0_5_F) V_ADD_F32 vDst(VGPR372) src0(VGPR370) src1(VGPR371) // VOP2 # 350: OpAccessChain: Float*: p[1] # OpStore: : tmp349 >> p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR1) src0(VGPR372) # 352: OpAccessChain: Float*: p[2] # 353: OpLoad: Float: tmp353 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR373) src0(VGPR2) # 354: OpExtInst(FAbs): Float: tmp354 << tmp353 V_ADD_F32 vDst(VGPR374) src0(VGPR373) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 356: OpFSub: Float: tmp356 << tmp354, const355 V_MOV_B32 vDst(VGPR375) src0(LITERAL_CONST) const: 0x3e19999a V_SUB_F32 vDst(VGPR376) src0(VGPR374) src1(VGPR375) // VOP2 # OpStore: : tmp356 >> d V_MOV_B32 vDst(VGPR319) src0(VGPR376) # 358: OpLoad: FloatVector3: tmp358 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR377) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR378) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR379) src0(VGPR2) # 359: OpVectorShuffle: FloatVector2: tmp359 << tmp358, tmp358, 0, 1 V_MOV_B32 vDst(VGPR380) src0(VGPR377) V_MOV_B32 vDst(VGPR381) src0(VGPR378) # 362: OpFSub: FloatVector2: tmp362 << tmp359, const361 V_MOV_B32 vDst(VGPR382) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR383) src0(LITERAL_CONST) const: 0x3f400000 V_SUB_F32 vDst(VGPR384) src0(VGPR380) src1(VGPR382) // VOP2 V_SUB_F32 vDst(VGPR385) src0(VGPR381) src1(VGPR383) // VOP2 # OpStore: : tmp362 >> param364 V_MOV_B32 vDst(VGPR320) src0(VGPR384) V_MOV_B32 vDst(VGPR321) src0(VGPR385) # OpStore: : const363 >> param365 V_MOV_B32 vDst(VGPR386) src0(LITERAL_CONST) const: 0x3e800000 V_MOV_B32 vDst(VGPR322) src0(VGPR386) # 366: OpFunctionCall: Float: sdCircle(vf2;f1;(param364, param365) S_ADD_U32 sDst(SGPR93) src0(LITERAL_CONST) src1(0) const: 0x140 # VGPR[320:321] S_ADD_U32 sDst(SGPR94) src0(LITERAL_CONST) src1(0) const: 0x142 # VGPR322 S_MOV_B64 sDst(SGPR124) src0(EXEC) S_MOV_B32 sDst(SGPR92) src0(LITERAL_CONST) const: 0x183 # VGPR387 # Indirect branch to sdCircle(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR90) src0(SGPR90) S_ADD_U32 sDst(SGPR90) src0(SGPR90) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR91) src0(SGPR91) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR90) src0(SGPR90) S_MOV_B64 sDst(EXEC) src0(SGPR124) # .lbl13 # 367: OpLoad: FloatVector3: tmp367 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR388) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR389) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR390) src0(VGPR2) # 368: OpVectorShuffle: FloatVector2: tmp368 << tmp367, tmp367, 0, 1 V_MOV_B32 vDst(VGPR391) src0(VGPR388) V_MOV_B32 vDst(VGPR392) src0(VGPR389) # 371: OpFSub: FloatVector2: tmp371 << tmp368, const370 V_MOV_B32 vDst(VGPR393) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR394) src0(LITERAL_CONST) const: 0x3ec00000 V_SUB_F32 vDst(VGPR395) src0(VGPR391) src1(VGPR393) // VOP2 V_SUB_F32 vDst(VGPR396) src0(VGPR392) src1(VGPR394) // VOP2 # OpStore: : tmp371 >> param373 V_MOV_B32 vDst(VGPR323) src0(VGPR395) V_MOV_B32 vDst(VGPR324) src0(VGPR396) # OpStore: : const372 >> param374 V_MOV_B32 vDst(VGPR397) src0(LITERAL_CONST) const: 0x3e800000 V_MOV_B32 vDst(VGPR398) src0(LITERAL_CONST) const: 0x3ec00000 V_MOV_B32 vDst(VGPR325) src0(VGPR397) V_MOV_B32 vDst(VGPR326) src0(VGPR398) # 375: OpFunctionCall: Float: sdRect(vf2;vf2;(param373, param374) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x143 # VGPR[323:324] S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x145 # VGPR[325:326] S_MOV_B64 sDst(SGPR126) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x18f # VGPR399 # Indirect branch to sdRect(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR126) # .lbl14 # OpStore: : sdCircle(vf2;f1; >> param376 V_MOV_B32 vDst(VGPR327) src0(VGPR387) # OpStore: : sdRect(vf2;vf2; >> param377 V_MOV_B32 vDst(VGPR328) src0(VGPR399) # 378: OpFunctionCall: Float: opU(f1;f1;(param376, param377) S_ADD_U32 sDst(SGPR101) src0(LITERAL_CONST) src1(0) const: 0x147 # VGPR327 S_ADD_U32 sDst(SGPR102) src0(LITERAL_CONST) src1(0) const: 0x148 # VGPR328 S_MOV_B64 sDst(SGPR128) src0(EXEC) S_MOV_B32 sDst(SGPR100) src0(LITERAL_CONST) const: 0x190 # VGPR400 # Indirect branch to opU(f1;f1;: ??? S_GETPC_B64 sDst(SGPR98) src0(SGPR98) S_ADD_U32 sDst(SGPR98) src0(SGPR98) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR99) src0(SGPR99) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR98) src0(SGPR98) S_MOV_B64 sDst(EXEC) src0(SGPR128) # .lbl15 # 380: OpLoad: Float: tmp380 << d # OpStore: : tmp380 >> param379 V_MOV_B32 vDst(VGPR329) src0(VGPR319) # OpStore: : opU(f1;f1; >> param381 V_MOV_B32 vDst(VGPR330) src0(VGPR400) # 383: OpFunctionCall: Float: opS(f1;f1;(param379, param381) S_ADD_U32 sDst(SGPR109) src0(LITERAL_CONST) src1(0) const: 0x149 # VGPR329 S_ADD_U32 sDst(SGPR110) src0(LITERAL_CONST) src1(0) const: 0x14a # VGPR330 S_MOV_B64 sDst(SGPR130) src0(EXEC) S_MOV_B32 sDst(SGPR108) src0(LITERAL_CONST) const: 0x191 # VGPR401 # Indirect branch to opS(f1;f1;: ??? S_GETPC_B64 sDst(SGPR106) src0(SGPR106) S_ADD_U32 sDst(SGPR106) src0(SGPR106) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR107) src0(SGPR107) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR106) src0(SGPR106) S_MOV_B64 sDst(EXEC) src0(SGPR130) # .lbl16 # OpStore: : opS(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR401) # 384: OpLoad: FloatVector3: tmp384 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR402) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR403) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR404) src0(VGPR2) # 385: OpVectorShuffle: FloatVector2: tmp385 << tmp384, tmp384, 0, 1 V_MOV_B32 vDst(VGPR405) src0(VGPR402) V_MOV_B32 vDst(VGPR406) src0(VGPR403) # 388: OpFSub: FloatVector2: tmp388 << tmp385, const387 V_MOV_B32 vDst(VGPR407) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR408) src0(LITERAL_CONST) const: 0x3eb33333 V_SUB_F32 vDst(VGPR409) src0(VGPR405) src1(VGPR407) // VOP2 V_SUB_F32 vDst(VGPR410) src0(VGPR406) src1(VGPR408) // VOP2 # OpStore: : tmp388 >> param392 V_MOV_B32 vDst(VGPR331) src0(VGPR409) V_MOV_B32 vDst(VGPR332) src0(VGPR410) # OpStore: : const391 >> param393 V_MOV_B32 vDst(VGPR411) src0(LITERAL_CONST) const: 0x3ee66666 V_MOV_B32 vDst(VGPR412) src0(LITERAL_CONST) const: 0x3e99999a V_MOV_B32 vDst(VGPR333) src0(VGPR411) V_MOV_B32 vDst(VGPR334) src0(VGPR412) # 394: OpFunctionCall: Float: sdRect(vf2;vf2;(param392, param393) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x14b # VGPR[331:332] S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x14d # VGPR[333:334] S_MOV_B64 sDst(SGPR132) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x19d # VGPR413 # Indirect branch to sdRect(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR132) # .lbl17 # 396: OpLoad: Float: tmp396 << d # OpStore: : tmp396 >> param395 V_MOV_B32 vDst(VGPR335) src0(VGPR319) # OpStore: : sdRect(vf2;vf2; >> param397 V_MOV_B32 vDst(VGPR336) src0(VGPR413) # 398: OpFunctionCall: Float: opS(f1;f1;(param395, param397) S_ADD_U32 sDst(SGPR109) src0(LITERAL_CONST) src1(0) const: 0x14f # VGPR335 S_ADD_U32 sDst(SGPR110) src0(LITERAL_CONST) src1(0) const: 0x150 # VGPR336 S_MOV_B64 sDst(SGPR134) src0(EXEC) S_MOV_B32 sDst(SGPR108) src0(LITERAL_CONST) const: 0x19e # VGPR414 # Indirect branch to opS(f1;f1;: ??? S_GETPC_B64 sDst(SGPR106) src0(SGPR106) S_ADD_U32 sDst(SGPR106) src0(SGPR106) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR107) src0(SGPR107) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR106) src0(SGPR106) S_MOV_B64 sDst(EXEC) src0(SGPR134) # .lbl18 # OpStore: : opS(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR414) # 399: OpLoad: FloatVector3: tmp399 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR415) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR416) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR417) src0(VGPR2) # 400: OpVectorShuffle: FloatVector2: tmp400 << tmp399, tmp399, 0, 2 V_MOV_B32 vDst(VGPR418) src0(VGPR415) V_MOV_B32 vDst(VGPR419) src0(VGPR417) # 402: OpFSub: FloatVector2: tmp402 << tmp400, const401 V_MOV_B32 vDst(VGPR420) src0(LITERAL_CONST) const: 0x3eb33333 V_MOV_B32 vDst(VGPR421) src0(LITERAL_CONST) const: 0x00000000 V_SUB_F32 vDst(VGPR422) src0(VGPR418) src1(VGPR420) // VOP2 V_SUB_F32 vDst(VGPR423) src0(VGPR419) src1(VGPR421) // VOP2 # OpStore: : tmp402 >> param404 V_MOV_B32 vDst(VGPR337) src0(VGPR422) V_MOV_B32 vDst(VGPR338) src0(VGPR423) # OpStore: : const403 >> param405 V_MOV_B32 vDst(VGPR424) src0(LITERAL_CONST) const: 0x3d99999a V_MOV_B32 vDst(VGPR339) src0(VGPR424) # 406: OpFunctionCall: Float: sdCircle(vf2;f1;(param404, param405) S_ADD_U32 sDst(SGPR93) src0(LITERAL_CONST) src1(0) const: 0x151 # VGPR[337:338] S_ADD_U32 sDst(SGPR94) src0(LITERAL_CONST) src1(0) const: 0x153 # VGPR339 S_MOV_B64 sDst(SGPR136) src0(EXEC) S_MOV_B32 sDst(SGPR92) src0(LITERAL_CONST) const: 0x1a9 # VGPR425 # Indirect branch to sdCircle(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR90) src0(SGPR90) S_ADD_U32 sDst(SGPR90) src0(SGPR90) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR91) src0(SGPR91) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR90) src0(SGPR90) S_MOV_B64 sDst(EXEC) src0(SGPR136) # .lbl19 # 408: OpLoad: Float: tmp408 << d # OpStore: : tmp408 >> param407 V_MOV_B32 vDst(VGPR340) src0(VGPR319) # OpStore: : sdCircle(vf2;f1; >> param409 V_MOV_B32 vDst(VGPR341) src0(VGPR425) # 410: OpFunctionCall: Float: opU(f1;f1;(param407, param409) S_ADD_U32 sDst(SGPR101) src0(LITERAL_CONST) src1(0) const: 0x154 # VGPR340 S_ADD_U32 sDst(SGPR102) src0(LITERAL_CONST) src1(0) const: 0x155 # VGPR341 S_MOV_B64 sDst(SGPR138) src0(EXEC) S_MOV_B32 sDst(SGPR100) src0(LITERAL_CONST) const: 0x1aa # VGPR426 # Indirect branch to opU(f1;f1;: ??? S_GETPC_B64 sDst(SGPR98) src0(SGPR98) S_ADD_U32 sDst(SGPR98) src0(SGPR98) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR99) src0(SGPR99) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR98) src0(SGPR98) S_MOV_B64 sDst(EXEC) src0(SGPR138) # .lbl20 # OpStore: : opU(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR426) # 411: OpAccessChain: Float*: p[2] # 412: OpLoad: Float: tmp412 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR427) src0(VGPR2) # 413: OpExtInst(FAbs): Float: tmp413 << tmp412 V_ADD_F32 vDst(VGPR428) src0(VGPR427) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 414: OpAccessChain: Float*: p[2] # OpStore: : tmp413 >> p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELD_B32 vDst(VGPR2) src0(VGPR428) # 415: OpLoad: FloatVector3: tmp415 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR429) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR430) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR431) src0(VGPR2) # 416: OpVectorShuffle: FloatVector2: tmp416 << tmp415, tmp415, 1, 2 V_MOV_B32 vDst(VGPR432) src0(VGPR430) V_MOV_B32 vDst(VGPR433) src0(VGPR431) # 419: OpFSub: FloatVector2: tmp419 << tmp416, const418 V_MOV_B32 vDst(VGPR434) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR435) src0(0_5_F) V_SUB_F32 vDst(VGPR436) src0(VGPR432) src1(VGPR434) // VOP2 V_SUB_F32 vDst(VGPR437) src0(VGPR433) src1(VGPR435) // VOP2 # OpStore: : tmp419 >> param422 V_MOV_B32 vDst(VGPR342) src0(VGPR436) V_MOV_B32 vDst(VGPR343) src0(VGPR437) # OpStore: : const421 >> param423 V_MOV_B32 vDst(VGPR438) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR439) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR344) src0(VGPR438) V_MOV_B32 vDst(VGPR345) src0(VGPR439) # 424: OpFunctionCall: Float: sdRect(vf2;vf2;(param422, param423) S_ADD_U32 sDst(SGPR85) src0(LITERAL_CONST) src1(0) const: 0x156 # VGPR[342:343] S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x158 # VGPR[344:345] S_MOV_B64 sDst(SGPR140) src0(EXEC) S_MOV_B32 sDst(SGPR84) src0(LITERAL_CONST) const: 0x1b8 # VGPR440 # Indirect branch to sdRect(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR82) src0(SGPR82) S_ADD_U32 sDst(SGPR82) src0(SGPR82) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR83) src0(SGPR83) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR82) src0(SGPR82) S_MOV_B64 sDst(EXEC) src0(SGPR140) # .lbl21 # 426: OpLoad: Float: tmp426 << d # OpStore: : tmp426 >> param425 V_MOV_B32 vDst(VGPR346) src0(VGPR319) # OpStore: : sdRect(vf2;vf2; >> param427 V_MOV_B32 vDst(VGPR347) src0(VGPR440) # 428: OpFunctionCall: Float: opS(f1;f1;(param425, param427) S_ADD_U32 sDst(SGPR109) src0(LITERAL_CONST) src1(0) const: 0x15a # VGPR346 S_ADD_U32 sDst(SGPR110) src0(LITERAL_CONST) src1(0) const: 0x15b # VGPR347 S_MOV_B64 sDst(SGPR142) src0(EXEC) S_MOV_B32 sDst(SGPR108) src0(LITERAL_CONST) const: 0x1b9 # VGPR441 # Indirect branch to opS(f1;f1;: ??? S_GETPC_B64 sDst(SGPR106) src0(SGPR106) S_ADD_U32 sDst(SGPR106) src0(SGPR106) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR107) src0(SGPR107) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR106) src0(SGPR106) S_MOV_B64 sDst(EXEC) src0(SGPR142) # .lbl22 # OpStore: : opS(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR441) # 429: OpAccessChain: Float*: p[1] # 430: OpLoad: Float: tmp430 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR117) const: 0x0 V_MOVRELS_B32 vDst(VGPR442) src0(VGPR1) # 431: OpFSub: Float: tmp431 << tmp430, const275 V_MOV_B32 vDst(VGPR443) src0(0_5_F) V_SUB_F32 vDst(VGPR444) src0(VGPR442) src1(VGPR443) // VOP2 # 432: OpExtInst(FAbs): Float: tmp432 << tmp431 V_ADD_F32 vDst(VGPR445) src0(VGPR444) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 433: OpFNegate: Float: tmp433 << tmp432 V_MUL_F32 vDst(VGPR446) src0(M1_0_F) src1(VGPR445) // VOP2 # 435: OpFAdd: Float: tmp435 << tmp433, const434 V_MOV_B32 vDst(VGPR447) src0(LITERAL_CONST) const: 0x3f4ccccd V_ADD_F32 vDst(VGPR448) src0(VGPR446) src1(VGPR447) // VOP2 # 437: OpLoad: Float: tmp437 << d # OpStore: : tmp437 >> param436 V_MOV_B32 vDst(VGPR348) src0(VGPR319) # OpStore: : tmp435 >> param438 V_MOV_B32 vDst(VGPR349) src0(VGPR448) # 439: OpFunctionCall: Float: opU(f1;f1;(param436, param438) S_ADD_U32 sDst(SGPR101) src0(LITERAL_CONST) src1(0) const: 0x15c # VGPR348 S_ADD_U32 sDst(SGPR102) src0(LITERAL_CONST) src1(0) const: 0x15d # VGPR349 S_MOV_B64 sDst(SGPR144) src0(EXEC) S_MOV_B32 sDst(SGPR100) src0(LITERAL_CONST) const: 0x1c1 # VGPR449 # Indirect branch to opU(f1;f1;: ??? S_GETPC_B64 sDst(SGPR98) src0(SGPR98) S_ADD_U32 sDst(SGPR98) src0(SGPR98) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR99) src0(SGPR99) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR98) src0(SGPR98) S_MOV_B64 sDst(EXEC) src0(SGPR144) # .lbl23 # OpStore: : opU(f1;f1; >> d V_MOV_B32 vDst(VGPR319) src0(VGPR449) # 440: OpLoad: Float: tmp440 << d # OpReturnValue: : << tmp440 S_MOV_B32 sDst(M0) src0(SGPR116) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR319) S_SETPC_B64 sDst(SGPR114) src0(SGPR114) # Float trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* maxDist, Float* steps) Function: Float trace(vf3;vf3;f1;f1;(, FloatVector3 map(vf3;.rd, Float map(vf3;.maxDist, Float map(vf3;.steps) S_MOV_B64 sDst(SGPR154) src0(EXEC) # lb65 Label: lb65 # OpStore: : const92 >> total V_MOV_B32 vDst(VGPR455) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR450) src0(VGPR455) # OpStore: : const92 >> steps S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR152) const: 0x0 V_MOV_B32 vDst(VGPR456) src0(LITERAL_CONST) const: 0x00000000 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR456) # OpStore: : const210 >> i V_MOV_B32 vDst(VGPR451) src0(0) # OpBranch: to lb445 # lb445 Label: lb445 # OpLoopMerge: (merge: lb447, continue: lb448) # CF Block: Merge: lb447, Continue: lb448 S_MOV_B64 sDst(SGPR156) src0(EXEC) S_MOV_B64 sDst(SGPR158) src0(EXEC) S_MOV_B64 sDst(SGPR160) src0(EXEC) Label: lb445Loop # OpBranch: to lb449 # lb449 Label: lb449 # 450: OpLoad: Int: tmp450 << i Decorators: RelaxedPrecision # 452: OpSLessThan: Bool: tmp452 << tmp450, const451 V_MOV_B32 vDst(VGPR457) src0(LITERAL_CONST) const: 0x00000064 V_CMP_LT_I32 dst(SGPR162) src0(VGPR451) src1(VGPR457) // VOP3a # OpBranchConditional: if(tmp452) then branch to lb446, else branch to lb447 # CF Block: Cond Branch: true: lb446, false: lb447 S_AND_B64 sDst(EXEC) src0(SGPR162) src1(EXEC) S_CBRANCH_EXECZ ??? lb447 # lb446 Label: lb446 S_MOV_B64 sDst(SGPR158) src0(EXEC) S_MOV_B64 sDst(SGPR160) src0(EXEC) # 453: OpLoad: Float: tmp453 << steps S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR152) const: 0x0 V_MOVRELS_B32 vDst(VGPR458) src0(VGPR0) # 454: OpFAdd: Float: tmp454 << tmp453, const117 V_MOV_B32 vDst(VGPR459) src0(1_0_F) V_ADD_F32 vDst(VGPR460) src0(VGPR458) src1(VGPR459) // VOP2 # OpStore: : tmp454 >> steps S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR152) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR460) # 456: OpLoad: FloatVector3: tmp456 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR149) const: 0x0 V_MOVRELS_B32 vDst(VGPR461) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR462) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR463) src0(VGPR2) # 457: OpLoad: FloatVector3: tmp457 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR150) const: 0x0 V_MOVRELS_B32 vDst(VGPR464) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR465) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR466) src0(VGPR2) # 458: OpLoad: Float: tmp458 << total # 459: OpVectorTimesScalar: FloatVector3: tmp459 << tmp457, tmp458 V_MUL_F32 vDst(VGPR467) src0(VGPR450) src1(VGPR464) // VOP2 V_MUL_F32 vDst(VGPR468) src0(VGPR450) src1(VGPR465) // VOP2 V_MUL_F32 vDst(VGPR469) src0(VGPR450) src1(VGPR466) // VOP2 # 460: OpFAdd: FloatVector3: tmp460 << tmp456, tmp459 V_ADD_F32 vDst(VGPR470) src0(VGPR461) src1(VGPR467) // VOP2 V_ADD_F32 vDst(VGPR471) src0(VGPR462) src1(VGPR468) // VOP2 V_ADD_F32 vDst(VGPR472) src0(VGPR463) src1(VGPR469) // VOP2 # OpStore: : tmp460 >> param461 V_MOV_B32 vDst(VGPR452) src0(VGPR470) V_MOV_B32 vDst(VGPR453) src0(VGPR471) V_MOV_B32 vDst(VGPR454) src0(VGPR472) # 462: OpFunctionCall: Float: map(vf3;(param461) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1c4 # VGPR[452:454] S_MOV_B64 sDst(SGPR164) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x1d9 # VGPR473 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR164) # .lbl24 # 464: OpLoad: Float: tmp464 << total # 465: OpFAdd: Float: tmp465 << tmp464, map(vf3; V_ADD_F32 vDst(VGPR474) src0(VGPR450) src1(VGPR473) // VOP2 # OpStore: : tmp465 >> total V_MOV_B32 vDst(VGPR450) src0(VGPR474) # 468: OpFOrdLessThan: Bool: tmp468 << map(vf3;, const467 V_MOV_B32 vDst(VGPR475) src0(LITERAL_CONST) const: 0x3727c5ac V_CMP_LT_F32 dst(SGPR166) src0(VGPR473) src1(VGPR475) // VOP3a # 469: OpLoad: Float: tmp469 << maxDist S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR151) const: 0x0 V_MOVRELS_B32 vDst(VGPR476) src0(VGPR0) # 470: OpLoad: Float: tmp470 << total # 471: OpFOrdLessThan: Bool: tmp471 << tmp469, tmp470 V_CMP_LT_F32 dst(SGPR168) src0(VGPR476) src1(VGPR450) // VOP3a # 472: OpLogicalOr: Bool: tmp472 << tmp468, tmp471 S_OR_B64 sDst(SGPR170) src0(SGPR166) src1(SGPR168) # OpSelectionMerge: (merge: lb474) # CF Block: Merge: lb474 S_MOV_B64 sDst(SGPR172) src0(EXEC) # OpBranchConditional: if(tmp472) then branch to lb473, else branch to lb474 # CF Block: Cond Branch: true: lb473, false: lb474 S_AND_B64 sDst(EXEC) src0(SGPR170) src1(EXEC) S_CBRANCH_EXECZ ??? lb474 # lb473 Label: lb473 # OpBranch: to lb447 S_ANDN2_B64 sDst(SGPR158) src0(SGPR158) src1(EXEC) S_ANDN2_B64 sDst(SGPR160) src0(SGPR160) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR160) src1(EXEC) # lb474 Label: lb474 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR172) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR160) # OpBranch: to lb448 # lb448 Label: lb448 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR158) # 476: OpLoad: Int: tmp476 << i Decorators: RelaxedPrecision # 477: OpIAdd: Int: tmp477 << tmp476, const234 Decorators: RelaxedPrecision V_MOV_B32 vDst(VGPR477) src0(1_INT) V_ADD_I32 vDst(VGPR478) src0(VGPR451) src1(VGPR477) // VOP2 # OpStore: : tmp477 >> i V_MOV_B32 vDst(VGPR451) src0(VGPR478) # OpBranch: to lb445 S_BRANCH ??? lb445Loop # lb447 Label: lb447 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR156) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR154) # 478: OpLoad: Float: tmp478 << total # OpReturnValue: : << tmp478 S_MOV_B32 sDst(M0) src0(SGPR148) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR450) S_SETPC_B64 sDst(SGPR146) src0(SGPR146) # FloatVector3 getNormal(vf3;(FloatVector3* p) Function: FloatVector3 getNormal(vf3;() S_MOV_B64 sDst(SGPR178) src0(EXEC) # lb69 Label: lb69 # 484: OpLoad: FloatVector3: tmp484 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR497) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR498) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR499) src0(VGPR2) # 486: OpVectorShuffle: FloatVector3: tmp486 << const483, const483, 0, 1, 1 V_MOV_B32 vDst(VGPR500) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR501) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR502) src0(VGPR500) V_MOV_B32 vDst(VGPR503) src0(VGPR501) V_MOV_B32 vDst(VGPR504) src0(VGPR501) # 487: OpFAdd: FloatVector3: tmp487 << tmp484, tmp486 V_ADD_F32 vDst(VGPR505) src0(VGPR497) src1(VGPR502) // VOP2 V_ADD_F32 vDst(VGPR506) src0(VGPR498) src1(VGPR503) // VOP2 V_ADD_F32 vDst(VGPR507) src0(VGPR499) src1(VGPR504) // VOP2 # OpStore: : tmp487 >> param488 V_MOV_B32 vDst(VGPR479) src0(VGPR505) V_MOV_B32 vDst(VGPR480) src0(VGPR506) V_MOV_B32 vDst(VGPR481) src0(VGPR507) # 489: OpFunctionCall: Float: map(vf3;(param488) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1df # VGPR[479:481] S_MOV_B64 sDst(SGPR180) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x1fc # VGPR508 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR180) # .lbl25 # 490: OpLoad: FloatVector3: tmp490 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR509) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR510) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR511) src0(VGPR2) # 492: OpVectorShuffle: FloatVector3: tmp492 << const483, const483, 0, 1, 1 V_MOV_B32 vDst(VGPR512) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR513) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR514) src0(VGPR512) V_MOV_B32 vDst(VGPR515) src0(VGPR513) V_MOV_B32 vDst(VGPR516) src0(VGPR513) # 493: OpFSub: FloatVector3: tmp493 << tmp490, tmp492 V_SUB_F32 vDst(VGPR517) src0(VGPR509) src1(VGPR514) // VOP2 V_SUB_F32 vDst(VGPR518) src0(VGPR510) src1(VGPR515) // VOP2 V_SUB_F32 vDst(VGPR519) src0(VGPR511) src1(VGPR516) // VOP2 # OpStore: : tmp493 >> param494 V_MOV_B32 vDst(VGPR482) src0(VGPR517) V_MOV_B32 vDst(VGPR483) src0(VGPR518) V_MOV_B32 vDst(VGPR484) src0(VGPR519) # 495: OpFunctionCall: Float: map(vf3;(param494) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1e2 # VGPR[482:484] S_MOV_B64 sDst(SGPR182) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x208 # VGPR520 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR182) # .lbl26 # 496: OpFSub: Float: tmp496 << map(vf3;, map(vf3; V_SUB_F32 vDst(VGPR521) src0(VGPR508) src1(VGPR520) // VOP2 # 497: OpLoad: FloatVector3: tmp497 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR522) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR523) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR524) src0(VGPR2) # 499: OpVectorShuffle: FloatVector3: tmp499 << const483, const483, 1, 0, 1 V_MOV_B32 vDst(VGPR525) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR526) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR527) src0(VGPR526) V_MOV_B32 vDst(VGPR528) src0(VGPR525) V_MOV_B32 vDst(VGPR529) src0(VGPR526) # 500: OpFAdd: FloatVector3: tmp500 << tmp497, tmp499 V_ADD_F32 vDst(VGPR530) src0(VGPR522) src1(VGPR527) // VOP2 V_ADD_F32 vDst(VGPR531) src0(VGPR523) src1(VGPR528) // VOP2 V_ADD_F32 vDst(VGPR532) src0(VGPR524) src1(VGPR529) // VOP2 # OpStore: : tmp500 >> param501 V_MOV_B32 vDst(VGPR485) src0(VGPR530) V_MOV_B32 vDst(VGPR486) src0(VGPR531) V_MOV_B32 vDst(VGPR487) src0(VGPR532) # 502: OpFunctionCall: Float: map(vf3;(param501) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1e5 # VGPR[485:487] S_MOV_B64 sDst(SGPR184) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x215 # VGPR533 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR184) # .lbl27 # 503: OpLoad: FloatVector3: tmp503 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR534) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR535) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR536) src0(VGPR2) # 505: OpVectorShuffle: FloatVector3: tmp505 << const483, const483, 1, 0, 1 V_MOV_B32 vDst(VGPR537) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR538) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR539) src0(VGPR538) V_MOV_B32 vDst(VGPR540) src0(VGPR537) V_MOV_B32 vDst(VGPR541) src0(VGPR538) # 506: OpFSub: FloatVector3: tmp506 << tmp503, tmp505 V_SUB_F32 vDst(VGPR542) src0(VGPR534) src1(VGPR539) // VOP2 V_SUB_F32 vDst(VGPR543) src0(VGPR535) src1(VGPR540) // VOP2 V_SUB_F32 vDst(VGPR544) src0(VGPR536) src1(VGPR541) // VOP2 # OpStore: : tmp506 >> param507 V_MOV_B32 vDst(VGPR488) src0(VGPR542) V_MOV_B32 vDst(VGPR489) src0(VGPR543) V_MOV_B32 vDst(VGPR490) src0(VGPR544) # 508: OpFunctionCall: Float: map(vf3;(param507) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1e8 # VGPR[488:490] S_MOV_B64 sDst(SGPR186) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x221 # VGPR545 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR186) # .lbl28 # 509: OpFSub: Float: tmp509 << map(vf3;, map(vf3; V_SUB_F32 vDst(VGPR546) src0(VGPR533) src1(VGPR545) // VOP2 # 510: OpLoad: FloatVector3: tmp510 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR547) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR548) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR549) src0(VGPR2) # 512: OpVectorShuffle: FloatVector3: tmp512 << const483, const483, 1, 1, 0 V_MOV_B32 vDst(VGPR550) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR551) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR552) src0(VGPR551) V_MOV_B32 vDst(VGPR553) src0(VGPR551) V_MOV_B32 vDst(VGPR554) src0(VGPR550) # 513: OpFAdd: FloatVector3: tmp513 << tmp510, tmp512 V_ADD_F32 vDst(VGPR555) src0(VGPR547) src1(VGPR552) // VOP2 V_ADD_F32 vDst(VGPR556) src0(VGPR548) src1(VGPR553) // VOP2 V_ADD_F32 vDst(VGPR557) src0(VGPR549) src1(VGPR554) // VOP2 # OpStore: : tmp513 >> param514 V_MOV_B32 vDst(VGPR491) src0(VGPR555) V_MOV_B32 vDst(VGPR492) src0(VGPR556) V_MOV_B32 vDst(VGPR493) src0(VGPR557) # 515: OpFunctionCall: Float: map(vf3;(param514) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1eb # VGPR[491:493] S_MOV_B64 sDst(SGPR188) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x22e # VGPR558 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR188) # .lbl29 # 516: OpLoad: FloatVector3: tmp516 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR177) const: 0x0 V_MOVRELS_B32 vDst(VGPR559) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR560) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR561) src0(VGPR2) # 518: OpVectorShuffle: FloatVector3: tmp518 << const483, const483, 1, 1, 0 V_MOV_B32 vDst(VGPR562) src0(LITERAL_CONST) const: 0x38d1b717 V_MOV_B32 vDst(VGPR563) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR564) src0(VGPR563) V_MOV_B32 vDst(VGPR565) src0(VGPR563) V_MOV_B32 vDst(VGPR566) src0(VGPR562) # 519: OpFSub: FloatVector3: tmp519 << tmp516, tmp518 V_SUB_F32 vDst(VGPR567) src0(VGPR559) src1(VGPR564) // VOP2 V_SUB_F32 vDst(VGPR568) src0(VGPR560) src1(VGPR565) // VOP2 V_SUB_F32 vDst(VGPR569) src0(VGPR561) src1(VGPR566) // VOP2 # OpStore: : tmp519 >> param520 V_MOV_B32 vDst(VGPR494) src0(VGPR567) V_MOV_B32 vDst(VGPR495) src0(VGPR568) V_MOV_B32 vDst(VGPR496) src0(VGPR569) # 521: OpFunctionCall: Float: map(vf3;(param520) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x1ee # VGPR[494:496] S_MOV_B64 sDst(SGPR190) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x23a # VGPR570 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR190) # .lbl30 # 522: OpFSub: Float: tmp522 << map(vf3;, map(vf3; V_SUB_F32 vDst(VGPR571) src0(VGPR558) src1(VGPR570) // VOP2 # 523: OpCompositeConstruct: FloatVector3: tmp523 << tmp496, tmp509, tmp522 V_MOV_B32 vDst(VGPR572) src0(VGPR521) V_MOV_B32 vDst(VGPR573) src0(VGPR546) V_MOV_B32 vDst(VGPR574) src0(VGPR571) # 524: OpExtInst(Normalize): FloatVector3: tmp524 << tmp523 V_MUL_F32 vDst(VGPR575) src0(VGPR572) src1(VGPR572) // VOP2 V_MAC_F32 vDst(VGPR575) src0(VGPR573) src1(VGPR573) // VOP2 V_MAC_F32 vDst(VGPR575) src0(VGPR574) src1(VGPR574) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR575) src0(VGPR575) V_MUL_F32 vDst(VGPR576) src0(VGPR572) src1(VGPR575) // VOP2 V_MUL_F32 vDst(VGPR577) src0(VGPR573) src1(VGPR575) // VOP2 V_MUL_F32 vDst(VGPR578) src0(VGPR574) src1(VGPR575) // VOP2 # OpReturnValue: : << tmp524 S_MOV_B32 sDst(M0) src0(SGPR176) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR576) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR577) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR578) S_SETPC_B64 sDst(SGPR174) src0(SGPR174) # Float calculateAO(vf3;vf3;(FloatVector3* p, FloatVector3* n) Function: Float calculateAO(vf3;vf3;(, FloatVector3 getNormal(vf3;.n) S_MOV_B64 sDst(SGPR198) src0(EXEC) # lb74 Label: lb74 # OpStore: : const92 >> r V_MOV_B32 vDst(VGPR585) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR579) src0(VGPR585) # OpStore: : const117 >> w V_MOV_B32 vDst(VGPR580) src0(1_0_F) # OpStore: : const117 >> i V_MOV_B32 vDst(VGPR581) src0(1_0_F) # OpBranch: to lb530 # lb530 Label: lb530 # OpLoopMerge: (merge: lb532, continue: lb533) # CF Block: Merge: lb532, Continue: lb533 S_MOV_B64 sDst(SGPR200) src0(EXEC) S_MOV_B64 sDst(SGPR202) src0(EXEC) S_MOV_B64 sDst(SGPR204) src0(EXEC) Label: lb530Loop # OpBranch: to lb534 # lb534 Label: lb534 # 535: OpLoad: Float: tmp535 << i # 537: OpFOrdLessThanEqual: Bool: tmp537 << tmp535, const536 V_MOV_B32 vDst(VGPR586) src0(LITERAL_CONST) const: 0x40a00000 V_CMP_LE_F32 dst(SGPR206) src0(VGPR581) src1(VGPR586) // VOP3a # OpBranchConditional: if(tmp537) then branch to lb531, else branch to lb532 # CF Block: Cond Branch: true: lb531, false: lb532 S_AND_B64 sDst(EXEC) src0(SGPR206) src1(EXEC) S_CBRANCH_EXECZ ??? lb532 # lb531 Label: lb531 S_MOV_B64 sDst(SGPR202) src0(EXEC) S_MOV_B64 sDst(SGPR204) src0(EXEC) # 539: OpLoad: Float: tmp539 << i # 540: OpFDiv: Float: tmp540 << tmp539, const536 V_MOV_B32 vDst(VGPR587) src0(LITERAL_CONST) const: 0x40a00000 V_RCP_F32 vDst(VGPR588) src0(VGPR587) V_MUL_F32 vDst(VGPR588) src0(VGPR581) src1(VGPR588) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR588) src0(VGPR588) src1(VGPR587) src2(VGPR581) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 541: OpFDiv: Float: tmp541 << tmp540, const220 V_MOV_B32 vDst(VGPR589) src0(LITERAL_CONST) const: 0x41200000 V_RCP_F32 vDst(VGPR590) src0(VGPR589) V_MUL_F32 vDst(VGPR590) src0(VGPR588) src1(VGPR590) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR590) src0(VGPR590) src1(VGPR589) src2(VGPR588) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 542: OpLoad: Float: tmp542 << w # 544: OpLoad: FloatVector3: tmp544 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR195) const: 0x0 V_MOVRELS_B32 vDst(VGPR591) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR592) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR593) src0(VGPR2) # 545: OpLoad: FloatVector3: tmp545 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR196) const: 0x0 V_MOVRELS_B32 vDst(VGPR594) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR595) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR596) src0(VGPR2) # 547: OpVectorTimesScalar: FloatVector3: tmp547 << tmp545, tmp541 V_MUL_F32 vDst(VGPR597) src0(VGPR590) src1(VGPR594) // VOP2 V_MUL_F32 vDst(VGPR598) src0(VGPR590) src1(VGPR595) // VOP2 V_MUL_F32 vDst(VGPR599) src0(VGPR590) src1(VGPR596) // VOP2 # 548: OpFAdd: FloatVector3: tmp548 << tmp544, tmp547 V_ADD_F32 vDst(VGPR600) src0(VGPR591) src1(VGPR597) // VOP2 V_ADD_F32 vDst(VGPR601) src0(VGPR592) src1(VGPR598) // VOP2 V_ADD_F32 vDst(VGPR602) src0(VGPR593) src1(VGPR599) // VOP2 # OpStore: : tmp548 >> param549 V_MOV_B32 vDst(VGPR582) src0(VGPR600) V_MOV_B32 vDst(VGPR583) src0(VGPR601) V_MOV_B32 vDst(VGPR584) src0(VGPR602) # 550: OpFunctionCall: Float: map(vf3;(param549) S_ADD_U32 sDst(SGPR117) src0(LITERAL_CONST) src1(0) const: 0x246 # VGPR[582:584] S_MOV_B64 sDst(SGPR208) src0(EXEC) S_MOV_B32 sDst(SGPR116) src0(LITERAL_CONST) const: 0x25b # VGPR603 # Indirect branch to map(vf3;: ??? S_GETPC_B64 sDst(SGPR114) src0(SGPR114) S_ADD_U32 sDst(SGPR114) src0(SGPR114) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR115) src0(SGPR115) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR114) src0(SGPR114) S_MOV_B64 sDst(EXEC) src0(SGPR208) # .lbl31 # 551: OpFSub: Float: tmp551 << tmp541, map(vf3; V_SUB_F32 vDst(VGPR604) src0(VGPR590) src1(VGPR603) // VOP2 # 552: OpFMul: Float: tmp552 << tmp542, tmp551 V_MUL_F32 vDst(VGPR605) src0(VGPR580) src1(VGPR604) // VOP2 # 553: OpLoad: Float: tmp553 << r # 554: OpFAdd: Float: tmp554 << tmp553, tmp552 V_ADD_F32 vDst(VGPR606) src0(VGPR579) src1(VGPR605) // VOP2 # OpStore: : tmp554 >> r V_MOV_B32 vDst(VGPR579) src0(VGPR606) # 555: OpLoad: Float: tmp555 << w # 556: OpFMul: Float: tmp556 << tmp555, const275 V_MOV_B32 vDst(VGPR607) src0(0_5_F) V_MUL_F32 vDst(VGPR608) src0(VGPR580) src1(VGPR607) // VOP2 # OpStore: : tmp556 >> w V_MOV_B32 vDst(VGPR580) src0(VGPR608) # OpBranch: to lb533 # lb533 Label: lb533 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR202) # 557: OpLoad: Float: tmp557 << i # 558: OpFAdd: Float: tmp558 << tmp557, const117 V_MOV_B32 vDst(VGPR609) src0(1_0_F) V_ADD_F32 vDst(VGPR610) src0(VGPR581) src1(VGPR609) // VOP2 # OpStore: : tmp558 >> i V_MOV_B32 vDst(VGPR581) src0(VGPR610) # OpBranch: to lb530 S_BRANCH ??? lb530Loop # lb532 Label: lb532 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR200) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR198) # 559: OpLoad: Float: tmp559 << r # 560: OpFMul: Float: tmp560 << tmp559, const220 V_MOV_B32 vDst(VGPR611) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR612) src0(VGPR579) src1(VGPR611) // VOP2 # 561: OpExtInst(FClamp): Float: tmp561 << tmp560, const92, const117 V_MOV_B32 vDst(VGPR613) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR614) src0(1_0_F) V_MAX_F32 vDst(VGPR615) src0(VGPR612) src1(VGPR613) // VOP2 V_MIN_F32 vDst(VGPR615) src0(VGPR615) src1(VGPR614) // VOP2 # 562: OpFSub: Float: tmp562 << const117, tmp561 V_SUB_F32 vDst(VGPR616) src0(1_0_F) src1(VGPR615) // VOP2 # OpReturnValue: : << tmp562 S_MOV_B32 sDst(M0) src0(SGPR194) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR616) S_SETPC_B64 sDst(SGPR192) src0(SGPR192) # Bool isWall(vf3;(FloatVector3* p) Function: Bool isWall(vf3;() S_MOV_B64 sDst(SGPR214) src0(EXEC) # lb79 Label: lb79 # 565: OpAccessChain: Float*: p[0] # 566: OpLoad: Float: tmp566 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR621) src0(VGPR0) # 567: OpFAdd: Float: tmp567 << tmp566, const386 V_MOV_B32 vDst(VGPR622) src0(LITERAL_CONST) const: 0x3eb33333 V_ADD_F32 vDst(VGPR623) src0(VGPR621) src1(VGPR622) // VOP2 # 568: OpAccessChain: Float*: p[0] # OpStore: : tmp567 >> p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR623) # 570: OpLoad: FloatVector3: tmp570 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR624) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR625) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR626) src0(VGPR2) # 571: OpVectorShuffle: FloatVector2: tmp571 << tmp570, tmp570, 0, 2 V_MOV_B32 vDst(VGPR627) src0(VGPR624) V_MOV_B32 vDst(VGPR628) src0(VGPR626) # OpStore: : tmp571 >> param569 V_MOV_B32 vDst(VGPR617) src0(VGPR627) V_MOV_B32 vDst(VGPR618) src0(VGPR628) # OpStore: : const334 >> param572 V_MOV_B32 vDst(VGPR629) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR630) src0(1_0_F) V_MOV_B32 vDst(VGPR619) src0(VGPR629) V_MOV_B32 vDst(VGPR620) src0(VGPR630) # 573: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param569, param572) S_ADD_U32 sDst(SGPR77) src0(LITERAL_CONST) src1(0) const: 0x269 # VGPR[617:618] S_ADD_U32 sDst(SGPR78) src0(LITERAL_CONST) src1(0) const: 0x26b # VGPR[619:620] S_MOV_B64 sDst(SGPR216) src0(EXEC) S_MOV_B32 sDst(SGPR76) src0(LITERAL_CONST) const: 0x277 # VGPR[631:632] # Indirect branch to tRepeat2(vf2;vf2;: ??? S_GETPC_B64 sDst(SGPR74) src0(SGPR74) S_ADD_U32 sDst(SGPR74) src0(SGPR74) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR75) src0(SGPR75) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR74) src0(SGPR74) S_MOV_B64 sDst(EXEC) src0(SGPR216) # .lbl32 # 574: OpLoad: FloatVector2: tmp574 << param569 # 575: OpLoad: FloatVector3: tmp575 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR633) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR634) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR635) src0(VGPR2) # 576: OpVectorShuffle: FloatVector3: tmp576 << tmp575, tmp574, 3, 1, 4 V_MOV_B32 vDst(VGPR636) src0(VGPR617) V_MOV_B32 vDst(VGPR637) src0(VGPR634) V_MOV_B32 vDst(VGPR638) src0(VGPR618) # OpStore: : tmp576 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR636) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR637) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR638) # 577: OpAccessChain: Float*: p[1] # 578: OpLoad: Float: tmp578 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR639) src0(VGPR1) # 579: OpFAdd: Float: tmp579 << tmp578, const355 V_MOV_B32 vDst(VGPR640) src0(LITERAL_CONST) const: 0x3e19999a V_ADD_F32 vDst(VGPR641) src0(VGPR639) src1(VGPR640) // VOP2 # 580: OpExtInst(FAbs): Float: tmp580 << tmp579 V_ADD_F32 vDst(VGPR642) src0(VGPR641) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 581: OpLoad: FloatVector3: tmp581 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR213) const: 0x0 V_MOVRELS_B32 vDst(VGPR643) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR644) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR645) src0(VGPR2) # 582: OpVectorShuffle: FloatVector2: tmp582 << tmp581, tmp581, 0, 2 V_MOV_B32 vDst(VGPR646) src0(VGPR643) V_MOV_B32 vDst(VGPR647) src0(VGPR645) # 583: OpExtInst(Length): Float: tmp583 << tmp582 V_MUL_F32 vDst(VGPR648) src0(VGPR646) src1(VGPR646) // VOP2 V_MAC_F32 vDst(VGPR648) src0(VGPR647) src1(VGPR647) // VOP2 V_SQRT_F32 vDst(VGPR648) src0(VGPR648) # 584: OpFAdd: Float: tmp584 << tmp580, tmp583 V_ADD_F32 vDst(VGPR649) src0(VGPR642) src1(VGPR648) // VOP2 # 585: OpFOrdLessThan: Bool: tmp585 << const369, tmp584 V_MOV_B32 vDst(VGPR650) src0(LITERAL_CONST) const: 0x3ec00000 V_CMP_LT_F32 dst(SGPR218) src0(VGPR650) src1(VGPR649) // VOP3a # OpReturnValue: : << tmp585 S_MOV_B32 sDst(M0) src0(SGPR212) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR218) S_SETPC_B64 sDst(SGPR210) src0(SGPR210) # FloatVector3 _texture(vf3;(FloatVector3* p) Function: FloatVector3 _texture(vf3;() S_MOV_B64 sDst(SGPR224) src0(EXEC) # lb82 Label: lb82 # 589: OpLoad: FloatVector3: tmp589 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR671) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR672) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR673) src0(VGPR2) # OpStore: : tmp589 >> param588 V_MOV_B32 vDst(VGPR651) src0(VGPR671) V_MOV_B32 vDst(VGPR652) src0(VGPR672) V_MOV_B32 vDst(VGPR653) src0(VGPR673) # 591: OpLoad: Float: tmp591 << _twist # OpStore: : tmp591 >> param590 V_MOV_B32 vDst(VGPR654) src0(VGPR24) # 592: OpFunctionCall: Void: tTwist(vf3;f1;(param588, param590) S_ADD_U32 sDst(SGPR68) src0(LITERAL_CONST) src1(0) const: 0x28b # VGPR[651:653] S_ADD_U32 sDst(SGPR69) src0(LITERAL_CONST) src1(0) const: 0x28e # VGPR654 S_MOV_B64 sDst(SGPR226) src0(EXEC) # Indirect branch to tTwist(vf3;f1;: ??? S_GETPC_B64 sDst(SGPR66) src0(SGPR66) S_ADD_U32 sDst(SGPR66) src0(SGPR66) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR67) src0(SGPR67) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR66) src0(SGPR66) S_MOV_B64 sDst(EXEC) src0(SGPR226) # .lbl33 # 593: OpLoad: FloatVector3: tmp593 << param588 # OpStore: : tmp593 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR651) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR652) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR653) # 597: OpLoad: FloatVector3: tmp597 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR674) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR675) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR676) src0(VGPR2) # OpStore: : tmp597 >> param596 V_MOV_B32 vDst(VGPR655) src0(VGPR674) V_MOV_B32 vDst(VGPR656) src0(VGPR675) V_MOV_B32 vDst(VGPR657) src0(VGPR676) # 598: OpFunctionCall: Bool: isWall(vf3;(param596) S_ADD_U32 sDst(SGPR213) src0(LITERAL_CONST) src1(0) const: 0x28f # VGPR[655:657] S_MOV_B64 sDst(SGPR228) src0(EXEC) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x2a5 # VGPR677 # Indirect branch to isWall(vf3;: ??? S_GETPC_B64 sDst(SGPR210) src0(SGPR210) S_ADD_U32 sDst(SGPR210) src0(SGPR210) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR211) src0(SGPR211) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR210) src0(SGPR210) S_MOV_B64 sDst(EXEC) src0(SGPR228) # .lbl34 # 600: OpLoad: FloatVector3: tmp600 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR678) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR679) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR680) src0(VGPR2) # OpSelectionMerge: (merge: lb604) # CF Block: Merge: lb604 S_MOV_B64 sDst(SGPR230) src0(EXEC) # OpBranchConditional: if(isWall(vf3;) then branch to lb603, else branch to lb605 # CF Block: Cond Branch: true: lb603, false: lb605 S_AND_B64 sDst(EXEC) src0(VGPR677) src1(EXEC) S_CBRANCH_EXECZ ??? lb605 # lb603 Label: lb603 # OpStore: : const92 >> var601 V_MOV_B32 vDst(VGPR681) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR661) src0(VGPR681) # OpBranch: to lb604 # lb605 Label: lb605 S_ANDN2_B64 sDst(EXEC) src0(SGPR230) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR224) src1(EXEC) S_CBRANCH_EXECZ ??? lb604 # 608: OpLoad: FloatVector3: tmp608 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR682) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR683) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR684) src0(VGPR2) # 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp608, const536 V_MOV_B32 vDst(VGPR688) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR685) src0(VGPR688) src1(VGPR682) // VOP2 V_MUL_F32 vDst(VGPR686) src0(VGPR688) src1(VGPR683) // VOP2 V_MUL_F32 vDst(VGPR687) src0(VGPR688) src1(VGPR684) // VOP2 # OpStore: : tmp609 >> param610 V_MOV_B32 vDst(VGPR662) src0(VGPR685) V_MOV_B32 vDst(VGPR663) src0(VGPR686) V_MOV_B32 vDst(VGPR664) src0(VGPR687) # 611: OpFunctionCall: Float: fbm(vf3;(param610) S_ADD_U32 sDst(SGPR47) src0(LITERAL_CONST) src1(0) const: 0x296 # VGPR[662:664] S_MOV_B64 sDst(SGPR232) src0(EXEC) S_MOV_B32 sDst(SGPR46) src0(LITERAL_CONST) const: 0x2b1 # VGPR689 # Indirect branch to fbm(vf3;: ??? S_GETPC_B64 sDst(SGPR44) src0(SGPR44) S_ADD_U32 sDst(SGPR44) src0(SGPR44) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR45) src0(SGPR45) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR44) src0(SGPR44) S_MOV_B64 sDst(EXEC) src0(SGPR232) # .lbl35 # 612: OpFMul: Float: tmp612 << const607, fbm(vf3; V_MOV_B32 vDst(VGPR690) src0(LITERAL_CONST) const: 0x3f666666 V_MUL_F32 vDst(VGPR691) src0(VGPR690) src1(VGPR689) // VOP2 # 613: OpFAdd: Float: tmp613 << const606, tmp612 V_MOV_B32 vDst(VGPR692) src0(LITERAL_CONST) const: 0x3dcccccd V_ADD_F32 vDst(VGPR693) src0(VGPR692) src1(VGPR691) // VOP2 # OpStore: : tmp613 >> var601 V_MOV_B32 vDst(VGPR661) src0(VGPR693) # OpBranch: to lb604 # lb604 Label: lb604 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR230) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR224) # 614: OpLoad: Float: tmp614 << var601 # 615: OpCompositeConstruct: FloatVector3: tmp615 << tmp614, tmp614, tmp614 V_MOV_B32 vDst(VGPR694) src0(VGPR661) V_MOV_B32 vDst(VGPR695) src0(VGPR661) V_MOV_B32 vDst(VGPR696) src0(VGPR661) # 616: OpFAdd: FloatVector3: tmp616 << tmp600, tmp615 V_ADD_F32 vDst(VGPR697) src0(VGPR678) src1(VGPR694) // VOP2 V_ADD_F32 vDst(VGPR698) src0(VGPR679) src1(VGPR695) // VOP2 V_ADD_F32 vDst(VGPR699) src0(VGPR680) src1(VGPR696) // VOP2 # 619: OpFMul: FloatVector3: tmp619 << tmp616, const618 V_MOV_B32 vDst(VGPR700) src0(LITERAL_CONST) const: 0x40a00000 V_MOV_B32 vDst(VGPR701) src0(LITERAL_CONST) const: 0x41a00000 V_MOV_B32 vDst(VGPR702) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR703) src0(VGPR697) src1(VGPR700) // VOP2 V_MUL_F32 vDst(VGPR704) src0(VGPR698) src1(VGPR701) // VOP2 V_MUL_F32 vDst(VGPR705) src0(VGPR699) src1(VGPR702) // VOP2 # OpStore: : tmp619 >> param620 V_MOV_B32 vDst(VGPR665) src0(VGPR703) V_MOV_B32 vDst(VGPR666) src0(VGPR704) V_MOV_B32 vDst(VGPR667) src0(VGPR705) # 621: OpFunctionCall: Float: fbm(vf3;(param620) S_ADD_U32 sDst(SGPR47) src0(LITERAL_CONST) src1(0) const: 0x299 # VGPR[665:667] S_MOV_B64 sDst(SGPR234) src0(EXEC) S_MOV_B32 sDst(SGPR46) src0(LITERAL_CONST) const: 0x2c2 # VGPR706 # Indirect branch to fbm(vf3;: ??? S_GETPC_B64 sDst(SGPR44) src0(SGPR44) S_ADD_U32 sDst(SGPR44) src0(SGPR44) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR45) src0(SGPR45) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR44) src0(SGPR44) S_MOV_B64 sDst(EXEC) src0(SGPR234) # .lbl36 # 623: OpVectorTimesScalar: FloatVector3: tmp623 << const622, fbm(vf3; V_MOV_B32 vDst(VGPR710) src0(1_0_F) V_MOV_B32 vDst(VGPR711) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR712) src0(LITERAL_CONST) const: 0x3ecccccd V_MUL_F32 vDst(VGPR707) src0(VGPR706) src1(VGPR710) // VOP2 V_MUL_F32 vDst(VGPR708) src0(VGPR706) src1(VGPR711) // VOP2 V_MUL_F32 vDst(VGPR709) src0(VGPR706) src1(VGPR712) // VOP2 # 624: OpVectorTimesScalar: FloatVector3: tmp624 << tmp623, const360 V_MOV_B32 vDst(VGPR716) src0(LITERAL_CONST) const: 0x3f400000 V_MUL_F32 vDst(VGPR713) src0(VGPR716) src1(VGPR707) // VOP2 V_MUL_F32 vDst(VGPR714) src0(VGPR716) src1(VGPR708) // VOP2 V_MUL_F32 vDst(VGPR715) src0(VGPR716) src1(VGPR709) // VOP2 # 625: OpLoad: FloatVector3: tmp625 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR223) const: 0x0 V_MOVRELS_B32 vDst(VGPR717) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR718) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR719) src0(VGPR2) # 627: OpFMul: FloatVector3: tmp627 << tmp625, const626 V_MOV_B32 vDst(VGPR720) src0(2_0_F) V_MOV_B32 vDst(VGPR721) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR722) src0(2_0_F) V_MUL_F32 vDst(VGPR723) src0(VGPR717) src1(VGPR720) // VOP2 V_MUL_F32 vDst(VGPR724) src0(VGPR718) src1(VGPR721) // VOP2 V_MUL_F32 vDst(VGPR725) src0(VGPR719) src1(VGPR722) // VOP2 # OpStore: : tmp627 >> param628 V_MOV_B32 vDst(VGPR668) src0(VGPR723) V_MOV_B32 vDst(VGPR669) src0(VGPR724) V_MOV_B32 vDst(VGPR670) src0(VGPR725) # 629: OpFunctionCall: Float: fbm(vf3;(param628) S_ADD_U32 sDst(SGPR47) src0(LITERAL_CONST) src1(0) const: 0x29c # VGPR[668:670] S_MOV_B64 sDst(SGPR236) src0(EXEC) S_MOV_B32 sDst(SGPR46) src0(LITERAL_CONST) const: 0x2d6 # VGPR726 # Indirect branch to fbm(vf3;: ??? S_GETPC_B64 sDst(SGPR44) src0(SGPR44) S_ADD_U32 sDst(SGPR44) src0(SGPR44) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR45) src0(SGPR45) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR44) src0(SGPR44) S_MOV_B64 sDst(EXEC) src0(SGPR236) # .lbl37 # 631: OpVectorTimesScalar: FloatVector3: tmp631 << const630, fbm(vf3; V_MOV_B32 vDst(VGPR730) src0(1_0_F) V_MOV_B32 vDst(VGPR731) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR732) src0(0_5_F) V_MUL_F32 vDst(VGPR727) src0(VGPR726) src1(VGPR730) // VOP2 V_MUL_F32 vDst(VGPR728) src0(VGPR726) src1(VGPR731) // VOP2 V_MUL_F32 vDst(VGPR729) src0(VGPR726) src1(VGPR732) // VOP2 # 632: OpVectorTimesScalar: FloatVector3: tmp632 << tmp631, const363 V_MOV_B32 vDst(VGPR736) src0(LITERAL_CONST) const: 0x3e800000 V_MUL_F32 vDst(VGPR733) src0(VGPR736) src1(VGPR727) // VOP2 V_MUL_F32 vDst(VGPR734) src0(VGPR736) src1(VGPR728) // VOP2 V_MUL_F32 vDst(VGPR735) src0(VGPR736) src1(VGPR729) // VOP2 # 633: OpFAdd: FloatVector3: tmp633 << tmp624, tmp632 V_ADD_F32 vDst(VGPR737) src0(VGPR713) src1(VGPR733) // VOP2 V_ADD_F32 vDst(VGPR738) src0(VGPR714) src1(VGPR734) // VOP2 V_ADD_F32 vDst(VGPR739) src0(VGPR715) src1(VGPR735) // VOP2 # OpStore: : tmp633 >> t V_MOV_B32 vDst(VGPR658) src0(VGPR737) V_MOV_B32 vDst(VGPR659) src0(VGPR738) V_MOV_B32 vDst(VGPR660) src0(VGPR739) # OpSelectionMerge: (merge: lb636) # CF Block: Merge: lb636 S_MOV_B64 sDst(SGPR238) src0(EXEC) # OpBranchConditional: if(isWall(vf3;) then branch to lb635, else branch to lb636 # CF Block: Cond Branch: true: lb635, false: lb636 S_AND_B64 sDst(EXEC) src0(VGPR677) src1(EXEC) S_CBRANCH_EXECZ ??? lb636 # lb635 Label: lb635 # 637: OpLoad: FloatVector3: tmp637 << t # 638: OpCompositeConstruct: FloatVector3: tmp638 << const275, const275, const275 V_MOV_B32 vDst(VGPR740) src0(0_5_F) V_MOV_B32 vDst(VGPR741) src0(0_5_F) V_MOV_B32 vDst(VGPR742) src0(0_5_F) # 639: OpExtInst(FMix): FloatVector3: tmp639 << tmp637, const172, tmp638 V_MOV_B32 vDst(VGPR743) src0(1_0_F) V_MOV_B32 vDst(VGPR744) src0(1_0_F) V_MOV_B32 vDst(VGPR745) src0(1_0_F) V_SUBREV_F32 vDst(VGPR746) src0(VGPR740) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR746) src0(VGPR658) src1(VGPR746) // VOP2 V_MAD_F32 vDst(VGPR746) src0(VGPR743) src1(VGPR740) src2(VGPR746) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR747) src0(VGPR741) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR747) src0(VGPR659) src1(VGPR747) // VOP2 V_MAD_F32 vDst(VGPR747) src0(VGPR744) src1(VGPR741) src2(VGPR747) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR748) src0(VGPR742) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR748) src0(VGPR660) src1(VGPR748) // VOP2 V_MAD_F32 vDst(VGPR748) src0(VGPR745) src1(VGPR742) src2(VGPR748) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp639 >> t V_MOV_B32 vDst(VGPR658) src0(VGPR746) V_MOV_B32 vDst(VGPR659) src0(VGPR747) V_MOV_B32 vDst(VGPR660) src0(VGPR748) # OpBranch: to lb636 # lb636 Label: lb636 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR238) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR224) # 640: OpLoad: FloatVector3: tmp640 << t # 641: OpCompositeConstruct: FloatVector3: tmp641 << const92, const92, const92 V_MOV_B32 vDst(VGPR752) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR749) src0(VGPR752) V_MOV_B32 vDst(VGPR753) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR750) src0(VGPR753) V_MOV_B32 vDst(VGPR754) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR751) src0(VGPR754) # 642: OpCompositeConstruct: FloatVector3: tmp642 << const117, const117, const117 V_MOV_B32 vDst(VGPR755) src0(1_0_F) V_MOV_B32 vDst(VGPR756) src0(1_0_F) V_MOV_B32 vDst(VGPR757) src0(1_0_F) # 643: OpExtInst(FClamp): FloatVector3: tmp643 << tmp640, tmp641, tmp642 V_MAX_F32 vDst(VGPR758) src0(VGPR658) src1(VGPR749) // VOP2 V_MAX_F32 vDst(VGPR759) src0(VGPR659) src1(VGPR750) // VOP2 V_MAX_F32 vDst(VGPR760) src0(VGPR660) src1(VGPR751) // VOP2 V_MIN_F32 vDst(VGPR758) src0(VGPR758) src1(VGPR755) // VOP2 V_MIN_F32 vDst(VGPR759) src0(VGPR759) src1(VGPR756) // VOP2 V_MIN_F32 vDst(VGPR760) src0(VGPR760) src1(VGPR757) // VOP2 # OpReturnValue: : << tmp643 S_MOV_B32 sDst(M0) src0(SGPR222) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR758) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR759) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR760) S_SETPC_B64 sDst(SGPR220) src0(SGPR220) # Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) Function: Void mainImage(vf4;vf2;(, FloatVector2 main.fragCoord) S_MOV_B64 sDst(SGPR240) src0(EXEC) # lb89 Label: lb89 # 647: OpLoad: FloatVector2: tmp647 << fragCoord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR13) const: 0x0 V_MOVRELS_B32 vDst(VGPR814) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR815) src0(VGPR1) # 650: OpLoad: FloatVector3: tmp650 << iResolution S_LOAD_DWORDX2_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR[242:243]) S_WAITCNT 0 S_LOAD_DWORD_IMM offset(8) sBase(SGPR[0:1]) sDst(SGPR244) S_WAITCNT 0 # 651: OpVectorShuffle: FloatVector2: tmp651 << tmp650, tmp650, 0, 1 V_MOV_B32 vDst(VGPR816) src0(SGPR242) V_MOV_B32 vDst(VGPR817) src0(SGPR243) # 652: OpFDiv: FloatVector2: tmp652 << tmp647, tmp651 V_RCP_F32 vDst(VGPR818) src0(VGPR816) V_RCP_F32 vDst(VGPR819) src0(VGPR817) V_MUL_F32 vDst(VGPR818) src0(VGPR814) src1(VGPR818) // VOP2 V_MUL_F32 vDst(VGPR819) src0(VGPR815) src1(VGPR819) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR818) src0(VGPR818) src1(VGPR816) src2(VGPR814) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR819) src0(VGPR819) src1(VGPR817) src2(VGPR815) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 653: OpVectorTimesScalar: FloatVector2: tmp653 << tmp652, const227 V_MOV_B32 vDst(VGPR822) src0(2_0_F) V_MUL_F32 vDst(VGPR820) src0(VGPR822) src1(VGPR818) // VOP2 V_MUL_F32 vDst(VGPR821) src0(VGPR822) src1(VGPR819) // VOP2 # 654: OpCompositeConstruct: FloatVector2: tmp654 << const117, const117 V_MOV_B32 vDst(VGPR823) src0(1_0_F) V_MOV_B32 vDst(VGPR824) src0(1_0_F) # 655: OpFSub: FloatVector2: tmp655 << tmp653, tmp654 V_SUB_F32 vDst(VGPR825) src0(VGPR820) src1(VGPR823) // VOP2 V_SUB_F32 vDst(VGPR826) src0(VGPR821) src1(VGPR824) // VOP2 # OpStore: : tmp655 >> uv V_MOV_B32 vDst(VGPR761) src0(VGPR825) V_MOV_B32 vDst(VGPR762) src0(VGPR826) # 657: OpAccessChain: Float*: iResolution[0] # 658: OpLoad: Float: tmp658 << iResolution[0] S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR245) S_WAITCNT 0 # 659: OpAccessChain: Float*: iResolution[1] # 660: OpLoad: Float: tmp660 << iResolution[1] S_LOAD_DWORD_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR246) S_WAITCNT 0 # 661: OpFDiv: Float: tmp661 << tmp658, tmp660 V_MOV_B32 vDst(VGPR827) src0(SGPR246) V_RCP_F32 vDst(VGPR828) src0(VGPR827) V_MUL_F32 vDst(VGPR828) src0(SGPR245) src1(VGPR828) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR828) src0(VGPR828) src1(VGPR827) src2(SGPR245) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 662: OpAccessChain: Float*: uv[0] # 663: OpLoad: Float: tmp663 << uv[0] V_MOV_B32 vDst(VGPR829) src0(VGPR761) # 664: OpFMul: Float: tmp664 << tmp663, tmp661 V_MUL_F32 vDst(VGPR830) src0(VGPR829) src1(VGPR828) // VOP2 # 665: OpAccessChain: Float*: uv[0] # OpStore: : tmp664 >> uv[0] V_MOV_B32 vDst(VGPR761) src0(VGPR830) # 668: OpLoad: Float: tmp668 << iTime S_LOAD_DWORD_IMM offset(12) sBase(SGPR[0:1]) sDst(SGPR247) S_WAITCNT 0 # 669: OpFMul: Float: tmp669 << tmp668, const275 V_MOV_B32 vDst(VGPR831) src0(0_5_F) V_MUL_F32 vDst(VGPR832) src0(SGPR247) src1(VGPR831) // VOP2 # OpStore: : tmp669 >> time V_MOV_B32 vDst(VGPR763) src0(VGPR832) # 670: OpLoad: Float: tmp670 << time # 671: OpExtInst(Sin): Float: tmp671 << tmp670 V_MUL_F32 vDst(VGPR833) src0(LITERAL_CONST) src1(VGPR763) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR833) src0(VGPR833) V_SIN_F32 vDst(VGPR833) src0(VGPR833) # 672: OpFMul: Float: tmp672 << tmp671, const420 V_MOV_B32 vDst(VGPR834) src0(LITERAL_CONST) const: 0x3ecccccd V_MUL_F32 vDst(VGPR835) src0(VGPR833) src1(VGPR834) // VOP2 # OpStore: : tmp672 >> _twist V_MOV_B32 vDst(VGPR24) src0(VGPR835) # 674: OpLoad: Float: tmp674 << time # 676: OpFMul: Float: tmp676 << tmp674, const675 V_MOV_B32 vDst(VGPR836) src0(LITERAL_CONST) const: 0x40490fdb V_MUL_F32 vDst(VGPR837) src0(VGPR763) src1(VGPR836) // VOP2 # 677: OpFDiv: Float: tmp677 << tmp676, const227 V_MOV_B32 vDst(VGPR838) src0(2_0_F) V_RCP_F32 vDst(VGPR839) src0(VGPR838) V_MUL_F32 vDst(VGPR839) src0(VGPR837) src1(VGPR839) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR839) src0(VGPR839) src1(VGPR838) src2(VGPR837) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 678: OpFAdd: Float: tmp678 << tmp677, const117 V_MOV_B32 vDst(VGPR840) src0(1_0_F) V_ADD_F32 vDst(VGPR841) src0(VGPR839) src1(VGPR840) // VOP2 # 679: OpExtInst(Sin): Float: tmp679 << tmp678 V_MUL_F32 vDst(VGPR842) src0(LITERAL_CONST) src1(VGPR841) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR842) src0(VGPR842) V_SIN_F32 vDst(VGPR842) src0(VGPR842) # 680: OpFMul: Float: tmp680 << tmp679, const117 V_MOV_B32 vDst(VGPR843) src0(1_0_F) V_MUL_F32 vDst(VGPR844) src0(VGPR842) src1(VGPR843) // VOP2 # 681: OpLoad: Float: tmp681 << time # 682: OpCompositeConstruct: FloatVector3: tmp682 << tmp680, const92, tmp681 V_MOV_B32 vDst(VGPR845) src0(VGPR844) V_MOV_B32 vDst(VGPR848) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR846) src0(VGPR848) V_MOV_B32 vDst(VGPR847) src0(VGPR763) # OpStore: : tmp682 >> ro V_MOV_B32 vDst(VGPR764) src0(VGPR845) V_MOV_B32 vDst(VGPR765) src0(VGPR846) V_MOV_B32 vDst(VGPR766) src0(VGPR847) # 684: OpLoad: FloatVector2: tmp684 << uv # 686: OpCompositeExtract: Float: tmp686 << tmp684, 0 V_MOV_B32 vDst(VGPR849) src0(VGPR761) # 687: OpCompositeExtract: Float: tmp687 << tmp684, 1 V_MOV_B32 vDst(VGPR850) src0(VGPR762) # 688: OpCompositeConstruct: FloatVector3: tmp688 << tmp686, tmp687, const685 V_MOV_B32 vDst(VGPR851) src0(VGPR849) V_MOV_B32 vDst(VGPR852) src0(VGPR850) V_MOV_B32 vDst(VGPR854) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR853) src0(VGPR854) # 689: OpExtInst(Normalize): FloatVector3: tmp689 << tmp688 V_MUL_F32 vDst(VGPR855) src0(VGPR851) src1(VGPR851) // VOP2 V_MAC_F32 vDst(VGPR855) src0(VGPR852) src1(VGPR852) // VOP2 V_MAC_F32 vDst(VGPR855) src0(VGPR853) src1(VGPR853) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR855) src0(VGPR855) V_MUL_F32 vDst(VGPR856) src0(VGPR851) src1(VGPR855) // VOP2 V_MUL_F32 vDst(VGPR857) src0(VGPR852) src1(VGPR855) // VOP2 V_MUL_F32 vDst(VGPR858) src0(VGPR853) src1(VGPR855) // VOP2 # OpStore: : tmp689 >> rd V_MOV_B32 vDst(VGPR767) src0(VGPR856) V_MOV_B32 vDst(VGPR768) src0(VGPR857) V_MOV_B32 vDst(VGPR769) src0(VGPR858) # 690: OpLoad: Float: tmp690 << time # 691: OpFAdd: Float: tmp691 << tmp690, const227 V_MOV_B32 vDst(VGPR859) src0(2_0_F) V_ADD_F32 vDst(VGPR860) src0(VGPR763) src1(VGPR859) // VOP2 # OpStore: : tmp691 >> time V_MOV_B32 vDst(VGPR763) src0(VGPR860) # 693: OpLoad: Float: tmp693 << time # 694: OpFMul: Float: tmp694 << tmp693, const675 V_MOV_B32 vDst(VGPR861) src0(LITERAL_CONST) const: 0x40490fdb V_MUL_F32 vDst(VGPR862) src0(VGPR763) src1(VGPR861) // VOP2 # 695: OpFDiv: Float: tmp695 << tmp694, const227 V_MOV_B32 vDst(VGPR863) src0(2_0_F) V_RCP_F32 vDst(VGPR864) src0(VGPR863) V_MUL_F32 vDst(VGPR864) src0(VGPR862) src1(VGPR864) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR864) src0(VGPR864) src1(VGPR863) src2(VGPR862) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 696: OpFAdd: Float: tmp696 << tmp695, const117 V_MOV_B32 vDst(VGPR865) src0(1_0_F) V_ADD_F32 vDst(VGPR866) src0(VGPR864) src1(VGPR865) // VOP2 # 697: OpExtInst(Sin): Float: tmp697 << tmp696 V_MUL_F32 vDst(VGPR867) src0(LITERAL_CONST) src1(VGPR866) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR867) src0(VGPR867) V_SIN_F32 vDst(VGPR867) src0(VGPR867) # 698: OpFMul: Float: tmp698 << tmp697, const117 V_MOV_B32 vDst(VGPR868) src0(1_0_F) V_MUL_F32 vDst(VGPR869) src0(VGPR867) src1(VGPR868) // VOP2 # 699: OpLoad: Float: tmp699 << time # 700: OpCompositeConstruct: FloatVector3: tmp700 << tmp698, const92, tmp699 V_MOV_B32 vDst(VGPR870) src0(VGPR869) V_MOV_B32 vDst(VGPR873) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR871) src0(VGPR873) V_MOV_B32 vDst(VGPR872) src0(VGPR763) # OpStore: : tmp700 >> light V_MOV_B32 vDst(VGPR770) src0(VGPR870) V_MOV_B32 vDst(VGPR771) src0(VGPR871) V_MOV_B32 vDst(VGPR772) src0(VGPR872) # 701: OpLoad: Float: tmp701 << time # 702: OpFSub: Float: tmp702 << tmp701, const227 V_MOV_B32 vDst(VGPR874) src0(2_0_F) V_SUB_F32 vDst(VGPR875) src0(VGPR763) src1(VGPR874) // VOP2 # OpStore: : tmp702 >> time V_MOV_B32 vDst(VGPR763) src0(VGPR875) # 703: OpLoad: Float: tmp703 << time # 704: OpFMul: Float: tmp704 << tmp703, const675 V_MOV_B32 vDst(VGPR876) src0(LITERAL_CONST) const: 0x40490fdb V_MUL_F32 vDst(VGPR877) src0(VGPR763) src1(VGPR876) // VOP2 # 705: OpFDiv: Float: tmp705 << tmp704, const227 V_MOV_B32 vDst(VGPR878) src0(2_0_F) V_RCP_F32 vDst(VGPR879) src0(VGPR878) V_MUL_F32 vDst(VGPR879) src0(VGPR877) src1(VGPR879) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR879) src0(VGPR879) src1(VGPR878) src2(VGPR877) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 706: OpFAdd: Float: tmp706 << tmp705, const117 V_MOV_B32 vDst(VGPR880) src0(1_0_F) V_ADD_F32 vDst(VGPR881) src0(VGPR879) src1(VGPR880) // VOP2 # 707: OpExtInst(Cos): Float: tmp707 << tmp706 V_MUL_F32 vDst(VGPR882) src0(LITERAL_CONST) src1(VGPR881) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR882) src0(VGPR882) V_COS_F32 vDst(VGPR882) src0(VGPR882) # 708: OpFNegate: Float: tmp708 << tmp707 V_MUL_F32 vDst(VGPR883) src0(M1_0_F) src1(VGPR882) // VOP2 # 709: OpFMul: Float: tmp709 << tmp708, const275 V_MOV_B32 vDst(VGPR884) src0(0_5_F) V_MUL_F32 vDst(VGPR885) src0(VGPR883) src1(VGPR884) // VOP2 # 711: OpLoad: FloatVector3: tmp711 << rd # 712: OpVectorShuffle: FloatVector2: tmp712 << tmp711, tmp711, 0, 2 V_MOV_B32 vDst(VGPR886) src0(VGPR767) V_MOV_B32 vDst(VGPR887) src0(VGPR769) # OpStore: : tmp712 >> param710 V_MOV_B32 vDst(VGPR773) src0(VGPR886) V_MOV_B32 vDst(VGPR774) src0(VGPR887) # OpStore: : tmp709 >> param713 V_MOV_B32 vDst(VGPR775) src0(VGPR885) # 714: OpFunctionCall: Void: tRotate(vf2;f1;(param710, param713) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x305 # VGPR[773:774] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x307 # VGPR775 S_MOV_B64 sDst(SGPR248) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR248) # .lbl38 # 715: OpLoad: FloatVector2: tmp715 << param710 # 716: OpLoad: FloatVector3: tmp716 << rd # 717: OpVectorShuffle: FloatVector3: tmp717 << tmp716, tmp715, 3, 1, 4 V_MOV_B32 vDst(VGPR888) src0(VGPR773) V_MOV_B32 vDst(VGPR889) src0(VGPR768) V_MOV_B32 vDst(VGPR890) src0(VGPR774) # OpStore: : tmp717 >> rd V_MOV_B32 vDst(VGPR767) src0(VGPR888) V_MOV_B32 vDst(VGPR768) src0(VGPR889) V_MOV_B32 vDst(VGPR769) src0(VGPR890) # 718: OpAccessChain: Float*: ro[2] # 719: OpLoad: Float: tmp719 << ro[2] V_MOV_B32 vDst(VGPR891) src0(VGPR766) # 720: OpFNegate: Float: tmp720 << tmp719 V_MUL_F32 vDst(VGPR892) src0(M1_0_F) src1(VGPR891) // VOP2 # 721: OpLoad: Float: tmp721 << _twist # 722: OpFMul: Float: tmp722 << tmp720, tmp721 V_MUL_F32 vDst(VGPR893) src0(VGPR892) src1(VGPR24) // VOP2 # 724: OpLoad: FloatVector3: tmp724 << ro # 725: OpVectorShuffle: FloatVector2: tmp725 << tmp724, tmp724, 0, 1 V_MOV_B32 vDst(VGPR894) src0(VGPR764) V_MOV_B32 vDst(VGPR895) src0(VGPR765) # OpStore: : tmp725 >> param723 V_MOV_B32 vDst(VGPR776) src0(VGPR894) V_MOV_B32 vDst(VGPR777) src0(VGPR895) # OpStore: : tmp722 >> param726 V_MOV_B32 vDst(VGPR778) src0(VGPR893) # 727: OpFunctionCall: Void: tRotate(vf2;f1;(param723, param726) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x308 # VGPR[776:777] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x30a # VGPR778 S_MOV_B64 sDst(SGPR250) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR250) # .lbl39 # 728: OpLoad: FloatVector2: tmp728 << param723 # 729: OpLoad: FloatVector3: tmp729 << ro # 730: OpVectorShuffle: FloatVector3: tmp730 << tmp729, tmp728, 3, 4, 2 V_MOV_B32 vDst(VGPR896) src0(VGPR776) V_MOV_B32 vDst(VGPR897) src0(VGPR777) V_MOV_B32 vDst(VGPR898) src0(VGPR766) # OpStore: : tmp730 >> ro V_MOV_B32 vDst(VGPR764) src0(VGPR896) V_MOV_B32 vDst(VGPR765) src0(VGPR897) V_MOV_B32 vDst(VGPR766) src0(VGPR898) # 731: OpAccessChain: Float*: light[2] # 732: OpLoad: Float: tmp732 << light[2] V_MOV_B32 vDst(VGPR899) src0(VGPR772) # 733: OpFNegate: Float: tmp733 << tmp732 V_MUL_F32 vDst(VGPR900) src0(M1_0_F) src1(VGPR899) // VOP2 # 734: OpLoad: Float: tmp734 << _twist # 735: OpFMul: Float: tmp735 << tmp733, tmp734 V_MUL_F32 vDst(VGPR901) src0(VGPR900) src1(VGPR24) // VOP2 # 737: OpLoad: FloatVector3: tmp737 << light # 738: OpVectorShuffle: FloatVector2: tmp738 << tmp737, tmp737, 0, 1 V_MOV_B32 vDst(VGPR902) src0(VGPR770) V_MOV_B32 vDst(VGPR903) src0(VGPR771) # OpStore: : tmp738 >> param736 V_MOV_B32 vDst(VGPR779) src0(VGPR902) V_MOV_B32 vDst(VGPR780) src0(VGPR903) # OpStore: : tmp735 >> param739 V_MOV_B32 vDst(VGPR781) src0(VGPR901) # 740: OpFunctionCall: Void: tRotate(vf2;f1;(param736, param739) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x30b # VGPR[779:780] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x30d # VGPR781 S_MOV_B64 sDst(SGPR252) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR252) # .lbl40 # 741: OpLoad: FloatVector2: tmp741 << param736 # 742: OpLoad: FloatVector3: tmp742 << light # 743: OpVectorShuffle: FloatVector3: tmp743 << tmp742, tmp741, 3, 4, 2 V_MOV_B32 vDst(VGPR904) src0(VGPR779) V_MOV_B32 vDst(VGPR905) src0(VGPR780) V_MOV_B32 vDst(VGPR906) src0(VGPR772) # OpStore: : tmp743 >> light V_MOV_B32 vDst(VGPR770) src0(VGPR904) V_MOV_B32 vDst(VGPR771) src0(VGPR905) V_MOV_B32 vDst(VGPR772) src0(VGPR906) # 744: OpAccessChain: Float*: ro[2] # 745: OpLoad: Float: tmp745 << ro[2] V_MOV_B32 vDst(VGPR907) src0(VGPR766) # 746: OpFNegate: Float: tmp746 << tmp745 V_MUL_F32 vDst(VGPR908) src0(M1_0_F) src1(VGPR907) // VOP2 # 747: OpLoad: Float: tmp747 << _twist # 748: OpFMul: Float: tmp748 << tmp746, tmp747 V_MUL_F32 vDst(VGPR909) src0(VGPR908) src1(VGPR24) // VOP2 # 750: OpLoad: FloatVector3: tmp750 << rd # 751: OpVectorShuffle: FloatVector2: tmp751 << tmp750, tmp750, 0, 1 V_MOV_B32 vDst(VGPR910) src0(VGPR767) V_MOV_B32 vDst(VGPR911) src0(VGPR768) # OpStore: : tmp751 >> param749 V_MOV_B32 vDst(VGPR782) src0(VGPR910) V_MOV_B32 vDst(VGPR783) src0(VGPR911) # OpStore: : tmp748 >> param752 V_MOV_B32 vDst(VGPR784) src0(VGPR909) # 753: OpFunctionCall: Void: tRotate(vf2;f1;(param749, param752) S_ADD_U32 sDst(SGPR62) src0(LITERAL_CONST) src1(0) const: 0x30e # VGPR[782:783] S_ADD_U32 sDst(SGPR63) src0(LITERAL_CONST) src1(0) const: 0x310 # VGPR784 S_MOV_B64 sDst(SGPR254) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: ??? S_GETPC_B64 sDst(SGPR60) src0(SGPR60) S_ADD_U32 sDst(SGPR60) src0(SGPR60) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR61) src0(SGPR61) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR60) src0(SGPR60) S_MOV_B64 sDst(EXEC) src0(SGPR254) # .lbl41 # 754: OpLoad: FloatVector2: tmp754 << param749 # 755: OpLoad: FloatVector3: tmp755 << rd # 756: OpVectorShuffle: FloatVector3: tmp756 << tmp755, tmp754, 3, 4, 2 V_MOV_B32 vDst(VGPR912) src0(VGPR782) V_MOV_B32 vDst(VGPR913) src0(VGPR783) V_MOV_B32 vDst(VGPR914) src0(VGPR769) # OpStore: : tmp756 >> rd V_MOV_B32 vDst(VGPR767) src0(VGPR912) V_MOV_B32 vDst(VGPR768) src0(VGPR913) V_MOV_B32 vDst(VGPR769) src0(VGPR914) # 760: OpLoad: FloatVector3: tmp760 << ro # OpStore: : tmp760 >> param759 V_MOV_B32 vDst(VGPR785) src0(VGPR764) V_MOV_B32 vDst(VGPR786) src0(VGPR765) V_MOV_B32 vDst(VGPR787) src0(VGPR766) # 762: OpLoad: FloatVector3: tmp762 << rd # OpStore: : tmp762 >> param761 V_MOV_B32 vDst(VGPR788) src0(VGPR767) V_MOV_B32 vDst(VGPR789) src0(VGPR768) V_MOV_B32 vDst(VGPR790) src0(VGPR769) # OpStore: : const220 >> param763 V_MOV_B32 vDst(VGPR915) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR791) src0(VGPR915) # 765: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param759, param761, param763, param764) S_ADD_U32 sDst(SGPR149) src0(LITERAL_CONST) src1(0) const: 0x311 # VGPR[785:787] S_ADD_U32 sDst(SGPR150) src0(LITERAL_CONST) src1(0) const: 0x314 # VGPR[788:790] S_ADD_U32 sDst(SGPR151) src0(LITERAL_CONST) src1(0) const: 0x317 # VGPR791 S_ADD_U32 sDst(SGPR152) src0(LITERAL_CONST) src1(0) const: 0x318 # VGPR792 S_MOV_B64 sDst(SGPR256) src0(EXEC) S_MOV_B32 sDst(SGPR148) src0(LITERAL_CONST) const: 0x394 # VGPR916 # Indirect branch to trace(vf3;vf3;f1;f1;: ??? S_GETPC_B64 sDst(SGPR146) src0(SGPR146) S_ADD_U32 sDst(SGPR146) src0(SGPR146) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR147) src0(SGPR147) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR146) src0(SGPR146) S_MOV_B64 sDst(EXEC) src0(SGPR256) # .lbl42 # 766: OpLoad: Float: tmp766 << param764 # 768: OpLoad: FloatVector3: tmp768 << ro # 769: OpLoad: FloatVector3: tmp769 << rd # 771: OpVectorTimesScalar: FloatVector3: tmp771 << tmp769, trace(vf3;vf3;f1;f1; V_MUL_F32 vDst(VGPR917) src0(VGPR916) src1(VGPR767) // VOP2 V_MUL_F32 vDst(VGPR918) src0(VGPR916) src1(VGPR768) // VOP2 V_MUL_F32 vDst(VGPR919) src0(VGPR916) src1(VGPR769) // VOP2 # 772: OpFAdd: FloatVector3: tmp772 << tmp768, tmp771 V_ADD_F32 vDst(VGPR920) src0(VGPR764) src1(VGPR917) // VOP2 V_ADD_F32 vDst(VGPR921) src0(VGPR765) src1(VGPR918) // VOP2 V_ADD_F32 vDst(VGPR922) src0(VGPR766) src1(VGPR919) // VOP2 # OpStore: : tmp772 >> param774 V_MOV_B32 vDst(VGPR793) src0(VGPR920) V_MOV_B32 vDst(VGPR794) src0(VGPR921) V_MOV_B32 vDst(VGPR795) src0(VGPR922) # 776: OpFunctionCall: FloatVector3: getNormal(vf3;(param774) S_ADD_U32 sDst(SGPR177) src0(LITERAL_CONST) src1(0) const: 0x319 # VGPR[793:795] S_MOV_B64 sDst(SGPR258) src0(EXEC) S_MOV_B32 sDst(SGPR176) src0(LITERAL_CONST) const: 0x39b # VGPR[923:925] # Indirect branch to getNormal(vf3;: ??? S_GETPC_B64 sDst(SGPR174) src0(SGPR174) S_ADD_U32 sDst(SGPR174) src0(SGPR174) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR175) src0(SGPR175) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR174) src0(SGPR174) S_MOV_B64 sDst(EXEC) src0(SGPR258) # .lbl43 # 778: OpLoad: FloatVector3: tmp778 << light # 780: OpFSub: FloatVector3: tmp780 << tmp778, tmp772 V_SUB_F32 vDst(VGPR926) src0(VGPR770) src1(VGPR920) // VOP2 V_SUB_F32 vDst(VGPR927) src0(VGPR771) src1(VGPR921) // VOP2 V_SUB_F32 vDst(VGPR928) src0(VGPR772) src1(VGPR922) // VOP2 # 781: OpExtInst(Normalize): FloatVector3: tmp781 << tmp780 V_MUL_F32 vDst(VGPR929) src0(VGPR926) src1(VGPR926) // VOP2 V_MAC_F32 vDst(VGPR929) src0(VGPR927) src1(VGPR927) // VOP2 V_MAC_F32 vDst(VGPR929) src0(VGPR928) src1(VGPR928) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR929) src0(VGPR929) V_MUL_F32 vDst(VGPR930) src0(VGPR926) src1(VGPR929) // VOP2 V_MUL_F32 vDst(VGPR931) src0(VGPR927) src1(VGPR929) // VOP2 V_MUL_F32 vDst(VGPR932) src0(VGPR928) src1(VGPR929) // VOP2 # 785: OpVectorTimesScalar: FloatVector3: tmp785 << getNormal(vf3;, const467 V_MOV_B32 vDst(VGPR936) src0(LITERAL_CONST) const: 0x3727c5ac V_MUL_F32 vDst(VGPR933) src0(VGPR936) src1(VGPR923) // VOP2 V_MUL_F32 vDst(VGPR934) src0(VGPR936) src1(VGPR924) // VOP2 V_MUL_F32 vDst(VGPR935) src0(VGPR936) src1(VGPR925) // VOP2 # 786: OpVectorTimesScalar: FloatVector3: tmp786 << tmp785, const220 V_MOV_B32 vDst(VGPR940) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR937) src0(VGPR940) src1(VGPR933) // VOP2 V_MUL_F32 vDst(VGPR938) src0(VGPR940) src1(VGPR934) // VOP2 V_MUL_F32 vDst(VGPR939) src0(VGPR940) src1(VGPR935) // VOP2 # 787: OpFAdd: FloatVector3: tmp787 << tmp772, tmp786 V_ADD_F32 vDst(VGPR941) src0(VGPR920) src1(VGPR937) // VOP2 V_ADD_F32 vDst(VGPR942) src0(VGPR921) src1(VGPR938) // VOP2 V_ADD_F32 vDst(VGPR943) src0(VGPR922) src1(VGPR939) // VOP2 # 790: OpLoad: FloatVector3: tmp790 << light # 791: OpExtInst(Distance): Float: tmp791 << tmp787, tmp790 V_SUB_F32 vDst(VGPR944) src0(VGPR941) src1(VGPR770) // VOP2 V_SUB_F32 vDst(VGPR945) src0(VGPR942) src1(VGPR771) // VOP2 V_SUB_F32 vDst(VGPR946) src0(VGPR943) src1(VGPR772) // VOP2 V_MUL_F32 vDst(VGPR947) src0(VGPR944) src1(VGPR944) // VOP2 V_MAC_F32 vDst(VGPR947) src0(VGPR945) src1(VGPR945) // VOP2 V_MAC_F32 vDst(VGPR947) src0(VGPR946) src1(VGPR946) // VOP2 V_SQRT_F32 vDst(VGPR947) src0(VGPR947) # OpStore: : tmp787 >> param794 V_MOV_B32 vDst(VGPR797) src0(VGPR941) V_MOV_B32 vDst(VGPR798) src0(VGPR942) V_MOV_B32 vDst(VGPR799) src0(VGPR943) # OpStore: : tmp781 >> param796 V_MOV_B32 vDst(VGPR800) src0(VGPR930) V_MOV_B32 vDst(VGPR801) src0(VGPR931) V_MOV_B32 vDst(VGPR802) src0(VGPR932) # OpStore: : tmp791 >> param798 V_MOV_B32 vDst(VGPR803) src0(VGPR947) # 801: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param794, param796, param798, param800) S_ADD_U32 sDst(SGPR149) src0(LITERAL_CONST) src1(0) const: 0x31d # VGPR[797:799] S_ADD_U32 sDst(SGPR150) src0(LITERAL_CONST) src1(0) const: 0x320 # VGPR[800:802] S_ADD_U32 sDst(SGPR151) src0(LITERAL_CONST) src1(0) const: 0x323 # VGPR803 S_ADD_U32 sDst(SGPR152) src0(LITERAL_CONST) src1(0) const: 0x324 # VGPR804 S_MOV_B64 sDst(SGPR260) src0(EXEC) S_MOV_B32 sDst(SGPR148) src0(LITERAL_CONST) const: 0x3b4 # VGPR948 # Indirect branch to trace(vf3;vf3;f1;f1;: ??? S_GETPC_B64 sDst(SGPR146) src0(SGPR146) S_ADD_U32 sDst(SGPR146) src0(SGPR146) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR147) src0(SGPR147) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR146) src0(SGPR146) S_MOV_B64 sDst(EXEC) src0(SGPR260) # .lbl44 # 802: OpLoad: Float: tmp802 << param800 # 804: OpFOrdGreaterThan: Bool: tmp804 << trace(vf3;vf3;f1;f1;, tmp791 V_CMP_GT_F32 dst(SGPR262) src0(VGPR948) src1(VGPR947) // VOP3a # 805: OpSelect: Float: tmp805 << tmp804, const117, const92 # CF Block: Merge: .lbl46 S_MOV_B64 sDst(SGPR264) src0(EXEC) # CF Block: Cond Branch: true: .lbl47, false: .lbl45 S_AND_B64 sDst(EXEC) src0(SGPR262) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl45 Label: .lbl47 V_MOV_B32 vDst(VGPR949) src0(1_0_F) Label: .lbl45 S_ANDN2_B64 sDst(EXEC) src0(SGPR264) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR240) src1(EXEC) S_CBRANCH_EXECZ ??? .lbl46 V_MOV_B32 vDst(VGPR950) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR949) src0(VGPR950) Label: .lbl46 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR264) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR240) # OpStore: : tmp805 >> shadow V_MOV_B32 vDst(VGPR796) src0(VGPR949) # 808: OpFDiv: Float: tmp808 << tmp802, const807 V_MOV_B32 vDst(VGPR951) src0(LITERAL_CONST) const: 0x42c80000 V_RCP_F32 vDst(VGPR952) src0(VGPR951) V_MUL_F32 vDst(VGPR952) src0(VGPR804) src1(VGPR952) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR952) src0(VGPR952) src1(VGPR951) src2(VGPR804) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 809: OpExtInst(Sqrt): Float: tmp809 << tmp808 V_SQRT_F32 vDst(VGPR953) src0(VGPR952) # 810: OpFSub: Float: tmp810 << const117, tmp809 V_SUB_F32 vDst(VGPR954) src0(1_0_F) src1(VGPR953) // VOP2 # 811: OpLoad: Float: tmp811 << shadow # 812: OpFMul: Float: tmp812 << tmp811, tmp810 V_MUL_F32 vDst(VGPR955) src0(VGPR796) src1(VGPR954) // VOP2 # OpStore: : tmp812 >> shadow V_MOV_B32 vDst(VGPR796) src0(VGPR955) # 817: OpDot: Float: tmp817 << tmp781, getNormal(vf3; V_MUL_F32 vDst(VGPR956) src0(VGPR930) src1(VGPR923) // VOP2 V_MAC_F32 vDst(VGPR956) src0(VGPR931) src1(VGPR924) // VOP2 V_MAC_F32 vDst(VGPR956) src0(VGPR932) src1(VGPR925) // VOP2 # 818: OpExtInst(FMax): Float: tmp818 << const92, tmp817 V_MOV_B32 vDst(VGPR957) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR958) src0(VGPR957) src1(VGPR956) // VOP2 # 821: OpFNegate: FloatVector3: tmp821 << tmp781 V_MUL_F32 vDst(VGPR959) src0(M1_0_F) src1(VGPR930) // VOP2 V_MUL_F32 vDst(VGPR960) src0(M1_0_F) src1(VGPR931) // VOP2 V_MUL_F32 vDst(VGPR961) src0(M1_0_F) src1(VGPR932) // VOP2 # 823: OpExtInst(Reflect): FloatVector3: tmp823 << tmp821, getNormal(vf3; V_MUL_F32 vDst(VGPR965) src0(VGPR959) src1(VGPR923) // VOP2 V_MAC_F32 vDst(VGPR965) src0(VGPR960) src1(VGPR924) // VOP2 V_MAC_F32 vDst(VGPR965) src0(VGPR961) src1(VGPR925) // VOP2 V_MUL_F32 vDst(VGPR965) src0(2_0_F) src1(VGPR965) // VOP2 V_MUL_F32 vDst(VGPR962) src0(VGPR923) src1(VGPR965) // VOP2 V_MUL_F32 vDst(VGPR963) src0(VGPR924) src1(VGPR965) // VOP2 V_MUL_F32 vDst(VGPR964) src0(VGPR925) src1(VGPR965) // VOP2 V_SUB_F32 vDst(VGPR962) src0(VGPR959) src1(VGPR962) // VOP2 V_SUB_F32 vDst(VGPR963) src0(VGPR960) src1(VGPR963) // VOP2 V_SUB_F32 vDst(VGPR964) src0(VGPR961) src1(VGPR964) // VOP2 # 824: OpLoad: FloatVector3: tmp824 << rd # 825: OpFNegate: FloatVector3: tmp825 << tmp824 V_MUL_F32 vDst(VGPR966) src0(M1_0_F) src1(VGPR767) // VOP2 V_MUL_F32 vDst(VGPR967) src0(M1_0_F) src1(VGPR768) // VOP2 V_MUL_F32 vDst(VGPR968) src0(M1_0_F) src1(VGPR769) // VOP2 # 826: OpDot: Float: tmp826 << tmp823, tmp825 V_MUL_F32 vDst(VGPR969) src0(VGPR962) src1(VGPR966) // VOP2 V_MAC_F32 vDst(VGPR969) src0(VGPR963) src1(VGPR967) // VOP2 V_MAC_F32 vDst(VGPR969) src0(VGPR964) src1(VGPR968) // VOP2 # 827: OpExtInst(FMax): Float: tmp827 << const92, tmp826 V_MOV_B32 vDst(VGPR970) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR971) src0(VGPR970) src1(VGPR969) // VOP2 # 829: OpExtInst(Pow): Float: tmp829 << tmp827, const828 V_MOV_B32 vDst(VGPR972) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR973) src0(VGPR971) V_MUL_F32 vDst(VGPR973) src0(VGPR972) src1(VGPR973) // VOP2 V_EXP_F32 vDst(VGPR973) src0(VGPR973) # OpStore: : tmp772 >> param831 V_MOV_B32 vDst(VGPR805) src0(VGPR920) V_MOV_B32 vDst(VGPR806) src0(VGPR921) V_MOV_B32 vDst(VGPR807) src0(VGPR922) # OpStore: : getNormal(vf3; >> param833 V_MOV_B32 vDst(VGPR808) src0(VGPR923) V_MOV_B32 vDst(VGPR809) src0(VGPR924) V_MOV_B32 vDst(VGPR810) src0(VGPR925) # 835: OpFunctionCall: Float: calculateAO(vf3;vf3;(param831, param833) S_ADD_U32 sDst(SGPR195) src0(LITERAL_CONST) src1(0) const: 0x325 # VGPR[805:807] S_ADD_U32 sDst(SGPR196) src0(LITERAL_CONST) src1(0) const: 0x328 # VGPR[808:810] S_MOV_B64 sDst(SGPR266) src0(EXEC) S_MOV_B32 sDst(SGPR194) src0(LITERAL_CONST) const: 0x3ce # VGPR974 # Indirect branch to calculateAO(vf3;vf3;: ??? S_GETPC_B64 sDst(SGPR192) src0(SGPR192) S_ADD_U32 sDst(SGPR192) src0(SGPR192) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR193) src0(SGPR193) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR192) src0(SGPR192) S_MOV_B64 sDst(EXEC) src0(SGPR266) # .lbl48 # OpStore: : tmp772 >> param837 V_MOV_B32 vDst(VGPR811) src0(VGPR920) V_MOV_B32 vDst(VGPR812) src0(VGPR921) V_MOV_B32 vDst(VGPR813) src0(VGPR922) # 839: OpFunctionCall: FloatVector3: _texture(vf3;(param837) S_ADD_U32 sDst(SGPR223) src0(LITERAL_CONST) src1(0) const: 0x32b # VGPR[811:813] S_MOV_B64 sDst(SGPR268) src0(EXEC) S_MOV_B32 sDst(SGPR222) src0(LITERAL_CONST) const: 0x3cf # VGPR[975:977] # Indirect branch to _texture(vf3;: ??? S_GETPC_B64 sDst(SGPR220) src0(SGPR220) S_ADD_U32 sDst(SGPR220) src0(SGPR220) src1(LITERAL_CONST) const: 0x0 S_ADDC_U32 sDst(SGPR221) src0(SGPR221) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR220) src0(SGPR220) S_MOV_B64 sDst(EXEC) src0(SGPR268) # .lbl49 # 840: OpVectorTimesScalar: FloatVector3: tmp840 << _texture(vf3;, calculateAO(vf3;vf3; V_MUL_F32 vDst(VGPR978) src0(VGPR974) src1(VGPR975) // VOP2 V_MUL_F32 vDst(VGPR979) src0(VGPR974) src1(VGPR976) // VOP2 V_MUL_F32 vDst(VGPR980) src0(VGPR974) src1(VGPR977) // VOP2 # 844: OpFAdd: Float: tmp844 << tmp829, tmp818 V_ADD_F32 vDst(VGPR981) src0(VGPR973) src1(VGPR958) // VOP2 # 845: OpLoad: Float: tmp845 << shadow # 846: OpFMul: Float: tmp846 << tmp844, tmp845 V_MUL_F32 vDst(VGPR982) src0(VGPR981) src1(VGPR796) // VOP2 # 847: OpFAdd: Float: tmp847 << const363, tmp846 V_MOV_B32 vDst(VGPR983) src0(LITERAL_CONST) const: 0x3e800000 V_ADD_F32 vDst(VGPR984) src0(VGPR983) src1(VGPR982) // VOP2 # 848: OpVectorTimesScalar: FloatVector3: tmp848 << tmp840, tmp847 V_MUL_F32 vDst(VGPR985) src0(VGPR984) src1(VGPR978) // VOP2 V_MUL_F32 vDst(VGPR986) src0(VGPR984) src1(VGPR979) // VOP2 V_MUL_F32 vDst(VGPR987) src0(VGPR984) src1(VGPR980) // VOP2 # 849: OpLoad: FloatVector4: tmp849 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR988) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR989) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR990) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR991) src0(VGPR3) # 850: OpVectorShuffle: FloatVector4: tmp850 << tmp849, tmp848, 4, 5, 6, 3 V_MOV_B32 vDst(VGPR992) src0(VGPR985) V_MOV_B32 vDst(VGPR993) src0(VGPR986) V_MOV_B32 vDst(VGPR994) src0(VGPR987) V_MOV_B32 vDst(VGPR995) src0(VGPR991) # OpStore: : tmp850 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR992) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR993) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR994) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR995) # 852: OpFDiv: Float: tmp852 << tmp766, const807 V_MOV_B32 vDst(VGPR996) src0(LITERAL_CONST) const: 0x42c80000 V_RCP_F32 vDst(VGPR997) src0(VGPR996) V_MUL_F32 vDst(VGPR997) src0(VGPR792) src1(VGPR997) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR997) src0(VGPR997) src1(VGPR996) src2(VGPR792) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 853: OpExtInst(Sqrt): Float: tmp853 << tmp852 V_SQRT_F32 vDst(VGPR998) src0(VGPR997) # 854: OpLoad: FloatVector4: tmp854 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR999) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1000) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1001) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1002) src0(VGPR3) # 855: OpVectorTimesScalar: FloatVector4: tmp855 << tmp854, tmp853 V_MUL_F32 vDst(VGPR1003) src0(VGPR998) src1(VGPR999) // VOP2 V_MUL_F32 vDst(VGPR1004) src0(VGPR998) src1(VGPR1000) // VOP2 V_MUL_F32 vDst(VGPR1005) src0(VGPR998) src1(VGPR1001) // VOP2 V_MUL_F32 vDst(VGPR1006) src0(VGPR998) src1(VGPR1002) // VOP2 # OpStore: : tmp855 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1003) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1004) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1005) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1006) # 856: OpLoad: FloatVector4: tmp856 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1007) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1008) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1009) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1010) src0(VGPR3) # 860: OpFMul: Float: tmp860 << trace(vf3;vf3;f1;f1;, trace(vf3;vf3;f1;f1; V_MUL_F32 vDst(VGPR1011) src0(VGPR916) src1(VGPR916) // VOP2 # 862: OpFMul: Float: tmp862 << tmp860, const861 V_MOV_B32 vDst(VGPR1012) src0(LITERAL_CONST) const: 0x3cf5c28f V_MUL_F32 vDst(VGPR1013) src0(VGPR1011) src1(VGPR1012) // VOP2 # 863: OpExtInst(FClamp): Float: tmp863 << tmp862, const92, const117 V_MOV_B32 vDst(VGPR1014) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR1015) src0(1_0_F) V_MAX_F32 vDst(VGPR1016) src0(VGPR1013) src1(VGPR1014) // VOP2 V_MIN_F32 vDst(VGPR1016) src0(VGPR1016) src1(VGPR1015) // VOP2 # 864: OpCompositeConstruct: FloatVector4: tmp864 << tmp863, tmp863, tmp863, tmp863 V_MOV_B32 vDst(VGPR1017) src0(VGPR1016) V_MOV_B32 vDst(VGPR1018) src0(VGPR1016) V_MOV_B32 vDst(VGPR1019) src0(VGPR1016) V_MOV_B32 vDst(VGPR1020) src0(VGPR1016) # 865: OpExtInst(FMix): FloatVector4: tmp865 << tmp856, const857, tmp864 V_MOV_B32 vDst(VGPR1021) src0(LITERAL_CONST) const: 0x3f666666 V_MOV_B32 vDst(VGPR1022) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR1023) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR1024) src0(1_0_F) V_SUBREV_F32 vDst(VGPR1025) src0(VGPR1017) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1025) src0(VGPR1007) src1(VGPR1025) // VOP2 V_MAD_F32 vDst(VGPR1025) src0(VGPR1021) src1(VGPR1017) src2(VGPR1025) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1026) src0(VGPR1018) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1026) src0(VGPR1008) src1(VGPR1026) // VOP2 V_MAD_F32 vDst(VGPR1026) src0(VGPR1022) src1(VGPR1018) src2(VGPR1026) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1027) src0(VGPR1019) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1027) src0(VGPR1009) src1(VGPR1027) // VOP2 V_MAD_F32 vDst(VGPR1027) src0(VGPR1023) src1(VGPR1019) src2(VGPR1027) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR1028) src0(VGPR1020) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR1028) src0(VGPR1010) src1(VGPR1028) // VOP2 V_MAD_F32 vDst(VGPR1028) src0(VGPR1024) src1(VGPR1020) src2(VGPR1028) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp865 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1025) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1026) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1027) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1028) # 866: OpLoad: FloatVector4: tmp866 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR1029) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR1030) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR1031) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR1032) src0(VGPR3) # 869: OpExtInst(Pow): FloatVector4: tmp869 << tmp866, const868 V_MOV_B32 vDst(VGPR1033) src0(LITERAL_CONST) const: 0x3ee8ba2f V_MOV_B32 vDst(VGPR1034) src0(LITERAL_CONST) const: 0x3ee8ba2f V_MOV_B32 vDst(VGPR1035) src0(LITERAL_CONST) const: 0x3ee8ba2f V_MOV_B32 vDst(VGPR1036) src0(LITERAL_CONST) const: 0x3ee8ba2f V_LOG_F32 vDst(VGPR1037) src0(VGPR1029) V_LOG_F32 vDst(VGPR1038) src0(VGPR1030) V_LOG_F32 vDst(VGPR1039) src0(VGPR1031) V_LOG_F32 vDst(VGPR1040) src0(VGPR1032) V_MUL_F32 vDst(VGPR1037) src0(VGPR1033) src1(VGPR1037) // VOP2 V_MUL_F32 vDst(VGPR1038) src0(VGPR1034) src1(VGPR1038) // VOP2 V_MUL_F32 vDst(VGPR1039) src0(VGPR1035) src1(VGPR1039) // VOP2 V_MUL_F32 vDst(VGPR1040) src0(VGPR1036) src1(VGPR1040) // VOP2 V_EXP_F32 vDst(VGPR1037) src0(VGPR1037) V_EXP_F32 vDst(VGPR1038) src0(VGPR1038) V_EXP_F32 vDst(VGPR1039) src0(VGPR1039) V_EXP_F32 vDst(VGPR1040) src0(VGPR1040) # OpStore: : tmp869 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR1037) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR1038) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR1039) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR1040) # OpReturn: S_SETPC_B64 sDst(SGPR10) src0(SGPR10) Performing register allocation... Register VGPR24 contains scalar/constant data. Will try converting to SGPR. Register VGPR24 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR893) src0(VGPR892) src1(VGPR24) // VOP2 Register VGPR25 contains scalar/constant data. Will try converting to SGPR. Register VGPR[26:29] contains scalar/constant data. Will try converting to SGPR. Register VGPR[30:31] contains scalar/constant data. Will try converting to SGPR. Register VGPR[39:41] contains scalar/constant data. Will try converting to SGPR. Register VGPR[39:41] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR42) src0(VGPR36) src1(VGPR39) // VOP2 Register VGPR44 contains scalar/constant data. Will try converting to SGPR. Register VGPR44 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR45) src0(VGPR43) src1(VGPR44) // VOP2 Register VGPR[77:79] contains scalar/constant data. Will try converting to SGPR. Register VGPR[77:79] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR80) src0(VGPR74) src1(VGPR77) // VOP2 Register VGPR[84:86] contains scalar/constant data. Will try converting to SGPR. Register VGPR[84:86] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR87) src0(VGPR74) src1(VGPR84) // VOP2 Register VGPR[91:93] contains scalar/constant data. Will try converting to SGPR. Register VGPR[91:93] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR94) src0(VGPR74) src1(VGPR91) // VOP2 Register VGPR[98:100] contains scalar/constant data. Will try converting to SGPR. Register VGPR[98:100] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR101) src0(VGPR74) src1(VGPR98) // VOP2 Register VGPR[124:126] contains scalar/constant data. Will try converting to SGPR. Register VGPR[124:126] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR127) src0(VGPR74) src1(VGPR124) // VOP2 Register VGPR[131:133] contains scalar/constant data. Will try converting to SGPR. Register VGPR[131:133] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR134) src0(VGPR74) src1(VGPR131) // VOP2 Register VGPR[138:140] contains scalar/constant data. Will try converting to SGPR. Register VGPR[138:140] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR141) src0(VGPR74) src1(VGPR138) // VOP2 Register VGPR[145:147] contains scalar/constant data. Will try converting to SGPR. Register VGPR[145:147] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR148) src0(VGPR74) src1(VGPR145) // VOP2 Register VGPR175 contains scalar/constant data. Will try converting to SGPR. Register VGPR175 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR194) src0(VGPR175) src1(VGPR191) // VOP2 Register VGPR176 contains scalar/constant data. Will try converting to SGPR. Register VGPR180 contains scalar/constant data. Will try converting to SGPR. Register VGPR181 contains scalar/constant data. Will try converting to SGPR. Register VGPR[185:187] contains scalar/constant data. Will try converting to SGPR. Register VGPR[185:187] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR191) src0(VGPR182) src1(VGPR185) // VOP2 Register VGPR188 contains scalar/constant data. Will try converting to SGPR. Register VGPR189 contains scalar/constant data. Will try converting to SGPR. Register VGPR190 contains scalar/constant data. Will try converting to SGPR. Register VGPR198 contains scalar/constant data. Will try converting to SGPR. Register VGPR198 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR199) src0(VGPR175) src1(VGPR198) // VOP2 Register VGPR199 contains scalar/constant data. Will try converting to SGPR. Register VGPR199 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR199) src0(VGPR175) src1(VGPR198) // VOP2 Register VGPR202 contains scalar/constant data. Will try converting to SGPR. Register VGPR203 contains scalar/constant data. Will try converting to SGPR. Register VGPR204 contains scalar/constant data. Will try converting to SGPR. Register VGPR204 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR204) src0(VGPR175) Register VGPR205 contains scalar/constant data. Will try converting to SGPR. Register VGPR205 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR205) src0(1_0_F) src1(VGPR204) // VOP2 Register VGPR247 contains scalar/constant data. Will try converting to SGPR. Register VGPR247 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR245) src0(VGPR247) src1(VGPR243) // VOP2 Register VGPR262 contains scalar/constant data. Will try converting to SGPR. Register VGPR262 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR260) src0(VGPR262) src1(VGPR258) // VOP2 Register VGPR273 contains scalar/constant data. Will try converting to SGPR. Register VGPR273 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR271) src0(VGPR273) src1(VGPR269) // VOP2 Register VGPR287 contains scalar/constant data. Will try converting to SGPR. Register VGPR287 can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR288) src0(VGPR286) src1(VGPR287) // VOP2 Register VGPR[291:292] contains scalar/constant data. Will try converting to SGPR. Register VGPR[291:292] can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR295) src0(VGPR289) src1(VGPR291) // VOP2 Register VGPR293 contains scalar/constant data. Will try converting to SGPR. Register VGPR294 contains scalar/constant data. Will try converting to SGPR. Register VGPR[358:359] contains scalar/constant data. Will try converting to SGPR. Register VGPR371 contains scalar/constant data. Will try converting to SGPR. Register VGPR371 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR372) src0(VGPR370) src1(VGPR371) // VOP2 Register VGPR375 contains scalar/constant data. Will try converting to SGPR. Register VGPR375 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR376) src0(VGPR374) src1(VGPR375) // VOP2 Register VGPR[382:383] contains scalar/constant data. Will try converting to SGPR. Register VGPR[382:383] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR384) src0(VGPR380) src1(VGPR382) // VOP2 Register VGPR386 contains scalar/constant data. Will try converting to SGPR. Register VGPR[393:394] contains scalar/constant data. Will try converting to SGPR. Register VGPR[393:394] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR395) src0(VGPR391) src1(VGPR393) // VOP2 Register VGPR[397:398] contains scalar/constant data. Will try converting to SGPR. Register VGPR[407:408] contains scalar/constant data. Will try converting to SGPR. Register VGPR[407:408] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR409) src0(VGPR405) src1(VGPR407) // VOP2 Register VGPR[411:412] contains scalar/constant data. Will try converting to SGPR. Register VGPR[420:421] contains scalar/constant data. Will try converting to SGPR. Register VGPR[420:421] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR422) src0(VGPR418) src1(VGPR420) // VOP2 Register VGPR424 contains scalar/constant data. Will try converting to SGPR. Register VGPR[434:435] contains scalar/constant data. Will try converting to SGPR. Register VGPR[434:435] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR436) src0(VGPR432) src1(VGPR434) // VOP2 Register VGPR[438:439] contains scalar/constant data. Will try converting to SGPR. Register VGPR443 contains scalar/constant data. Will try converting to SGPR. Register VGPR443 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR444) src0(VGPR442) src1(VGPR443) // VOP2 Register VGPR447 contains scalar/constant data. Will try converting to SGPR. Register VGPR447 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR448) src0(VGPR446) src1(VGPR447) // VOP2 Register VGPR451 contains scalar/constant data. Will try converting to SGPR. Register VGPR455 contains scalar/constant data. Will try converting to SGPR. Register VGPR456 contains scalar/constant data. Will try converting to SGPR. Register VGPR457 contains scalar/constant data. Will try converting to SGPR. Register VGPR459 contains scalar/constant data. Will try converting to SGPR. Register VGPR459 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR460) src0(VGPR458) src1(VGPR459) // VOP2 Register VGPR475 contains scalar/constant data. Will try converting to SGPR. Register VGPR477 contains scalar/constant data. Will try converting to SGPR. Register VGPR478 contains scalar/constant data. Will try converting to SGPR. Register VGPR[500:501] contains scalar/constant data. Will try converting to SGPR. Register VGPR[502:504] contains scalar/constant data. Will try converting to SGPR. Register VGPR[502:504] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR505) src0(VGPR497) src1(VGPR502) // VOP2 Register VGPR[512:513] contains scalar/constant data. Will try converting to SGPR. Register VGPR[514:516] contains scalar/constant data. Will try converting to SGPR. Register VGPR[514:516] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR517) src0(VGPR509) src1(VGPR514) // VOP2 Register VGPR[525:526] contains scalar/constant data. Will try converting to SGPR. Register VGPR[527:529] contains scalar/constant data. Will try converting to SGPR. Register VGPR[527:529] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR530) src0(VGPR522) src1(VGPR527) // VOP2 Register VGPR[537:538] contains scalar/constant data. Will try converting to SGPR. Register VGPR[539:541] contains scalar/constant data. Will try converting to SGPR. Register VGPR[539:541] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR542) src0(VGPR534) src1(VGPR539) // VOP2 Register VGPR[550:551] contains scalar/constant data. Will try converting to SGPR. Register VGPR[552:554] contains scalar/constant data. Will try converting to SGPR. Register VGPR[552:554] can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR555) src0(VGPR547) src1(VGPR552) // VOP2 Register VGPR[562:563] contains scalar/constant data. Will try converting to SGPR. Register VGPR[564:566] contains scalar/constant data. Will try converting to SGPR. Register VGPR[564:566] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR567) src0(VGPR559) src1(VGPR564) // VOP2 Register VGPR580 contains scalar/constant data. Will try converting to SGPR. Register VGPR580 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR605) src0(VGPR580) src1(VGPR604) // VOP2 Register VGPR581 contains scalar/constant data. Will try converting to SGPR. Register VGPR581 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR588) src0(VGPR581) src1(VGPR588) // VOP2 Register VGPR585 contains scalar/constant data. Will try converting to SGPR. Register VGPR586 contains scalar/constant data. Will try converting to SGPR. Register VGPR587 contains scalar/constant data. Will try converting to SGPR. Register VGPR587 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR588) src0(VGPR587) Register VGPR588 contains scalar/constant data. Will try converting to SGPR. Register VGPR588 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR588) src0(VGPR587) Register VGPR589 contains scalar/constant data. Will try converting to SGPR. Register VGPR589 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR590) src0(VGPR589) Register VGPR590 contains scalar/constant data. Will try converting to SGPR. Register VGPR590 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR590) src0(VGPR589) Register VGPR607 contains scalar/constant data. Will try converting to SGPR. Register VGPR607 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR608) src0(VGPR580) src1(VGPR607) // VOP2 Register VGPR608 contains scalar/constant data. Will try converting to SGPR. Register VGPR608 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR608) src0(VGPR580) src1(VGPR607) // VOP2 Register VGPR609 contains scalar/constant data. Will try converting to SGPR. Register VGPR609 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR610) src0(VGPR581) src1(VGPR609) // VOP2 Register VGPR610 contains scalar/constant data. Will try converting to SGPR. Register VGPR610 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR610) src0(VGPR581) src1(VGPR609) // VOP2 Register VGPR611 contains scalar/constant data. Will try converting to SGPR. Register VGPR611 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR612) src0(VGPR579) src1(VGPR611) // VOP2 Register VGPR613 contains scalar/constant data. Will try converting to SGPR. Register VGPR613 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR615) src0(VGPR612) src1(VGPR613) // VOP2 Register VGPR614 contains scalar/constant data. Will try converting to SGPR. Register VGPR614 can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR615) src0(VGPR615) src1(VGPR614) // VOP2 Register VGPR622 contains scalar/constant data. Will try converting to SGPR. Register VGPR622 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR623) src0(VGPR621) src1(VGPR622) // VOP2 Register VGPR[629:630] contains scalar/constant data. Will try converting to SGPR. Register VGPR640 contains scalar/constant data. Will try converting to SGPR. Register VGPR640 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR641) src0(VGPR639) src1(VGPR640) // VOP2 Register VGPR650 contains scalar/constant data. Will try converting to SGPR. Register VGPR681 contains scalar/constant data. Will try converting to SGPR. Register VGPR688 contains scalar/constant data. Will try converting to SGPR. Register VGPR688 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR685) src0(VGPR688) src1(VGPR682) // VOP2 Register VGPR690 contains scalar/constant data. Will try converting to SGPR. Register VGPR690 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR691) src0(VGPR690) src1(VGPR689) // VOP2 Register VGPR692 contains scalar/constant data. Will try converting to SGPR. Register VGPR692 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR693) src0(VGPR692) src1(VGPR691) // VOP2 Register VGPR[700:702] contains scalar/constant data. Will try converting to SGPR. Register VGPR[700:702] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR703) src0(VGPR697) src1(VGPR700) // VOP2 Register VGPR[710:712] contains scalar/constant data. Will try converting to SGPR. Register VGPR[710:712] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR707) src0(VGPR706) src1(VGPR710) // VOP2 Register VGPR716 contains scalar/constant data. Will try converting to SGPR. Register VGPR716 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR713) src0(VGPR716) src1(VGPR707) // VOP2 Register VGPR[720:722] contains scalar/constant data. Will try converting to SGPR. Register VGPR[720:722] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR723) src0(VGPR717) src1(VGPR720) // VOP2 Register VGPR[730:732] contains scalar/constant data. Will try converting to SGPR. Register VGPR[730:732] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR727) src0(VGPR726) src1(VGPR730) // VOP2 Register VGPR736 contains scalar/constant data. Will try converting to SGPR. Register VGPR736 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR733) src0(VGPR736) src1(VGPR727) // VOP2 Register VGPR[740:742] contains scalar/constant data. Will try converting to SGPR. Register VGPR[740:742] can't be converted to SGPR, because the following instruction can't be converted: V_SUBREV_F32 vDst(VGPR746) src0(VGPR740) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR[743:745] contains scalar/constant data. Will try converting to SGPR. Register VGPR[743:745] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR746) src0(VGPR743) src1(VGPR740) src2(VGPR746) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR[749:751] contains scalar/constant data. Will try converting to SGPR. Register VGPR[749:751] can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR758) src0(VGPR658) src1(VGPR749) // VOP2 Register VGPR752 contains scalar/constant data. Will try converting to SGPR. Register VGPR753 contains scalar/constant data. Will try converting to SGPR. Register VGPR754 contains scalar/constant data. Will try converting to SGPR. Register VGPR[755:757] contains scalar/constant data. Will try converting to SGPR. Register VGPR[755:757] can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR758) src0(VGPR758) src1(VGPR755) // VOP2 Register VGPR763 contains scalar/constant data. Will try converting to SGPR. Register VGPR763 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR833) src0(LITERAL_CONST) src1(VGPR763) // VOP2 const: 0x3e22f983 Register VGPR[816:817] contains scalar/constant data. Will try converting to SGPR. Register VGPR[816:817] can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR818) src0(VGPR816) Register VGPR822 contains scalar/constant data. Will try converting to SGPR. Register VGPR822 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR820) src0(VGPR822) src1(VGPR818) // VOP2 Register VGPR[823:824] contains scalar/constant data. Will try converting to SGPR. Register VGPR[823:824] can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR825) src0(VGPR820) src1(VGPR823) // VOP2 Register VGPR827 contains scalar/constant data. Will try converting to SGPR. Register VGPR827 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR828) src0(VGPR827) Register VGPR828 contains scalar/constant data. Will try converting to SGPR. Register VGPR828 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR828) src0(VGPR827) Register VGPR831 contains scalar/constant data. Will try converting to SGPR. Register VGPR831 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR832) src0(SGPR247) src1(VGPR831) // VOP2 Register VGPR832 contains scalar/constant data. Will try converting to SGPR. Register VGPR832 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR832) src0(SGPR247) src1(VGPR831) // VOP2 Register VGPR833 contains scalar/constant data. Will try converting to SGPR. Register VGPR833 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR833) src0(LITERAL_CONST) src1(VGPR763) // VOP2 const: 0x3e22f983 Register VGPR834 contains scalar/constant data. Will try converting to SGPR. Register VGPR834 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR835) src0(VGPR833) src1(VGPR834) // VOP2 Register VGPR835 contains scalar/constant data. Will try converting to SGPR. Register VGPR835 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR835) src0(VGPR833) src1(VGPR834) // VOP2 Register VGPR836 contains scalar/constant data. Will try converting to SGPR. Register VGPR836 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR837) src0(VGPR763) src1(VGPR836) // VOP2 Register VGPR837 contains scalar/constant data. Will try converting to SGPR. Register VGPR837 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR837) src0(VGPR763) src1(VGPR836) // VOP2 Register VGPR838 contains scalar/constant data. Will try converting to SGPR. Register VGPR838 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR839) src0(VGPR838) Register VGPR839 contains scalar/constant data. Will try converting to SGPR. Register VGPR839 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR839) src0(VGPR838) Register VGPR840 contains scalar/constant data. Will try converting to SGPR. Register VGPR840 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR841) src0(VGPR839) src1(VGPR840) // VOP2 Register VGPR841 contains scalar/constant data. Will try converting to SGPR. Register VGPR841 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR841) src0(VGPR839) src1(VGPR840) // VOP2 Register VGPR842 contains scalar/constant data. Will try converting to SGPR. Register VGPR842 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR842) src0(LITERAL_CONST) src1(VGPR841) // VOP2 const: 0x3e22f983 Register VGPR843 contains scalar/constant data. Will try converting to SGPR. Register VGPR843 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR844) src0(VGPR842) src1(VGPR843) // VOP2 Register VGPR844 contains scalar/constant data. Will try converting to SGPR. Register VGPR844 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR844) src0(VGPR842) src1(VGPR843) // VOP2 Register VGPR[845:847] contains scalar/constant data. Will try converting to SGPR. Register VGPR848 contains scalar/constant data. Will try converting to SGPR. Register VGPR854 contains scalar/constant data. Will try converting to SGPR. Register VGPR859 contains scalar/constant data. Will try converting to SGPR. Register VGPR859 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR860) src0(VGPR763) src1(VGPR859) // VOP2 Register VGPR860 contains scalar/constant data. Will try converting to SGPR. Register VGPR860 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR860) src0(VGPR763) src1(VGPR859) // VOP2 Register VGPR861 contains scalar/constant data. Will try converting to SGPR. Register VGPR861 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR862) src0(VGPR763) src1(VGPR861) // VOP2 Register VGPR862 contains scalar/constant data. Will try converting to SGPR. Register VGPR862 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR862) src0(VGPR763) src1(VGPR861) // VOP2 Register VGPR863 contains scalar/constant data. Will try converting to SGPR. Register VGPR863 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR864) src0(VGPR863) Register VGPR864 contains scalar/constant data. Will try converting to SGPR. Register VGPR864 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR864) src0(VGPR863) Register VGPR865 contains scalar/constant data. Will try converting to SGPR. Register VGPR865 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR866) src0(VGPR864) src1(VGPR865) // VOP2 Register VGPR866 contains scalar/constant data. Will try converting to SGPR. Register VGPR866 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR866) src0(VGPR864) src1(VGPR865) // VOP2 Register VGPR867 contains scalar/constant data. Will try converting to SGPR. Register VGPR867 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR867) src0(LITERAL_CONST) src1(VGPR866) // VOP2 const: 0x3e22f983 Register VGPR868 contains scalar/constant data. Will try converting to SGPR. Register VGPR868 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR869) src0(VGPR867) src1(VGPR868) // VOP2 Register VGPR869 contains scalar/constant data. Will try converting to SGPR. Register VGPR869 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR869) src0(VGPR867) src1(VGPR868) // VOP2 Register VGPR[870:872] contains scalar/constant data. Will try converting to SGPR. Register VGPR873 contains scalar/constant data. Will try converting to SGPR. Register VGPR874 contains scalar/constant data. Will try converting to SGPR. Register VGPR874 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR875) src0(VGPR763) src1(VGPR874) // VOP2 Register VGPR875 contains scalar/constant data. Will try converting to SGPR. Register VGPR875 can't be converted to SGPR, because the following instruction can't be converted: V_SUB_F32 vDst(VGPR875) src0(VGPR763) src1(VGPR874) // VOP2 Register VGPR876 contains scalar/constant data. Will try converting to SGPR. Register VGPR876 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR877) src0(VGPR763) src1(VGPR876) // VOP2 Register VGPR877 contains scalar/constant data. Will try converting to SGPR. Register VGPR877 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR877) src0(VGPR763) src1(VGPR876) // VOP2 Register VGPR878 contains scalar/constant data. Will try converting to SGPR. Register VGPR878 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR879) src0(VGPR878) Register VGPR879 contains scalar/constant data. Will try converting to SGPR. Register VGPR879 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR879) src0(VGPR878) Register VGPR880 contains scalar/constant data. Will try converting to SGPR. Register VGPR880 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR881) src0(VGPR879) src1(VGPR880) // VOP2 Register VGPR881 contains scalar/constant data. Will try converting to SGPR. Register VGPR881 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR881) src0(VGPR879) src1(VGPR880) // VOP2 Register VGPR882 contains scalar/constant data. Will try converting to SGPR. Register VGPR882 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR882) src0(LITERAL_CONST) src1(VGPR881) // VOP2 const: 0x3e22f983 Register VGPR883 contains scalar/constant data. Will try converting to SGPR. Register VGPR883 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR883) src0(M1_0_F) src1(VGPR882) // VOP2 Register VGPR884 contains scalar/constant data. Will try converting to SGPR. Register VGPR884 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR885) src0(VGPR883) src1(VGPR884) // VOP2 Register VGPR885 contains scalar/constant data. Will try converting to SGPR. Register VGPR885 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR885) src0(VGPR883) src1(VGPR884) // VOP2 Register VGPR915 contains scalar/constant data. Will try converting to SGPR. Register VGPR936 contains scalar/constant data. Will try converting to SGPR. Register VGPR936 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR933) src0(VGPR936) src1(VGPR923) // VOP2 Register VGPR940 contains scalar/constant data. Will try converting to SGPR. Register VGPR940 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR937) src0(VGPR940) src1(VGPR933) // VOP2 Register VGPR950 contains scalar/constant data. Will try converting to SGPR. Register VGPR951 contains scalar/constant data. Will try converting to SGPR. Register VGPR951 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR952) src0(VGPR951) Register VGPR957 contains scalar/constant data. Will try converting to SGPR. Register VGPR957 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR958) src0(VGPR957) src1(VGPR956) // VOP2 Register VGPR970 contains scalar/constant data. Will try converting to SGPR. Register VGPR970 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR971) src0(VGPR970) src1(VGPR969) // VOP2 Register VGPR972 contains scalar/constant data. Will try converting to SGPR. Register VGPR972 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR973) src0(VGPR972) src1(VGPR973) // VOP2 Register VGPR983 contains scalar/constant data. Will try converting to SGPR. Register VGPR983 can't be converted to SGPR, because the following instruction can't be converted: V_ADD_F32 vDst(VGPR984) src0(VGPR983) src1(VGPR982) // VOP2 Register VGPR996 contains scalar/constant data. Will try converting to SGPR. Register VGPR996 can't be converted to SGPR, because the following instruction can't be converted: V_RCP_F32 vDst(VGPR997) src0(VGPR996) Register VGPR1012 contains scalar/constant data. Will try converting to SGPR. Register VGPR1012 can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1013) src0(VGPR1011) src1(VGPR1012) // VOP2 Register VGPR1014 contains scalar/constant data. Will try converting to SGPR. Register VGPR1014 can't be converted to SGPR, because the following instruction can't be converted: V_MAX_F32 vDst(VGPR1016) src0(VGPR1013) src1(VGPR1014) // VOP2 Register VGPR1015 contains scalar/constant data. Will try converting to SGPR. Register VGPR1015 can't be converted to SGPR, because the following instruction can't be converted: V_MIN_F32 vDst(VGPR1016) src0(VGPR1016) src1(VGPR1015) // VOP2 Register VGPR[1021:1024] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1021:1024] can't be converted to SGPR, because the following instruction can't be converted: V_MAD_F32 vDst(VGPR1025) src0(VGPR1021) src1(VGPR1017) src2(VGPR1025) abs(0) clamp(0) omod(0) neg(0) // VOP3a Register VGPR[1033:1036] contains scalar/constant data. Will try converting to SGPR. Register VGPR[1033:1036] can't be converted to SGPR, because the following instruction can't be converted: V_MUL_F32 vDst(VGPR1037) src0(VGPR1033) src1(VGPR1037) // VOP2 Register VGPR25 contains scalar/constant data. Will try converting to SGPR. Register VGPR176 contains scalar/constant data. Will try converting to SGPR. Register VGPR180 contains scalar/constant data. Will try converting to SGPR. Register VGPR181 contains scalar/constant data. Will try converting to SGPR. Register VGPR188 contains scalar/constant data. Will try converting to SGPR. Register VGPR189 contains scalar/constant data. Will try converting to SGPR. Register VGPR190 contains scalar/constant data. Will try converting to SGPR. Register VGPR202 contains scalar/constant data. Will try converting to SGPR. Register VGPR203 contains scalar/constant data. Will try converting to SGPR. Register VGPR293 contains scalar/constant data. Will try converting to SGPR. Register VGPR294 contains scalar/constant data. Will try converting to SGPR. Register VGPR[358:359] contains scalar/constant data. Will try converting to SGPR. Register VGPR386 contains scalar/constant data. Will try converting to SGPR. Register VGPR[397:398] contains scalar/constant data. Will try converting to SGPR. Register VGPR[411:412] contains scalar/constant data. Will try converting to SGPR. Register VGPR424 contains scalar/constant data. Will try converting to SGPR. Register VGPR[438:439] contains scalar/constant data. Will try converting to SGPR. Register VGPR451 contains scalar/constant data. Will try converting to SGPR. Register VGPR455 contains scalar/constant data. Will try converting to SGPR. Register VGPR456 contains scalar/constant data. Will try converting to SGPR. Register VGPR457 contains scalar/constant data. Will try converting to SGPR. Register VGPR475 contains scalar/constant data. Will try converting to SGPR. Register VGPR477 contains scalar/constant data. Will try converting to SGPR. Register VGPR478 contains scalar/constant data. Will try converting to SGPR. Register VGPR[500:501] contains scalar/constant data. Will try converting to SGPR. Register VGPR[512:513] contains scalar/constant data. Will try converting to SGPR. Register VGPR[525:526] contains scalar/constant data. Will try converting to SGPR. Register VGPR[537:538] contains scalar/constant data. Will try converting to SGPR. Register VGPR[550:551] contains scalar/constant data. Will try converting to SGPR. Register VGPR[562:563] contains scalar/constant data. Will try converting to SGPR. Register VGPR585 contains scalar/constant data. Will try converting to SGPR. Register VGPR586 contains scalar/constant data. Will try converting to SGPR. Register VGPR[629:630] contains scalar/constant data. Will try converting to SGPR. Register VGPR650 contains scalar/constant data. Will try converting to SGPR. Register VGPR681 contains scalar/constant data. Will try converting to SGPR. Register VGPR752 contains scalar/constant data. Will try converting to SGPR. Register VGPR753 contains scalar/constant data. Will try converting to SGPR. Register VGPR754 contains scalar/constant data. Will try converting to SGPR. Register VGPR848 contains scalar/constant data. Will try converting to SGPR. Register VGPR854 contains scalar/constant data. Will try converting to SGPR. Register VGPR873 contains scalar/constant data. Will try converting to SGPR. Register VGPR915 contains scalar/constant data. Will try converting to SGPR. Register VGPR950 contains scalar/constant data. Will try converting to SGPR. No need to convert VGPR181 because it's only used for VGPR comparisons. No need to convert VGPR457 because it's only used for VGPR comparisons. No need to convert VGPR475 because it's only used for VGPR comparisons. No need to convert VGPR586 because it's only used for VGPR comparisons. No need to convert VGPR650 because it's only used for VGPR comparisons. Converting VGPR25 to SGPR, and adjusting instructions. Converting VGPR176 to SGPR, and adjusting instructions. Converting VGPR180 to SGPR, and adjusting instructions. Converting VGPR188 to SGPR, and adjusting instructions. Converting VGPR189 to SGPR, and adjusting instructions. Converting VGPR190 to SGPR, and adjusting instructions. Converting VGPR202 to SGPR, and adjusting instructions. Converting VGPR203 to SGPR, and adjusting instructions. Converting VGPR293 to SGPR, and adjusting instructions. Converting VGPR294 to SGPR, and adjusting instructions. Converting VGPR[358:359] to SGPR, and adjusting instructions. Converting VGPR386 to SGPR, and adjusting instructions. Converting VGPR[397:398] to SGPR, and adjusting instructions. Converting VGPR[411:412] to SGPR, and adjusting instructions. Converting VGPR424 to SGPR, and adjusting instructions. Converting VGPR[438:439] to SGPR, and adjusting instructions. Converting VGPR451 to SGPR, and adjusting instructions. Converting VGPR455 to SGPR, and adjusting instructions. Converting VGPR456 to SGPR, and adjusting instructions. Converting VGPR477 to SGPR, and adjusting instructions. Converting VGPR478 to SGPR, and adjusting instructions. Converting VGPR[500:501] to SGPR, and adjusting instructions. Converting VGPR[512:513] to SGPR, and adjusting instructions. Converting VGPR[525:526] to SGPR, and adjusting instructions. Converting VGPR[537:538] to SGPR, and adjusting instructions. Converting VGPR[550:551] to SGPR, and adjusting instructions. Converting VGPR[562:563] to SGPR, and adjusting instructions. Converting VGPR585 to SGPR, and adjusting instructions. Converting VGPR[629:630] to SGPR, and adjusting instructions. Converting VGPR681 to SGPR, and adjusting instructions. Converting VGPR752 to SGPR, and adjusting instructions. Converting VGPR753 to SGPR, and adjusting instructions. Converting VGPR754 to SGPR, and adjusting instructions. Converting VGPR848 to SGPR, and adjusting instructions. Converting VGPR854 to SGPR, and adjusting instructions. Converting VGPR873 to SGPR, and adjusting instructions. Converting VGPR915 to SGPR, and adjusting instructions. Converting VGPR950 to SGPR, and adjusting instructions. VGPR=>SGPR conversions done. Register lifetime ranges REG NAME START END SGPR[0:1] 0 2629 fixed SGPR2 0 2629 fixed SGPR3 0 2629 fixed SGPR[4:5] 0 2629 fixed SGPR[6:7] 0 2629 fixed SGPR8 0 2629 fixed SGPR[10:11] 0 2629 keep-active SGPR12 0 2629 keep-active SGPR13 0 2629 keep-active SGPR[14:15] 0 2629 keep-active SGPR[16:17] 0 2629 keep-active SGPR18 0 2629 keep-active SGPR19 0 2629 keep-active SGPR[20:21] 42 42 SGPR[22:23] 0 2629 keep-active SGPR24 0 2629 keep-active SGPR25 0 2629 keep-active SGPR[26:27] 72 72 SGPR[28:29] 0 2629 keep-active SGPR[30:31] 0 2629 keep-active SGPR[32:33] 0 2629 keep-active SGPR[34:35] 0 2629 keep-active SGPR[36:37] 0 2629 keep-active SGPR[38:39] 0 2629 keep-active SGPR[40:41] 0 2629 keep-active SGPR[42:43] 0 2629 keep-active SGPR[44:45] 0 2629 keep-active SGPR46 0 2629 keep-active SGPR47 0 2629 keep-active SGPR[48:49] 0 2629 keep-active SGPR[50:51] 0 2629 keep-active SGPR[52:53] 0 2629 keep-active SGPR[54:55] 0 2629 keep-active SGPR[56:57] 368 371 SGPR[58:59] 0 2629 keep-active SGPR[60:61] 0 2629 keep-active SGPR62 0 2629 keep-active SGPR63 0 2629 keep-active SGPR[64:65] 462 462 SGPR[66:67] 0 2629 keep-active SGPR68 0 2629 keep-active SGPR69 0 2629 keep-active SGPR[70:71] 509 509 SGPR[72:73] 0 2629 keep-active SGPR[74:75] 0 2629 keep-active SGPR76 0 2629 keep-active SGPR77 0 2629 keep-active SGPR78 0 2629 keep-active SGPR[80:81] 562 562 SGPR[82:83] 0 2629 keep-active SGPR84 0 2629 keep-active SGPR85 0 2629 keep-active SGPR86 0 2629 keep-active SGPR[88:89] 646 646 SGPR[90:91] 0 2629 keep-active SGPR92 0 2629 keep-active SGPR93 0 2629 keep-active SGPR94 0 2629 keep-active SGPR[96:97] 704 704 SGPR[98:99] 0 2629 keep-active SGPR100 0 2629 keep-active SGPR101 0 2629 keep-active SGPR102 0 2629 keep-active SGPR[104:105] 726 726 SGPR[106:107] 0 2629 keep-active SGPR108 0 2629 keep-active SGPR109 0 2629 keep-active SGPR110 0 2629 keep-active SGPR[112:113] 743 743 SGPR[114:115] 0 2629 keep-active SGPR116 0 2629 keep-active SGPR117 0 2629 keep-active SGPR[118:119] 762 762 SGPR[120:121] 0 2629 keep-active SGPR[122:123] 0 2629 keep-active SGPR[124:125] 0 2629 keep-active SGPR[126:127] 0 2629 keep-active SGPR[128:129] 0 2629 keep-active SGPR[130:131] 0 2629 keep-active SGPR[132:133] 0 2629 keep-active SGPR[134:135] 0 2629 keep-active SGPR[136:137] 0 2629 keep-active SGPR[138:139] 0 2629 keep-active SGPR[140:141] 0 2629 keep-active SGPR[142:143] 0 2629 keep-active SGPR[144:145] 0 2629 keep-active SGPR[146:147] 0 2629 keep-active SGPR148 0 2629 keep-active SGPR149 0 2629 keep-active SGPR150 0 2629 keep-active SGPR151 0 2629 keep-active SGPR152 0 2629 keep-active SGPR[154:155] 0 2629 keep-active SGPR[156:157] 0 2629 keep-active SGPR[158:159] 0 2629 keep-active SGPR[160:161] 0 2629 keep-active SGPR[162:163] 1182 1185 SGPR[164:165] 0 2629 keep-active SGPR[166:167] 1239 1247 SGPR[168:169] 1245 1247 SGPR[170:171] 1247 1252 SGPR[172:173] 1249 1263 SGPR[174:175] 0 2629 keep-active SGPR176 0 2629 keep-active SGPR177 0 2629 keep-active SGPR[178:179] 1290 1290 SGPR[180:181] 0 2629 keep-active SGPR[182:183] 0 2629 keep-active SGPR[184:185] 0 2629 keep-active SGPR[186:187] 0 2629 keep-active SGPR[188:189] 0 2629 keep-active SGPR[190:191] 0 2629 keep-active SGPR[192:193] 0 2629 keep-active SGPR194 0 2629 keep-active SGPR195 0 2629 keep-active SGPR196 0 2629 keep-active SGPR[198:199] 0 2629 keep-active SGPR[200:201] 0 2629 keep-active SGPR[202:203] 0 2629 keep-active SGPR[204:205] 0 2629 keep-active SGPR[206:207] 1509 1512 SGPR[208:209] 0 2629 keep-active SGPR[210:211] 0 2629 keep-active SGPR212 0 2629 keep-active SGPR213 0 2629 keep-active SGPR[214:215] 1611 1611 SGPR[216:217] 0 2629 keep-active SGPR[218:219] 1692 1695 SGPR[220:221] 0 2629 keep-active SGPR222 0 2629 keep-active SGPR223 0 2629 keep-active SGPR[224:225] 0 2629 keep-active SGPR[226:227] 0 2629 keep-active SGPR[228:229] 0 2629 keep-active SGPR[230:231] 0 2629 keep-active SGPR[232:233] 0 2629 keep-active SGPR[234:235] 0 2629 keep-active SGPR[236:237] 0 2629 keep-active SGPR[238:239] 1893 1926 SGPR[240:241] 0 2629 keep-active SGPR[242:244] 1963 1969 SGPR245 1992 2002 SGPR246 1996 1999 SGPR247 2012 2016 SGPR[248:249] 0 2629 keep-active SGPR[250:251] 0 2629 keep-active SGPR[252:253] 0 2629 keep-active SGPR[254:255] 0 2629 keep-active SGPR[256:257] 0 2629 keep-active SGPR[258:259] 0 2629 keep-active SGPR[260:261] 0 2629 keep-active SGPR[262:263] 2393 2397 SGPR[264:265] 2395 2409 SGPR[266:267] 0 2629 keep-active SGPR[268:269] 0 2629 keep-active SGPR270 6 7 SGPR271 0 2629 keep-active SGPR272 350 351 SGPR273 383 384 SGPR274 385 386 SGPR275 387 388 SGPR276 433 434 SGPR277 434 436 SGPR278 685 686 SGPR279 687 688 SGPR[280:281] 804 807 SGPR282 883 884 SGPR[283:284] 913 916 SGPR[285:286] 978 981 SGPR287 1028 1029 SGPR[288:289] 1086 1089 SGPR290 0 2629 keep-active SGPR291 1162 1163 SGPR292 1166 1167 SGPR293 1272 1273 SGPR294 1273 1275 SGPR[295:296] 1299 1303 SGPR[297:298] 1327 1331 SGPR[299:300] 1357 1361 SGPR[301:302] 1385 1389 SGPR[303:304] 1415 1419 SGPR[305:306] 1443 1447 SGPR307 1491 1492 SGPR[308:309] 1637 1640 SGPR310 1761 1762 SGPR311 1930 1931 SGPR312 1932 1933 SGPR313 1934 1935 SGPR314 2051 2052 SGPR315 2066 2067 SGPR316 2108 2109 SGPR317 2289 2290 SGPR318 2405 2406 VGPR[0:1] 0 2629 fixed VGPR[0:1] 0 2629 fixed VGPR[4:5] 0 2629 fixed VGPR[6:7] 0 2629 fixed VGPR[8:9] 0 2629 fixed VGPR[10:11] 0 2629 fixed VGPR12 0 2629 fixed VGPR[2:5] 0 2629 fixed VGPR17 0 2629 fixed VGPR[18:21] 0 2629 keep-active VGPR[22:23] 0 2629 keep-active VGPR24 0 2629 keep-active VGPR[26:29] 9 15 VGPR[30:31] 14 18 VGPR[32:35] 30 37 VGPR[36:38] 47 56 VGPR[39:41] 51 56 VGPR42 54 58 VGPR43 58 63 VGPR44 62 63 VGPR45 63 65 VGPR46 65 68 VGPR[47:49] 0 2629 keep-active VGPR[50:52] 0 2629 keep-active VGPR[53:55] 0 2629 keep-active VGPR[56:58] 0 2629 keep-active VGPR[59:61] 0 2629 keep-active VGPR[62:64] 0 2629 keep-active VGPR[65:67] 0 2629 keep-active VGPR[68:70] 0 2629 keep-active VGPR[71:73] 77 83 VGPR[74:76] 0 2629 keep-active VGPR[77:79] 85 90 VGPR[80:82] 88 94 VGPR83 0 2629 keep-active VGPR[84:86] 105 110 VGPR[87:89] 108 114 VGPR90 0 2629 keep-active VGPR[91:93] 125 130 VGPR[94:96] 128 134 VGPR97 0 2629 keep-active VGPR[98:100] 145 150 VGPR[101:103] 148 154 VGPR104 0 2629 keep-active VGPR[105:108] 165 174 VGPR[109:110] 170 189 VGPR[111:112] 173 190 VGPR113 178 180 VGPR114 180 183 VGPR[115:116] 182 190 VGPR[117:118] 185 196 VGPR119 193 205 VGPR120 196 206 VGPR121 200 202 VGPR122 202 206 VGPR123 0 2629 keep-active VGPR[124:126] 208 213 VGPR[127:129] 211 217 VGPR130 0 2629 keep-active VGPR[131:133] 228 233 VGPR[134:136] 231 237 VGPR137 0 2629 keep-active VGPR[138:140] 248 253 VGPR[141:143] 251 257 VGPR144 0 2629 keep-active VGPR[145:147] 268 273 VGPR[148:150] 271 277 VGPR151 0 2629 keep-active VGPR[152:155] 288 297 VGPR[156:157] 293 312 VGPR[158:159] 296 313 VGPR160 301 303 VGPR161 303 306 VGPR[162:163] 305 313 VGPR[164:165] 308 319 VGPR166 316 328 VGPR167 319 329 VGPR168 323 325 VGPR169 325 329 VGPR170 327 339 VGPR171 333 335 VGPR172 335 339 VGPR173 337 342 VGPR174 0 2629 keep-active VGPR175 0 2629 keep-active VGPR[177:179] 0 2629 keep-active VGPR181 367 368 VGPR[182:184] 379 392 VGPR[185:187] 384 392 VGPR[191:193] 390 397 VGPR[194:196] 395 401 VGPR197 0 2629 keep-active VGPR198 413 414 VGPR199 414 420 VGPR200 418 423 VGPR201 423 425 VGPR204 447 451 VGPR205 451 455 VGPR206 453 458 VGPR207 467 469 VGPR208 469 485 VGPR209 474 476 VGPR210 476 486 VGPR211 480 483 VGPR[212:213] 482 489 VGPR[214:215] 485 491 VGPR[216:219] 488 500 VGPR[220:221] 494 500 VGPR[222:223] 497 504 VGPR[224:225] 0 2629 keep-active VGPR226 0 2629 keep-active VGPR227 515 520 VGPR228 518 520 VGPR229 520 533 VGPR[230:232] 523 528 VGPR[233:234] 527 531 VGPR[235:237] 546 552 VGPR[238:240] 550 557 VGPR[241:242] 567 579 VGPR[243:244] 571 576 VGPR[245:246] 575 579 VGPR247 574 576 VGPR[248:249] 578 590 VGPR[250:251] 582 590 VGPR[252:253] 585 593 VGPR[254:255] 592 642 VGPR[256:257] 596 608 VGPR[258:259] 600 605 VGPR[260:261] 604 608 VGPR262 603 605 VGPR[263:264] 607 623 VGPR[265:266] 611 623 VGPR[267:268] 614 634 VGPR[269:270] 626 631 VGPR[271:272] 630 634 VGPR273 629 631 VGPR[274:275] 633 638 VGPR[276:277] 651 655 VGPR[278:279] 654 662 VGPR[280:281] 658 662 VGPR[282:283] 661 666 VGPR284 670 676 VGPR285 674 676 VGPR286 676 679 VGPR287 678 679 VGPR288 679 697 VGPR[289:290] 682 691 VGPR[291:292] 686 691 VGPR[295:296] 690 694 VGPR297 693 697 VGPR298 697 700 VGPR[299:300] 709 713 VGPR301 712 719 VGPR302 717 719 VGPR303 719 722 VGPR304 731 736 VGPR305 734 736 VGPR306 736 739 VGPR307 748 755 VGPR308 751 753 VGPR309 753 755 VGPR310 755 758 VGPR[311:313] 0 2629 keep-active VGPR314 0 2629 keep-active VGPR[315:316] 0 2629 keep-active VGPR[317:318] 0 2629 keep-active VGPR319 0 2629 keep-active VGPR[320:321] 0 2629 keep-active VGPR322 0 2629 keep-active VGPR[323:324] 0 2629 keep-active VGPR[325:326] 0 2629 keep-active VGPR327 0 2629 keep-active VGPR328 0 2629 keep-active VGPR329 0 2629 keep-active VGPR330 0 2629 keep-active VGPR[331:332] 0 2629 keep-active VGPR[333:334] 0 2629 keep-active VGPR335 0 2629 keep-active VGPR336 0 2629 keep-active VGPR[337:338] 0 2629 keep-active VGPR339 0 2629 keep-active VGPR340 0 2629 keep-active VGPR341 0 2629 keep-active VGPR[342:343] 0 2629 keep-active VGPR[344:345] 0 2629 keep-active VGPR346 0 2629 keep-active VGPR347 0 2629 keep-active VGPR348 0 2629 keep-active VGPR349 0 2629 keep-active VGPR[350:352] 767 773 VGPR[353:355] 794 799 VGPR[356:357] 798 802 VGPR[360:361] 815 815 VGPR[362:364] 822 827 VGPR[365:367] 826 833 VGPR368 837 839 VGPR369 839 843 VGPR370 847 850 VGPR371 849 850 VGPR372 850 854 VGPR373 858 860 VGPR374 860 863 VGPR375 862 863 VGPR376 863 865 VGPR[377:379] 868 873 VGPR[380:381] 872 878 VGPR[382:383] 875 878 VGPR[384:385] 877 881 VGPR387 0 2629 keep-active VGPR[388:390] 898 903 VGPR[391:392] 902 908 VGPR[393:394] 905 908 VGPR[395:396] 907 911 VGPR399 0 2629 keep-active VGPR400 0 2629 keep-active VGPR401 0 2629 keep-active VGPR[402:404] 963 968 VGPR[405:406] 967 973 VGPR[407:408] 970 973 VGPR[409:410] 972 976 VGPR413 0 2629 keep-active VGPR414 0 2629 keep-active VGPR[415:417] 1013 1018 VGPR[418:419] 1017 1023 VGPR[420:421] 1020 1023 VGPR[422:423] 1022 1026 VGPR425 0 2629 keep-active VGPR426 0 2629 keep-active VGPR427 1062 1064 VGPR428 1064 1068 VGPR[429:431] 1071 1076 VGPR[432:433] 1075 1081 VGPR[434:435] 1078 1081 VGPR[436:437] 1080 1084 VGPR440 0 2629 keep-active VGPR441 0 2629 keep-active VGPR442 1122 1125 VGPR443 1124 1125 VGPR444 1125 1127 VGPR445 1127 1129 VGPR446 1129 1132 VGPR447 1131 1132 VGPR448 1132 1137 VGPR449 0 2629 keep-active VGPR450 0 2629 keep-active VGPR[452:454] 0 2629 keep-active VGPR457 1181 1182 VGPR458 1193 1196 VGPR459 1195 1196 VGPR460 1196 1199 VGPR[461:463] 1202 1218 VGPR[464:466] 1207 1214 VGPR[467:469] 1212 1218 VGPR[470:472] 1216 1222 VGPR473 0 2629 keep-active VGPR474 1234 1236 VGPR475 1238 1239 VGPR476 1242 1245 VGPR[479:481] 0 2629 keep-active VGPR[482:484] 0 2629 keep-active VGPR[485:487] 0 2629 keep-active VGPR[488:490] 0 2629 keep-active VGPR[491:493] 0 2629 keep-active VGPR[494:496] 0 2629 keep-active VGPR[497:499] 1295 1307 VGPR[502:504] 1301 1307 VGPR[505:507] 1305 1311 VGPR508 0 2629 keep-active VGPR[509:511] 1323 1335 VGPR[514:516] 1329 1335 VGPR[517:519] 1333 1339 VGPR520 0 2629 keep-active VGPR521 0 2629 keep-active VGPR[522:524] 1353 1365 VGPR[527:529] 1359 1365 VGPR[530:532] 1363 1369 VGPR533 0 2629 keep-active VGPR[534:536] 1381 1393 VGPR[539:541] 1387 1393 VGPR[542:544] 1391 1397 VGPR545 0 2629 keep-active VGPR546 0 2629 keep-active VGPR[547:549] 1411 1423 VGPR[552:554] 1417 1423 VGPR[555:557] 1421 1427 VGPR558 0 2629 keep-active VGPR[559:561] 1439 1451 VGPR[564:566] 1445 1451 VGPR[567:569] 1449 1455 VGPR570 0 2629 keep-active VGPR571 1466 1470 VGPR[572:574] 1468 1478 VGPR575 1472 1478 VGPR[576:578] 1476 1483 VGPR579 0 2629 keep-active VGPR580 0 2629 keep-active VGPR581 0 2629 keep-active VGPR[582:584] 0 2629 keep-active VGPR586 1508 1509 VGPR587 1520 1523 VGPR588 1521 1528 VGPR589 1525 1528 VGPR590 0 2629 keep-active VGPR[591:593] 1532 1547 VGPR[594:596] 1537 1543 VGPR[597:599] 1541 1547 VGPR[600:602] 1545 1551 VGPR603 0 2629 keep-active VGPR604 1562 1564 VGPR605 1564 1567 VGPR606 1567 1569 VGPR607 1572 1573 VGPR608 1573 1575 VGPR609 1583 1584 VGPR610 1584 1586 VGPR611 1596 1597 VGPR612 1597 1601 VGPR613 1599 1601 VGPR614 1600 1602 VGPR615 1601 1604 VGPR616 1604 1607 VGPR[617:618] 0 2629 keep-active VGPR[619:620] 0 2629 keep-active VGPR621 1617 1620 VGPR622 1619 1620 VGPR623 1620 1624 VGPR[624:626] 1627 1632 VGPR[627:628] 1631 1635 VGPR[631:632] 1648 1648 VGPR[633:635] 1655 1660 VGPR[636:638] 1659 1666 VGPR639 1670 1673 VGPR640 1672 1673 VGPR641 1673 1675 VGPR642 1675 1689 VGPR[643:645] 1678 1683 VGPR[646:647] 1682 1686 VGPR648 1685 1689 VGPR649 1689 1692 VGPR650 1691 1692 VGPR[651:653] 0 2629 keep-active VGPR654 0 2629 keep-active VGPR[655:657] 0 2629 keep-active VGPR[658:660] 1889 1943 VGPR661 0 2629 keep-active VGPR[662:664] 0 2629 keep-active VGPR[665:667] 0 2629 keep-active VGPR[668:670] 0 2629 keep-active VGPR[671:673] 1704 1710 VGPR[674:676] 1731 1737 VGPR677 0 2629 keep-active VGPR[678:680] 0 2629 keep-active VGPR[682:684] 1771 1778 VGPR[685:687] 1776 1782 VGPR688 1775 1778 VGPR689 0 2629 keep-active VGPR690 1793 1794 VGPR691 1794 1797 VGPR692 1796 1797 VGPR693 1797 1799 VGPR[694:696] 1808 1814 VGPR[697:699] 1812 1821 VGPR[700:702] 1816 1821 VGPR[703:705] 1819 1825 VGPR706 0 2629 keep-active VGPR[707:709] 1839 1846 VGPR[710:712] 1836 1841 VGPR[713:715] 0 2629 keep-active VGPR716 1843 1846 VGPR[717:719] 1849 1858 VGPR[720:722] 1853 1858 VGPR[723:725] 1856 1862 VGPR726 0 2629 keep-active VGPR[727:729] 1876 1883 VGPR[730:732] 1873 1878 VGPR[733:735] 1881 1887 VGPR736 1880 1883 VGPR[737:739] 1885 1891 VGPR[740:742] 1902 1917 VGPR[743:745] 1906 1917 VGPR[746:748] 1909 1921 VGPR[749:751] 1931 1943 VGPR[755:757] 1937 1946 VGPR[758:760] 1941 1951 VGPR[761:762] 1988 2062 VGPR763 2018 2124 VGPR[764:766] 0 2629 keep-active VGPR[767:769] 0 2629 keep-active VGPR[770:772] 0 2629 keep-active VGPR[773:774] 0 2629 keep-active VGPR775 0 2629 keep-active VGPR[776:777] 0 2629 keep-active VGPR778 0 2629 keep-active VGPR[779:780] 0 2629 keep-active VGPR781 0 2629 keep-active VGPR[782:783] 0 2629 keep-active VGPR784 0 2629 keep-active VGPR[785:787] 0 2629 keep-active VGPR[788:790] 0 2629 keep-active VGPR791 0 2629 keep-active VGPR792 0 2629 keep-active VGPR[793:795] 0 2629 keep-active VGPR796 0 2629 keep-active VGPR[797:799] 0 2629 keep-active VGPR[800:802] 0 2629 keep-active VGPR803 0 2629 keep-active VGPR804 0 2629 keep-active VGPR[805:807] 0 2629 keep-active VGPR[808:810] 0 2629 keep-active VGPR[811:813] 0 2629 keep-active VGPR[814:815] 1960 1976 VGPR[816:817] 1968 1976 VGPR[818:819] 1971 1980 VGPR[820:821] 1979 1986 VGPR822 1978 1980 VGPR[823:824] 1982 1986 VGPR[825:826] 1985 1989 VGPR827 1999 2002 VGPR828 2000 2007 VGPR829 2005 2007 VGPR830 2007 2010 VGPR831 2015 2016 VGPR832 2016 2018 VGPR833 2021 2026 VGPR834 2025 2026 VGPR835 2026 2028 VGPR836 2031 2032 VGPR837 2032 2037 VGPR838 2034 2037 VGPR839 2035 2040 VGPR840 2039 2040 VGPR841 2040 2042 VGPR842 2042 2047 VGPR843 2046 2047 VGPR844 2047 2050 VGPR[845:847] 2050 2057 VGPR849 2060 2064 VGPR850 2062 2065 VGPR[851:853] 2064 2075 VGPR855 2069 2075 VGPR[856:858] 2073 2079 VGPR859 2082 2083 VGPR860 2083 2085 VGPR861 2088 2089 VGPR862 2089 2094 VGPR863 2091 2094 VGPR864 2092 2097 VGPR865 2096 2097 VGPR866 2097 2099 VGPR867 2099 2104 VGPR868 2103 2104 VGPR869 2104 2107 VGPR[870:872] 2107 2114 VGPR874 2117 2118 VGPR875 2118 2120 VGPR876 2123 2124 VGPR877 2124 2129 VGPR878 2126 2129 VGPR879 2127 2132 VGPR880 2131 2132 VGPR881 2132 2134 VGPR882 2134 2138 VGPR883 2138 2141 VGPR884 2140 2141 VGPR885 2141 2150 VGPR[886:887] 2144 2148 VGPR[888:890] 2163 2169 VGPR891 2172 2174 VGPR892 2174 2177 VGPR893 2177 2186 VGPR[894:895] 2180 2184 VGPR[896:898] 2199 2205 VGPR899 2208 2210 VGPR900 2210 2213 VGPR901 2213 2222 VGPR[902:903] 2216 2220 VGPR[904:906] 2235 2241 VGPR907 2244 2246 VGPR908 2246 2249 VGPR909 2249 2258 VGPR[910:911] 2252 2256 VGPR[912:914] 2271 2277 VGPR916 0 2629 keep-active VGPR[917:919] 2310 2316 VGPR[920:922] 0 2629 keep-active VGPR[923:925] 0 2629 keep-active VGPR[926:928] 2332 2342 VGPR929 2336 2342 VGPR[930:932] 0 2629 keep-active VGPR[933:935] 2345 2352 VGPR936 2344 2347 VGPR[937:939] 2350 2356 VGPR940 2349 2352 VGPR[941:943] 2354 2369 VGPR[944:946] 2359 2364 VGPR947 0 2629 keep-active VGPR948 0 2629 keep-active VGPR949 2400 2412 VGPR951 2414 2417 VGPR952 2415 2419 VGPR953 2419 2421 VGPR954 2421 2424 VGPR955 2424 2426 VGPR956 2428 2433 VGPR957 2432 2433 VGPR958 0 2629 keep-active VGPR[959:961] 2435 2448 VGPR[962:964] 2443 2457 VGPR965 2439 2445 VGPR[966:968] 2451 2457 VGPR969 2455 2460 VGPR970 2459 2460 VGPR971 2460 2463 VGPR972 2462 2464 VGPR973 0 2629 keep-active VGPR974 0 2629 keep-active VGPR[975:977] 0 2629 keep-active VGPR[978:980] 2499 2513 VGPR981 2503 2506 VGPR982 2506 2509 VGPR983 2508 2509 VGPR984 2509 2513 VGPR[985:987] 2511 2523 VGPR[988:991] 2516 2524 VGPR[992:995] 2521 2530 VGPR996 2532 2535 VGPR997 2533 2537 VGPR998 2537 2548 VGPR[999:1002] 2540 2548 VGPR[1003:1006] 2545 2554 VGPR[1007:1010] 2557 2591 VGPR1011 2562 2565 VGPR1012 2564 2565 VGPR1013 2565 2569 VGPR1014 2567 2569 VGPR1015 2568 2570 VGPR1016 2569 2575 VGPR[1017:1020] 2572 2592 VGPR[1021:1024] 2577 2592 VGPR[1025:1028] 2581 2598 VGPR[1029:1032] 2601 2613 VGPR[1033:1036] 2606 2617 VGPR[1037:1040] 2610 2627 Register final registers REG NAME START END SGPR[0:1] 0 2629 fixed SGPR2 0 2629 fixed SGPR3 0 2629 fixed SGPR[4:5] 0 2629 fixed SGPR[6:7] 0 2629 fixed SGPR8 0 2629 fixed SGPR9 0 2629 keep-active SGPR[10:11] 0 2629 keep-active SGPR12 0 2629 keep-active SGPR13 0 2629 keep-active SGPR[14:15] 0 2629 keep-active SGPR[16:17] 0 2629 keep-active SGPR18 0 2629 keep-active SGPR19 0 2629 keep-active SGPR[20:21] 0 2629 keep-active SGPR22 0 2629 keep-active SGPR23 0 2629 keep-active SGPR[24:25] 0 2629 keep-active SGPR[26:27] 0 2629 keep-active SGPR[28:29] 0 2629 keep-active SGPR[30:31] 0 2629 keep-active SGPR[32:33] 0 2629 keep-active SGPR[34:35] 0 2629 keep-active SGPR[36:37] 0 2629 keep-active SGPR[38:39] 0 2629 keep-active SGPR[40:41] 0 2629 keep-active SGPR42 0 2629 keep-active SGPR43 0 2629 keep-active SGPR[44:45] 0 2629 keep-active SGPR[46:47] 0 2629 keep-active SGPR[48:49] 0 2629 keep-active SGPR[50:51] 0 2629 keep-active SGPR[52:53] 0 2629 keep-active SGPR[54:55] 0 2629 keep-active SGPR56 0 2629 keep-active SGPR57 0 2629 keep-active SGPR[58:59] 0 2629 keep-active SGPR60 0 2629 keep-active SGPR61 0 2629 keep-active SGPR[62:63] 0 2629 keep-active SGPR[64:65] 0 2629 keep-active SGPR66 0 2629 keep-active SGPR67 0 2629 keep-active SGPR[68:69] 0 2629 keep-active SGPR70 0 2629 keep-active SGPR71 0 2629 keep-active SGPR72 0 2629 keep-active SGPR73 0 2629 keep-active SGPR[74:75] 0 2629 keep-active SGPR76 0 2629 keep-active SGPR77 0 2629 keep-active SGPR[78:79] 0 2629 keep-active SGPR80 0 2629 keep-active SGPR81 0 2629 keep-active SGPR82 0 2629 keep-active SGPR83 0 2629 keep-active SGPR[84:85] 0 2629 keep-active SGPR86 0 2629 keep-active SGPR87 0 2629 keep-active SGPR[88:89] 0 2629 keep-active SGPR90 0 2629 keep-active SGPR91 0 2629 keep-active SGPR[92:93] 0 2629 keep-active SGPR[94:95] 0 2629 keep-active SGPR[96:97] 0 2629 keep-active SGPR[98:99] 0 2629 keep-active SGPR[100:101] 0 2629 keep-active SGPR[102:103] 0 2629 keep-active SGPR[104:105] 0 2629 keep-active SGPR[106:107] 0 2629 keep-active SGPR[108:109] 0 2629 keep-active SGPR[110:111] 0 2629 keep-active SGPR[112:113] 0 2629 keep-active SGPR[114:115] 0 2629 keep-active SGPR[116:117] 0 2629 keep-active SGPR[118:119] 0 2629 keep-active SGPR120 0 2629 keep-active SGPR121 0 2629 keep-active SGPR122 0 2629 keep-active SGPR123 0 2629 keep-active SGPR124 0 2629 keep-active SGPR125 0 2629 keep-active SGPR[126:127] 0 2629 keep-active SGPR[128:129] 0 2629 keep-active SGPR[130:131] 0 2629 keep-active SGPR[132:133] 0 2629 keep-active SGPR[134:135] 0 2629 keep-active SGPR[136:137] 0 2629 keep-active SGPR138 0 2629 keep-active SGPR139 0 2629 keep-active SGPR[140:141] 0 2629 keep-active SGPR[142:143] 0 2629 keep-active SGPR[144:145] 0 2629 keep-active SGPR[146:147] 0 2629 keep-active SGPR[148:149] 0 2629 keep-active SGPR[150:151] 0 2629 keep-active SGPR[152:153] 0 2629 keep-active SGPR154 0 2629 keep-active SGPR155 0 2629 keep-active SGPR[156:157] 0 2629 keep-active SGPR[158:159] 0 2629 keep-active SGPR[160:161] 0 2629 keep-active SGPR[162:163] 0 2629 keep-active SGPR[164:165] 0 2629 keep-active SGPR[166:167] 0 2629 keep-active SGPR168 0 2629 keep-active SGPR169 0 2629 keep-active SGPR[170:171] 0 2629 keep-active SGPR[172:173] 0 2629 keep-active SGPR174 0 2629 keep-active SGPR175 0 2629 keep-active SGPR[176:177] 0 2629 keep-active SGPR[178:179] 0 2629 keep-active SGPR[180:181] 0 2629 keep-active SGPR[182:183] 0 2629 keep-active SGPR[184:185] 0 2629 keep-active SGPR[186:187] 0 2629 keep-active SGPR[188:189] 0 2629 keep-active SGPR[190:191] 0 2629 keep-active SGPR[192:193] 0 2629 keep-active SGPR[194:195] 0 2629 keep-active SGPR[196:197] 0 2629 keep-active SGPR[198:199] 0 2629 keep-active SGPR[200:201] 0 2629 keep-active SGPR[202:203] 0 2629 keep-active SGPR[204:205] 0 2629 keep-active SGPR[206:207] 0 2629 keep-active SGPR[208:209] 0 2629 keep-active SGPR210 0 2629 keep-active SGPR211 0 2629 keep-active SGPR212 6 7 SGPR[212:213] 42 42 SGPR[212:213] 72 72 SGPR212 350 351 SGPR[212:213] 368 371 SGPR212 383 384 SGPR212 385 386 SGPR212 387 388 SGPR212 433 434 SGPR[212:213] 509 509 SGPR[212:213] 562 562 SGPR[212:213] 646 646 SGPR212 685 686 SGPR212 687 688 SGPR[212:213] 704 704 SGPR[212:213] 726 726 SGPR[212:213] 743 743 SGPR[212:213] 762 762 SGPR[212:213] 804 807 SGPR212 883 884 SGPR[212:213] 913 916 SGPR[212:213] 978 981 SGPR212 1028 1029 SGPR[212:213] 1086 1089 SGPR212 1162 1163 SGPR212 1166 1167 SGPR[212:213] 1182 1185 SGPR[212:213] 1239 1247 SGPR[212:213] 1249 1263 SGPR212 1272 1273 SGPR[212:213] 1299 1303 SGPR[212:213] 1327 1331 SGPR[212:213] 1357 1361 SGPR[212:213] 1385 1389 SGPR[212:213] 1415 1419 SGPR[212:213] 1443 1447 SGPR212 1491 1492 SGPR[212:213] 1509 1512 SGPR[212:213] 1611 1611 SGPR[212:213] 1637 1640 SGPR[212:213] 1692 1695 SGPR212 1761 1762 SGPR[212:213] 1893 1926 SGPR212 1930 1931 SGPR212 1932 1933 SGPR212 1934 1935 SGPR212 1992 2002 SGPR212 2012 2016 SGPR212 2051 2052 SGPR212 2066 2067 SGPR212 2108 2109 SGPR212 2289 2290 SGPR[212:213] 2395 2409 SGPR213 434 436 SGPR213 1273 1275 SGPR213 1996 1999 SGPR[214:215] 462 462 SGPR[214:215] 1245 1247 SGPR[214:215] 1290 1290 SGPR[214:215] 2393 2397 SGPR214 2405 2406 SGPR[216:217] 1247 1252 SGPR[216:218] 1963 1969 VGPR[0:1] 0 2629 fixed VGPR[0:1] 0 2629 fixed VGPR[2:5] 0 2629 fixed VGPR[4:5] 0 2629 fixed VGPR[6:7] 0 2629 fixed VGPR[8:9] 0 2629 fixed VGPR[10:11] 0 2629 fixed VGPR12 0 2629 fixed VGPR[13:16] 0 2629 keep-active VGPR17 0 2629 fixed VGPR[18:19] 0 2629 keep-active VGPR20 0 2629 keep-active VGPR[21:23] 0 2629 keep-active VGPR[24:26] 0 2629 keep-active VGPR[27:29] 0 2629 keep-active VGPR[30:32] 0 2629 keep-active VGPR[33:35] 0 2629 keep-active VGPR[36:38] 0 2629 keep-active VGPR[39:41] 0 2629 keep-active VGPR[42:44] 0 2629 keep-active VGPR[45:47] 0 2629 keep-active VGPR48 0 2629 keep-active VGPR49 0 2629 keep-active VGPR50 0 2629 keep-active VGPR51 0 2629 keep-active VGPR52 0 2629 keep-active VGPR53 0 2629 keep-active VGPR54 0 2629 keep-active VGPR55 0 2629 keep-active VGPR56 0 2629 keep-active VGPR57 0 2629 keep-active VGPR58 0 2629 keep-active VGPR[59:61] 0 2629 keep-active VGPR62 0 2629 keep-active VGPR[63:64] 0 2629 keep-active VGPR65 0 2629 keep-active VGPR[66:68] 0 2629 keep-active VGPR69 0 2629 keep-active VGPR[70:71] 0 2629 keep-active VGPR[72:73] 0 2629 keep-active VGPR74 0 2629 keep-active VGPR[75:76] 0 2629 keep-active VGPR77 0 2629 keep-active VGPR[78:79] 0 2629 keep-active VGPR[80:81] 0 2629 keep-active VGPR82 0 2629 keep-active VGPR83 0 2629 keep-active VGPR84 0 2629 keep-active VGPR85 0 2629 keep-active VGPR[86:87] 0 2629 keep-active VGPR[88:89] 0 2629 keep-active VGPR90 0 2629 keep-active VGPR91 0 2629 keep-active VGPR[92:93] 0 2629 keep-active VGPR94 0 2629 keep-active VGPR95 0 2629 keep-active VGPR96 0 2629 keep-active VGPR[97:98] 0 2629 keep-active VGPR[99:100] 0 2629 keep-active VGPR101 0 2629 keep-active VGPR102 0 2629 keep-active VGPR103 0 2629 keep-active VGPR104 0 2629 keep-active VGPR105 0 2629 keep-active VGPR106 0 2629 keep-active VGPR107 0 2629 keep-active VGPR108 0 2629 keep-active VGPR109 0 2629 keep-active VGPR110 0 2629 keep-active VGPR111 0 2629 keep-active VGPR112 0 2629 keep-active VGPR113 0 2629 keep-active VGPR114 0 2629 keep-active VGPR115 0 2629 keep-active VGPR116 0 2629 keep-active VGPR[117:119] 0 2629 keep-active VGPR120 0 2629 keep-active VGPR[121:123] 0 2629 keep-active VGPR[124:126] 0 2629 keep-active VGPR[127:129] 0 2629 keep-active VGPR[130:132] 0 2629 keep-active VGPR[133:135] 0 2629 keep-active VGPR[136:138] 0 2629 keep-active VGPR139 0 2629 keep-active VGPR140 0 2629 keep-active VGPR141 0 2629 keep-active VGPR142 0 2629 keep-active VGPR143 0 2629 keep-active VGPR144 0 2629 keep-active VGPR145 0 2629 keep-active VGPR146 0 2629 keep-active VGPR147 0 2629 keep-active VGPR148 0 2629 keep-active VGPR149 0 2629 keep-active VGPR[150:152] 0 2629 keep-active VGPR153 0 2629 keep-active VGPR154 0 2629 keep-active VGPR[155:156] 0 2629 keep-active VGPR[157:158] 0 2629 keep-active VGPR[159:161] 0 2629 keep-active VGPR162 0 2629 keep-active VGPR[163:165] 0 2629 keep-active VGPR166 0 2629 keep-active VGPR[167:169] 0 2629 keep-active VGPR[170:172] 0 2629 keep-active VGPR[173:175] 0 2629 keep-active VGPR176 0 2629 keep-active VGPR[177:179] 0 2629 keep-active VGPR180 0 2629 keep-active VGPR181 0 2629 keep-active VGPR[182:184] 0 2629 keep-active VGPR185 0 2629 keep-active VGPR[186:188] 0 2629 keep-active VGPR[189:191] 0 2629 keep-active VGPR[192:194] 0 2629 keep-active VGPR[195:196] 0 2629 keep-active VGPR197 0 2629 keep-active VGPR[198:199] 0 2629 keep-active VGPR200 0 2629 keep-active VGPR[201:202] 0 2629 keep-active VGPR203 0 2629 keep-active VGPR[204:205] 0 2629 keep-active VGPR206 0 2629 keep-active VGPR[207:209] 0 2629 keep-active VGPR[210:212] 0 2629 keep-active VGPR213 0 2629 keep-active VGPR214 0 2629 keep-active VGPR[215:217] 0 2629 keep-active VGPR218 0 2629 keep-active VGPR[219:221] 0 2629 keep-active VGPR[222:224] 0 2629 keep-active VGPR225 0 2629 keep-active VGPR226 0 2629 keep-active VGPR[227:229] 0 2629 keep-active VGPR[230:232] 0 2629 keep-active VGPR[233:235] 0 2629 keep-active VGPR236 0 2629 keep-active VGPR[237:239] 0 2629 keep-active VGPR[240:242] 0 2629 keep-active VGPR[243:245] 0 2629 keep-active VGPR246 0 2629 keep-active VGPR247 0 2629 keep-active VGPR248 0 2629 keep-active VGPR249 0 2629 keep-active VGPR250 0 2629 keep-active VGPR[251:253] 0 2629 keep-active VGPR[254:257] 9 15 VGPR[254:257] 30 37 VGPR[254:256] 47 56 VGPR254 58 63 VGPR254 65 68 VGPR[254:256] 77 83 VGPR[254:256] 85 90 VGPR[254:256] 105 110 VGPR[254:256] 125 130 VGPR[254:256] 145 150 VGPR[254:255] 170 189 VGPR254 193 205 VGPR[254:256] 211 217 VGPR[254:256] 228 233 VGPR[254:256] 248 253 VGPR[254:256] 268 273 VGPR[254:255] 293 312 VGPR254 316 328 VGPR254 333 335 VGPR254 337 342 VGPR254 367 368 VGPR[254:256] 379 392 VGPR[254:256] 395 401 VGPR254 413 414 VGPR254 418 423 VGPR254 447 451 VGPR254 453 458 VGPR254 467 469 VGPR254 474 476 VGPR254 480 483 VGPR[254:255] 494 500 VGPR254 515 520 VGPR[254:255] 527 531 VGPR[254:256] 546 552 VGPR[254:255] 567 579 VGPR[254:255] 582 590 VGPR[254:255] 592 642 VGPR[254:255] 651 655 VGPR[254:255] 658 662 VGPR254 670 676 VGPR254 678 679 VGPR254 693 697 VGPR254 712 719 VGPR254 731 736 VGPR254 748 755 VGPR[254:256] 767 773 VGPR[254:256] 794 799 VGPR[254:255] 815 815 VGPR[254:256] 822 827 VGPR254 837 839 VGPR254 847 850 VGPR254 858 860 VGPR254 862 863 VGPR[254:256] 868 873 VGPR[254:255] 875 878 VGPR[254:256] 898 903 VGPR[254:255] 905 908 VGPR[254:256] 963 968 VGPR[254:255] 970 973 VGPR[254:256] 1013 1018 VGPR[254:255] 1020 1023 VGPR254 1062 1064 VGPR[254:255] 1075 1081 VGPR254 1122 1125 VGPR254 1127 1129 VGPR254 1131 1132 VGPR254 1181 1182 VGPR254 1193 1196 VGPR[254:256] 1202 1218 VGPR254 1234 1236 VGPR254 1238 1239 VGPR254 1242 1245 VGPR[254:256] 1295 1307 VGPR[254:256] 1323 1335 VGPR[254:256] 1353 1365 VGPR[254:256] 1381 1393 VGPR[254:256] 1411 1423 VGPR[254:256] 1439 1451 VGPR254 1466 1470 VGPR254 1472 1478 VGPR254 1508 1509 VGPR254 1520 1523 VGPR254 1525 1528 VGPR254 1562 1564 VGPR254 1567 1569 VGPR254 1572 1573 VGPR254 1583 1584 VGPR254 1596 1597 VGPR254 1599 1601 VGPR254 1604 1607 VGPR254 1617 1620 VGPR[254:256] 1627 1632 VGPR[254:255] 1648 1648 VGPR[254:256] 1655 1660 VGPR254 1670 1673 VGPR254 1675 1689 VGPR254 1691 1692 VGPR[254:256] 1771 1778 VGPR254 1793 1794 VGPR254 1796 1797 VGPR[254:256] 1808 1814 VGPR[254:256] 1816 1821 VGPR[254:256] 1836 1841 VGPR254 1843 1846 VGPR[254:256] 1849 1858 VGPR[254:256] 1873 1878 VGPR254 1880 1883 VGPR[254:256] 1885 1891 VGPR[254:256] 1902 1917 VGPR[254:256] 1931 1943 VGPR[254:255] 1960 1976 VGPR254 1978 1980 VGPR[254:255] 1988 2062 VGPR254 2069 2075 VGPR254 2082 2083 VGPR254 2088 2089 VGPR254 2091 2094 VGPR254 2096 2097 VGPR254 2099 2104 VGPR254 2117 2118 VGPR254 2123 2124 VGPR254 2126 2129 VGPR254 2131 2132 VGPR254 2134 2138 VGPR254 2140 2141 VGPR[254:256] 2163 2169 VGPR254 2172 2174 VGPR254 2177 2186 VGPR254 2208 2210 VGPR254 2213 2222 VGPR254 2244 2246 VGPR254 2249 2258 VGPR[254:256] 2310 2316 VGPR[254:256] 2332 2342 VGPR254 2344 2347 VGPR254 2349 2352 VGPR[254:256] 2359 2364 VGPR254 2400 2412 VGPR254 2414 2417 VGPR254 2419 2421 VGPR254 2424 2426 VGPR254 2428 2433 VGPR254 2439 2445 VGPR254 2455 2460 VGPR254 2462 2464 VGPR[254:256] 2499 2513 VGPR[254:257] 2516 2524 VGPR254 2532 2535 VGPR254 2537 2548 VGPR[254:257] 2557 2591 VGPR[254:257] 2601 2613 VGPR255 62 63 VGPR255 196 206 VGPR255 319 329 VGPR255 335 339 VGPR255 414 420 VGPR255 423 425 VGPR255 451 455 VGPR255 469 485 VGPR255 518 520 VGPR255 674 676 VGPR255 679 697 VGPR255 717 719 VGPR255 734 736 VGPR255 751 753 VGPR255 755 758 VGPR255 839 843 VGPR255 849 850 VGPR255 860 863 VGPR255 1064 1068 VGPR255 1124 1125 VGPR255 1129 1132 VGPR255 1195 1196 VGPR[255:257] 1468 1478 VGPR255 1521 1528 VGPR255 1564 1567 VGPR255 1573 1575 VGPR255 1584 1586 VGPR255 1597 1601 VGPR255 1619 1620 VGPR255 1672 1673 VGPR[255:256] 1682 1686 VGPR255 1689 1692 VGPR255 1794 1797 VGPR[255:256] 1979 1986 VGPR255 2083 2085 VGPR255 2089 2094 VGPR255 2097 2099 VGPR255 2103 2104 VGPR255 2118 2120 VGPR255 2124 2129 VGPR255 2132 2134 VGPR255 2138 2141 VGPR255 2174 2177 VGPR[255:256] 2180 2184 VGPR255 2210 2213 VGPR[255:256] 2216 2220 VGPR255 2246 2249 VGPR[255:256] 2252 2256 VGPR[255:257] 2345 2352 VGPR255 2415 2419 VGPR255 2421 2424 VGPR255 2432 2433 VGPR255 2459 2460 VGPR255 2533 2537 VGPR[255:258] 2540 2548 VGPR256 63 65 VGPR[256:257] 173 190 VGPR256 200 202 VGPR[256:257] 296 313 VGPR256 323 325 VGPR256 327 339 VGPR256 476 486 VGPR[256:257] 497 504 VGPR256 520 533 VGPR[256:257] 571 576 VGPR[256:257] 578 590 VGPR[256:257] 596 608 VGPR[256:257] 611 623 VGPR[256:257] 626 631 VGPR[256:257] 633 638 VGPR[256:257] 654 662 VGPR256 676 679 VGPR[256:257] 682 691 VGPR256 697 700 VGPR[256:257] 709 713 VGPR256 719 722 VGPR256 736 739 VGPR256 753 755 VGPR256 850 854 VGPR256 863 865 VGPR[256:258] 1071 1076 VGPR[256:257] 1078 1081 VGPR256 1125 1127 VGPR256 1132 1137 VGPR256 1196 1199 VGPR[256:258] 1532 1547 VGPR256 1600 1602 VGPR256 1620 1624 VGPR256 1673 1675 VGPR[256:258] 1704 1710 VGPR256 1797 1799 VGPR[256:257] 1968 1976 VGPR256 1999 2002 VGPR256 2005 2007 VGPR256 2015 2016 VGPR256 2018 2124 VGPR256 2127 2132 VGPR256 2141 2150 VGPR[256:258] 2435 2448 VGPR256 2460 2463 VGPR[257:259] 51 56 VGPR[257:259] 88 94 VGPR[257:259] 108 114 VGPR[257:259] 128 134 VGPR[257:259] 148 154 VGPR257 202 206 VGPR[257:259] 231 237 VGPR[257:259] 251 257 VGPR[257:259] 271 277 VGPR257 325 329 VGPR[257:259] 384 392 VGPR[257:258] 482 489 VGPR[257:259] 523 528 VGPR[257:259] 550 557 VGPR[257:258] 798 802 VGPR[257:259] 826 833 VGPR[257:258] 872 878 VGPR[257:258] 902 908 VGPR[257:258] 967 973 VGPR[257:258] 1017 1023 VGPR[257:259] 1207 1214 VGPR[257:259] 1216 1222 VGPR[257:259] 1301 1307 VGPR[257:259] 1329 1335 VGPR[257:259] 1359 1365 VGPR[257:259] 1387 1393 VGPR[257:259] 1417 1423 VGPR[257:259] 1445 1451 VGPR257 1601 1604 VGPR[257:258] 1631 1635 VGPR[257:259] 1659 1666 VGPR[257:259] 1678 1683 VGPR257 1685 1689 VGPR257 1775 1778 VGPR[257:259] 1812 1821 VGPR[257:259] 1839 1846 VGPR[257:259] 1853 1858 VGPR[257:259] 1876 1883 VGPR[257:259] 1889 1943 VGPR[257:258] 1982 1986 VGPR257 2000 2007 VGPR257 2016 2018 VGPR257 2021 2026 VGPR257 2031 2032 VGPR257 2034 2037 VGPR257 2039 2040 VGPR257 2042 2047 VGPR257 2060 2064 VGPR257 2092 2097 VGPR257 2104 2107 VGPR[257:258] 2144 2148 VGPR[257:259] 2199 2205 VGPR[257:259] 2235 2241 VGPR[257:259] 2271 2277 VGPR257 2336 2342 VGPR257 2503 2506 VGPR257 2508 2509 VGPR[258:259] 14 18 VGPR258 178 180 VGPR[258:259] 185 196 VGPR[258:260] 208 213 VGPR258 301 303 VGPR[258:259] 308 319 VGPR258 574 576 VGPR[258:259] 585 593 VGPR[258:259] 600 605 VGPR[258:259] 607 623 VGPR258 629 631 VGPR[258:259] 661 666 VGPR[258:259] 686 691 VGPR[258:259] 1080 1084 VGPR[258:260] 1476 1483 VGPR[258:260] 1776 1782 VGPR[258:259] 1971 1980 VGPR258 2007 2010 VGPR258 2025 2026 VGPR258 2032 2037 VGPR258 2040 2042 VGPR258 2046 2047 VGPR258 2062 2065 VGPR[258:260] 2107 2114 VGPR[258:260] 2350 2356 VGPR258 2506 2509 VGPR258 2562 2565 VGPR258 2567 2569 VGPR[258:261] 2581 2598 VGPR[258:261] 2606 2617 VGPR259 180 183 VGPR259 303 306 VGPR[259:260] 485 491 VGPR[259:260] 575 579 VGPR[259:260] 877 881 VGPR[259:260] 907 911 VGPR[259:260] 972 976 VGPR[259:260] 1022 1026 VGPR[259:261] 1537 1543 VGPR[259:261] 1545 1551 VGPR[259:261] 1731 1737 VGPR[259:260] 1985 1989 VGPR259 2026 2028 VGPR259 2035 2040 VGPR259 2047 2050 VGPR[259:261] 2064 2075 VGPR[259:261] 2443 2457 VGPR259 2509 2513 VGPR[259:262] 2545 2554 VGPR259 2564 2565 VGPR259 2568 2570 VGPR260 54 58 VGPR[260:263] 165 174 VGPR[260:261] 182 190 VGPR[260:263] 288 297 VGPR[260:261] 305 313 VGPR[260:262] 390 397 VGPR260 603 605 VGPR[260:261] 614 634 VGPR[260:261] 690 694 VGPR[260:262] 1212 1218 VGPR[260:262] 1305 1311 VGPR[260:262] 1333 1339 VGPR[260:262] 1363 1369 VGPR[260:262] 1391 1397 VGPR[260:262] 1421 1427 VGPR[260:262] 1449 1455 VGPR[260:262] 1819 1825 VGPR[260:262] 1856 1862 VGPR[260:262] 1881 1887 VGPR[260:262] 1906 1917 VGPR[260:262] 1937 1946 VGPR[260:262] 2050 2057 VGPR[260:262] 2511 2523 VGPR260 2565 2569 VGPR[261:264] 488 500 VGPR[261:262] 604 608 VGPR[261:263] 2354 2369 VGPR261 2569 2575 VGPR[262:263] 630 634 VGPR[262:264] 1541 1547 VGPR[262:264] 2073 2079 VGPR[262:264] 2451 2457 VGPR[262:265] 2572 2592 VGPR[262:265] 2610 2627 VGPR[263:265] 1909 1921 VGPR[263:265] 1941 1951 VGPR[263:266] 2521 2530 VGPR[266:269] 2577 2592 Linking branch instructions to their targets... Final disassembly: Program Type: Fragment Special Input Variables: offset: unset, size: 16, FloatVector4 gl_FragCoord BuiltIn(FragCoord) Textures: offset: 0, size: 4, Float iChannel0 offset: 1, size: 4, Float iChannel1 offset: 2, size: 4, Float iChannel2 offset: 3, size: 4, Float iChannel3 Output Variables: offset: 0, size: 16, FloatVector4 finalColor Uniform Constants: offset: 0, size: 12, FloatVector3 iResolution offset: 12, size: 4, Float iTime offset: 16, size: 16, FloatVector4 iMouse offset: 32, size: 16, FloatVector4 iDate offset: 48, size: 4, Float iFrame offset: 52, size: 48, FloatVector3 iChannelResolution[4] Private Global Variables: offset: unset, size: 4, Float _twist Constants: Float const92: 0 Float const95: 0.0091239 Float const96: 0.00231233 Float const97: 0.00532234 FloatVector3 const98: {0.0091239, 0.00231233, 0.00532234} Float const101: 111112 FloatVector3 const112: {0, 0, 0} Float const117: 1 FloatVector3 const118: {0, 1, 0} FloatVector3 const123: {1, 0, 0} FloatVector3 const128: {1, 1, 0} UInt32 const139: 1 UInt32 const146: 0 FloatVector3 const157: {0, 0, 1} FloatVector3 const162: {0, 1, 1} FloatVector3 const167: {1, 0, 1} FloatVector3 const172: {1, 1, 1} UInt32 const198: 2 Int32 const210: 0 Int32 const217: 5 Float const220: 10 Float const227: 2 Int32 const234: 1 Float const275: 0.5 Float const333: 0.7 FloatVector2 const334: {0.7, 1} Float const355: 0.15 Float const360: 0.75 FloatVector2 const361: {0, 0.75} Float const363: 0.25 Float const369: 0.375 FloatVector2 const370: {0, 0.375} FloatVector2 const372: {0.25, 0.375} Float const386: 0.35 FloatVector2 const387: {0, 0.35} Float const389: 0.45 Float const390: 0.3 FloatVector2 const391: {0.45, 0.3} FloatVector2 const401: {0.35, 0} Float const403: 0.075 Float const417: 0.6 FloatVector2 const418: {0.6, 0.5} Float const420: 0.4 FloatVector2 const421: {0.6, 0.4} Float const434: 0.8 Int32 const451: 100 Float const467: 1e-05 Float const482: 0.0001 FloatVector2 const483: {0.0001, 0} Float const536: 5 Float const606: 0.1 Float const607: 0.9 Float const617: 20 FloatVector3 const618: {5, 20, 5} FloatVector3 const622: {1, 0.7, 0.4} FloatVector3 const626: {2, 10, 2} FloatVector3 const630: {1, 0.8, 0.5} Float const675: 3.14159 Float const685: 1.5 Float const807: 100 Float const828: 8 FloatVector4 const857: {0.9, 0.8, 0.7, 1} Float const861: 0.03 Float const867: 0.454545 FloatVector4 const868: {0.454545, 0.454545, 0.454545, 0.454545} UInt32 const886: 4 Function Local Variables: offset: unset, size: 16, FloatVector4 main.param873 offset: unset, size: 8, FloatVector2 main.param874 offset: unset, size: 16, FloatVector4 main.fragColor offset: unset, size: 8, FloatVector2 main.fragCoord offset: unset, size: 12, FloatVector3 main.uv offset: unset, size: 12, FloatVector3 hash(vf3;.uv offset: unset, size: 12, FloatVector3 noise(vf3;.param114 offset: unset, size: 12, FloatVector3 noise(vf3;.param120 offset: unset, size: 12, FloatVector3 noise(vf3;.param125 offset: unset, size: 12, FloatVector3 noise(vf3;.param130 offset: unset, size: 12, FloatVector3 noise(vf3;.param159 offset: unset, size: 12, FloatVector3 noise(vf3;.param164 offset: unset, size: 12, FloatVector3 noise(vf3;.param169 offset: unset, size: 12, FloatVector3 noise(vf3;.param174 offset: unset, size: 12, FloatVector3 noise(vf3;.uv offset: unset, size: 4, Float fbm(vf3;.f offset: unset, size: 4, Float fbm(vf3;.r offset: unset, size: 4, Int32 fbm(vf3;.i offset: unset, size: 12, FloatVector3 fbm(vf3;.param225 offset: unset, size: 8, FloatVector2 fbm(vf3;.p offset: unset, size: 4, Float fbm(vf3;.angel offset: unset, size: 12, FloatVector3 tRotate(vf2;f1;.p offset: unset, size: 4, Float tRotate(vf2;f1;.a offset: unset, size: 8, FloatVector2 tTwist(vf3;f1;.param264 offset: unset, size: 4, Float tTwist(vf3;f1;.param267 offset: unset, size: 8, FloatVector2 tTwist(vf3;f1;.p offset: unset, size: 8, FloatVector2 tTwist(vf3;f1;.r offset: unset, size: 8, FloatVector2 tRepeat2(vf2;vf2;.p offset: unset, size: 8, FloatVector2 tRepeat2(vf2;vf2;.r offset: unset, size: 8, FloatVector2 sdRect(vf2;vf2;.p offset: unset, size: 4, Float sdRect(vf2;vf2;.r offset: unset, size: 4, Float sdCircle(vf2;f1;.a offset: unset, size: 4, Float sdCircle(vf2;f1;.b offset: unset, size: 4, Float opU(f1;f1;.a offset: unset, size: 4, Float opU(f1;f1;.b offset: unset, size: 12, FloatVector3 opS(f1;f1;.p offset: unset, size: 12, FloatVector3 map(vf3;.param327 offset: unset, size: 4, Float map(vf3;.param329 offset: unset, size: 8, FloatVector2 map(vf3;.param335 offset: unset, size: 8, FloatVector2 map(vf3;.param338 offset: unset, size: 4, Float map(vf3;.d offset: unset, size: 8, FloatVector2 map(vf3;.param364 offset: unset, size: 4, Float map(vf3;.param365 offset: unset, size: 8, FloatVector2 map(vf3;.param373 offset: unset, size: 8, FloatVector2 map(vf3;.param374 offset: unset, size: 4, Float map(vf3;.param376 offset: unset, size: 4, Float map(vf3;.param377 offset: unset, size: 4, Float map(vf3;.param379 offset: unset, size: 4, Float map(vf3;.param381 offset: unset, size: 8, FloatVector2 map(vf3;.param392 offset: unset, size: 8, FloatVector2 map(vf3;.param393 offset: unset, size: 4, Float map(vf3;.param395 offset: unset, size: 4, Float map(vf3;.param397 offset: unset, size: 8, FloatVector2 map(vf3;.param404 offset: unset, size: 4, Float map(vf3;.param405 offset: unset, size: 4, Float map(vf3;.param407 offset: unset, size: 4, Float map(vf3;.param409 offset: unset, size: 8, FloatVector2 map(vf3;.param422 offset: unset, size: 8, FloatVector2 map(vf3;.param423 offset: unset, size: 4, Float map(vf3;.param425 offset: unset, size: 4, Float map(vf3;.param427 offset: unset, size: 4, Float map(vf3;.param436 offset: unset, size: 4, Float map(vf3;.param438 offset: unset, size: 12, FloatVector3 map(vf3;.ro offset: unset, size: 12, FloatVector3 map(vf3;.rd offset: unset, size: 4, Float map(vf3;.maxDist offset: unset, size: 4, Float map(vf3;.steps offset: unset, size: 4, Float trace(vf3;vf3;f1;f1;.total offset: unset, size: 4, Int32 trace(vf3;vf3;f1;f1;.i offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.param461 offset: unset, size: 12, FloatVector3 trace(vf3;vf3;f1;f1;.p offset: unset, size: 12, FloatVector3 getNormal(vf3;.param488 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param494 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param501 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param507 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param514 offset: unset, size: 12, FloatVector3 getNormal(vf3;.param520 offset: unset, size: 12, FloatVector3 getNormal(vf3;.p offset: unset, size: 12, FloatVector3 getNormal(vf3;.n offset: unset, size: 4, Float calculateAO(vf3;vf3;.r offset: unset, size: 4, Float calculateAO(vf3;vf3;.w offset: unset, size: 4, Float calculateAO(vf3;vf3;.i offset: unset, size: 12, FloatVector3 calculateAO(vf3;vf3;.param549 offset: unset, size: 12, FloatVector3 calculateAO(vf3;vf3;.p offset: unset, size: 8, FloatVector2 isWall(vf3;.param569 offset: unset, size: 8, FloatVector2 isWall(vf3;.param572 offset: unset, size: 12, FloatVector3 isWall(vf3;.p offset: unset, size: 12, FloatVector3 _texture(vf3;.param588 offset: unset, size: 4, Float _texture(vf3;.param590 offset: unset, size: 12, FloatVector3 _texture(vf3;.param596 offset: unset, size: 12, FloatVector3 _texture(vf3;.t offset: unset, size: 4, Float _texture(vf3;.var601 offset: unset, size: 12, FloatVector3 _texture(vf3;.param610 offset: unset, size: 12, FloatVector3 _texture(vf3;.param620 offset: unset, size: 12, FloatVector3 _texture(vf3;.param628 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.uv offset: unset, size: 4, Float mainImage(vf4;vf2;.time offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.ro offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.rd offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.light offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param710 offset: unset, size: 4, Float mainImage(vf4;vf2;.param713 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param723 offset: unset, size: 4, Float mainImage(vf4;vf2;.param726 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param736 offset: unset, size: 4, Float mainImage(vf4;vf2;.param739 offset: unset, size: 8, FloatVector2 mainImage(vf4;vf2;.param749 offset: unset, size: 4, Float mainImage(vf4;vf2;.param752 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param759 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param761 offset: unset, size: 4, Float mainImage(vf4;vf2;.param763 offset: unset, size: 4, Float mainImage(vf4;vf2;.param764 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param774 offset: unset, size: 4, Float mainImage(vf4;vf2;.shadow offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param794 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param796 offset: unset, size: 4, Float mainImage(vf4;vf2;.param798 offset: unset, size: 4, Float mainImage(vf4;vf2;.param800 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param831 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param833 offset: unset, size: 12, FloatVector3 mainImage(vf4;vf2;.param837 Instructions: V_SUB_F32 vDst(VGPR3) src0(SGPR2) src1(VGPR3) // VOP2 # Void main() Function: Void main() # lb5 Label: lb5 # OpStore: : const92 >> _twist S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR20) src0(SGPR212) # 875: OpLoad: FloatVector4: tmp875 << gl_FragCoord V_MOV_B32 vDst(VGPR254) src0(VGPR2) V_MOV_B32 vDst(VGPR255) src0(VGPR3) V_MOV_B32 vDst(VGPR256) src0(VGPR4) V_MOV_B32 vDst(VGPR257) src0(VGPR5) # 876: OpVectorShuffle: FloatVector2: tmp876 << tmp875, tmp875, 0, 1 V_MOV_B32 vDst(VGPR258) src0(VGPR254) V_MOV_B32 vDst(VGPR259) src0(VGPR255) # OpStore: : tmp876 >> param874 V_MOV_B32 vDst(VGPR18) src0(VGPR258) V_MOV_B32 vDst(VGPR19) src0(VGPR259) # 877: OpFunctionCall: Void: mainImage(vf4;vf2;(param873, param874) S_ADD_U32 sDst(SGPR9) src0(LITERAL_CONST) src1(0) const: 0xd # VGPR[18:21] S_ADD_U32 sDst(SGPR12) src0(LITERAL_CONST) src1(0) const: 0x12 # VGPR[22:23] S_MOV_B64 sDst(SGPR14) src0(EXEC) # Indirect branch to mainImage(vf4;vf2;: 6832 S_GETPC_B64 sDst(SGPR10) src0(SGPR10) S_ADD_U32 sDst(SGPR10) src0(SGPR10) src1(LITERAL_CONST) const: 0x1ab0 S_ADDC_U32 sDst(SGPR11) src0(SGPR11) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR10) src0(SGPR10) S_MOV_B64 sDst(EXEC) src0(SGPR14) # .lbl0 # 878: OpLoad: FloatVector4: tmp878 << param873 # OpStore: : tmp878 >> finalColor V_MOV_B32 vDst(VGPR254) src0(VGPR13) V_MOV_B32 vDst(VGPR255) src0(VGPR14) V_MOV_B32 vDst(VGPR256) src0(VGPR15) V_MOV_B32 vDst(VGPR257) src0(VGPR16) # OpReturn: V_CVT_PKRTZ_F16_F32 vDst(VGPR254) src0(VGPR254) src1(VGPR255) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_CVT_PKRTZ_F16_F32 vDst(VGPR255) src0(VGPR256) src1(VGPR257) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a EXP en(0xf) tgt(0) compr(1) done(1) vm(1) vsrc0(VGPR254) vsrc1(VGPR255) vsrc2(VGPR256) vsrc3(VGPR257) S_WAITCNT 0 S_ENDPGM 0 # Float hash(vf3;(FloatVector3* uv) Function: Float hash(vf3;() S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb12 Label: lb12 # 94: OpLoad: FloatVector3: tmp94 << uv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR18) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 99: OpDot: Float: tmp99 << tmp94, const98 V_MOV_B32 vDst(VGPR257) src0(LITERAL_CONST) const: 0x3c157c67 V_MOV_B32 vDst(VGPR258) src0(LITERAL_CONST) const: 0x3b178a76 V_MOV_B32 vDst(VGPR259) src0(LITERAL_CONST) const: 0x3bae6706 V_MUL_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_MAC_F32 vDst(VGPR260) src0(VGPR255) src1(VGPR258) // VOP2 V_MAC_F32 vDst(VGPR260) src0(VGPR256) src1(VGPR259) // VOP2 # 100: OpExtInst(Sin): Float: tmp100 << tmp99 V_MUL_F32 vDst(VGPR254) src0(LITERAL_CONST) src1(VGPR260) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR254) src0(VGPR254) V_SIN_F32 vDst(VGPR254) src0(VGPR254) # 102: OpFMul: Float: tmp102 << tmp100, const101 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x47d903c6 V_MUL_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # 103: OpExtInst(Fract): Float: tmp103 << tmp102 V_FRACT_F32 vDst(VGPR254) src0(VGPR256) # OpReturnValue: : << tmp103 S_MOV_B32 sDst(M0) src0(SGPR13) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR254) S_SETPC_B64 sDst(SGPR16) src0(SGPR16) # Float noise(vf3;(FloatVector3* uv) Function: Float noise(vf3;() S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb15 Label: lb15 # 108: OpLoad: FloatVector3: tmp108 << uv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR22) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 109: OpExtInst(Floor): FloatVector3: tmp109 << tmp108 V_FLOOR_F32 vDst(VGPR45) src0(VGPR254) V_FLOOR_F32 vDst(VGPR46) src0(VGPR255) V_FLOOR_F32 vDst(VGPR47) src0(VGPR256) # 113: OpFAdd: FloatVector3: tmp113 << tmp109, const112 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR256) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR257) src0(VGPR45) src1(VGPR254) // VOP2 V_ADD_F32 vDst(VGPR258) src0(VGPR46) src1(VGPR255) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR47) src1(VGPR256) // VOP2 # OpStore: : tmp113 >> param114 V_MOV_B32 vDst(VGPR21) src0(VGPR257) V_MOV_B32 vDst(VGPR22) src0(VGPR258) V_MOV_B32 vDst(VGPR23) src0(VGPR259) # 115: OpFunctionCall: Float: hash(vf3;(param114) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x15 # VGPR[47:49] S_MOV_B64 sDst(SGPR24) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x30 # VGPR83 # Indirect branch to hash(vf3;: -212 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0xd4 S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR24) # .lbl1 # 119: OpFAdd: FloatVector3: tmp119 << tmp109, const118 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR255) src0(1_0_F) V_MOV_B32 vDst(VGPR256) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR257) src0(VGPR45) src1(VGPR254) // VOP2 V_ADD_F32 vDst(VGPR258) src0(VGPR46) src1(VGPR255) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR47) src1(VGPR256) // VOP2 # OpStore: : tmp119 >> param120 V_MOV_B32 vDst(VGPR24) src0(VGPR257) V_MOV_B32 vDst(VGPR25) src0(VGPR258) V_MOV_B32 vDst(VGPR26) src0(VGPR259) # 121: OpFunctionCall: Float: hash(vf3;(param120) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x18 # VGPR[50:52] S_MOV_B64 sDst(SGPR26) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x31 # VGPR90 # Indirect branch to hash(vf3;: -304 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x130 S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR26) # .lbl2 # 124: OpFAdd: FloatVector3: tmp124 << tmp109, const123 V_MOV_B32 vDst(VGPR254) src0(1_0_F) V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR256) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR257) src0(VGPR45) src1(VGPR254) // VOP2 V_ADD_F32 vDst(VGPR258) src0(VGPR46) src1(VGPR255) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR47) src1(VGPR256) // VOP2 # OpStore: : tmp124 >> param125 V_MOV_B32 vDst(VGPR27) src0(VGPR257) V_MOV_B32 vDst(VGPR28) src0(VGPR258) V_MOV_B32 vDst(VGPR29) src0(VGPR259) # 126: OpFunctionCall: Float: hash(vf3;(param125) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x1b # VGPR[53:55] S_MOV_B64 sDst(SGPR28) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x32 # VGPR97 # Indirect branch to hash(vf3;: -396 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x18c S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR28) # .lbl3 # 129: OpFAdd: FloatVector3: tmp129 << tmp109, const128 V_MOV_B32 vDst(VGPR254) src0(1_0_F) V_MOV_B32 vDst(VGPR255) src0(1_0_F) V_MOV_B32 vDst(VGPR256) src0(LITERAL_CONST) const: 0x00000000 V_ADD_F32 vDst(VGPR257) src0(VGPR45) src1(VGPR254) // VOP2 V_ADD_F32 vDst(VGPR258) src0(VGPR46) src1(VGPR255) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR47) src1(VGPR256) // VOP2 # OpStore: : tmp129 >> param130 V_MOV_B32 vDst(VGPR30) src0(VGPR257) V_MOV_B32 vDst(VGPR31) src0(VGPR258) V_MOV_B32 vDst(VGPR32) src0(VGPR259) # 131: OpFunctionCall: Float: hash(vf3;(param130) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x1e # VGPR[56:58] S_MOV_B64 sDst(SGPR30) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x33 # VGPR104 # Indirect branch to hash(vf3;: -484 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x1e4 S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR30) # .lbl4 # 132: OpCompositeConstruct: FloatVector4: tmp132 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; V_MOV_B32 vDst(VGPR260) src0(VGPR48) V_MOV_B32 vDst(VGPR261) src0(VGPR49) V_MOV_B32 vDst(VGPR262) src0(VGPR50) V_MOV_B32 vDst(VGPR263) src0(VGPR51) # 135: OpVectorShuffle: FloatVector2: tmp135 << tmp132, tmp132, 0, 2 V_MOV_B32 vDst(VGPR254) src0(VGPR260) V_MOV_B32 vDst(VGPR255) src0(VGPR262) # 137: OpVectorShuffle: FloatVector2: tmp137 << tmp132, tmp132, 1, 3 V_MOV_B32 vDst(VGPR256) src0(VGPR261) V_MOV_B32 vDst(VGPR257) src0(VGPR263) # 140: OpAccessChain: Float*: uv[1] # 141: OpLoad: Float: tmp141 << uv[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR22) const: 0x0 V_MOVRELS_B32 vDst(VGPR258) src0(VGPR1) # 142: OpExtInst(Fract): Float: tmp142 << tmp141 V_FRACT_F32 vDst(VGPR259) src0(VGPR258) # 143: OpCompositeConstruct: FloatVector2: tmp143 << tmp142, tmp142 V_MOV_B32 vDst(VGPR260) src0(VGPR259) V_MOV_B32 vDst(VGPR261) src0(VGPR259) # 144: OpExtInst(FMix): FloatVector2: tmp144 << tmp135, tmp137, tmp143 V_SUBREV_F32 vDst(VGPR258) src0(VGPR260) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR258) src0(VGPR254) src1(VGPR258) // VOP2 V_MAD_F32 vDst(VGPR258) src0(VGPR256) src1(VGPR260) src2(VGPR258) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR259) src0(VGPR261) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR259) src0(VGPR255) src1(VGPR259) // VOP2 V_MAD_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR261) src2(VGPR259) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 147: OpAccessChain: Float*: axis0[0] # 148: OpCompositeExtract: Float: tmp148 << tmp144, 0 V_MOV_B32 vDst(VGPR254) src0(VGPR258) # 149: OpAccessChain: Float*: axis0[1] # 150: OpCompositeExtract: Float: tmp150 << tmp144, 1 V_MOV_B32 vDst(VGPR255) src0(VGPR259) # 151: OpAccessChain: Float*: uv[0] # 152: OpLoad: Float: tmp152 << uv[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR22) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) # 153: OpExtInst(Fract): Float: tmp153 << tmp152 V_FRACT_F32 vDst(VGPR257) src0(VGPR256) # 154: OpExtInst(FMix): Float: tmp154 << tmp148, tmp150, tmp153 V_SUBREV_F32 vDst(VGPR52) src0(VGPR257) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR52) src0(VGPR254) src1(VGPR52) // VOP2 V_MAD_F32 vDst(VGPR52) src0(VGPR255) src1(VGPR257) src2(VGPR52) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 158: OpFAdd: FloatVector3: tmp158 << tmp109, const157 V_MOV_B32 vDst(VGPR258) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR259) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR260) src0(1_0_F) V_ADD_F32 vDst(VGPR254) src0(VGPR45) src1(VGPR258) // VOP2 V_ADD_F32 vDst(VGPR255) src0(VGPR46) src1(VGPR259) // VOP2 V_ADD_F32 vDst(VGPR256) src0(VGPR47) src1(VGPR260) // VOP2 # OpStore: : tmp158 >> param159 V_MOV_B32 vDst(VGPR33) src0(VGPR254) V_MOV_B32 vDst(VGPR34) src0(VGPR255) V_MOV_B32 vDst(VGPR35) src0(VGPR256) # 160: OpFunctionCall: Float: hash(vf3;(param159) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x21 # VGPR[59:61] S_MOV_B64 sDst(SGPR32) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x35 # VGPR130 # Indirect branch to hash(vf3;: -716 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x2cc S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR32) # .lbl5 # 163: OpFAdd: FloatVector3: tmp163 << tmp109, const162 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR255) src0(1_0_F) V_MOV_B32 vDst(VGPR256) src0(1_0_F) V_ADD_F32 vDst(VGPR257) src0(VGPR45) src1(VGPR254) // VOP2 V_ADD_F32 vDst(VGPR258) src0(VGPR46) src1(VGPR255) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR47) src1(VGPR256) // VOP2 # OpStore: : tmp163 >> param164 V_MOV_B32 vDst(VGPR36) src0(VGPR257) V_MOV_B32 vDst(VGPR37) src0(VGPR258) V_MOV_B32 vDst(VGPR38) src0(VGPR259) # 165: OpFunctionCall: Float: hash(vf3;(param164) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x24 # VGPR[62:64] S_MOV_B64 sDst(SGPR34) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x36 # VGPR137 # Indirect branch to hash(vf3;: -804 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x324 S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR34) # .lbl6 # 168: OpFAdd: FloatVector3: tmp168 << tmp109, const167 V_MOV_B32 vDst(VGPR254) src0(1_0_F) V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR256) src0(1_0_F) V_ADD_F32 vDst(VGPR257) src0(VGPR45) src1(VGPR254) // VOP2 V_ADD_F32 vDst(VGPR258) src0(VGPR46) src1(VGPR255) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR47) src1(VGPR256) // VOP2 # OpStore: : tmp168 >> param169 V_MOV_B32 vDst(VGPR39) src0(VGPR257) V_MOV_B32 vDst(VGPR40) src0(VGPR258) V_MOV_B32 vDst(VGPR41) src0(VGPR259) # 170: OpFunctionCall: Float: hash(vf3;(param169) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x27 # VGPR[65:67] S_MOV_B64 sDst(SGPR36) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x37 # VGPR144 # Indirect branch to hash(vf3;: -892 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x37c S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR36) # .lbl7 # 173: OpFAdd: FloatVector3: tmp173 << tmp109, const172 V_MOV_B32 vDst(VGPR254) src0(1_0_F) V_MOV_B32 vDst(VGPR255) src0(1_0_F) V_MOV_B32 vDst(VGPR256) src0(1_0_F) V_ADD_F32 vDst(VGPR257) src0(VGPR45) src1(VGPR254) // VOP2 V_ADD_F32 vDst(VGPR258) src0(VGPR46) src1(VGPR255) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR47) src1(VGPR256) // VOP2 # OpStore: : tmp173 >> param174 V_MOV_B32 vDst(VGPR42) src0(VGPR257) V_MOV_B32 vDst(VGPR43) src0(VGPR258) V_MOV_B32 vDst(VGPR44) src0(VGPR259) # 175: OpFunctionCall: Float: hash(vf3;(param174) S_ADD_U32 sDst(SGPR18) src0(LITERAL_CONST) src1(0) const: 0x2a # VGPR[68:70] S_MOV_B64 sDst(SGPR38) src0(EXEC) S_MOV_B32 sDst(SGPR13) src0(LITERAL_CONST) const: 0x38 # VGPR151 # Indirect branch to hash(vf3;: -976 S_GETPC_B64 sDst(SGPR16) src0(SGPR16) S_SUB_U32 sDst(SGPR16) src0(SGPR16) src1(LITERAL_CONST) const: 0x3d0 S_SUBB_U32 sDst(SGPR17) src0(SGPR17) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR16) src0(SGPR16) S_MOV_B64 sDst(EXEC) src0(SGPR38) # .lbl8 # 176: OpCompositeConstruct: FloatVector4: tmp176 << hash(vf3;, hash(vf3;, hash(vf3;, hash(vf3; V_MOV_B32 vDst(VGPR260) src0(VGPR53) V_MOV_B32 vDst(VGPR261) src0(VGPR54) V_MOV_B32 vDst(VGPR262) src0(VGPR55) V_MOV_B32 vDst(VGPR263) src0(VGPR56) # 179: OpVectorShuffle: FloatVector2: tmp179 << tmp176, tmp176, 0, 2 V_MOV_B32 vDst(VGPR254) src0(VGPR260) V_MOV_B32 vDst(VGPR255) src0(VGPR262) # 181: OpVectorShuffle: FloatVector2: tmp181 << tmp176, tmp176, 1, 3 V_MOV_B32 vDst(VGPR256) src0(VGPR261) V_MOV_B32 vDst(VGPR257) src0(VGPR263) # 182: OpAccessChain: Float*: uv[1] # 183: OpLoad: Float: tmp183 << uv[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR22) const: 0x0 V_MOVRELS_B32 vDst(VGPR258) src0(VGPR1) # 184: OpExtInst(Fract): Float: tmp184 << tmp183 V_FRACT_F32 vDst(VGPR259) src0(VGPR258) # 185: OpCompositeConstruct: FloatVector2: tmp185 << tmp184, tmp184 V_MOV_B32 vDst(VGPR260) src0(VGPR259) V_MOV_B32 vDst(VGPR261) src0(VGPR259) # 186: OpExtInst(FMix): FloatVector2: tmp186 << tmp179, tmp181, tmp185 V_SUBREV_F32 vDst(VGPR258) src0(VGPR260) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR258) src0(VGPR254) src1(VGPR258) // VOP2 V_MAD_F32 vDst(VGPR258) src0(VGPR256) src1(VGPR260) src2(VGPR258) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR259) src0(VGPR261) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR259) src0(VGPR255) src1(VGPR259) // VOP2 V_MAD_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR261) src2(VGPR259) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 188: OpAccessChain: Float*: axis1[0] # 189: OpCompositeExtract: Float: tmp189 << tmp186, 0 V_MOV_B32 vDst(VGPR254) src0(VGPR258) # 190: OpAccessChain: Float*: axis1[1] # 191: OpCompositeExtract: Float: tmp191 << tmp186, 1 V_MOV_B32 vDst(VGPR255) src0(VGPR259) # 192: OpAccessChain: Float*: uv[0] # 193: OpLoad: Float: tmp193 << uv[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR22) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) # 194: OpExtInst(Fract): Float: tmp194 << tmp193 V_FRACT_F32 vDst(VGPR257) src0(VGPR256) # 195: OpExtInst(FMix): Float: tmp195 << tmp189, tmp191, tmp194 V_SUBREV_F32 vDst(VGPR256) src0(VGPR257) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR256) // VOP2 V_MAD_F32 vDst(VGPR256) src0(VGPR255) src1(VGPR257) src2(VGPR256) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 199: OpAccessChain: Float*: uv[2] # 200: OpLoad: Float: tmp200 << uv[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR22) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR2) # 201: OpExtInst(Fract): Float: tmp201 << tmp200 V_FRACT_F32 vDst(VGPR255) src0(VGPR254) # 202: OpExtInst(FMix): Float: tmp202 << tmp154, tmp195, tmp201 V_SUBREV_F32 vDst(VGPR254) src0(VGPR255) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR254) src0(VGPR52) src1(VGPR254) // VOP2 V_MAD_F32 vDst(VGPR254) src0(VGPR256) src1(VGPR255) src2(VGPR254) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp202 S_MOV_B32 sDst(M0) src0(SGPR19) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR254) S_SETPC_B64 sDst(SGPR20) src0(SGPR20) # Float fbm(vf3;(FloatVector3* uv) Function: Float fbm(vf3;() S_MOV_B64 sDst(SGPR44) src0(EXEC) # lb18 Label: lb18 # OpStore: : const92 >> f S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR57) src0(SGPR212) # OpStore: : const117 >> r V_MOV_B32 vDst(VGPR58) src0(1_0_F) # OpStore: : const210 >> i S_MOV_B32 sDst(SGPR210) src0(0) # OpBranch: to lb211 # lb211 Label: lb211 # OpLoopMerge: (merge: lb213, continue: lb214) # CF Block: Merge: lb213, Continue: lb214 S_MOV_B64 sDst(SGPR46) src0(EXEC) S_MOV_B64 sDst(SGPR48) src0(EXEC) S_MOV_B64 sDst(SGPR50) src0(EXEC) Label: lb211Loop # OpBranch: to lb215 # lb215 Label: lb215 # 216: OpLoad: Int: tmp216 << i Decorators: RelaxedPrecision # 218: OpSLessThan: Bool: tmp218 << tmp216, const217 V_MOV_B32 vDst(VGPR254) src0(5_INT) V_CMP_LT_I32 dst(SGPR212) src0(SGPR210) src1(VGPR254) // VOP3a # OpBranchConditional: if(tmp218) then branch to lb212, else branch to lb213 # CF Block: Cond Branch: true: lb212, false: lb213 S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 51 lb213 # lb212 Label: lb212 S_MOV_B64 sDst(SGPR48) src0(EXEC) S_MOV_B64 sDst(SGPR50) src0(EXEC) # 219: OpLoad: FloatVector3: tmp219 << uv S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR42) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 221: OpCompositeConstruct: FloatVector3: tmp221 << const220, const220, const220 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR257) src0(SGPR212) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR258) src0(SGPR212) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR259) src0(SGPR212) # 222: OpFAdd: FloatVector3: tmp222 << tmp219, tmp221 V_ADD_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_ADD_F32 vDst(VGPR261) src0(VGPR255) src1(VGPR258) // VOP2 V_ADD_F32 vDst(VGPR262) src0(VGPR256) src1(VGPR259) // VOP2 # 223: OpLoad: Float: tmp223 << r # 224: OpVectorTimesScalar: FloatVector3: tmp224 << tmp222, tmp223 V_MUL_F32 vDst(VGPR254) src0(VGPR58) src1(VGPR260) // VOP2 V_MUL_F32 vDst(VGPR255) src0(VGPR58) src1(VGPR261) // VOP2 V_MUL_F32 vDst(VGPR256) src0(VGPR58) src1(VGPR262) // VOP2 # OpStore: : tmp224 >> param225 V_MOV_B32 vDst(VGPR59) src0(VGPR254) V_MOV_B32 vDst(VGPR60) src0(VGPR255) V_MOV_B32 vDst(VGPR61) src0(VGPR256) # 226: OpFunctionCall: Float: noise(vf3;(param225) S_ADD_U32 sDst(SGPR22) src0(LITERAL_CONST) src1(0) const: 0x3b # VGPR[177:179] S_MOV_B64 sDst(SGPR52) src0(EXEC) S_MOV_B32 sDst(SGPR19) src0(LITERAL_CONST) const: 0x3e # VGPR197 # Indirect branch to noise(vf3;: -1264 S_GETPC_B64 sDst(SGPR20) src0(SGPR20) S_SUB_U32 sDst(SGPR20) src0(SGPR20) src1(LITERAL_CONST) const: 0x4f0 S_SUBB_U32 sDst(SGPR21) src0(SGPR21) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR20) src0(SGPR20) S_MOV_B64 sDst(EXEC) src0(SGPR52) # .lbl9 # 228: OpLoad: Float: tmp228 << r # 229: OpFMul: Float: tmp229 << tmp228, const227 V_MOV_B32 vDst(VGPR254) src0(2_0_F) V_MUL_F32 vDst(VGPR255) src0(VGPR58) src1(VGPR254) // VOP2 # OpStore: : tmp229 >> r V_MOV_B32 vDst(VGPR58) src0(VGPR255) # 230: OpFDiv: Float: tmp230 << noise(vf3;, tmp229 V_RCP_F32 vDst(VGPR254) src0(VGPR255) V_MUL_F32 vDst(VGPR254) src0(VGPR62) src1(VGPR254) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR254) src0(VGPR254) src1(VGPR255) src2(VGPR62) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 231: OpLoad: Float: tmp231 << f # 232: OpFAdd: Float: tmp232 << tmp231, tmp230 V_ADD_F32 vDst(VGPR255) src0(VGPR57) src1(VGPR254) // VOP2 # OpStore: : tmp232 >> f V_MOV_B32 vDst(VGPR57) src0(VGPR255) # OpBranch: to lb214 # lb214 Label: lb214 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR48) # 233: OpLoad: Int: tmp233 << i Decorators: RelaxedPrecision # 235: OpIAdd: Int: tmp235 << tmp233, const234 Decorators: RelaxedPrecision S_MOV_B32 sDst(SGPR212) src0(1_INT) S_ADD_I32 sDst(SGPR213) src0(SGPR210) src1(SGPR212) # OpStore: : tmp235 >> i S_MOV_B32 sDst(SGPR210) src0(SGPR213) # OpBranch: to lb211 S_BRANCH -56 lb211Loop # lb213 Label: lb213 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR46) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR44) # 236: OpLoad: Float: tmp236 << f # 237: OpLoad: Float: tmp237 << r # 238: OpFDiv: Float: tmp238 << const117, tmp237 V_RCP_F32 vDst(VGPR254) src0(VGPR58) V_MUL_F32 vDst(VGPR254) src0(1_0_F) src1(VGPR254) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR254) src0(VGPR254) src1(VGPR58) src2(1_0_F) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 239: OpFSub: Float: tmp239 << const117, tmp238 V_SUB_F32 vDst(VGPR255) src0(1_0_F) src1(VGPR254) // VOP2 # 240: OpFDiv: Float: tmp240 << tmp236, tmp239 V_RCP_F32 vDst(VGPR254) src0(VGPR255) V_MUL_F32 vDst(VGPR254) src0(VGPR57) src1(VGPR254) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR254) src0(VGPR254) src1(VGPR255) src2(VGPR57) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpReturnValue: : << tmp240 S_MOV_B32 sDst(M0) src0(SGPR23) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR254) S_SETPC_B64 sDst(SGPR40) src0(SGPR40) # Void tRotate(vf2;f1;(FloatVector2* p, Float* angel) Function: Void tRotate(vf2;f1;(, Float fbm(vf3;.angel) S_MOV_B64 sDst(SGPR214) src0(EXEC) # lb26 Label: lb26 # 244: OpLoad: Float: tmp244 << angel S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR56) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 245: OpExtInst(Sin): Float: tmp245 << tmp244 V_MUL_F32 vDst(VGPR255) src0(LITERAL_CONST) src1(VGPR254) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR255) src0(VGPR255) V_SIN_F32 vDst(VGPR255) src0(VGPR255) # 247: OpLoad: Float: tmp247 << angel S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR56) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 248: OpExtInst(Cos): Float: tmp248 << tmp247 V_MUL_F32 vDst(VGPR256) src0(LITERAL_CONST) src1(VGPR254) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR256) src0(VGPR256) V_COS_F32 vDst(VGPR256) src0(VGPR256) # 251: OpFNegate: Float: tmp251 << tmp245 V_MUL_F32 vDst(VGPR254) src0(M1_0_F) src1(VGPR255) // VOP2 # 255: OpCompositeConstruct: FloatVector2: tmp255 << tmp248, tmp251 V_MOV_B32 vDst(VGPR257) src0(VGPR256) V_MOV_B32 vDst(VGPR258) src0(VGPR254) # 256: OpCompositeConstruct: FloatVector2: tmp256 << tmp245, tmp248 V_MOV_B32 vDst(VGPR259) src0(VGPR255) V_MOV_B32 vDst(VGPR260) src0(VGPR256) # 257: OpCompositeConstruct: FloatMatrix2x2: tmp257 << tmp255, tmp256 V_MOV_B32 vDst(VGPR261) src0(VGPR257) V_MOV_B32 vDst(VGPR262) src0(VGPR258) V_MOV_B32 vDst(VGPR263) src0(VGPR259) V_MOV_B32 vDst(VGPR264) src0(VGPR260) # 258: OpLoad: FloatVector2: tmp258 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR43) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) # 259: OpVectorTimesMatrix: FloatVector2: tmp259 << tmp258, tmp257 V_MUL_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR261) // VOP2 V_MUL_F32 vDst(VGPR257) src0(VGPR254) src1(VGPR263) // VOP2 V_MAC_F32 vDst(VGPR256) src0(VGPR255) src1(VGPR262) // VOP2 V_MAC_F32 vDst(VGPR257) src0(VGPR255) src1(VGPR264) // VOP2 # OpStore: : tmp259 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR43) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR256) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR257) # OpReturn: S_SETPC_B64 sDst(SGPR54) src0(SGPR54) # Void tTwist(vf3;f1;(FloatVector3* p, Float* a) Function: Void tTwist(vf3;f1;(, Float tRotate(vf2;f1;.a) S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb31 Label: lb31 # 260: OpAccessChain: Float*: p[2] # 261: OpLoad: Float: tmp261 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR57) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR2) # 262: OpLoad: Float: tmp262 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR60) const: 0x0 V_MOVRELS_B32 vDst(VGPR255) src0(VGPR0) # 263: OpFMul: Float: tmp263 << tmp261, tmp262 V_MUL_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # 265: OpLoad: FloatVector3: tmp265 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR57) const: 0x0 V_MOVRELS_B32 vDst(VGPR257) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR258) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR259) src0(VGPR2) # 266: OpVectorShuffle: FloatVector2: tmp266 << tmp265, tmp265, 0, 1 V_MOV_B32 vDst(VGPR254) src0(VGPR257) V_MOV_B32 vDst(VGPR255) src0(VGPR258) # OpStore: : tmp266 >> param264 V_MOV_B32 vDst(VGPR63) src0(VGPR254) V_MOV_B32 vDst(VGPR64) src0(VGPR255) # OpStore: : tmp263 >> param267 V_MOV_B32 vDst(VGPR65) src0(VGPR256) # 268: OpFunctionCall: Void: tRotate(vf2;f1;(param264, param267) S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0x3f # VGPR[224:225] S_ADD_U32 sDst(SGPR56) src0(LITERAL_CONST) src1(0) const: 0x41 # VGPR226 S_MOV_B64 sDst(SGPR62) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: -244 S_GETPC_B64 sDst(SGPR54) src0(SGPR54) S_SUB_U32 sDst(SGPR54) src0(SGPR54) src1(LITERAL_CONST) const: 0xf4 S_SUBB_U32 sDst(SGPR55) src0(SGPR55) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR54) src0(SGPR54) S_MOV_B64 sDst(EXEC) src0(SGPR62) # .lbl10 # 269: OpLoad: FloatVector2: tmp269 << param264 # 270: OpLoad: FloatVector3: tmp270 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR57) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 271: OpVectorShuffle: FloatVector3: tmp271 << tmp270, tmp269, 3, 4, 2 V_MOV_B32 vDst(VGPR257) src0(VGPR63) V_MOV_B32 vDst(VGPR258) src0(VGPR64) V_MOV_B32 vDst(VGPR259) src0(VGPR256) # OpStore: : tmp271 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR57) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR257) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR258) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR259) # OpReturn: S_SETPC_B64 sDst(SGPR58) src0(SGPR58) # FloatVector2 tRepeat2(vf2;vf2;(FloatVector2* p, FloatVector2* r) Function: FloatVector2 tRepeat2(vf2;vf2;(, FloatVector2 tTwist(vf3;f1;.r) S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb36 Label: lb36 # 273: OpLoad: FloatVector2: tmp273 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR66) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) # 274: OpLoad: FloatVector2: tmp274 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR67) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) # 276: OpVectorTimesScalar: FloatVector2: tmp276 << tmp274, const275 V_MOV_B32 vDst(VGPR258) src0(0_5_F) V_MUL_F32 vDst(VGPR259) src0(VGPR258) src1(VGPR256) // VOP2 V_MUL_F32 vDst(VGPR260) src0(VGPR258) src1(VGPR257) // VOP2 # 277: OpFAdd: FloatVector2: tmp277 << tmp273, tmp276 V_ADD_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR259) // VOP2 V_ADD_F32 vDst(VGPR257) src0(VGPR255) src1(VGPR260) // VOP2 # 278: OpLoad: FloatVector2: tmp278 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR67) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) # 279: OpFDiv: FloatVector2: tmp279 << tmp277, tmp278 V_RCP_F32 vDst(VGPR258) src0(VGPR254) V_RCP_F32 vDst(VGPR259) src0(VGPR255) V_MUL_F32 vDst(VGPR258) src0(VGPR256) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR259) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR258) src0(VGPR258) src1(VGPR254) src2(VGPR256) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR259) src0(VGPR259) src1(VGPR255) src2(VGPR257) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 280: OpExtInst(Floor): FloatVector2: tmp280 << tmp279 V_FLOOR_F32 vDst(VGPR254) src0(VGPR258) V_FLOOR_F32 vDst(VGPR255) src0(VGPR259) # 281: OpLoad: FloatVector2: tmp281 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR66) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) # 282: OpLoad: FloatVector2: tmp282 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR67) const: 0x0 V_MOVRELS_B32 vDst(VGPR258) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR259) src0(VGPR1) # 283: OpVectorTimesScalar: FloatVector2: tmp283 << tmp282, const275 V_MOV_B32 vDst(VGPR260) src0(0_5_F) V_MUL_F32 vDst(VGPR261) src0(VGPR260) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR262) src0(VGPR260) src1(VGPR259) // VOP2 # 284: OpFAdd: FloatVector2: tmp284 << tmp281, tmp283 V_ADD_F32 vDst(VGPR258) src0(VGPR256) src1(VGPR261) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR262) // VOP2 # 285: OpLoad: FloatVector2: tmp285 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR67) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) # 286: OpFMod: FloatVector2: tmp286 << tmp284, tmp285 V_RCP_F32 vDst(VGPR260) src0(VGPR256) V_MUL_F32 vDst(VGPR260) src0(VGPR258) src1(VGPR260) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR260) src0(VGPR260) src1(VGPR256) src2(VGPR258) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR260) src0(VGPR260) V_RCP_F32 vDst(VGPR261) src0(VGPR257) V_MUL_F32 vDst(VGPR261) src0(VGPR259) src1(VGPR261) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR261) src0(VGPR261) src1(VGPR257) src2(VGPR259) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_FLOOR_F32 vDst(VGPR261) src0(VGPR261) V_MAD_F32 vDst(VGPR260) src0(VGPR256) src1(VGPR260) src2(VGPR258) abs(0) clamp(0) omod(0) neg(1) // VOP3a V_MAD_F32 vDst(VGPR261) src0(VGPR257) src1(VGPR261) src2(VGPR259) abs(0) clamp(0) omod(0) neg(1) // VOP3a # 287: OpLoad: FloatVector2: tmp287 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR67) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) # 288: OpVectorTimesScalar: FloatVector2: tmp288 << tmp287, const275 V_MOV_B32 vDst(VGPR258) src0(0_5_F) V_MUL_F32 vDst(VGPR262) src0(VGPR258) src1(VGPR256) // VOP2 V_MUL_F32 vDst(VGPR263) src0(VGPR258) src1(VGPR257) // VOP2 # 289: OpFSub: FloatVector2: tmp289 << tmp286, tmp288 V_SUB_F32 vDst(VGPR256) src0(VGPR260) src1(VGPR262) // VOP2 V_SUB_F32 vDst(VGPR257) src0(VGPR261) src1(VGPR263) // VOP2 # OpStore: : tmp289 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR66) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR256) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR257) # OpReturnValue: : << tmp280 S_MOV_B32 sDst(M0) src0(SGPR61) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR254) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR255) S_SETPC_B64 sDst(SGPR64) src0(SGPR64) # Float sdRect(vf2;vf2;(FloatVector2* p, FloatVector2* r) Function: Float sdRect(vf2;vf2;(, FloatVector2 tRepeat2(vf2;vf2;.r) S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb41 Label: lb41 # 293: OpLoad: FloatVector2: tmp293 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) # 294: OpExtInst(FAbs): FloatVector2: tmp294 << tmp293 V_ADD_F32 vDst(VGPR256) src0(VGPR254) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a V_ADD_F32 vDst(VGPR257) src0(VGPR255) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 295: OpLoad: FloatVector2: tmp295 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR72) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) # 296: OpFSub: FloatVector2: tmp296 << tmp294, tmp295 V_SUB_F32 vDst(VGPR258) src0(VGPR256) src1(VGPR254) // VOP2 V_SUB_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR255) // VOP2 # OpStore: : tmp296 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR258) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR259) # 297: OpAccessChain: Float*: p[0] # 298: OpLoad: Float: tmp298 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 299: OpAccessChain: Float*: p[1] # 300: OpLoad: Float: tmp300 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) # 301: OpExtInst(FMax): Float: tmp301 << tmp298, tmp300 V_MAX_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # 302: OpExtInst(FMin): Float: tmp302 << tmp301, const92 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x00000000 V_MIN_F32 vDst(VGPR255) src0(VGPR256) src1(VGPR254) // VOP2 # 303: OpLoad: FloatVector2: tmp303 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR71) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) # 304: OpCompositeConstruct: FloatVector2: tmp304 << const92, const92 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR258) src0(SGPR212) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR259) src0(SGPR212) # 305: OpExtInst(FMax): FloatVector2: tmp305 << tmp303, tmp304 V_MAX_F32 vDst(VGPR260) src0(VGPR256) src1(VGPR258) // VOP2 V_MAX_F32 vDst(VGPR261) src0(VGPR257) src1(VGPR259) // VOP2 # 306: OpExtInst(Length): Float: tmp306 << tmp305 V_MUL_F32 vDst(VGPR254) src0(VGPR260) src1(VGPR260) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR261) src1(VGPR261) // VOP2 V_SQRT_F32 vDst(VGPR254) src0(VGPR254) # 307: OpFAdd: Float: tmp307 << tmp302, tmp306 V_ADD_F32 vDst(VGPR256) src0(VGPR255) src1(VGPR254) // VOP2 # OpReturnValue: : << tmp307 S_MOV_B32 sDst(M0) src0(SGPR70) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR256) S_SETPC_B64 sDst(SGPR68) src0(SGPR68) # Float sdCircle(vf2;f1;(FloatVector2* p, Float* r) Function: Float sdCircle(vf2;f1;(, Float sdRect(vf2;vf2;.r) S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb46 Label: lb46 # 310: OpLoad: FloatVector2: tmp310 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR76) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) # 311: OpExtInst(Length): Float: tmp311 << tmp310 V_MUL_F32 vDst(VGPR254) src0(VGPR256) src1(VGPR256) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR257) src1(VGPR257) // VOP2 V_SQRT_F32 vDst(VGPR254) src0(VGPR254) # 312: OpLoad: Float: tmp312 << r S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR77) const: 0x0 V_MOVRELS_B32 vDst(VGPR255) src0(VGPR0) # 313: OpFSub: Float: tmp313 << tmp311, tmp312 V_SUB_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # OpReturnValue: : << tmp313 S_MOV_B32 sDst(M0) src0(SGPR73) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR256) S_SETPC_B64 sDst(SGPR74) src0(SGPR74) # Float opU(f1;f1;(Float* a, Float* b) Function: Float opU(f1;f1;(, Float sdCircle(vf2;f1;.b) S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb51 Label: lb51 # 316: OpLoad: Float: tmp316 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR81) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 317: OpLoad: Float: tmp317 << b S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR82) const: 0x0 V_MOVRELS_B32 vDst(VGPR255) src0(VGPR0) # 318: OpExtInst(FMin): Float: tmp318 << tmp316, tmp317 V_MIN_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # OpReturnValue: : << tmp318 S_MOV_B32 sDst(M0) src0(SGPR80) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR256) S_SETPC_B64 sDst(SGPR78) src0(SGPR78) # Float opS(f1;f1;(Float* a, Float* b) Function: Float opS(f1;f1;(, Float opU(f1;f1;.b) S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb55 Label: lb55 # 321: OpLoad: Float: tmp321 << a S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR86) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 322: OpLoad: Float: tmp322 << b S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR87) const: 0x0 V_MOVRELS_B32 vDst(VGPR255) src0(VGPR0) # 323: OpFNegate: Float: tmp323 << tmp322 V_MUL_F32 vDst(VGPR256) src0(M1_0_F) src1(VGPR255) // VOP2 # 324: OpExtInst(FMax): Float: tmp324 << tmp321, tmp323 V_MAX_F32 vDst(VGPR255) src0(VGPR254) src1(VGPR256) // VOP2 # OpReturnValue: : << tmp324 S_MOV_B32 sDst(M0) src0(SGPR83) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR255) S_SETPC_B64 sDst(SGPR84) src0(SGPR84) # Float map(vf3;(FloatVector3* p) Function: Float map(vf3;() S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb58 Label: lb58 # 328: OpLoad: FloatVector3: tmp328 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # OpStore: : tmp328 >> param327 V_MOV_B32 vDst(VGPR66) src0(VGPR254) V_MOV_B32 vDst(VGPR67) src0(VGPR255) V_MOV_B32 vDst(VGPR68) src0(VGPR256) # 330: OpLoad: Float: tmp330 << _twist # OpStore: : tmp330 >> param329 V_MOV_B32 vDst(VGPR69) src0(VGPR20) # 331: OpFunctionCall: Void: tTwist(vf3;f1;(param327, param329) S_ADD_U32 sDst(SGPR57) src0(LITERAL_CONST) src1(0) const: 0x42 # VGPR[311:313] S_ADD_U32 sDst(SGPR60) src0(LITERAL_CONST) src1(0) const: 0x45 # VGPR314 S_MOV_B64 sDst(SGPR92) src0(EXEC) # Indirect branch to tTwist(vf3;f1;: -888 S_GETPC_B64 sDst(SGPR58) src0(SGPR58) S_SUB_U32 sDst(SGPR58) src0(SGPR58) src1(LITERAL_CONST) const: 0x378 S_SUBB_U32 sDst(SGPR59) src0(SGPR59) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR58) src0(SGPR58) S_MOV_B64 sDst(EXEC) src0(SGPR92) # .lbl11 # 332: OpLoad: FloatVector3: tmp332 << param327 # OpStore: : tmp332 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR66) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR67) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR68) # 336: OpLoad: FloatVector3: tmp336 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 337: OpVectorShuffle: FloatVector2: tmp337 << tmp336, tmp336, 0, 2 V_MOV_B32 vDst(VGPR257) src0(VGPR254) V_MOV_B32 vDst(VGPR258) src0(VGPR256) # OpStore: : tmp337 >> param335 V_MOV_B32 vDst(VGPR70) src0(VGPR257) V_MOV_B32 vDst(VGPR71) src0(VGPR258) # OpStore: : const334 >> param338 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x3f333333 S_MOV_B32 sDst(SGPR213) src0(1_0_F) V_MOV_B32 vDst(VGPR72) src0(SGPR212) V_MOV_B32 vDst(VGPR73) src0(SGPR213) # 339: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param335, param338) S_ADD_U32 sDst(SGPR66) src0(LITERAL_CONST) src1(0) const: 0x46 # VGPR[315:316] S_ADD_U32 sDst(SGPR67) src0(LITERAL_CONST) src1(0) const: 0x48 # VGPR[317:318] S_MOV_B64 sDst(SGPR94) src0(EXEC) S_MOV_B32 sDst(SGPR61) src0(LITERAL_CONST) const: 0xfe # VGPR[360:361] # Indirect branch to tRepeat2(vf2;vf2;: -844 S_GETPC_B64 sDst(SGPR64) src0(SGPR64) S_SUB_U32 sDst(SGPR64) src0(SGPR64) src1(LITERAL_CONST) const: 0x34c S_SUBB_U32 sDst(SGPR65) src0(SGPR65) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR64) src0(SGPR64) S_MOV_B64 sDst(EXEC) src0(SGPR94) # .lbl12 # 340: OpLoad: FloatVector2: tmp340 << param335 # 341: OpLoad: FloatVector3: tmp341 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 342: OpVectorShuffle: FloatVector3: tmp342 << tmp341, tmp340, 3, 1, 4 V_MOV_B32 vDst(VGPR257) src0(VGPR70) V_MOV_B32 vDst(VGPR258) src0(VGPR255) V_MOV_B32 vDst(VGPR259) src0(VGPR71) # OpStore: : tmp342 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR257) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR258) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR259) # 343: OpAccessChain: Float*: p[0] # 344: OpLoad: Float: tmp344 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 345: OpExtInst(FAbs): Float: tmp345 << tmp344 V_ADD_F32 vDst(VGPR255) src0(VGPR254) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 346: OpAccessChain: Float*: p[0] # OpStore: : tmp345 >> p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR255) # 347: OpAccessChain: Float*: p[1] # 348: OpLoad: Float: tmp348 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR1) # 349: OpFAdd: Float: tmp349 << tmp348, const275 V_MOV_B32 vDst(VGPR255) src0(0_5_F) V_ADD_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # 350: OpAccessChain: Float*: p[1] # OpStore: : tmp349 >> p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELD_B32 vDst(VGPR1) src0(VGPR256) # 352: OpAccessChain: Float*: p[2] # 353: OpLoad: Float: tmp353 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR2) # 354: OpExtInst(FAbs): Float: tmp354 << tmp353 V_ADD_F32 vDst(VGPR255) src0(VGPR254) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 356: OpFSub: Float: tmp356 << tmp354, const355 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3e19999a V_SUB_F32 vDst(VGPR256) src0(VGPR255) src1(VGPR254) // VOP2 # OpStore: : tmp356 >> d V_MOV_B32 vDst(VGPR74) src0(VGPR256) # 358: OpLoad: FloatVector3: tmp358 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 359: OpVectorShuffle: FloatVector2: tmp359 << tmp358, tmp358, 0, 1 V_MOV_B32 vDst(VGPR257) src0(VGPR254) V_MOV_B32 vDst(VGPR258) src0(VGPR255) # 362: OpFSub: FloatVector2: tmp362 << tmp359, const361 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x3f400000 V_SUB_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR254) // VOP2 V_SUB_F32 vDst(VGPR260) src0(VGPR258) src1(VGPR255) // VOP2 # OpStore: : tmp362 >> param364 V_MOV_B32 vDst(VGPR75) src0(VGPR259) V_MOV_B32 vDst(VGPR76) src0(VGPR260) # OpStore: : const363 >> param365 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x3e800000 V_MOV_B32 vDst(VGPR77) src0(SGPR212) # 366: OpFunctionCall: Float: sdCircle(vf2;f1;(param364, param365) S_ADD_U32 sDst(SGPR76) src0(LITERAL_CONST) src1(0) const: 0x4b # VGPR[320:321] S_ADD_U32 sDst(SGPR77) src0(LITERAL_CONST) src1(0) const: 0x4d # VGPR322 S_MOV_B64 sDst(SGPR96) src0(EXEC) S_MOV_B32 sDst(SGPR73) src0(LITERAL_CONST) const: 0x69 # VGPR387 # Indirect branch to sdCircle(vf2;f1;: -628 S_GETPC_B64 sDst(SGPR74) src0(SGPR74) S_SUB_U32 sDst(SGPR74) src0(SGPR74) src1(LITERAL_CONST) const: 0x274 S_SUBB_U32 sDst(SGPR75) src0(SGPR75) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR74) src0(SGPR74) S_MOV_B64 sDst(EXEC) src0(SGPR96) # .lbl13 # 367: OpLoad: FloatVector3: tmp367 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 368: OpVectorShuffle: FloatVector2: tmp368 << tmp367, tmp367, 0, 1 V_MOV_B32 vDst(VGPR257) src0(VGPR254) V_MOV_B32 vDst(VGPR258) src0(VGPR255) # 371: OpFSub: FloatVector2: tmp371 << tmp368, const370 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x3ec00000 V_SUB_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR254) // VOP2 V_SUB_F32 vDst(VGPR260) src0(VGPR258) src1(VGPR255) // VOP2 # OpStore: : tmp371 >> param373 V_MOV_B32 vDst(VGPR78) src0(VGPR259) V_MOV_B32 vDst(VGPR79) src0(VGPR260) # OpStore: : const372 >> param374 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x3e800000 S_MOV_B32 sDst(SGPR213) src0(LITERAL_CONST) const: 0x3ec00000 V_MOV_B32 vDst(VGPR80) src0(SGPR212) V_MOV_B32 vDst(VGPR81) src0(SGPR213) # 375: OpFunctionCall: Float: sdRect(vf2;vf2;(param373, param374) S_ADD_U32 sDst(SGPR71) src0(LITERAL_CONST) src1(0) const: 0x4e # VGPR[323:324] S_ADD_U32 sDst(SGPR72) src0(LITERAL_CONST) src1(0) const: 0x50 # VGPR[325:326] S_MOV_B64 sDst(SGPR98) src0(EXEC) S_MOV_B32 sDst(SGPR70) src0(LITERAL_CONST) const: 0x6a # VGPR399 # Indirect branch to sdRect(vf2;vf2;: -960 S_GETPC_B64 sDst(SGPR68) src0(SGPR68) S_SUB_U32 sDst(SGPR68) src0(SGPR68) src1(LITERAL_CONST) const: 0x3c0 S_SUBB_U32 sDst(SGPR69) src0(SGPR69) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR68) src0(SGPR68) S_MOV_B64 sDst(EXEC) src0(SGPR98) # .lbl14 # OpStore: : sdCircle(vf2;f1; >> param376 V_MOV_B32 vDst(VGPR82) src0(VGPR105) # OpStore: : sdRect(vf2;vf2; >> param377 V_MOV_B32 vDst(VGPR83) src0(VGPR106) # 378: OpFunctionCall: Float: opU(f1;f1;(param376, param377) S_ADD_U32 sDst(SGPR81) src0(LITERAL_CONST) src1(0) const: 0x52 # VGPR327 S_ADD_U32 sDst(SGPR82) src0(LITERAL_CONST) src1(0) const: 0x53 # VGPR328 S_MOV_B64 sDst(SGPR100) src0(EXEC) S_MOV_B32 sDst(SGPR80) src0(LITERAL_CONST) const: 0x6b # VGPR400 # Indirect branch to opU(f1;f1;: -772 S_GETPC_B64 sDst(SGPR78) src0(SGPR78) S_SUB_U32 sDst(SGPR78) src0(SGPR78) src1(LITERAL_CONST) const: 0x304 S_SUBB_U32 sDst(SGPR79) src0(SGPR79) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR78) src0(SGPR78) S_MOV_B64 sDst(EXEC) src0(SGPR100) # .lbl15 # 380: OpLoad: Float: tmp380 << d # OpStore: : tmp380 >> param379 V_MOV_B32 vDst(VGPR84) src0(VGPR74) # OpStore: : opU(f1;f1; >> param381 V_MOV_B32 vDst(VGPR85) src0(VGPR107) # 383: OpFunctionCall: Float: opS(f1;f1;(param379, param381) S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x54 # VGPR329 S_ADD_U32 sDst(SGPR87) src0(LITERAL_CONST) src1(0) const: 0x55 # VGPR330 S_MOV_B64 sDst(SGPR102) src0(EXEC) S_MOV_B32 sDst(SGPR83) src0(LITERAL_CONST) const: 0x6c # VGPR401 # Indirect branch to opS(f1;f1;: -792 S_GETPC_B64 sDst(SGPR84) src0(SGPR84) S_SUB_U32 sDst(SGPR84) src0(SGPR84) src1(LITERAL_CONST) const: 0x318 S_SUBB_U32 sDst(SGPR85) src0(SGPR85) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR84) src0(SGPR84) S_MOV_B64 sDst(EXEC) src0(SGPR102) # .lbl16 # OpStore: : opS(f1;f1; >> d V_MOV_B32 vDst(VGPR74) src0(VGPR108) # 384: OpLoad: FloatVector3: tmp384 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 385: OpVectorShuffle: FloatVector2: tmp385 << tmp384, tmp384, 0, 1 V_MOV_B32 vDst(VGPR257) src0(VGPR254) V_MOV_B32 vDst(VGPR258) src0(VGPR255) # 388: OpFSub: FloatVector2: tmp388 << tmp385, const387 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x3eb33333 V_SUB_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR254) // VOP2 V_SUB_F32 vDst(VGPR260) src0(VGPR258) src1(VGPR255) // VOP2 # OpStore: : tmp388 >> param392 V_MOV_B32 vDst(VGPR86) src0(VGPR259) V_MOV_B32 vDst(VGPR87) src0(VGPR260) # OpStore: : const391 >> param393 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x3ee66666 S_MOV_B32 sDst(SGPR213) src0(LITERAL_CONST) const: 0x3e99999a V_MOV_B32 vDst(VGPR88) src0(SGPR212) V_MOV_B32 vDst(VGPR89) src0(SGPR213) # 394: OpFunctionCall: Float: sdRect(vf2;vf2;(param392, param393) S_ADD_U32 sDst(SGPR71) src0(LITERAL_CONST) src1(0) const: 0x56 # VGPR[331:332] S_ADD_U32 sDst(SGPR72) src0(LITERAL_CONST) src1(0) const: 0x58 # VGPR[333:334] S_MOV_B64 sDst(SGPR104) src0(EXEC) S_MOV_B32 sDst(SGPR70) src0(LITERAL_CONST) const: 0x6d # VGPR413 # Indirect branch to sdRect(vf2;vf2;: -1232 S_GETPC_B64 sDst(SGPR68) src0(SGPR68) S_SUB_U32 sDst(SGPR68) src0(SGPR68) src1(LITERAL_CONST) const: 0x4d0 S_SUBB_U32 sDst(SGPR69) src0(SGPR69) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR68) src0(SGPR68) S_MOV_B64 sDst(EXEC) src0(SGPR104) # .lbl17 # 396: OpLoad: Float: tmp396 << d # OpStore: : tmp396 >> param395 V_MOV_B32 vDst(VGPR90) src0(VGPR74) # OpStore: : sdRect(vf2;vf2; >> param397 V_MOV_B32 vDst(VGPR91) src0(VGPR109) # 398: OpFunctionCall: Float: opS(f1;f1;(param395, param397) S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x5a # VGPR335 S_ADD_U32 sDst(SGPR87) src0(LITERAL_CONST) src1(0) const: 0x5b # VGPR336 S_MOV_B64 sDst(SGPR106) src0(EXEC) S_MOV_B32 sDst(SGPR83) src0(LITERAL_CONST) const: 0x6e # VGPR414 # Indirect branch to opS(f1;f1;: -1000 S_GETPC_B64 sDst(SGPR84) src0(SGPR84) S_SUB_U32 sDst(SGPR84) src0(SGPR84) src1(LITERAL_CONST) const: 0x3e8 S_SUBB_U32 sDst(SGPR85) src0(SGPR85) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR84) src0(SGPR84) S_MOV_B64 sDst(EXEC) src0(SGPR106) # .lbl18 # OpStore: : opS(f1;f1; >> d V_MOV_B32 vDst(VGPR74) src0(VGPR110) # 399: OpLoad: FloatVector3: tmp399 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 400: OpVectorShuffle: FloatVector2: tmp400 << tmp399, tmp399, 0, 2 V_MOV_B32 vDst(VGPR257) src0(VGPR254) V_MOV_B32 vDst(VGPR258) src0(VGPR256) # 402: OpFSub: FloatVector2: tmp402 << tmp400, const401 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3eb33333 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x00000000 V_SUB_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR254) // VOP2 V_SUB_F32 vDst(VGPR260) src0(VGPR258) src1(VGPR255) // VOP2 # OpStore: : tmp402 >> param404 V_MOV_B32 vDst(VGPR92) src0(VGPR259) V_MOV_B32 vDst(VGPR93) src0(VGPR260) # OpStore: : const403 >> param405 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x3d99999a V_MOV_B32 vDst(VGPR94) src0(SGPR212) # 406: OpFunctionCall: Float: sdCircle(vf2;f1;(param404, param405) S_ADD_U32 sDst(SGPR76) src0(LITERAL_CONST) src1(0) const: 0x5c # VGPR[337:338] S_ADD_U32 sDst(SGPR77) src0(LITERAL_CONST) src1(0) const: 0x5e # VGPR339 S_MOV_B64 sDst(SGPR108) src0(EXEC) S_MOV_B32 sDst(SGPR73) src0(LITERAL_CONST) const: 0x6f # VGPR425 # Indirect branch to sdCircle(vf2;f1;: -1236 S_GETPC_B64 sDst(SGPR74) src0(SGPR74) S_SUB_U32 sDst(SGPR74) src0(SGPR74) src1(LITERAL_CONST) const: 0x4d4 S_SUBB_U32 sDst(SGPR75) src0(SGPR75) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR74) src0(SGPR74) S_MOV_B64 sDst(EXEC) src0(SGPR108) # .lbl19 # 408: OpLoad: Float: tmp408 << d # OpStore: : tmp408 >> param407 V_MOV_B32 vDst(VGPR95) src0(VGPR74) # OpStore: : sdCircle(vf2;f1; >> param409 V_MOV_B32 vDst(VGPR96) src0(VGPR111) # 410: OpFunctionCall: Float: opU(f1;f1;(param407, param409) S_ADD_U32 sDst(SGPR81) src0(LITERAL_CONST) src1(0) const: 0x5f # VGPR340 S_ADD_U32 sDst(SGPR82) src0(LITERAL_CONST) src1(0) const: 0x60 # VGPR341 S_MOV_B64 sDst(SGPR110) src0(EXEC) S_MOV_B32 sDst(SGPR80) src0(LITERAL_CONST) const: 0x70 # VGPR426 # Indirect branch to opU(f1;f1;: -1240 S_GETPC_B64 sDst(SGPR78) src0(SGPR78) S_SUB_U32 sDst(SGPR78) src0(SGPR78) src1(LITERAL_CONST) const: 0x4d8 S_SUBB_U32 sDst(SGPR79) src0(SGPR79) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR78) src0(SGPR78) S_MOV_B64 sDst(EXEC) src0(SGPR110) # .lbl20 # OpStore: : opU(f1;f1; >> d V_MOV_B32 vDst(VGPR74) src0(VGPR112) # 411: OpAccessChain: Float*: p[2] # 412: OpLoad: Float: tmp412 << p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR2) # 413: OpExtInst(FAbs): Float: tmp413 << tmp412 V_ADD_F32 vDst(VGPR255) src0(VGPR254) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 414: OpAccessChain: Float*: p[2] # OpStore: : tmp413 >> p[2] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELD_B32 vDst(VGPR2) src0(VGPR255) # 415: OpLoad: FloatVector3: tmp415 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR258) src0(VGPR2) # 416: OpVectorShuffle: FloatVector2: tmp416 << tmp415, tmp415, 1, 2 V_MOV_B32 vDst(VGPR254) src0(VGPR257) V_MOV_B32 vDst(VGPR255) src0(VGPR258) # 419: OpFSub: FloatVector2: tmp419 << tmp416, const418 V_MOV_B32 vDst(VGPR256) src0(LITERAL_CONST) const: 0x3f19999a V_MOV_B32 vDst(VGPR257) src0(0_5_F) V_SUB_F32 vDst(VGPR258) src0(VGPR254) src1(VGPR256) // VOP2 V_SUB_F32 vDst(VGPR259) src0(VGPR255) src1(VGPR257) // VOP2 # OpStore: : tmp419 >> param422 V_MOV_B32 vDst(VGPR97) src0(VGPR258) V_MOV_B32 vDst(VGPR98) src0(VGPR259) # OpStore: : const421 >> param423 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x3f19999a S_MOV_B32 sDst(SGPR213) src0(LITERAL_CONST) const: 0x3ecccccd V_MOV_B32 vDst(VGPR99) src0(SGPR212) V_MOV_B32 vDst(VGPR100) src0(SGPR213) # 424: OpFunctionCall: Float: sdRect(vf2;vf2;(param422, param423) S_ADD_U32 sDst(SGPR71) src0(LITERAL_CONST) src1(0) const: 0x61 # VGPR[342:343] S_ADD_U32 sDst(SGPR72) src0(LITERAL_CONST) src1(0) const: 0x63 # VGPR[344:345] S_MOV_B64 sDst(SGPR112) src0(EXEC) S_MOV_B32 sDst(SGPR70) src0(LITERAL_CONST) const: 0x71 # VGPR440 # Indirect branch to sdRect(vf2;vf2;: -1664 S_GETPC_B64 sDst(SGPR68) src0(SGPR68) S_SUB_U32 sDst(SGPR68) src0(SGPR68) src1(LITERAL_CONST) const: 0x680 S_SUBB_U32 sDst(SGPR69) src0(SGPR69) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR68) src0(SGPR68) S_MOV_B64 sDst(EXEC) src0(SGPR112) # .lbl21 # 426: OpLoad: Float: tmp426 << d # OpStore: : tmp426 >> param425 V_MOV_B32 vDst(VGPR101) src0(VGPR74) # OpStore: : sdRect(vf2;vf2; >> param427 V_MOV_B32 vDst(VGPR102) src0(VGPR113) # 428: OpFunctionCall: Float: opS(f1;f1;(param425, param427) S_ADD_U32 sDst(SGPR86) src0(LITERAL_CONST) src1(0) const: 0x65 # VGPR346 S_ADD_U32 sDst(SGPR87) src0(LITERAL_CONST) src1(0) const: 0x66 # VGPR347 S_MOV_B64 sDst(SGPR114) src0(EXEC) S_MOV_B32 sDst(SGPR83) src0(LITERAL_CONST) const: 0x72 # VGPR441 # Indirect branch to opS(f1;f1;: -1432 S_GETPC_B64 sDst(SGPR84) src0(SGPR84) S_SUB_U32 sDst(SGPR84) src0(SGPR84) src1(LITERAL_CONST) const: 0x598 S_SUBB_U32 sDst(SGPR85) src0(SGPR85) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR84) src0(SGPR84) S_MOV_B64 sDst(EXEC) src0(SGPR114) # .lbl22 # OpStore: : opS(f1;f1; >> d V_MOV_B32 vDst(VGPR74) src0(VGPR114) # 429: OpAccessChain: Float*: p[1] # 430: OpLoad: Float: tmp430 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR91) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR1) # 431: OpFSub: Float: tmp431 << tmp430, const275 V_MOV_B32 vDst(VGPR255) src0(0_5_F) V_SUB_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # 432: OpExtInst(FAbs): Float: tmp432 << tmp431 V_ADD_F32 vDst(VGPR254) src0(VGPR256) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 433: OpFNegate: Float: tmp433 << tmp432 V_MUL_F32 vDst(VGPR255) src0(M1_0_F) src1(VGPR254) // VOP2 # 435: OpFAdd: Float: tmp435 << tmp433, const434 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3f4ccccd V_ADD_F32 vDst(VGPR256) src0(VGPR255) src1(VGPR254) // VOP2 # 437: OpLoad: Float: tmp437 << d # OpStore: : tmp437 >> param436 V_MOV_B32 vDst(VGPR103) src0(VGPR74) # OpStore: : tmp435 >> param438 V_MOV_B32 vDst(VGPR104) src0(VGPR256) # 439: OpFunctionCall: Float: opU(f1;f1;(param436, param438) S_ADD_U32 sDst(SGPR81) src0(LITERAL_CONST) src1(0) const: 0x67 # VGPR348 S_ADD_U32 sDst(SGPR82) src0(LITERAL_CONST) src1(0) const: 0x68 # VGPR349 S_MOV_B64 sDst(SGPR116) src0(EXEC) S_MOV_B32 sDst(SGPR80) src0(LITERAL_CONST) const: 0x73 # VGPR449 # Indirect branch to opU(f1;f1;: -1588 S_GETPC_B64 sDst(SGPR78) src0(SGPR78) S_SUB_U32 sDst(SGPR78) src0(SGPR78) src1(LITERAL_CONST) const: 0x634 S_SUBB_U32 sDst(SGPR79) src0(SGPR79) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR78) src0(SGPR78) S_MOV_B64 sDst(EXEC) src0(SGPR116) # .lbl23 # OpStore: : opU(f1;f1; >> d V_MOV_B32 vDst(VGPR74) src0(VGPR115) # 440: OpLoad: Float: tmp440 << d # OpReturnValue: : << tmp440 S_MOV_B32 sDst(M0) src0(SGPR90) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR74) S_SETPC_B64 sDst(SGPR88) src0(SGPR88) # Float trace(vf3;vf3;f1;f1;(FloatVector3* ro, FloatVector3* rd, Float* maxDist, Float* steps) Function: Float trace(vf3;vf3;f1;f1;(, FloatVector3 map(vf3;.rd, Float map(vf3;.maxDist, Float map(vf3;.steps) S_MOV_B64 sDst(SGPR126) src0(EXEC) # lb65 Label: lb65 # OpStore: : const92 >> total S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR116) src0(SGPR212) # OpStore: : const92 >> steps S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(SGPR212) # OpStore: : const210 >> i S_MOV_B32 sDst(SGPR211) src0(0) # OpBranch: to lb445 # lb445 Label: lb445 # OpLoopMerge: (merge: lb447, continue: lb448) # CF Block: Merge: lb447, Continue: lb448 S_MOV_B64 sDst(SGPR128) src0(EXEC) S_MOV_B64 sDst(SGPR130) src0(EXEC) S_MOV_B64 sDst(SGPR132) src0(EXEC) Label: lb445Loop # OpBranch: to lb449 # lb449 Label: lb449 # 450: OpLoad: Int: tmp450 << i Decorators: RelaxedPrecision # 452: OpSLessThan: Bool: tmp452 << tmp450, const451 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x00000064 V_CMP_LT_I32 dst(SGPR212) src0(SGPR211) src1(VGPR254) // VOP3a # OpBranchConditional: if(tmp452) then branch to lb446, else branch to lb447 # CF Block: Cond Branch: true: lb446, false: lb447 S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 66 lb447 # lb446 Label: lb446 S_MOV_B64 sDst(SGPR130) src0(EXEC) S_MOV_B64 sDst(SGPR132) src0(EXEC) # 453: OpLoad: Float: tmp453 << steps S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 454: OpFAdd: Float: tmp454 << tmp453, const117 V_MOV_B32 vDst(VGPR255) src0(1_0_F) V_ADD_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # OpStore: : tmp454 >> steps S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR124) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR256) # 456: OpLoad: FloatVector3: tmp456 << ro S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR121) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 457: OpLoad: FloatVector3: tmp457 << rd S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR122) const: 0x0 V_MOVRELS_B32 vDst(VGPR257) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR258) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR259) src0(VGPR2) # 458: OpLoad: Float: tmp458 << total # 459: OpVectorTimesScalar: FloatVector3: tmp459 << tmp457, tmp458 V_MUL_F32 vDst(VGPR260) src0(VGPR116) src1(VGPR257) // VOP2 V_MUL_F32 vDst(VGPR261) src0(VGPR116) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR262) src0(VGPR116) src1(VGPR259) // VOP2 # 460: OpFAdd: FloatVector3: tmp460 << tmp456, tmp459 V_ADD_F32 vDst(VGPR257) src0(VGPR254) src1(VGPR260) // VOP2 V_ADD_F32 vDst(VGPR258) src0(VGPR255) src1(VGPR261) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR256) src1(VGPR262) // VOP2 # OpStore: : tmp460 >> param461 V_MOV_B32 vDst(VGPR117) src0(VGPR257) V_MOV_B32 vDst(VGPR118) src0(VGPR258) V_MOV_B32 vDst(VGPR119) src0(VGPR259) # 462: OpFunctionCall: Float: map(vf3;(param461) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x75 # VGPR[452:454] S_MOV_B64 sDst(SGPR134) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x78 # VGPR473 # Indirect branch to map(vf3;: -1752 S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_SUB_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x6d8 S_SUBB_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR134) # .lbl24 # 464: OpLoad: Float: tmp464 << total # 465: OpFAdd: Float: tmp465 << tmp464, map(vf3; V_ADD_F32 vDst(VGPR254) src0(VGPR116) src1(VGPR120) // VOP2 # OpStore: : tmp465 >> total V_MOV_B32 vDst(VGPR116) src0(VGPR254) # 468: OpFOrdLessThan: Bool: tmp468 << map(vf3;, const467 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3727c5ac V_CMP_LT_F32 dst(SGPR212) src0(VGPR120) src1(VGPR254) // VOP3a # 469: OpLoad: Float: tmp469 << maxDist S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR123) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 470: OpLoad: Float: tmp470 << total # 471: OpFOrdLessThan: Bool: tmp471 << tmp469, tmp470 V_CMP_LT_F32 dst(SGPR214) src0(VGPR254) src1(VGPR116) // VOP3a # 472: OpLogicalOr: Bool: tmp472 << tmp468, tmp471 S_OR_B64 sDst(SGPR216) src0(SGPR212) src1(SGPR214) # OpSelectionMerge: (merge: lb474) # CF Block: Merge: lb474 S_MOV_B64 sDst(SGPR212) src0(EXEC) # OpBranchConditional: if(tmp472) then branch to lb473, else branch to lb474 # CF Block: Cond Branch: true: lb473, false: lb474 S_AND_B64 sDst(EXEC) src0(SGPR216) src1(EXEC) S_CBRANCH_EXECZ 3 lb474 # lb473 Label: lb473 # OpBranch: to lb447 S_ANDN2_B64 sDst(SGPR130) src0(SGPR130) src1(EXEC) S_ANDN2_B64 sDst(SGPR132) src0(SGPR132) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR132) src1(EXEC) # lb474 Label: lb474 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR212) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR132) # OpBranch: to lb448 # lb448 Label: lb448 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR130) # 476: OpLoad: Int: tmp476 << i Decorators: RelaxedPrecision # 477: OpIAdd: Int: tmp477 << tmp476, const234 Decorators: RelaxedPrecision S_MOV_B32 sDst(SGPR212) src0(1_INT) S_ADD_I32 sDst(SGPR213) src0(SGPR211) src1(SGPR212) # OpStore: : tmp477 >> i S_MOV_B32 sDst(SGPR211) src0(SGPR213) # OpBranch: to lb445 S_BRANCH -72 lb445Loop # lb447 Label: lb447 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR128) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR126) # 478: OpLoad: Float: tmp478 << total # OpReturnValue: : << tmp478 S_MOV_B32 sDst(M0) src0(SGPR120) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR116) S_SETPC_B64 sDst(SGPR118) src0(SGPR118) # FloatVector3 getNormal(vf3;(FloatVector3* p) Function: FloatVector3 getNormal(vf3;() S_MOV_B64 sDst(SGPR214) src0(EXEC) # lb69 Label: lb69 # 484: OpLoad: FloatVector3: tmp484 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR138) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 486: OpVectorShuffle: FloatVector3: tmp486 << const483, const483, 0, 1, 1 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x38d1b717 S_MOV_B32 sDst(SGPR213) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR257) src0(SGPR212) V_MOV_B32 vDst(VGPR258) src0(SGPR213) V_MOV_B32 vDst(VGPR259) src0(SGPR213) # 487: OpFAdd: FloatVector3: tmp487 << tmp484, tmp486 V_ADD_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_ADD_F32 vDst(VGPR261) src0(VGPR255) src1(VGPR258) // VOP2 V_ADD_F32 vDst(VGPR262) src0(VGPR256) src1(VGPR259) // VOP2 # OpStore: : tmp487 >> param488 V_MOV_B32 vDst(VGPR121) src0(VGPR260) V_MOV_B32 vDst(VGPR122) src0(VGPR261) V_MOV_B32 vDst(VGPR123) src0(VGPR262) # 489: OpFunctionCall: Float: map(vf3;(param488) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x79 # VGPR[479:481] S_MOV_B64 sDst(SGPR140) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x8b # VGPR508 # Indirect branch to map(vf3;: -1996 S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_SUB_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x7cc S_SUBB_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR140) # .lbl25 # 490: OpLoad: FloatVector3: tmp490 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR138) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 492: OpVectorShuffle: FloatVector3: tmp492 << const483, const483, 0, 1, 1 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x38d1b717 S_MOV_B32 sDst(SGPR213) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR257) src0(SGPR212) V_MOV_B32 vDst(VGPR258) src0(SGPR213) V_MOV_B32 vDst(VGPR259) src0(SGPR213) # 493: OpFSub: FloatVector3: tmp493 << tmp490, tmp492 V_SUB_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_SUB_F32 vDst(VGPR261) src0(VGPR255) src1(VGPR258) // VOP2 V_SUB_F32 vDst(VGPR262) src0(VGPR256) src1(VGPR259) // VOP2 # OpStore: : tmp493 >> param494 V_MOV_B32 vDst(VGPR124) src0(VGPR260) V_MOV_B32 vDst(VGPR125) src0(VGPR261) V_MOV_B32 vDst(VGPR126) src0(VGPR262) # 495: OpFunctionCall: Float: map(vf3;(param494) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x7c # VGPR[482:484] S_MOV_B64 sDst(SGPR142) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x8c # VGPR520 # Indirect branch to map(vf3;: -2116 S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_SUB_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x844 S_SUBB_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR142) # .lbl26 # 496: OpFSub: Float: tmp496 << map(vf3;, map(vf3; V_SUB_F32 vDst(VGPR141) src0(VGPR139) src1(VGPR140) // VOP2 # 497: OpLoad: FloatVector3: tmp497 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR138) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 499: OpVectorShuffle: FloatVector3: tmp499 << const483, const483, 1, 0, 1 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x38d1b717 S_MOV_B32 sDst(SGPR213) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR257) src0(SGPR213) V_MOV_B32 vDst(VGPR258) src0(SGPR212) V_MOV_B32 vDst(VGPR259) src0(SGPR213) # 500: OpFAdd: FloatVector3: tmp500 << tmp497, tmp499 V_ADD_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_ADD_F32 vDst(VGPR261) src0(VGPR255) src1(VGPR258) // VOP2 V_ADD_F32 vDst(VGPR262) src0(VGPR256) src1(VGPR259) // VOP2 # OpStore: : tmp500 >> param501 V_MOV_B32 vDst(VGPR127) src0(VGPR260) V_MOV_B32 vDst(VGPR128) src0(VGPR261) V_MOV_B32 vDst(VGPR129) src0(VGPR262) # 502: OpFunctionCall: Float: map(vf3;(param501) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x7f # VGPR[485:487] S_MOV_B64 sDst(SGPR144) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x8e # VGPR533 # Indirect branch to map(vf3;: -2240 S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_SUB_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x8c0 S_SUBB_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR144) # .lbl27 # 503: OpLoad: FloatVector3: tmp503 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR138) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 505: OpVectorShuffle: FloatVector3: tmp505 << const483, const483, 1, 0, 1 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x38d1b717 S_MOV_B32 sDst(SGPR213) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR257) src0(SGPR213) V_MOV_B32 vDst(VGPR258) src0(SGPR212) V_MOV_B32 vDst(VGPR259) src0(SGPR213) # 506: OpFSub: FloatVector3: tmp506 << tmp503, tmp505 V_SUB_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_SUB_F32 vDst(VGPR261) src0(VGPR255) src1(VGPR258) // VOP2 V_SUB_F32 vDst(VGPR262) src0(VGPR256) src1(VGPR259) // VOP2 # OpStore: : tmp506 >> param507 V_MOV_B32 vDst(VGPR130) src0(VGPR260) V_MOV_B32 vDst(VGPR131) src0(VGPR261) V_MOV_B32 vDst(VGPR132) src0(VGPR262) # 508: OpFunctionCall: Float: map(vf3;(param507) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x82 # VGPR[488:490] S_MOV_B64 sDst(SGPR146) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x8f # VGPR545 # Indirect branch to map(vf3;: -2360 S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_SUB_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x938 S_SUBB_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR146) # .lbl28 # 509: OpFSub: Float: tmp509 << map(vf3;, map(vf3; V_SUB_F32 vDst(VGPR144) src0(VGPR142) src1(VGPR143) // VOP2 # 510: OpLoad: FloatVector3: tmp510 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR138) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 512: OpVectorShuffle: FloatVector3: tmp512 << const483, const483, 1, 1, 0 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x38d1b717 S_MOV_B32 sDst(SGPR213) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR257) src0(SGPR213) V_MOV_B32 vDst(VGPR258) src0(SGPR213) V_MOV_B32 vDst(VGPR259) src0(SGPR212) # 513: OpFAdd: FloatVector3: tmp513 << tmp510, tmp512 V_ADD_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_ADD_F32 vDst(VGPR261) src0(VGPR255) src1(VGPR258) // VOP2 V_ADD_F32 vDst(VGPR262) src0(VGPR256) src1(VGPR259) // VOP2 # OpStore: : tmp513 >> param514 V_MOV_B32 vDst(VGPR133) src0(VGPR260) V_MOV_B32 vDst(VGPR134) src0(VGPR261) V_MOV_B32 vDst(VGPR135) src0(VGPR262) # 515: OpFunctionCall: Float: map(vf3;(param514) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x85 # VGPR[491:493] S_MOV_B64 sDst(SGPR148) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x91 # VGPR558 # Indirect branch to map(vf3;: -2484 S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_SUB_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0x9b4 S_SUBB_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR148) # .lbl29 # 516: OpLoad: FloatVector3: tmp516 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR138) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 518: OpVectorShuffle: FloatVector3: tmp518 << const483, const483, 1, 1, 0 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x38d1b717 S_MOV_B32 sDst(SGPR213) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR257) src0(SGPR213) V_MOV_B32 vDst(VGPR258) src0(SGPR213) V_MOV_B32 vDst(VGPR259) src0(SGPR212) # 519: OpFSub: FloatVector3: tmp519 << tmp516, tmp518 V_SUB_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_SUB_F32 vDst(VGPR261) src0(VGPR255) src1(VGPR258) // VOP2 V_SUB_F32 vDst(VGPR262) src0(VGPR256) src1(VGPR259) // VOP2 # OpStore: : tmp519 >> param520 V_MOV_B32 vDst(VGPR136) src0(VGPR260) V_MOV_B32 vDst(VGPR137) src0(VGPR261) V_MOV_B32 vDst(VGPR138) src0(VGPR262) # 521: OpFunctionCall: Float: map(vf3;(param520) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x88 # VGPR[494:496] S_MOV_B64 sDst(SGPR150) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x92 # VGPR570 # Indirect branch to map(vf3;: -2604 S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_SUB_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0xa2c S_SUBB_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR150) # .lbl30 # 522: OpFSub: Float: tmp522 << map(vf3;, map(vf3; V_SUB_F32 vDst(VGPR254) src0(VGPR145) src1(VGPR146) // VOP2 # 523: OpCompositeConstruct: FloatVector3: tmp523 << tmp496, tmp509, tmp522 V_MOV_B32 vDst(VGPR255) src0(VGPR141) V_MOV_B32 vDst(VGPR256) src0(VGPR144) V_MOV_B32 vDst(VGPR257) src0(VGPR254) # 524: OpExtInst(Normalize): FloatVector3: tmp524 << tmp523 V_MUL_F32 vDst(VGPR254) src0(VGPR255) src1(VGPR255) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR256) src1(VGPR256) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR257) src1(VGPR257) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR254) src0(VGPR254) V_MUL_F32 vDst(VGPR258) src0(VGPR255) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR259) src0(VGPR256) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR260) src0(VGPR257) src1(VGPR254) // VOP2 # OpReturnValue: : << tmp524 S_MOV_B32 sDst(M0) src0(SGPR125) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR258) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR259) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR260) S_SETPC_B64 sDst(SGPR136) src0(SGPR136) # Float calculateAO(vf3;vf3;(FloatVector3* p, FloatVector3* n) Function: Float calculateAO(vf3;vf3;(, FloatVector3 getNormal(vf3;.n) S_MOV_B64 sDst(SGPR156) src0(EXEC) # lb74 Label: lb74 # OpStore: : const92 >> r S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR147) src0(SGPR212) # OpStore: : const117 >> w V_MOV_B32 vDst(VGPR148) src0(1_0_F) # OpStore: : const117 >> i V_MOV_B32 vDst(VGPR149) src0(1_0_F) # OpBranch: to lb530 # lb530 Label: lb530 # OpLoopMerge: (merge: lb532, continue: lb533) # CF Block: Merge: lb532, Continue: lb533 S_MOV_B64 sDst(SGPR158) src0(EXEC) S_MOV_B64 sDst(SGPR160) src0(EXEC) S_MOV_B64 sDst(SGPR162) src0(EXEC) Label: lb530Loop # OpBranch: to lb534 # lb534 Label: lb534 # 535: OpLoad: Float: tmp535 << i # 537: OpFOrdLessThanEqual: Bool: tmp537 << tmp535, const536 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x40a00000 V_CMP_LE_F32 dst(SGPR212) src0(VGPR149) src1(VGPR254) // VOP3a # OpBranchConditional: if(tmp537) then branch to lb531, else branch to lb532 # CF Block: Cond Branch: true: lb531, false: lb532 S_AND_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_CBRANCH_EXECZ 57 lb532 # lb531 Label: lb531 S_MOV_B64 sDst(SGPR160) src0(EXEC) S_MOV_B64 sDst(SGPR162) src0(EXEC) # 539: OpLoad: Float: tmp539 << i # 540: OpFDiv: Float: tmp540 << tmp539, const536 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x40a00000 V_RCP_F32 vDst(VGPR255) src0(VGPR254) V_MUL_F32 vDst(VGPR255) src0(VGPR149) src1(VGPR255) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR255) src0(VGPR255) src1(VGPR254) src2(VGPR149) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 541: OpFDiv: Float: tmp541 << tmp540, const220 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x41200000 V_RCP_F32 vDst(VGPR153) src0(VGPR254) V_MUL_F32 vDst(VGPR153) src0(VGPR255) src1(VGPR153) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR153) src0(VGPR153) src1(VGPR254) src2(VGPR255) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 542: OpLoad: Float: tmp542 << w # 544: OpLoad: FloatVector3: tmp544 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR154) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR258) src0(VGPR2) # 545: OpLoad: FloatVector3: tmp545 << n S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR155) const: 0x0 V_MOVRELS_B32 vDst(VGPR259) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR260) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR261) src0(VGPR2) # 547: OpVectorTimesScalar: FloatVector3: tmp547 << tmp545, tmp541 V_MUL_F32 vDst(VGPR262) src0(VGPR153) src1(VGPR259) // VOP2 V_MUL_F32 vDst(VGPR263) src0(VGPR153) src1(VGPR260) // VOP2 V_MUL_F32 vDst(VGPR264) src0(VGPR153) src1(VGPR261) // VOP2 # 548: OpFAdd: FloatVector3: tmp548 << tmp544, tmp547 V_ADD_F32 vDst(VGPR259) src0(VGPR256) src1(VGPR262) // VOP2 V_ADD_F32 vDst(VGPR260) src0(VGPR257) src1(VGPR263) // VOP2 V_ADD_F32 vDst(VGPR261) src0(VGPR258) src1(VGPR264) // VOP2 # OpStore: : tmp548 >> param549 V_MOV_B32 vDst(VGPR150) src0(VGPR259) V_MOV_B32 vDst(VGPR151) src0(VGPR260) V_MOV_B32 vDst(VGPR152) src0(VGPR261) # 550: OpFunctionCall: Float: map(vf3;(param549) S_ADD_U32 sDst(SGPR91) src0(LITERAL_CONST) src1(0) const: 0x96 # VGPR[582:584] S_MOV_B64 sDst(SGPR164) src0(EXEC) S_MOV_B32 sDst(SGPR90) src0(LITERAL_CONST) const: 0x9a # VGPR603 # Indirect branch to map(vf3;: -2908 S_GETPC_B64 sDst(SGPR88) src0(SGPR88) S_SUB_U32 sDst(SGPR88) src0(SGPR88) src1(LITERAL_CONST) const: 0xb5c S_SUBB_U32 sDst(SGPR89) src0(SGPR89) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR88) src0(SGPR88) S_MOV_B64 sDst(EXEC) src0(SGPR164) # .lbl31 # 551: OpFSub: Float: tmp551 << tmp541, map(vf3; V_SUB_F32 vDst(VGPR254) src0(VGPR153) src1(VGPR154) // VOP2 # 552: OpFMul: Float: tmp552 << tmp542, tmp551 V_MUL_F32 vDst(VGPR255) src0(VGPR148) src1(VGPR254) // VOP2 # 553: OpLoad: Float: tmp553 << r # 554: OpFAdd: Float: tmp554 << tmp553, tmp552 V_ADD_F32 vDst(VGPR254) src0(VGPR147) src1(VGPR255) // VOP2 # OpStore: : tmp554 >> r V_MOV_B32 vDst(VGPR147) src0(VGPR254) # 555: OpLoad: Float: tmp555 << w # 556: OpFMul: Float: tmp556 << tmp555, const275 V_MOV_B32 vDst(VGPR254) src0(0_5_F) V_MUL_F32 vDst(VGPR255) src0(VGPR148) src1(VGPR254) // VOP2 # OpStore: : tmp556 >> w V_MOV_B32 vDst(VGPR148) src0(VGPR255) # OpBranch: to lb533 # lb533 Label: lb533 # CF Continue Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR160) # 557: OpLoad: Float: tmp557 << i # 558: OpFAdd: Float: tmp558 << tmp557, const117 V_MOV_B32 vDst(VGPR254) src0(1_0_F) V_ADD_F32 vDst(VGPR255) src0(VGPR149) src1(VGPR254) // VOP2 # OpStore: : tmp558 >> i V_MOV_B32 vDst(VGPR149) src0(VGPR255) # OpBranch: to lb530 S_BRANCH -63 lb530Loop # lb532 Label: lb532 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR158) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR156) # 559: OpLoad: Float: tmp559 << r # 560: OpFMul: Float: tmp560 << tmp559, const220 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR255) src0(VGPR147) src1(VGPR254) // VOP2 # 561: OpExtInst(FClamp): Float: tmp561 << tmp560, const92, const117 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR256) src0(1_0_F) V_MAX_F32 vDst(VGPR257) src0(VGPR255) src1(VGPR254) // VOP2 V_MIN_F32 vDst(VGPR257) src0(VGPR257) src1(VGPR256) // VOP2 # 562: OpFSub: Float: tmp562 << const117, tmp561 V_SUB_F32 vDst(VGPR254) src0(1_0_F) src1(VGPR257) // VOP2 # OpReturnValue: : << tmp562 S_MOV_B32 sDst(M0) src0(SGPR139) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR254) S_SETPC_B64 sDst(SGPR152) src0(SGPR152) # Bool isWall(vf3;(FloatVector3* p) Function: Bool isWall(vf3;() S_MOV_B64 sDst(SGPR212) src0(EXEC) # lb79 Label: lb79 # 565: OpAccessChain: Float*: p[0] # 566: OpLoad: Float: tmp566 << p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) # 567: OpFAdd: Float: tmp567 << tmp566, const386 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x3eb33333 V_ADD_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # 568: OpAccessChain: Float*: p[0] # OpStore: : tmp567 >> p[0] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR256) # 570: OpLoad: FloatVector3: tmp570 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 571: OpVectorShuffle: FloatVector2: tmp571 << tmp570, tmp570, 0, 2 V_MOV_B32 vDst(VGPR257) src0(VGPR254) V_MOV_B32 vDst(VGPR258) src0(VGPR256) # OpStore: : tmp571 >> param569 V_MOV_B32 vDst(VGPR155) src0(VGPR257) V_MOV_B32 vDst(VGPR156) src0(VGPR258) # OpStore: : const334 >> param572 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x3f333333 S_MOV_B32 sDst(SGPR213) src0(1_0_F) V_MOV_B32 vDst(VGPR157) src0(SGPR212) V_MOV_B32 vDst(VGPR158) src0(SGPR213) # 573: OpFunctionCall: FloatVector2: tRepeat2(vf2;vf2;(param569, param572) S_ADD_U32 sDst(SGPR66) src0(LITERAL_CONST) src1(0) const: 0x9b # VGPR[617:618] S_ADD_U32 sDst(SGPR67) src0(LITERAL_CONST) src1(0) const: 0x9d # VGPR[619:620] S_MOV_B64 sDst(SGPR170) src0(EXEC) S_MOV_B32 sDst(SGPR61) src0(LITERAL_CONST) const: 0xfe # VGPR[631:632] # Indirect branch to tRepeat2(vf2;vf2;: -3812 S_GETPC_B64 sDst(SGPR64) src0(SGPR64) S_SUB_U32 sDst(SGPR64) src0(SGPR64) src1(LITERAL_CONST) const: 0xee4 S_SUBB_U32 sDst(SGPR65) src0(SGPR65) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR64) src0(SGPR64) S_MOV_B64 sDst(EXEC) src0(SGPR170) # .lbl32 # 574: OpLoad: FloatVector2: tmp574 << param569 # 575: OpLoad: FloatVector3: tmp575 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 576: OpVectorShuffle: FloatVector3: tmp576 << tmp575, tmp574, 3, 1, 4 V_MOV_B32 vDst(VGPR257) src0(VGPR155) V_MOV_B32 vDst(VGPR258) src0(VGPR255) V_MOV_B32 vDst(VGPR259) src0(VGPR156) # OpStore: : tmp576 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR257) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR258) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR259) # 577: OpAccessChain: Float*: p[1] # 578: OpLoad: Float: tmp578 << p[1] S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR1) # 579: OpFAdd: Float: tmp579 << tmp578, const355 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x3e19999a V_ADD_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # 580: OpExtInst(FAbs): Float: tmp580 << tmp579 V_ADD_F32 vDst(VGPR254) src0(VGPR256) src1(0) src2(N/A) abs(1) clamp(0) omod(0) neg(0) // VOP3a # 581: OpLoad: FloatVector3: tmp581 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR169) const: 0x0 V_MOVRELS_B32 vDst(VGPR257) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR258) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR259) src0(VGPR2) # 582: OpVectorShuffle: FloatVector2: tmp582 << tmp581, tmp581, 0, 2 V_MOV_B32 vDst(VGPR255) src0(VGPR257) V_MOV_B32 vDst(VGPR256) src0(VGPR259) # 583: OpExtInst(Length): Float: tmp583 << tmp582 V_MUL_F32 vDst(VGPR257) src0(VGPR255) src1(VGPR255) // VOP2 V_MAC_F32 vDst(VGPR257) src0(VGPR256) src1(VGPR256) // VOP2 V_SQRT_F32 vDst(VGPR257) src0(VGPR257) # 584: OpFAdd: Float: tmp584 << tmp580, tmp583 V_ADD_F32 vDst(VGPR255) src0(VGPR254) src1(VGPR257) // VOP2 # 585: OpFOrdLessThan: Bool: tmp585 << const369, tmp584 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3ec00000 V_CMP_LT_F32 dst(SGPR212) src0(VGPR254) src1(VGPR255) // VOP3a # OpReturnValue: : << tmp585 S_MOV_B32 sDst(M0) src0(SGPR168) V_MOVRELD_B32 vDst(VGPR0) src0(SGPR212) S_SETPC_B64 sDst(SGPR166) src0(SGPR166) # FloatVector3 _texture(vf3;(FloatVector3* p) Function: FloatVector3 _texture(vf3;() S_MOV_B64 sDst(SGPR176) src0(EXEC) # lb82 Label: lb82 # 589: OpLoad: FloatVector3: tmp589 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR175) const: 0x0 V_MOVRELS_B32 vDst(VGPR256) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR258) src0(VGPR2) # OpStore: : tmp589 >> param588 V_MOV_B32 vDst(VGPR159) src0(VGPR256) V_MOV_B32 vDst(VGPR160) src0(VGPR257) V_MOV_B32 vDst(VGPR161) src0(VGPR258) # 591: OpLoad: Float: tmp591 << _twist # OpStore: : tmp591 >> param590 V_MOV_B32 vDst(VGPR162) src0(VGPR20) # 592: OpFunctionCall: Void: tTwist(vf3;f1;(param588, param590) S_ADD_U32 sDst(SGPR57) src0(LITERAL_CONST) src1(0) const: 0x9f # VGPR[651:653] S_ADD_U32 sDst(SGPR60) src0(LITERAL_CONST) src1(0) const: 0xa2 # VGPR654 S_MOV_B64 sDst(SGPR178) src0(EXEC) # Indirect branch to tTwist(vf3;f1;: -4232 S_GETPC_B64 sDst(SGPR58) src0(SGPR58) S_SUB_U32 sDst(SGPR58) src0(SGPR58) src1(LITERAL_CONST) const: 0x1088 S_SUBB_U32 sDst(SGPR59) src0(SGPR59) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR58) src0(SGPR58) S_MOV_B64 sDst(EXEC) src0(SGPR178) # .lbl33 # 593: OpLoad: FloatVector3: tmp593 << param588 # OpStore: : tmp593 >> p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR175) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR159) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR160) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR161) # 597: OpLoad: FloatVector3: tmp597 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR175) const: 0x0 V_MOVRELS_B32 vDst(VGPR259) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR260) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR261) src0(VGPR2) # OpStore: : tmp597 >> param596 V_MOV_B32 vDst(VGPR163) src0(VGPR259) V_MOV_B32 vDst(VGPR164) src0(VGPR260) V_MOV_B32 vDst(VGPR165) src0(VGPR261) # 598: OpFunctionCall: Bool: isWall(vf3;(param596) S_ADD_U32 sDst(SGPR169) src0(LITERAL_CONST) src1(0) const: 0xa3 # VGPR[655:657] S_MOV_B64 sDst(SGPR180) src0(EXEC) S_MOV_B32 sDst(SGPR168) src0(LITERAL_CONST) const: 0xb0 # VGPR677 # Indirect branch to isWall(vf3;: -472 S_GETPC_B64 sDst(SGPR166) src0(SGPR166) S_SUB_U32 sDst(SGPR166) src0(SGPR166) src1(LITERAL_CONST) const: 0x1d8 S_SUBB_U32 sDst(SGPR167) src0(SGPR167) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR166) src0(SGPR166) S_MOV_B64 sDst(EXEC) src0(SGPR180) # .lbl34 # 600: OpLoad: FloatVector3: tmp600 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR175) const: 0x0 V_MOVRELS_B32 vDst(VGPR177) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR178) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR179) src0(VGPR2) # OpSelectionMerge: (merge: lb604) # CF Block: Merge: lb604 S_MOV_B64 sDst(SGPR182) src0(EXEC) # OpBranchConditional: if(isWall(vf3;) then branch to lb603, else branch to lb605 # CF Block: Cond Branch: true: lb603, false: lb605 S_AND_B64 sDst(EXEC) src0(VGPR176) src1(EXEC) S_CBRANCH_EXECZ 3 lb605 # lb603 Label: lb603 # OpStore: : const92 >> var601 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR166) src0(SGPR212) # OpBranch: to lb604 # lb605 Label: lb605 S_ANDN2_B64 sDst(EXEC) src0(SGPR182) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR176) src1(EXEC) S_CBRANCH_EXECZ 32 lb604 # 608: OpLoad: FloatVector3: tmp608 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR175) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 609: OpVectorTimesScalar: FloatVector3: tmp609 << tmp608, const536 V_MOV_B32 vDst(VGPR257) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR258) src0(VGPR257) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR255) // VOP2 V_MUL_F32 vDst(VGPR260) src0(VGPR257) src1(VGPR256) // VOP2 # OpStore: : tmp609 >> param610 V_MOV_B32 vDst(VGPR167) src0(VGPR258) V_MOV_B32 vDst(VGPR168) src0(VGPR259) V_MOV_B32 vDst(VGPR169) src0(VGPR260) # 611: OpFunctionCall: Float: fbm(vf3;(param610) S_ADD_U32 sDst(SGPR42) src0(LITERAL_CONST) src1(0) const: 0xa7 # VGPR[662:664] S_MOV_B64 sDst(SGPR184) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0xb4 # VGPR689 # Indirect branch to fbm(vf3;: -4952 S_GETPC_B64 sDst(SGPR40) src0(SGPR40) S_SUB_U32 sDst(SGPR40) src0(SGPR40) src1(LITERAL_CONST) const: 0x1358 S_SUBB_U32 sDst(SGPR41) src0(SGPR41) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR40) src0(SGPR40) S_MOV_B64 sDst(EXEC) src0(SGPR184) # .lbl35 # 612: OpFMul: Float: tmp612 << const607, fbm(vf3; V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3f666666 V_MUL_F32 vDst(VGPR255) src0(VGPR254) src1(VGPR180) // VOP2 # 613: OpFAdd: Float: tmp613 << const606, tmp612 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3dcccccd V_ADD_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR255) // VOP2 # OpStore: : tmp613 >> var601 V_MOV_B32 vDst(VGPR166) src0(VGPR256) # OpBranch: to lb604 # lb604 Label: lb604 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR182) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR176) # 614: OpLoad: Float: tmp614 << var601 # 615: OpCompositeConstruct: FloatVector3: tmp615 << tmp614, tmp614, tmp614 V_MOV_B32 vDst(VGPR254) src0(VGPR166) V_MOV_B32 vDst(VGPR255) src0(VGPR166) V_MOV_B32 vDst(VGPR256) src0(VGPR166) # 616: OpFAdd: FloatVector3: tmp616 << tmp600, tmp615 V_ADD_F32 vDst(VGPR257) src0(VGPR177) src1(VGPR254) // VOP2 V_ADD_F32 vDst(VGPR258) src0(VGPR178) src1(VGPR255) // VOP2 V_ADD_F32 vDst(VGPR259) src0(VGPR179) src1(VGPR256) // VOP2 # 619: OpFMul: FloatVector3: tmp619 << tmp616, const618 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x40a00000 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x41a00000 V_MOV_B32 vDst(VGPR256) src0(LITERAL_CONST) const: 0x40a00000 V_MUL_F32 vDst(VGPR260) src0(VGPR257) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR261) src0(VGPR258) src1(VGPR255) // VOP2 V_MUL_F32 vDst(VGPR262) src0(VGPR259) src1(VGPR256) // VOP2 # OpStore: : tmp619 >> param620 V_MOV_B32 vDst(VGPR170) src0(VGPR260) V_MOV_B32 vDst(VGPR171) src0(VGPR261) V_MOV_B32 vDst(VGPR172) src0(VGPR262) # 621: OpFunctionCall: Float: fbm(vf3;(param620) S_ADD_U32 sDst(SGPR42) src0(LITERAL_CONST) src1(0) const: 0xaa # VGPR[665:667] S_MOV_B64 sDst(SGPR186) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0xb5 # VGPR706 # Indirect branch to fbm(vf3;: -5108 S_GETPC_B64 sDst(SGPR40) src0(SGPR40) S_SUB_U32 sDst(SGPR40) src0(SGPR40) src1(LITERAL_CONST) const: 0x13f4 S_SUBB_U32 sDst(SGPR41) src0(SGPR41) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR40) src0(SGPR40) S_MOV_B64 sDst(EXEC) src0(SGPR186) # .lbl36 # 623: OpVectorTimesScalar: FloatVector3: tmp623 << const622, fbm(vf3; V_MOV_B32 vDst(VGPR254) src0(1_0_F) V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR256) src0(LITERAL_CONST) const: 0x3ecccccd V_MUL_F32 vDst(VGPR257) src0(VGPR181) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR258) src0(VGPR181) src1(VGPR255) // VOP2 V_MUL_F32 vDst(VGPR259) src0(VGPR181) src1(VGPR256) // VOP2 # 624: OpVectorTimesScalar: FloatVector3: tmp624 << tmp623, const360 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3f400000 V_MUL_F32 vDst(VGPR182) src0(VGPR254) src1(VGPR257) // VOP2 V_MUL_F32 vDst(VGPR183) src0(VGPR254) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR184) src0(VGPR254) src1(VGPR259) // VOP2 # 625: OpLoad: FloatVector3: tmp625 << p S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR175) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) # 627: OpFMul: FloatVector3: tmp627 << tmp625, const626 V_MOV_B32 vDst(VGPR257) src0(2_0_F) V_MOV_B32 vDst(VGPR258) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR259) src0(2_0_F) V_MUL_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_MUL_F32 vDst(VGPR261) src0(VGPR255) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR262) src0(VGPR256) src1(VGPR259) // VOP2 # OpStore: : tmp627 >> param628 V_MOV_B32 vDst(VGPR173) src0(VGPR260) V_MOV_B32 vDst(VGPR174) src0(VGPR261) V_MOV_B32 vDst(VGPR175) src0(VGPR262) # 629: OpFunctionCall: Float: fbm(vf3;(param628) S_ADD_U32 sDst(SGPR42) src0(LITERAL_CONST) src1(0) const: 0xad # VGPR[668:670] S_MOV_B64 sDst(SGPR188) src0(EXEC) S_MOV_B32 sDst(SGPR23) src0(LITERAL_CONST) const: 0xb9 # VGPR726 # Indirect branch to fbm(vf3;: -5268 S_GETPC_B64 sDst(SGPR40) src0(SGPR40) S_SUB_U32 sDst(SGPR40) src0(SGPR40) src1(LITERAL_CONST) const: 0x1494 S_SUBB_U32 sDst(SGPR41) src0(SGPR41) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR40) src0(SGPR40) S_MOV_B64 sDst(EXEC) src0(SGPR188) # .lbl37 # 631: OpVectorTimesScalar: FloatVector3: tmp631 << const630, fbm(vf3; V_MOV_B32 vDst(VGPR254) src0(1_0_F) V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR256) src0(0_5_F) V_MUL_F32 vDst(VGPR257) src0(VGPR185) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR258) src0(VGPR185) src1(VGPR255) // VOP2 V_MUL_F32 vDst(VGPR259) src0(VGPR185) src1(VGPR256) // VOP2 # 632: OpVectorTimesScalar: FloatVector3: tmp632 << tmp631, const363 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3e800000 V_MUL_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 V_MUL_F32 vDst(VGPR261) src0(VGPR254) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR262) src0(VGPR254) src1(VGPR259) // VOP2 # 633: OpFAdd: FloatVector3: tmp633 << tmp624, tmp632 V_ADD_F32 vDst(VGPR254) src0(VGPR182) src1(VGPR260) // VOP2 V_ADD_F32 vDst(VGPR255) src0(VGPR183) src1(VGPR261) // VOP2 V_ADD_F32 vDst(VGPR256) src0(VGPR184) src1(VGPR262) // VOP2 # OpStore: : tmp633 >> t V_MOV_B32 vDst(VGPR257) src0(VGPR254) V_MOV_B32 vDst(VGPR258) src0(VGPR255) V_MOV_B32 vDst(VGPR259) src0(VGPR256) # OpSelectionMerge: (merge: lb636) # CF Block: Merge: lb636 S_MOV_B64 sDst(SGPR212) src0(EXEC) # OpBranchConditional: if(isWall(vf3;) then branch to lb635, else branch to lb636 # CF Block: Cond Branch: true: lb635, false: lb636 S_AND_B64 sDst(EXEC) src0(VGPR176) src1(EXEC) S_CBRANCH_EXECZ 24 lb636 # lb635 Label: lb635 # 637: OpLoad: FloatVector3: tmp637 << t # 638: OpCompositeConstruct: FloatVector3: tmp638 << const275, const275, const275 V_MOV_B32 vDst(VGPR254) src0(0_5_F) V_MOV_B32 vDst(VGPR255) src0(0_5_F) V_MOV_B32 vDst(VGPR256) src0(0_5_F) # 639: OpExtInst(FMix): FloatVector3: tmp639 << tmp637, const172, tmp638 V_MOV_B32 vDst(VGPR260) src0(1_0_F) V_MOV_B32 vDst(VGPR261) src0(1_0_F) V_MOV_B32 vDst(VGPR262) src0(1_0_F) V_SUBREV_F32 vDst(VGPR263) src0(VGPR254) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR263) src0(VGPR257) src1(VGPR263) // VOP2 V_MAD_F32 vDst(VGPR263) src0(VGPR260) src1(VGPR254) src2(VGPR263) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR264) src0(VGPR255) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR264) src0(VGPR258) src1(VGPR264) // VOP2 V_MAD_F32 vDst(VGPR264) src0(VGPR261) src1(VGPR255) src2(VGPR264) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR265) src0(VGPR256) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR265) src0(VGPR259) src1(VGPR265) // VOP2 V_MAD_F32 vDst(VGPR265) src0(VGPR262) src1(VGPR256) src2(VGPR265) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp639 >> t V_MOV_B32 vDst(VGPR257) src0(VGPR263) V_MOV_B32 vDst(VGPR258) src0(VGPR264) V_MOV_B32 vDst(VGPR259) src0(VGPR265) # OpBranch: to lb636 # lb636 Label: lb636 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR212) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR176) # 640: OpLoad: FloatVector3: tmp640 << t # 641: OpCompositeConstruct: FloatVector3: tmp641 << const92, const92, const92 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR254) src0(SGPR212) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR255) src0(SGPR212) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR256) src0(SGPR212) # 642: OpCompositeConstruct: FloatVector3: tmp642 << const117, const117, const117 V_MOV_B32 vDst(VGPR260) src0(1_0_F) V_MOV_B32 vDst(VGPR261) src0(1_0_F) V_MOV_B32 vDst(VGPR262) src0(1_0_F) # 643: OpExtInst(FClamp): FloatVector3: tmp643 << tmp640, tmp641, tmp642 V_MAX_F32 vDst(VGPR263) src0(VGPR257) src1(VGPR254) // VOP2 V_MAX_F32 vDst(VGPR264) src0(VGPR258) src1(VGPR255) // VOP2 V_MAX_F32 vDst(VGPR265) src0(VGPR259) src1(VGPR256) // VOP2 V_MIN_F32 vDst(VGPR263) src0(VGPR263) src1(VGPR260) // VOP2 V_MIN_F32 vDst(VGPR264) src0(VGPR264) src1(VGPR261) // VOP2 V_MIN_F32 vDst(VGPR265) src0(VGPR265) src1(VGPR262) // VOP2 # OpReturnValue: : << tmp643 S_MOV_B32 sDst(M0) src0(SGPR174) V_MOVRELD_B32 vDst(VGPR0) src0(VGPR263) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR264) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR265) S_SETPC_B64 sDst(SGPR172) src0(SGPR172) # Void mainImage(vf4;vf2;(FloatVector4* fragColor, FloatVector2* fragCoord) Function: Void mainImage(vf4;vf2;(, FloatVector2 main.fragCoord) S_MOV_B64 sDst(SGPR190) src0(EXEC) # lb89 Label: lb89 # 647: OpLoad: FloatVector2: tmp647 << fragCoord S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR12) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) # 650: OpLoad: FloatVector3: tmp650 << iResolution S_LOAD_DWORDX2_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR[216:217]) S_WAITCNT 0 S_LOAD_DWORD_IMM offset(8) sBase(SGPR[0:1]) sDst(SGPR218) S_WAITCNT 0 # 651: OpVectorShuffle: FloatVector2: tmp651 << tmp650, tmp650, 0, 1 V_MOV_B32 vDst(VGPR256) src0(SGPR216) V_MOV_B32 vDst(VGPR257) src0(SGPR217) # 652: OpFDiv: FloatVector2: tmp652 << tmp647, tmp651 V_RCP_F32 vDst(VGPR258) src0(VGPR256) V_RCP_F32 vDst(VGPR259) src0(VGPR257) V_MUL_F32 vDst(VGPR258) src0(VGPR254) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR259) src0(VGPR255) src1(VGPR259) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR258) src0(VGPR258) src1(VGPR256) src2(VGPR254) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_DIV_FIXUP_F32 vDst(VGPR259) src0(VGPR259) src1(VGPR257) src2(VGPR255) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 653: OpVectorTimesScalar: FloatVector2: tmp653 << tmp652, const227 V_MOV_B32 vDst(VGPR254) src0(2_0_F) V_MUL_F32 vDst(VGPR255) src0(VGPR254) src1(VGPR258) // VOP2 V_MUL_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR259) // VOP2 # 654: OpCompositeConstruct: FloatVector2: tmp654 << const117, const117 V_MOV_B32 vDst(VGPR257) src0(1_0_F) V_MOV_B32 vDst(VGPR258) src0(1_0_F) # 655: OpFSub: FloatVector2: tmp655 << tmp653, tmp654 V_SUB_F32 vDst(VGPR259) src0(VGPR255) src1(VGPR257) // VOP2 V_SUB_F32 vDst(VGPR260) src0(VGPR256) src1(VGPR258) // VOP2 # OpStore: : tmp655 >> uv V_MOV_B32 vDst(VGPR254) src0(VGPR259) V_MOV_B32 vDst(VGPR255) src0(VGPR260) # 657: OpAccessChain: Float*: iResolution[0] # 658: OpLoad: Float: tmp658 << iResolution[0] S_LOAD_DWORD_IMM offset(0) sBase(SGPR[0:1]) sDst(SGPR212) S_WAITCNT 0 # 659: OpAccessChain: Float*: iResolution[1] # 660: OpLoad: Float: tmp660 << iResolution[1] S_LOAD_DWORD_IMM offset(4) sBase(SGPR[0:1]) sDst(SGPR213) S_WAITCNT 0 # 661: OpFDiv: Float: tmp661 << tmp658, tmp660 V_MOV_B32 vDst(VGPR256) src0(SGPR213) V_RCP_F32 vDst(VGPR257) src0(VGPR256) V_MUL_F32 vDst(VGPR257) src0(SGPR212) src1(VGPR257) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR257) src0(VGPR257) src1(VGPR256) src2(SGPR212) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 662: OpAccessChain: Float*: uv[0] # 663: OpLoad: Float: tmp663 << uv[0] V_MOV_B32 vDst(VGPR256) src0(VGPR254) # 664: OpFMul: Float: tmp664 << tmp663, tmp661 V_MUL_F32 vDst(VGPR258) src0(VGPR256) src1(VGPR257) // VOP2 # 665: OpAccessChain: Float*: uv[0] # OpStore: : tmp664 >> uv[0] V_MOV_B32 vDst(VGPR254) src0(VGPR258) # 668: OpLoad: Float: tmp668 << iTime S_LOAD_DWORD_IMM offset(12) sBase(SGPR[0:1]) sDst(SGPR212) S_WAITCNT 0 # 669: OpFMul: Float: tmp669 << tmp668, const275 V_MOV_B32 vDst(VGPR256) src0(0_5_F) V_MUL_F32 vDst(VGPR257) src0(SGPR212) src1(VGPR256) // VOP2 # OpStore: : tmp669 >> time V_MOV_B32 vDst(VGPR256) src0(VGPR257) # 670: OpLoad: Float: tmp670 << time # 671: OpExtInst(Sin): Float: tmp671 << tmp670 V_MUL_F32 vDst(VGPR257) src0(LITERAL_CONST) src1(VGPR256) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR257) src0(VGPR257) V_SIN_F32 vDst(VGPR257) src0(VGPR257) # 672: OpFMul: Float: tmp672 << tmp671, const420 V_MOV_B32 vDst(VGPR258) src0(LITERAL_CONST) const: 0x3ecccccd V_MUL_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR258) // VOP2 # OpStore: : tmp672 >> _twist V_MOV_B32 vDst(VGPR20) src0(VGPR259) # 674: OpLoad: Float: tmp674 << time # 676: OpFMul: Float: tmp676 << tmp674, const675 V_MOV_B32 vDst(VGPR257) src0(LITERAL_CONST) const: 0x40490fdb V_MUL_F32 vDst(VGPR258) src0(VGPR256) src1(VGPR257) // VOP2 # 677: OpFDiv: Float: tmp677 << tmp676, const227 V_MOV_B32 vDst(VGPR257) src0(2_0_F) V_RCP_F32 vDst(VGPR259) src0(VGPR257) V_MUL_F32 vDst(VGPR259) src0(VGPR258) src1(VGPR259) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR259) src0(VGPR259) src1(VGPR257) src2(VGPR258) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 678: OpFAdd: Float: tmp678 << tmp677, const117 V_MOV_B32 vDst(VGPR257) src0(1_0_F) V_ADD_F32 vDst(VGPR258) src0(VGPR259) src1(VGPR257) // VOP2 # 679: OpExtInst(Sin): Float: tmp679 << tmp678 V_MUL_F32 vDst(VGPR257) src0(LITERAL_CONST) src1(VGPR258) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR257) src0(VGPR257) V_SIN_F32 vDst(VGPR257) src0(VGPR257) # 680: OpFMul: Float: tmp680 << tmp679, const117 V_MOV_B32 vDst(VGPR258) src0(1_0_F) V_MUL_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR258) // VOP2 # 681: OpLoad: Float: tmp681 << time # 682: OpCompositeConstruct: FloatVector3: tmp682 << tmp680, const92, tmp681 V_MOV_B32 vDst(VGPR260) src0(VGPR259) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR261) src0(SGPR212) V_MOV_B32 vDst(VGPR262) src0(VGPR256) # OpStore: : tmp682 >> ro V_MOV_B32 vDst(VGPR186) src0(VGPR260) V_MOV_B32 vDst(VGPR187) src0(VGPR261) V_MOV_B32 vDst(VGPR188) src0(VGPR262) # 684: OpLoad: FloatVector2: tmp684 << uv # 686: OpCompositeExtract: Float: tmp686 << tmp684, 0 V_MOV_B32 vDst(VGPR257) src0(VGPR254) # 687: OpCompositeExtract: Float: tmp687 << tmp684, 1 V_MOV_B32 vDst(VGPR258) src0(VGPR255) # 688: OpCompositeConstruct: FloatVector3: tmp688 << tmp686, tmp687, const685 V_MOV_B32 vDst(VGPR259) src0(VGPR257) V_MOV_B32 vDst(VGPR260) src0(VGPR258) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x3fc00000 V_MOV_B32 vDst(VGPR261) src0(SGPR212) # 689: OpExtInst(Normalize): FloatVector3: tmp689 << tmp688 V_MUL_F32 vDst(VGPR254) src0(VGPR259) src1(VGPR259) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR260) src1(VGPR260) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR261) src1(VGPR261) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR254) src0(VGPR254) V_MUL_F32 vDst(VGPR262) src0(VGPR259) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR263) src0(VGPR260) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR264) src0(VGPR261) src1(VGPR254) // VOP2 # OpStore: : tmp689 >> rd V_MOV_B32 vDst(VGPR189) src0(VGPR262) V_MOV_B32 vDst(VGPR190) src0(VGPR263) V_MOV_B32 vDst(VGPR191) src0(VGPR264) # 690: OpLoad: Float: tmp690 << time # 691: OpFAdd: Float: tmp691 << tmp690, const227 V_MOV_B32 vDst(VGPR254) src0(2_0_F) V_ADD_F32 vDst(VGPR255) src0(VGPR256) src1(VGPR254) // VOP2 # OpStore: : tmp691 >> time V_MOV_B32 vDst(VGPR256) src0(VGPR255) # 693: OpLoad: Float: tmp693 << time # 694: OpFMul: Float: tmp694 << tmp693, const675 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x40490fdb V_MUL_F32 vDst(VGPR255) src0(VGPR256) src1(VGPR254) // VOP2 # 695: OpFDiv: Float: tmp695 << tmp694, const227 V_MOV_B32 vDst(VGPR254) src0(2_0_F) V_RCP_F32 vDst(VGPR257) src0(VGPR254) V_MUL_F32 vDst(VGPR257) src0(VGPR255) src1(VGPR257) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR257) src0(VGPR257) src1(VGPR254) src2(VGPR255) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 696: OpFAdd: Float: tmp696 << tmp695, const117 V_MOV_B32 vDst(VGPR254) src0(1_0_F) V_ADD_F32 vDst(VGPR255) src0(VGPR257) src1(VGPR254) // VOP2 # 697: OpExtInst(Sin): Float: tmp697 << tmp696 V_MUL_F32 vDst(VGPR254) src0(LITERAL_CONST) src1(VGPR255) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR254) src0(VGPR254) V_SIN_F32 vDst(VGPR254) src0(VGPR254) # 698: OpFMul: Float: tmp698 << tmp697, const117 V_MOV_B32 vDst(VGPR255) src0(1_0_F) V_MUL_F32 vDst(VGPR257) src0(VGPR254) src1(VGPR255) // VOP2 # 699: OpLoad: Float: tmp699 << time # 700: OpCompositeConstruct: FloatVector3: tmp700 << tmp698, const92, tmp699 V_MOV_B32 vDst(VGPR258) src0(VGPR257) S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR259) src0(SGPR212) V_MOV_B32 vDst(VGPR260) src0(VGPR256) # OpStore: : tmp700 >> light V_MOV_B32 vDst(VGPR192) src0(VGPR258) V_MOV_B32 vDst(VGPR193) src0(VGPR259) V_MOV_B32 vDst(VGPR194) src0(VGPR260) # 701: OpLoad: Float: tmp701 << time # 702: OpFSub: Float: tmp702 << tmp701, const227 V_MOV_B32 vDst(VGPR254) src0(2_0_F) V_SUB_F32 vDst(VGPR255) src0(VGPR256) src1(VGPR254) // VOP2 # OpStore: : tmp702 >> time V_MOV_B32 vDst(VGPR256) src0(VGPR255) # 703: OpLoad: Float: tmp703 << time # 704: OpFMul: Float: tmp704 << tmp703, const675 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x40490fdb V_MUL_F32 vDst(VGPR255) src0(VGPR256) src1(VGPR254) // VOP2 # 705: OpFDiv: Float: tmp705 << tmp704, const227 V_MOV_B32 vDst(VGPR254) src0(2_0_F) V_RCP_F32 vDst(VGPR256) src0(VGPR254) V_MUL_F32 vDst(VGPR256) src0(VGPR255) src1(VGPR256) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR256) src0(VGPR256) src1(VGPR254) src2(VGPR255) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 706: OpFAdd: Float: tmp706 << tmp705, const117 V_MOV_B32 vDst(VGPR254) src0(1_0_F) V_ADD_F32 vDst(VGPR255) src0(VGPR256) src1(VGPR254) // VOP2 # 707: OpExtInst(Cos): Float: tmp707 << tmp706 V_MUL_F32 vDst(VGPR254) src0(LITERAL_CONST) src1(VGPR255) // VOP2 const: 0x3e22f983 V_FRACT_F32 vDst(VGPR254) src0(VGPR254) V_COS_F32 vDst(VGPR254) src0(VGPR254) # 708: OpFNegate: Float: tmp708 << tmp707 V_MUL_F32 vDst(VGPR255) src0(M1_0_F) src1(VGPR254) // VOP2 # 709: OpFMul: Float: tmp709 << tmp708, const275 V_MOV_B32 vDst(VGPR254) src0(0_5_F) V_MUL_F32 vDst(VGPR256) src0(VGPR255) src1(VGPR254) // VOP2 # 711: OpLoad: FloatVector3: tmp711 << rd # 712: OpVectorShuffle: FloatVector2: tmp712 << tmp711, tmp711, 0, 2 V_MOV_B32 vDst(VGPR257) src0(VGPR189) V_MOV_B32 vDst(VGPR258) src0(VGPR191) # OpStore: : tmp712 >> param710 V_MOV_B32 vDst(VGPR195) src0(VGPR257) V_MOV_B32 vDst(VGPR196) src0(VGPR258) # OpStore: : tmp709 >> param713 V_MOV_B32 vDst(VGPR197) src0(VGPR256) # 714: OpFunctionCall: Void: tRotate(vf2;f1;(param710, param713) S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0xc3 # VGPR[773:774] S_ADD_U32 sDst(SGPR56) src0(LITERAL_CONST) src1(0) const: 0xc5 # VGPR775 S_MOV_B64 sDst(SGPR192) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: -5884 S_GETPC_B64 sDst(SGPR54) src0(SGPR54) S_SUB_U32 sDst(SGPR54) src0(SGPR54) src1(LITERAL_CONST) const: 0x16fc S_SUBB_U32 sDst(SGPR55) src0(SGPR55) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR54) src0(SGPR54) S_MOV_B64 sDst(EXEC) src0(SGPR192) # .lbl38 # 715: OpLoad: FloatVector2: tmp715 << param710 # 716: OpLoad: FloatVector3: tmp716 << rd # 717: OpVectorShuffle: FloatVector3: tmp717 << tmp716, tmp715, 3, 1, 4 V_MOV_B32 vDst(VGPR254) src0(VGPR195) V_MOV_B32 vDst(VGPR255) src0(VGPR190) V_MOV_B32 vDst(VGPR256) src0(VGPR196) # OpStore: : tmp717 >> rd V_MOV_B32 vDst(VGPR189) src0(VGPR254) V_MOV_B32 vDst(VGPR190) src0(VGPR255) V_MOV_B32 vDst(VGPR191) src0(VGPR256) # 718: OpAccessChain: Float*: ro[2] # 719: OpLoad: Float: tmp719 << ro[2] V_MOV_B32 vDst(VGPR254) src0(VGPR188) # 720: OpFNegate: Float: tmp720 << tmp719 V_MUL_F32 vDst(VGPR255) src0(M1_0_F) src1(VGPR254) // VOP2 # 721: OpLoad: Float: tmp721 << _twist # 722: OpFMul: Float: tmp722 << tmp720, tmp721 V_MUL_F32 vDst(VGPR254) src0(VGPR255) src1(VGPR20) // VOP2 # 724: OpLoad: FloatVector3: tmp724 << ro # 725: OpVectorShuffle: FloatVector2: tmp725 << tmp724, tmp724, 0, 1 V_MOV_B32 vDst(VGPR255) src0(VGPR186) V_MOV_B32 vDst(VGPR256) src0(VGPR187) # OpStore: : tmp725 >> param723 V_MOV_B32 vDst(VGPR198) src0(VGPR255) V_MOV_B32 vDst(VGPR199) src0(VGPR256) # OpStore: : tmp722 >> param726 V_MOV_B32 vDst(VGPR200) src0(VGPR254) # 727: OpFunctionCall: Void: tRotate(vf2;f1;(param723, param726) S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0xc6 # VGPR[776:777] S_ADD_U32 sDst(SGPR56) src0(LITERAL_CONST) src1(0) const: 0xc8 # VGPR778 S_MOV_B64 sDst(SGPR194) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: -5988 S_GETPC_B64 sDst(SGPR54) src0(SGPR54) S_SUB_U32 sDst(SGPR54) src0(SGPR54) src1(LITERAL_CONST) const: 0x1764 S_SUBB_U32 sDst(SGPR55) src0(SGPR55) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR54) src0(SGPR54) S_MOV_B64 sDst(EXEC) src0(SGPR194) # .lbl39 # 728: OpLoad: FloatVector2: tmp728 << param723 # 729: OpLoad: FloatVector3: tmp729 << ro # 730: OpVectorShuffle: FloatVector3: tmp730 << tmp729, tmp728, 3, 4, 2 V_MOV_B32 vDst(VGPR257) src0(VGPR198) V_MOV_B32 vDst(VGPR258) src0(VGPR199) V_MOV_B32 vDst(VGPR259) src0(VGPR188) # OpStore: : tmp730 >> ro V_MOV_B32 vDst(VGPR186) src0(VGPR257) V_MOV_B32 vDst(VGPR187) src0(VGPR258) V_MOV_B32 vDst(VGPR188) src0(VGPR259) # 731: OpAccessChain: Float*: light[2] # 732: OpLoad: Float: tmp732 << light[2] V_MOV_B32 vDst(VGPR254) src0(VGPR194) # 733: OpFNegate: Float: tmp733 << tmp732 V_MUL_F32 vDst(VGPR255) src0(M1_0_F) src1(VGPR254) // VOP2 # 734: OpLoad: Float: tmp734 << _twist # 735: OpFMul: Float: tmp735 << tmp733, tmp734 V_MUL_F32 vDst(VGPR254) src0(VGPR255) src1(VGPR20) // VOP2 # 737: OpLoad: FloatVector3: tmp737 << light # 738: OpVectorShuffle: FloatVector2: tmp738 << tmp737, tmp737, 0, 1 V_MOV_B32 vDst(VGPR255) src0(VGPR192) V_MOV_B32 vDst(VGPR256) src0(VGPR193) # OpStore: : tmp738 >> param736 V_MOV_B32 vDst(VGPR201) src0(VGPR255) V_MOV_B32 vDst(VGPR202) src0(VGPR256) # OpStore: : tmp735 >> param739 V_MOV_B32 vDst(VGPR203) src0(VGPR254) # 740: OpFunctionCall: Void: tRotate(vf2;f1;(param736, param739) S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0xc9 # VGPR[779:780] S_ADD_U32 sDst(SGPR56) src0(LITERAL_CONST) src1(0) const: 0xcb # VGPR781 S_MOV_B64 sDst(SGPR196) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: -6092 S_GETPC_B64 sDst(SGPR54) src0(SGPR54) S_SUB_U32 sDst(SGPR54) src0(SGPR54) src1(LITERAL_CONST) const: 0x17cc S_SUBB_U32 sDst(SGPR55) src0(SGPR55) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR54) src0(SGPR54) S_MOV_B64 sDst(EXEC) src0(SGPR196) # .lbl40 # 741: OpLoad: FloatVector2: tmp741 << param736 # 742: OpLoad: FloatVector3: tmp742 << light # 743: OpVectorShuffle: FloatVector3: tmp743 << tmp742, tmp741, 3, 4, 2 V_MOV_B32 vDst(VGPR257) src0(VGPR201) V_MOV_B32 vDst(VGPR258) src0(VGPR202) V_MOV_B32 vDst(VGPR259) src0(VGPR194) # OpStore: : tmp743 >> light V_MOV_B32 vDst(VGPR192) src0(VGPR257) V_MOV_B32 vDst(VGPR193) src0(VGPR258) V_MOV_B32 vDst(VGPR194) src0(VGPR259) # 744: OpAccessChain: Float*: ro[2] # 745: OpLoad: Float: tmp745 << ro[2] V_MOV_B32 vDst(VGPR254) src0(VGPR188) # 746: OpFNegate: Float: tmp746 << tmp745 V_MUL_F32 vDst(VGPR255) src0(M1_0_F) src1(VGPR254) // VOP2 # 747: OpLoad: Float: tmp747 << _twist # 748: OpFMul: Float: tmp748 << tmp746, tmp747 V_MUL_F32 vDst(VGPR254) src0(VGPR255) src1(VGPR20) // VOP2 # 750: OpLoad: FloatVector3: tmp750 << rd # 751: OpVectorShuffle: FloatVector2: tmp751 << tmp750, tmp750, 0, 1 V_MOV_B32 vDst(VGPR255) src0(VGPR189) V_MOV_B32 vDst(VGPR256) src0(VGPR190) # OpStore: : tmp751 >> param749 V_MOV_B32 vDst(VGPR204) src0(VGPR255) V_MOV_B32 vDst(VGPR205) src0(VGPR256) # OpStore: : tmp748 >> param752 V_MOV_B32 vDst(VGPR206) src0(VGPR254) # 753: OpFunctionCall: Void: tRotate(vf2;f1;(param749, param752) S_ADD_U32 sDst(SGPR43) src0(LITERAL_CONST) src1(0) const: 0xcc # VGPR[782:783] S_ADD_U32 sDst(SGPR56) src0(LITERAL_CONST) src1(0) const: 0xce # VGPR784 S_MOV_B64 sDst(SGPR198) src0(EXEC) # Indirect branch to tRotate(vf2;f1;: -6196 S_GETPC_B64 sDst(SGPR54) src0(SGPR54) S_SUB_U32 sDst(SGPR54) src0(SGPR54) src1(LITERAL_CONST) const: 0x1834 S_SUBB_U32 sDst(SGPR55) src0(SGPR55) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR54) src0(SGPR54) S_MOV_B64 sDst(EXEC) src0(SGPR198) # .lbl41 # 754: OpLoad: FloatVector2: tmp754 << param749 # 755: OpLoad: FloatVector3: tmp755 << rd # 756: OpVectorShuffle: FloatVector3: tmp756 << tmp755, tmp754, 3, 4, 2 V_MOV_B32 vDst(VGPR257) src0(VGPR204) V_MOV_B32 vDst(VGPR258) src0(VGPR205) V_MOV_B32 vDst(VGPR259) src0(VGPR191) # OpStore: : tmp756 >> rd V_MOV_B32 vDst(VGPR189) src0(VGPR257) V_MOV_B32 vDst(VGPR190) src0(VGPR258) V_MOV_B32 vDst(VGPR191) src0(VGPR259) # 760: OpLoad: FloatVector3: tmp760 << ro # OpStore: : tmp760 >> param759 V_MOV_B32 vDst(VGPR207) src0(VGPR186) V_MOV_B32 vDst(VGPR208) src0(VGPR187) V_MOV_B32 vDst(VGPR209) src0(VGPR188) # 762: OpLoad: FloatVector3: tmp762 << rd # OpStore: : tmp762 >> param761 V_MOV_B32 vDst(VGPR210) src0(VGPR189) V_MOV_B32 vDst(VGPR211) src0(VGPR190) V_MOV_B32 vDst(VGPR212) src0(VGPR191) # OpStore: : const220 >> param763 S_MOV_B32 sDst(SGPR212) src0(LITERAL_CONST) const: 0x41200000 V_MOV_B32 vDst(VGPR213) src0(SGPR212) # 765: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param759, param761, param763, param764) S_ADD_U32 sDst(SGPR121) src0(LITERAL_CONST) src1(0) const: 0xcf # VGPR[785:787] S_ADD_U32 sDst(SGPR122) src0(LITERAL_CONST) src1(0) const: 0xd2 # VGPR[788:790] S_ADD_U32 sDst(SGPR123) src0(LITERAL_CONST) src1(0) const: 0xd5 # VGPR791 S_ADD_U32 sDst(SGPR124) src0(LITERAL_CONST) src1(0) const: 0xd6 # VGPR792 S_MOV_B64 sDst(SGPR200) src0(EXEC) S_MOV_B32 sDst(SGPR120) src0(LITERAL_CONST) const: 0xec # VGPR916 # Indirect branch to trace(vf3;vf3;f1;f1;: -3820 S_GETPC_B64 sDst(SGPR118) src0(SGPR118) S_SUB_U32 sDst(SGPR118) src0(SGPR118) src1(LITERAL_CONST) const: 0xeec S_SUBB_U32 sDst(SGPR119) src0(SGPR119) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR118) src0(SGPR118) S_MOV_B64 sDst(EXEC) src0(SGPR200) # .lbl42 # 766: OpLoad: Float: tmp766 << param764 # 768: OpLoad: FloatVector3: tmp768 << ro # 769: OpLoad: FloatVector3: tmp769 << rd # 771: OpVectorTimesScalar: FloatVector3: tmp771 << tmp769, trace(vf3;vf3;f1;f1; V_MUL_F32 vDst(VGPR254) src0(VGPR236) src1(VGPR189) // VOP2 V_MUL_F32 vDst(VGPR255) src0(VGPR236) src1(VGPR190) // VOP2 V_MUL_F32 vDst(VGPR256) src0(VGPR236) src1(VGPR191) // VOP2 # 772: OpFAdd: FloatVector3: tmp772 << tmp768, tmp771 V_ADD_F32 vDst(VGPR237) src0(VGPR186) src1(VGPR254) // VOP2 V_ADD_F32 vDst(VGPR238) src0(VGPR187) src1(VGPR255) // VOP2 V_ADD_F32 vDst(VGPR239) src0(VGPR188) src1(VGPR256) // VOP2 # OpStore: : tmp772 >> param774 V_MOV_B32 vDst(VGPR215) src0(VGPR237) V_MOV_B32 vDst(VGPR216) src0(VGPR238) V_MOV_B32 vDst(VGPR217) src0(VGPR239) # 776: OpFunctionCall: FloatVector3: getNormal(vf3;(param774) S_ADD_U32 sDst(SGPR138) src0(LITERAL_CONST) src1(0) const: 0xd7 # VGPR[793:795] S_MOV_B64 sDst(SGPR202) src0(EXEC) S_MOV_B32 sDst(SGPR125) src0(LITERAL_CONST) const: 0xf0 # VGPR[923:925] # Indirect branch to getNormal(vf3;: -3544 S_GETPC_B64 sDst(SGPR136) src0(SGPR136) S_SUB_U32 sDst(SGPR136) src0(SGPR136) src1(LITERAL_CONST) const: 0xdd8 S_SUBB_U32 sDst(SGPR137) src0(SGPR137) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR136) src0(SGPR136) S_MOV_B64 sDst(EXEC) src0(SGPR202) # .lbl43 # 778: OpLoad: FloatVector3: tmp778 << light # 780: OpFSub: FloatVector3: tmp780 << tmp778, tmp772 V_SUB_F32 vDst(VGPR254) src0(VGPR192) src1(VGPR237) // VOP2 V_SUB_F32 vDst(VGPR255) src0(VGPR193) src1(VGPR238) // VOP2 V_SUB_F32 vDst(VGPR256) src0(VGPR194) src1(VGPR239) // VOP2 # 781: OpExtInst(Normalize): FloatVector3: tmp781 << tmp780 V_MUL_F32 vDst(VGPR257) src0(VGPR254) src1(VGPR254) // VOP2 V_MAC_F32 vDst(VGPR257) src0(VGPR255) src1(VGPR255) // VOP2 V_MAC_F32 vDst(VGPR257) src0(VGPR256) src1(VGPR256) // VOP2 V_RSQ_CLAMP_F32 vDst(VGPR257) src0(VGPR257) V_MUL_F32 vDst(VGPR243) src0(VGPR254) src1(VGPR257) // VOP2 V_MUL_F32 vDst(VGPR244) src0(VGPR255) src1(VGPR257) // VOP2 V_MUL_F32 vDst(VGPR245) src0(VGPR256) src1(VGPR257) // VOP2 # 785: OpVectorTimesScalar: FloatVector3: tmp785 << getNormal(vf3;, const467 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x3727c5ac V_MUL_F32 vDst(VGPR255) src0(VGPR254) src1(VGPR240) // VOP2 V_MUL_F32 vDst(VGPR256) src0(VGPR254) src1(VGPR241) // VOP2 V_MUL_F32 vDst(VGPR257) src0(VGPR254) src1(VGPR242) // VOP2 # 786: OpVectorTimesScalar: FloatVector3: tmp786 << tmp785, const220 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x41200000 V_MUL_F32 vDst(VGPR258) src0(VGPR254) src1(VGPR255) // VOP2 V_MUL_F32 vDst(VGPR259) src0(VGPR254) src1(VGPR256) // VOP2 V_MUL_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR257) // VOP2 # 787: OpFAdd: FloatVector3: tmp787 << tmp772, tmp786 V_ADD_F32 vDst(VGPR261) src0(VGPR237) src1(VGPR258) // VOP2 V_ADD_F32 vDst(VGPR262) src0(VGPR238) src1(VGPR259) // VOP2 V_ADD_F32 vDst(VGPR263) src0(VGPR239) src1(VGPR260) // VOP2 # 790: OpLoad: FloatVector3: tmp790 << light # 791: OpExtInst(Distance): Float: tmp791 << tmp787, tmp790 V_SUB_F32 vDst(VGPR254) src0(VGPR261) src1(VGPR192) // VOP2 V_SUB_F32 vDst(VGPR255) src0(VGPR262) src1(VGPR193) // VOP2 V_SUB_F32 vDst(VGPR256) src0(VGPR263) src1(VGPR194) // VOP2 V_MUL_F32 vDst(VGPR246) src0(VGPR254) src1(VGPR254) // VOP2 V_MAC_F32 vDst(VGPR246) src0(VGPR255) src1(VGPR255) // VOP2 V_MAC_F32 vDst(VGPR246) src0(VGPR256) src1(VGPR256) // VOP2 V_SQRT_F32 vDst(VGPR246) src0(VGPR246) # OpStore: : tmp787 >> param794 V_MOV_B32 vDst(VGPR219) src0(VGPR261) V_MOV_B32 vDst(VGPR220) src0(VGPR262) V_MOV_B32 vDst(VGPR221) src0(VGPR263) # OpStore: : tmp781 >> param796 V_MOV_B32 vDst(VGPR222) src0(VGPR243) V_MOV_B32 vDst(VGPR223) src0(VGPR244) V_MOV_B32 vDst(VGPR224) src0(VGPR245) # OpStore: : tmp791 >> param798 V_MOV_B32 vDst(VGPR225) src0(VGPR246) # 801: OpFunctionCall: Float: trace(vf3;vf3;f1;f1;(param794, param796, param798, param800) S_ADD_U32 sDst(SGPR121) src0(LITERAL_CONST) src1(0) const: 0xdb # VGPR[797:799] S_ADD_U32 sDst(SGPR122) src0(LITERAL_CONST) src1(0) const: 0xde # VGPR[800:802] S_ADD_U32 sDst(SGPR123) src0(LITERAL_CONST) src1(0) const: 0xe1 # VGPR803 S_ADD_U32 sDst(SGPR124) src0(LITERAL_CONST) src1(0) const: 0xe2 # VGPR804 S_MOV_B64 sDst(SGPR204) src0(EXEC) S_MOV_B32 sDst(SGPR120) src0(LITERAL_CONST) const: 0xf7 # VGPR948 # Indirect branch to trace(vf3;vf3;f1;f1;: -4124 S_GETPC_B64 sDst(SGPR118) src0(SGPR118) S_SUB_U32 sDst(SGPR118) src0(SGPR118) src1(LITERAL_CONST) const: 0x101c S_SUBB_U32 sDst(SGPR119) src0(SGPR119) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR118) src0(SGPR118) S_MOV_B64 sDst(EXEC) src0(SGPR204) # .lbl44 # 802: OpLoad: Float: tmp802 << param800 # 804: OpFOrdGreaterThan: Bool: tmp804 << trace(vf3;vf3;f1;f1;, tmp791 V_CMP_GT_F32 dst(SGPR214) src0(VGPR247) src1(VGPR246) // VOP3a # 805: OpSelect: Float: tmp805 << tmp804, const117, const92 # CF Block: Merge: .lbl46 S_MOV_B64 sDst(SGPR212) src0(EXEC) # CF Block: Cond Branch: true: .lbl47, false: .lbl45 S_AND_B64 sDst(EXEC) src0(SGPR214) src1(EXEC) S_CBRANCH_EXECZ 1 .lbl45 Label: .lbl47 V_MOV_B32 vDst(VGPR254) src0(1_0_F) Label: .lbl45 S_ANDN2_B64 sDst(EXEC) src0(SGPR212) src1(EXEC) S_AND_B64 sDst(EXEC) src0(SGPR190) src1(EXEC) S_CBRANCH_EXECZ 3 .lbl46 S_MOV_B32 sDst(SGPR214) src0(LITERAL_CONST) const: 0x0 V_MOV_B32 vDst(VGPR254) src0(SGPR214) Label: .lbl46 # CF Merge Point: Restore EXEC. S_MOV_B64 sDst(EXEC) src0(SGPR212) S_AND_B64 sDst(EXEC) src0(EXEC) src1(SGPR190) # OpStore: : tmp805 >> shadow V_MOV_B32 vDst(VGPR218) src0(VGPR254) # 808: OpFDiv: Float: tmp808 << tmp802, const807 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x42c80000 V_RCP_F32 vDst(VGPR255) src0(VGPR254) V_MUL_F32 vDst(VGPR255) src0(VGPR226) src1(VGPR255) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR255) src0(VGPR255) src1(VGPR254) src2(VGPR226) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 809: OpExtInst(Sqrt): Float: tmp809 << tmp808 V_SQRT_F32 vDst(VGPR254) src0(VGPR255) # 810: OpFSub: Float: tmp810 << const117, tmp809 V_SUB_F32 vDst(VGPR255) src0(1_0_F) src1(VGPR254) // VOP2 # 811: OpLoad: Float: tmp811 << shadow # 812: OpFMul: Float: tmp812 << tmp811, tmp810 V_MUL_F32 vDst(VGPR254) src0(VGPR218) src1(VGPR255) // VOP2 # OpStore: : tmp812 >> shadow V_MOV_B32 vDst(VGPR218) src0(VGPR254) # 817: OpDot: Float: tmp817 << tmp781, getNormal(vf3; V_MUL_F32 vDst(VGPR254) src0(VGPR243) src1(VGPR240) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR244) src1(VGPR241) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR245) src1(VGPR242) // VOP2 # 818: OpExtInst(FMax): Float: tmp818 << const92, tmp817 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR248) src0(VGPR255) src1(VGPR254) // VOP2 # 821: OpFNegate: FloatVector3: tmp821 << tmp781 V_MUL_F32 vDst(VGPR256) src0(M1_0_F) src1(VGPR243) // VOP2 V_MUL_F32 vDst(VGPR257) src0(M1_0_F) src1(VGPR244) // VOP2 V_MUL_F32 vDst(VGPR258) src0(M1_0_F) src1(VGPR245) // VOP2 # 823: OpExtInst(Reflect): FloatVector3: tmp823 << tmp821, getNormal(vf3; V_MUL_F32 vDst(VGPR254) src0(VGPR256) src1(VGPR240) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR257) src1(VGPR241) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR258) src1(VGPR242) // VOP2 V_MUL_F32 vDst(VGPR254) src0(2_0_F) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR259) src0(VGPR240) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR260) src0(VGPR241) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR261) src0(VGPR242) src1(VGPR254) // VOP2 V_SUB_F32 vDst(VGPR259) src0(VGPR256) src1(VGPR259) // VOP2 V_SUB_F32 vDst(VGPR260) src0(VGPR257) src1(VGPR260) // VOP2 V_SUB_F32 vDst(VGPR261) src0(VGPR258) src1(VGPR261) // VOP2 # 824: OpLoad: FloatVector3: tmp824 << rd # 825: OpFNegate: FloatVector3: tmp825 << tmp824 V_MUL_F32 vDst(VGPR262) src0(M1_0_F) src1(VGPR189) // VOP2 V_MUL_F32 vDst(VGPR263) src0(M1_0_F) src1(VGPR190) // VOP2 V_MUL_F32 vDst(VGPR264) src0(M1_0_F) src1(VGPR191) // VOP2 # 826: OpDot: Float: tmp826 << tmp823, tmp825 V_MUL_F32 vDst(VGPR254) src0(VGPR259) src1(VGPR262) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR260) src1(VGPR263) // VOP2 V_MAC_F32 vDst(VGPR254) src0(VGPR261) src1(VGPR264) // VOP2 # 827: OpExtInst(FMax): Float: tmp827 << const92, tmp826 V_MOV_B32 vDst(VGPR255) src0(LITERAL_CONST) const: 0x00000000 V_MAX_F32 vDst(VGPR256) src0(VGPR255) src1(VGPR254) // VOP2 # 829: OpExtInst(Pow): Float: tmp829 << tmp827, const828 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x41000000 V_LOG_F32 vDst(VGPR249) src0(VGPR256) V_MUL_F32 vDst(VGPR249) src0(VGPR254) src1(VGPR249) // VOP2 V_EXP_F32 vDst(VGPR249) src0(VGPR249) # OpStore: : tmp772 >> param831 V_MOV_B32 vDst(VGPR227) src0(VGPR237) V_MOV_B32 vDst(VGPR228) src0(VGPR238) V_MOV_B32 vDst(VGPR229) src0(VGPR239) # OpStore: : getNormal(vf3; >> param833 V_MOV_B32 vDst(VGPR230) src0(VGPR240) V_MOV_B32 vDst(VGPR231) src0(VGPR241) V_MOV_B32 vDst(VGPR232) src0(VGPR242) # 835: OpFunctionCall: Float: calculateAO(vf3;vf3;(param831, param833) S_ADD_U32 sDst(SGPR154) src0(LITERAL_CONST) src1(0) const: 0xe3 # VGPR[805:807] S_ADD_U32 sDst(SGPR155) src0(LITERAL_CONST) src1(0) const: 0xe6 # VGPR[808:810] S_MOV_B64 sDst(SGPR206) src0(EXEC) S_MOV_B32 sDst(SGPR139) src0(LITERAL_CONST) const: 0xfa # VGPR974 # Indirect branch to calculateAO(vf3;vf3;: -3280 S_GETPC_B64 sDst(SGPR152) src0(SGPR152) S_SUB_U32 sDst(SGPR152) src0(SGPR152) src1(LITERAL_CONST) const: 0xcd0 S_SUBB_U32 sDst(SGPR153) src0(SGPR153) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR152) src0(SGPR152) S_MOV_B64 sDst(EXEC) src0(SGPR206) # .lbl48 # OpStore: : tmp772 >> param837 V_MOV_B32 vDst(VGPR233) src0(VGPR237) V_MOV_B32 vDst(VGPR234) src0(VGPR238) V_MOV_B32 vDst(VGPR235) src0(VGPR239) # 839: OpFunctionCall: FloatVector3: _texture(vf3;(param837) S_ADD_U32 sDst(SGPR175) src0(LITERAL_CONST) src1(0) const: 0xe9 # VGPR[811:813] S_MOV_B64 sDst(SGPR208) src0(EXEC) S_MOV_B32 sDst(SGPR174) src0(LITERAL_CONST) const: 0xfb # VGPR[975:977] # Indirect branch to _texture(vf3;: -2688 S_GETPC_B64 sDst(SGPR172) src0(SGPR172) S_SUB_U32 sDst(SGPR172) src0(SGPR172) src1(LITERAL_CONST) const: 0xa80 S_SUBB_U32 sDst(SGPR173) src0(SGPR173) src1(LITERAL_CONST) const: 0x0 S_SWAPPC_B64 sDst(SGPR172) src0(SGPR172) S_MOV_B64 sDst(EXEC) src0(SGPR208) # .lbl49 # 840: OpVectorTimesScalar: FloatVector3: tmp840 << _texture(vf3;, calculateAO(vf3;vf3; V_MUL_F32 vDst(VGPR254) src0(VGPR250) src1(VGPR251) // VOP2 V_MUL_F32 vDst(VGPR255) src0(VGPR250) src1(VGPR252) // VOP2 V_MUL_F32 vDst(VGPR256) src0(VGPR250) src1(VGPR253) // VOP2 # 844: OpFAdd: Float: tmp844 << tmp829, tmp818 V_ADD_F32 vDst(VGPR257) src0(VGPR249) src1(VGPR248) // VOP2 # 845: OpLoad: Float: tmp845 << shadow # 846: OpFMul: Float: tmp846 << tmp844, tmp845 V_MUL_F32 vDst(VGPR258) src0(VGPR257) src1(VGPR218) // VOP2 # 847: OpFAdd: Float: tmp847 << const363, tmp846 V_MOV_B32 vDst(VGPR257) src0(LITERAL_CONST) const: 0x3e800000 V_ADD_F32 vDst(VGPR259) src0(VGPR257) src1(VGPR258) // VOP2 # 848: OpVectorTimesScalar: FloatVector3: tmp848 << tmp840, tmp847 V_MUL_F32 vDst(VGPR260) src0(VGPR259) src1(VGPR254) // VOP2 V_MUL_F32 vDst(VGPR261) src0(VGPR259) src1(VGPR255) // VOP2 V_MUL_F32 vDst(VGPR262) src0(VGPR259) src1(VGPR256) // VOP2 # 849: OpLoad: FloatVector4: tmp849 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR3) # 850: OpVectorShuffle: FloatVector4: tmp850 << tmp849, tmp848, 4, 5, 6, 3 V_MOV_B32 vDst(VGPR263) src0(VGPR260) V_MOV_B32 vDst(VGPR264) src0(VGPR261) V_MOV_B32 vDst(VGPR265) src0(VGPR262) V_MOV_B32 vDst(VGPR266) src0(VGPR257) # OpStore: : tmp850 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR263) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR264) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR265) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR266) # 852: OpFDiv: Float: tmp852 << tmp766, const807 V_MOV_B32 vDst(VGPR254) src0(LITERAL_CONST) const: 0x42c80000 V_RCP_F32 vDst(VGPR255) src0(VGPR254) V_MUL_F32 vDst(VGPR255) src0(VGPR214) src1(VGPR255) // VOP2 V_DIV_FIXUP_F32 vDst(VGPR255) src0(VGPR255) src1(VGPR254) src2(VGPR214) abs(0) clamp(0) omod(0) neg(0) // VOP3a # 853: OpExtInst(Sqrt): Float: tmp853 << tmp852 V_SQRT_F32 vDst(VGPR254) src0(VGPR255) # 854: OpLoad: FloatVector4: tmp854 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELS_B32 vDst(VGPR255) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR258) src0(VGPR3) # 855: OpVectorTimesScalar: FloatVector4: tmp855 << tmp854, tmp853 V_MUL_F32 vDst(VGPR259) src0(VGPR254) src1(VGPR255) // VOP2 V_MUL_F32 vDst(VGPR260) src0(VGPR254) src1(VGPR256) // VOP2 V_MUL_F32 vDst(VGPR261) src0(VGPR254) src1(VGPR257) // VOP2 V_MUL_F32 vDst(VGPR262) src0(VGPR254) src1(VGPR258) // VOP2 # OpStore: : tmp855 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR259) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR260) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR261) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR262) # 856: OpLoad: FloatVector4: tmp856 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR3) # 860: OpFMul: Float: tmp860 << trace(vf3;vf3;f1;f1;, trace(vf3;vf3;f1;f1; V_MUL_F32 vDst(VGPR258) src0(VGPR236) src1(VGPR236) // VOP2 # 862: OpFMul: Float: tmp862 << tmp860, const861 V_MOV_B32 vDst(VGPR259) src0(LITERAL_CONST) const: 0x3cf5c28f V_MUL_F32 vDst(VGPR260) src0(VGPR258) src1(VGPR259) // VOP2 # 863: OpExtInst(FClamp): Float: tmp863 << tmp862, const92, const117 V_MOV_B32 vDst(VGPR258) src0(LITERAL_CONST) const: 0x00000000 V_MOV_B32 vDst(VGPR259) src0(1_0_F) V_MAX_F32 vDst(VGPR261) src0(VGPR260) src1(VGPR258) // VOP2 V_MIN_F32 vDst(VGPR261) src0(VGPR261) src1(VGPR259) // VOP2 # 864: OpCompositeConstruct: FloatVector4: tmp864 << tmp863, tmp863, tmp863, tmp863 V_MOV_B32 vDst(VGPR262) src0(VGPR261) V_MOV_B32 vDst(VGPR263) src0(VGPR261) V_MOV_B32 vDst(VGPR264) src0(VGPR261) V_MOV_B32 vDst(VGPR265) src0(VGPR261) # 865: OpExtInst(FMix): FloatVector4: tmp865 << tmp856, const857, tmp864 V_MOV_B32 vDst(VGPR266) src0(LITERAL_CONST) const: 0x3f666666 V_MOV_B32 vDst(VGPR267) src0(LITERAL_CONST) const: 0x3f4ccccd V_MOV_B32 vDst(VGPR268) src0(LITERAL_CONST) const: 0x3f333333 V_MOV_B32 vDst(VGPR269) src0(1_0_F) V_SUBREV_F32 vDst(VGPR258) src0(VGPR262) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR258) src0(VGPR254) src1(VGPR258) // VOP2 V_MAD_F32 vDst(VGPR258) src0(VGPR266) src1(VGPR262) src2(VGPR258) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR259) src0(VGPR263) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR259) src0(VGPR255) src1(VGPR259) // VOP2 V_MAD_F32 vDst(VGPR259) src0(VGPR267) src1(VGPR263) src2(VGPR259) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR260) src0(VGPR264) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR260) src0(VGPR256) src1(VGPR260) // VOP2 V_MAD_F32 vDst(VGPR260) src0(VGPR268) src1(VGPR264) src2(VGPR260) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_SUBREV_F32 vDst(VGPR261) src0(VGPR265) src1(1_0_F) src2(N/A) abs(0) clamp(0) omod(0) neg(0) // VOP3a V_MUL_F32 vDst(VGPR261) src0(VGPR257) src1(VGPR261) // VOP2 V_MAD_F32 vDst(VGPR261) src0(VGPR269) src1(VGPR265) src2(VGPR261) abs(0) clamp(0) omod(0) neg(0) // VOP3a # OpStore: : tmp865 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR258) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR259) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR260) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR261) # 866: OpLoad: FloatVector4: tmp866 << fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELS_B32 vDst(VGPR254) src0(VGPR0) V_MOVRELS_B32 vDst(VGPR255) src0(VGPR1) V_MOVRELS_B32 vDst(VGPR256) src0(VGPR2) V_MOVRELS_B32 vDst(VGPR257) src0(VGPR3) # 869: OpExtInst(Pow): FloatVector4: tmp869 << tmp866, const868 V_MOV_B32 vDst(VGPR258) src0(LITERAL_CONST) const: 0x3ee8ba2f V_MOV_B32 vDst(VGPR259) src0(LITERAL_CONST) const: 0x3ee8ba2f V_MOV_B32 vDst(VGPR260) src0(LITERAL_CONST) const: 0x3ee8ba2f V_MOV_B32 vDst(VGPR261) src0(LITERAL_CONST) const: 0x3ee8ba2f V_LOG_F32 vDst(VGPR262) src0(VGPR254) V_LOG_F32 vDst(VGPR263) src0(VGPR255) V_LOG_F32 vDst(VGPR264) src0(VGPR256) V_LOG_F32 vDst(VGPR265) src0(VGPR257) V_MUL_F32 vDst(VGPR262) src0(VGPR258) src1(VGPR262) // VOP2 V_MUL_F32 vDst(VGPR263) src0(VGPR259) src1(VGPR263) // VOP2 V_MUL_F32 vDst(VGPR264) src0(VGPR260) src1(VGPR264) // VOP2 V_MUL_F32 vDst(VGPR265) src0(VGPR261) src1(VGPR265) // VOP2 V_EXP_F32 vDst(VGPR262) src0(VGPR262) V_EXP_F32 vDst(VGPR263) src0(VGPR263) V_EXP_F32 vDst(VGPR264) src0(VGPR264) V_EXP_F32 vDst(VGPR265) src0(VGPR265) # OpStore: : tmp869 >> fragColor S_ADD_U32 sDst(M0) src0(LITERAL_CONST) src1(SGPR9) const: 0x0 V_MOVRELD_B32 vDst(VGPR0) src0(VGPR262) V_MOVRELD_B32 vDst(VGPR1) src0(VGPR263) V_MOVRELD_B32 vDst(VGPR2) src0(VGPR264) V_MOVRELD_B32 vDst(VGPR3) src0(VGPR265) # OpReturn: S_SETPC_B64 sDst(SGPR10) src0(SGPR10) Generating the final byte-code... ERROR: Code generation failed. Error log: Need 222 SGPRs, which exceeds the maximum of 102 Need 270 VGPRs, which exceeds the maximum of 256 Done.